From: Yifei Jiang <jiangyifei@huawei.com>
To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>
Cc: <kvm-riscv@lists.infradead.org>, <kvm@vger.kernel.org>,
<libvir-list@redhat.com>, <anup@brainfault.org>,
<palmer@dabbelt.com>, <Alistair.Francis@wdc.com>,
<bin.meng@windriver.com>, <fanliang@huawei.com>,
<wu.wubin@huawei.com>, <wanghaibin.wang@huawei.com>,
<wanbo13@huawei.com>, Yifei Jiang <jiangyifei@huawei.com>,
Mingwang Li <limingwang@huawei.com>,
Alistair Francis <alistair.francis@wdc.com>,
Anup Patel <anup.patel@wdc.com>
Subject: [PATCH v5 09/13] target/riscv: Add host cpu type
Date: Wed, 12 Jan 2022 16:13:25 +0800 [thread overview]
Message-ID: <20220112081329.1835-10-jiangyifei@huawei.com> (raw)
In-Reply-To: <20220112081329.1835-1-jiangyifei@huawei.com>
'host' type cpu is set isa to RV32 or RV64 simply, more isa info
will obtain from KVM in kvm_arch_init_vcpu()
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
---
target/riscv/cpu.c | 15 +++++++++++++++
target/riscv/cpu.h | 1 +
2 files changed, 16 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 53b0524830..32879f1403 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -235,6 +235,18 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
}
#endif
+#if defined(CONFIG_KVM)
+static void riscv_host_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+#if defined(TARGET_RISCV32)
+ set_misa(env, MXL_RV32, 0);
+#elif defined(TARGET_RISCV64)
+ set_misa(env, MXL_RV64, 0);
+#endif
+}
+#endif
+
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
@@ -847,6 +859,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.class_init = riscv_cpu_class_init,
},
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
+#if defined(CONFIG_KVM)
+ DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init),
+#endif
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 8fa6fdcd77..73ced2116b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -47,6 +47,7 @@
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
+#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
#if defined(TARGET_RISCV32)
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
--
2.19.1
next prev parent reply other threads:[~2022-01-12 8:13 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-12 8:13 [PATCH v5 00/13] Add riscv kvm accel support Yifei Jiang
2022-01-12 8:13 ` [PATCH v5 01/13] update-linux-headers: Add asm-riscv/kvm.h Yifei Jiang
2022-01-12 8:13 ` [PATCH v5 02/13] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang
2022-01-12 8:13 ` [PATCH v5 03/13] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang
2022-01-12 8:13 ` [PATCH v5 04/13] target/riscv: Implement kvm_arch_get_registers Yifei Jiang
2022-01-12 8:13 ` [PATCH v5 05/13] target/riscv: Implement kvm_arch_put_registers Yifei Jiang
2022-01-12 8:13 ` [PATCH v5 06/13] target/riscv: Support start kernel directly by KVM Yifei Jiang
2022-01-13 4:35 ` Anup Patel
2022-01-12 8:13 ` [PATCH v5 07/13] target/riscv: Support setting external interrupt " Yifei Jiang
2022-01-12 8:13 ` [PATCH v5 08/13] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang [this message]
2022-01-12 8:13 ` [PATCH v5 10/13] target/riscv: Add kvm_riscv_get/put_regs_timer Yifei Jiang
2022-01-12 8:13 ` [PATCH v5 11/13] target/riscv: Implement virtual time adjusting with vm state changing Yifei Jiang
2022-01-12 8:13 ` [PATCH v5 12/13] target/riscv: Support virtual time context synchronization Yifei Jiang
2022-01-12 8:13 ` [PATCH v5 13/13] target/riscv: enable riscv kvm accel Yifei Jiang
2022-01-13 4:30 ` Alistair Francis
2022-01-13 4:41 ` Anup Patel
2022-01-17 22:48 ` [PATCH v5 00/13] Add riscv kvm accel support Alistair Francis
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