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From: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
To: qemu-devel@nongnu.org
Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk,
	kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com,
	palmer@dabbelt.com, alistair.francis@wdc.com,
	bin.meng@windriver.com, pbonzini@redhat.com,
	philipp.tomsich@vrull.eu, kvm@vger.kernel.org,
	Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Subject: [PATCH 19/45] target/riscv: Add vaesdf.vv decoding, translation and execution support
Date: Fri, 10 Mar 2023 16:03:20 +0000	[thread overview]
Message-ID: <20230310160346.1193597-20-lawrence.hunter@codethink.co.uk> (raw)
In-Reply-To: <20230310160346.1193597-1-lawrence.hunter@codethink.co.uk>

Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
---
 target/riscv/helper.h                        |  1 +
 target/riscv/insn32.decode                   |  1 +
 target/riscv/insn_trans/trans_rvzvkned.c.inc |  1 +
 target/riscv/vcrypto_helper.c                | 31 ++++++++++++++++++++
 4 files changed, 34 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index fb30b4d13e..c626ddcee1 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1190,3 +1190,4 @@ DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32)
 
 DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32)
 DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 5d1bb6ccc6..e9ccc56915 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -930,3 +930,4 @@ vandn_vx        000001 . ..... ..... 100 ..... 1010111 @r_vm
 # *** RV64 Zvkned vector crypto extension ***
 vaesef_vv       101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1
 vaesef_vs       101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1
+vaesdf_vv       101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1
diff --git a/target/riscv/insn_trans/trans_rvzvkned.c.inc b/target/riscv/insn_trans/trans_rvzvkned.c.inc
index 69bf7f9fee..134fd59df8 100644
--- a/target/riscv/insn_trans/trans_rvzvkned.c.inc
+++ b/target/riscv/insn_trans/trans_rvzvkned.c.inc
@@ -90,3 +90,4 @@ static bool vaes_check_vs(DisasContext *s, arg_rmr *a)
 
 GEN_V_UNMASKED_TRANS(vaesef_vv, vaes_check_vv)
 GEN_V_UNMASKED_TRANS(vaesef_vs, vaes_check_vs)
+GEN_V_UNMASKED_TRANS(vaesdf_vv, vaes_check_vv)
diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
index b079b543c7..8f448de86e 100644
--- a/target/riscv/vcrypto_helper.c
+++ b/target/riscv/vcrypto_helper.c
@@ -181,6 +181,34 @@ static inline void xor_round_key(uint8_t round_state[4][4], uint8_t *round_key)
     }
 }
 
+static inline void aes_inv_sub_bytes(uint8_t round_state[4][4])
+{
+    for (int j = 0; j < 16; j++) {
+        round_state[j / 4][j % 4] = AES_isbox[round_state[j / 4][j % 4]];
+    }
+}
+
+static inline void aes_inv_shift_bytes(uint8_t round_state[4][4])
+{
+    uint8_t temp;
+    temp = round_state[3][1];
+    round_state[3][1] = round_state[2][1];
+    round_state[2][1] = round_state[1][1];
+    round_state[1][1] = round_state[0][1];
+    round_state[0][1] = temp;
+    temp = round_state[0][2];
+    round_state[0][2] = round_state[2][2];
+    round_state[2][2] = temp;
+    temp = round_state[1][2];
+    round_state[1][2] = round_state[3][2];
+    round_state[3][2] = temp;
+    temp = round_state[0][3];
+    round_state[0][3] = round_state[1][3];
+    round_state[1][3] = round_state[2][3];
+    round_state[2][3] = round_state[3][3];
+    round_state[3][3] = temp;
+}
+
 #define GEN_ZVKNED_HELPER_VV(NAME, ...)                                   \
 void HELPER(NAME)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env,      \
                   uint32_t desc)                                          \
@@ -253,3 +281,6 @@ GEN_ZVKNED_HELPER_VV(vaesef_vv, aes_sub_bytes(round_state);
 GEN_ZVKNED_HELPER_VS(vaesef_vs, aes_sub_bytes(round_state);
                     aes_shift_bytes(round_state);
                     xor_round_key(round_state, (uint8_t *)round_key);)
+GEN_ZVKNED_HELPER_VV(vaesdf_vv, aes_inv_shift_bytes(round_state);
+                    aes_inv_sub_bytes(round_state);
+                    xor_round_key(round_state, (uint8_t *)round_key);)
-- 
2.39.2


  parent reply	other threads:[~2023-03-10 16:07 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-10 16:03 [PATCH 00/45] Add RISC-V vector cryptographic instruction set support Lawrence Hunter
2023-03-10 16:03 ` [PATCH 01/45] target/riscv: Add zvkb cpu property Lawrence Hunter
2023-03-10 16:03 ` [PATCH 02/45] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-03-21 12:02   ` Christoph Müllner
2023-03-23 11:34     ` Lawrence Hunter
2023-03-10 16:03 ` [PATCH 03/45] target/riscv: Add vclmul.vv decoding, translation and execution support Lawrence Hunter
2023-03-10 16:03 ` [PATCH 04/45] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-03-10 16:03 ` [PATCH 05/45] target/riscv: Add vclmul.vx decoding, translation and execution support Lawrence Hunter
2023-03-10 16:03 ` [PATCH 06/45] target/riscv: Add vclmulh.vv " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 07/45] target/riscv: Add vclmulh.vx " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 08/45] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-03-10 16:03 ` [PATCH 09/45] qemu/bitops.h: Limit rotate amounts Lawrence Hunter
2023-03-10 16:03 ` [PATCH 10/45] target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] decoding, translation and execution support Lawrence Hunter
2023-03-10 16:03 ` [PATCH 11/45] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-03-10 16:03 ` [PATCH 12/45] target/riscv: Add vbrev8.v decoding, translation and execution support Lawrence Hunter
2023-03-10 16:03 ` [PATCH 13/45] target/riscv: Add vrev8.v " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 14/45] target/riscv: Add vandn.[vv,vx] " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 15/45] target/riscv: Expose zvkb cpu property Lawrence Hunter
2023-03-10 16:03 ` [PATCH 16/45] target/riscv: Add zvkned " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 17/45] target/riscv: Add vaesef.vv decoding, translation and execution support Lawrence Hunter
2023-03-10 16:03 ` [PATCH 18/45] target/riscv: Add vaesef.vs " Lawrence Hunter
2023-03-10 16:03 ` Lawrence Hunter [this message]
2023-03-10 16:03 ` [PATCH 20/45] target/riscv: Add vaesdf.vs " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 21/45] target/riscv: Add vaesdm.vv " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 22/45] target/riscv: Add vaesdm.vs " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 23/45] target/riscv: Add vaesz.vs " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 24/45] target/riscv: Add vaesem.vv " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 25/45] target/riscv: Add vaesem.vs " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 26/45] target/riscv: Add vaeskf1.vi " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 27/45] target/riscv: Add vaeskf2.vi " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 28/45] target/riscv: Expose zvkned cpu property Lawrence Hunter
2023-03-10 16:03 ` [PATCH 29/45] target/riscv: Add zvknh cpu properties Lawrence Hunter
2023-03-10 16:03 ` [PATCH 30/45] target/riscv: Add vsha2ms.vv decoding, translation and execution support Lawrence Hunter
2023-03-10 16:03 ` [PATCH 31/45] target/riscv: Add vsha2c[hl].vv " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 32/45] target/riscv: Expose zvknh cpu properties Lawrence Hunter
2023-03-10 16:03 ` [PATCH 33/45] target/riscv: Add zvksh cpu property Lawrence Hunter
2023-03-10 16:03 ` [PATCH 34/45] target/riscv: Add vsm3me.vv decoding, translation and execution support Lawrence Hunter
2023-03-10 16:03 ` [PATCH 35/45] target/riscv: Add vsm3c.vi " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 36/45] target/riscv: Expose zvksh cpu property Lawrence Hunter
2023-03-10 16:03 ` [PATCH 37/45] target/riscv: Add zvkg " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 38/45] target/riscv: Add vgmul.vv decoding, translation and execution support Lawrence Hunter
2023-03-10 16:03 ` [PATCH 39/45] target/riscv: Add vghsh.vv " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 40/45] target/riscv: Expose zvkg cpu property Lawrence Hunter
2023-03-10 16:03 ` [PATCH 41/45] crypto: Create sm4_subword Lawrence Hunter
2023-03-10 16:03 ` [PATCH 42/45] crypto: Add SM4 constant parameter CK Lawrence Hunter
2023-03-10 16:03 ` [PATCH 43/45] target/riscv: Add zvksed cfg property Lawrence Hunter
2023-03-10 16:03 ` [PATCH 44/45] target/riscv: Add Zvksed support Lawrence Hunter
2023-03-10 16:03 ` [PATCH 45/45] target/riscv: Expose Zvksed property Lawrence Hunter
2023-03-23 12:51 ` [PATCH 00/45] Add RISC-V vector cryptographic instruction set support Daniel Henrique Barboza
  -- strict thread matches above, loose matches on Subject: below --
2023-03-10  9:11 Lawrence Hunter
2023-03-10  9:11 ` [PATCH 19/45] target/riscv: Add vaesdf.vv decoding, translation and execution support Lawrence Hunter

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