From: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
To: qemu-devel@nongnu.org
Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk,
kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com,
palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, pbonzini@redhat.com,
philipp.tomsich@vrull.eu, kvm@vger.kernel.org,
Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Subject: [PATCH 07/45] target/riscv: Add vclmulh.vx decoding, translation and execution support
Date: Fri, 10 Mar 2023 16:03:08 +0000 [thread overview]
Message-ID: <20230310160346.1193597-8-lawrence.hunter@codethink.co.uk> (raw)
In-Reply-To: <20230310160346.1193597-1-lawrence.hunter@codethink.co.uk>
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
---
target/riscv/helper.h | 1 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 +
target/riscv/vcrypto_helper.c | 2 ++
4 files changed, 5 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 1c69c34a78..37f2e162f6 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1147,3 +1147,4 @@ DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vclmulh_vx, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 3ad8e2055b..488e01ca59 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -913,3 +913,4 @@ czero_nez 0000111 ..... ..... 111 ..... 0110011 @r
vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm
vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm
vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm
+vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn_trans/trans_rvzvkb.c.inc
index 63a8778acc..810e469e13 100644
--- a/target/riscv/insn_trans/trans_rvzvkb.c.inc
+++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc
@@ -87,3 +87,4 @@ static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a)
}
GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check)
+GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check)
diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
index 1891c29767..8b7c63d499 100644
--- a/target/riscv/vcrypto_helper.c
+++ b/target/riscv/vcrypto_helper.c
@@ -55,3 +55,5 @@ RVVCALL(OPIVX2, vclmul_vx, OP_UUU_D, H8, H8, clmul64)
GEN_VEXT_VX(vclmul_vx, 8)
RVVCALL(OPIVV2, vclmulh_vv, OP_UUU_D, H8, H8, H8, clmulh64)
GEN_VEXT_VV(vclmulh_vv, 8)
+RVVCALL(OPIVX2, vclmulh_vx, OP_UUU_D, H8, H8, clmulh64)
+GEN_VEXT_VX(vclmulh_vx, 8)
--
2.39.2
next prev parent reply other threads:[~2023-03-10 16:06 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-10 16:03 [PATCH 00/45] Add RISC-V vector cryptographic instruction set support Lawrence Hunter
2023-03-10 16:03 ` [PATCH 01/45] target/riscv: Add zvkb cpu property Lawrence Hunter
2023-03-10 16:03 ` [PATCH 02/45] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-03-21 12:02 ` Christoph Müllner
2023-03-23 11:34 ` Lawrence Hunter
2023-03-10 16:03 ` [PATCH 03/45] target/riscv: Add vclmul.vv decoding, translation and execution support Lawrence Hunter
2023-03-10 16:03 ` [PATCH 04/45] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-03-10 16:03 ` [PATCH 05/45] target/riscv: Add vclmul.vx decoding, translation and execution support Lawrence Hunter
2023-03-10 16:03 ` [PATCH 06/45] target/riscv: Add vclmulh.vv " Lawrence Hunter
2023-03-10 16:03 ` Lawrence Hunter [this message]
2023-03-10 16:03 ` [PATCH 08/45] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-03-10 16:03 ` [PATCH 09/45] qemu/bitops.h: Limit rotate amounts Lawrence Hunter
2023-03-10 16:03 ` [PATCH 10/45] target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] decoding, translation and execution support Lawrence Hunter
2023-03-10 16:03 ` [PATCH 11/45] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-03-10 16:03 ` [PATCH 12/45] target/riscv: Add vbrev8.v decoding, translation and execution support Lawrence Hunter
2023-03-10 16:03 ` [PATCH 13/45] target/riscv: Add vrev8.v " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 14/45] target/riscv: Add vandn.[vv,vx] " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 15/45] target/riscv: Expose zvkb cpu property Lawrence Hunter
2023-03-10 16:03 ` [PATCH 16/45] target/riscv: Add zvkned " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 17/45] target/riscv: Add vaesef.vv decoding, translation and execution support Lawrence Hunter
2023-03-10 16:03 ` [PATCH 18/45] target/riscv: Add vaesef.vs " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 19/45] target/riscv: Add vaesdf.vv " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 20/45] target/riscv: Add vaesdf.vs " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 21/45] target/riscv: Add vaesdm.vv " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 22/45] target/riscv: Add vaesdm.vs " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 23/45] target/riscv: Add vaesz.vs " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 24/45] target/riscv: Add vaesem.vv " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 25/45] target/riscv: Add vaesem.vs " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 26/45] target/riscv: Add vaeskf1.vi " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 27/45] target/riscv: Add vaeskf2.vi " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 28/45] target/riscv: Expose zvkned cpu property Lawrence Hunter
2023-03-10 16:03 ` [PATCH 29/45] target/riscv: Add zvknh cpu properties Lawrence Hunter
2023-03-10 16:03 ` [PATCH 30/45] target/riscv: Add vsha2ms.vv decoding, translation and execution support Lawrence Hunter
2023-03-10 16:03 ` [PATCH 31/45] target/riscv: Add vsha2c[hl].vv " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 32/45] target/riscv: Expose zvknh cpu properties Lawrence Hunter
2023-03-10 16:03 ` [PATCH 33/45] target/riscv: Add zvksh cpu property Lawrence Hunter
2023-03-10 16:03 ` [PATCH 34/45] target/riscv: Add vsm3me.vv decoding, translation and execution support Lawrence Hunter
2023-03-10 16:03 ` [PATCH 35/45] target/riscv: Add vsm3c.vi " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 36/45] target/riscv: Expose zvksh cpu property Lawrence Hunter
2023-03-10 16:03 ` [PATCH 37/45] target/riscv: Add zvkg " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 38/45] target/riscv: Add vgmul.vv decoding, translation and execution support Lawrence Hunter
2023-03-10 16:03 ` [PATCH 39/45] target/riscv: Add vghsh.vv " Lawrence Hunter
2023-03-10 16:03 ` [PATCH 40/45] target/riscv: Expose zvkg cpu property Lawrence Hunter
2023-03-10 16:03 ` [PATCH 41/45] crypto: Create sm4_subword Lawrence Hunter
2023-03-10 16:03 ` [PATCH 42/45] crypto: Add SM4 constant parameter CK Lawrence Hunter
2023-03-10 16:03 ` [PATCH 43/45] target/riscv: Add zvksed cfg property Lawrence Hunter
2023-03-10 16:03 ` [PATCH 44/45] target/riscv: Add Zvksed support Lawrence Hunter
2023-03-10 16:03 ` [PATCH 45/45] target/riscv: Expose Zvksed property Lawrence Hunter
2023-03-23 12:51 ` [PATCH 00/45] Add RISC-V vector cryptographic instruction set support Daniel Henrique Barboza
-- strict thread matches above, loose matches on Subject: below --
2023-03-10 9:11 Lawrence Hunter
2023-03-10 9:11 ` [PATCH 07/45] target/riscv: Add vclmulh.vx decoding, translation and execution support Lawrence Hunter
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