* [PTACH v2 1/6] update-linux-headers: sync-up header with Linux for KVM AIA support
[not found] <20230505113946.23433-1-yongxuan.wang@sifive.com>
@ 2023-05-05 11:39 ` Yong-Xuan Wang
2023-05-05 16:17 ` Alex Williamson
2023-05-05 11:39 ` [PTACH v2 3/6] target/riscv: check the in-kernel irqchip support Yong-Xuan Wang
2023-05-05 11:39 ` [PTACH v2 4/6] target/riscv: Create an KVM AIA irqchip Yong-Xuan Wang
2 siblings, 1 reply; 7+ messages in thread
From: Yong-Xuan Wang @ 2023-05-05 11:39 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: rkanwal, anup, dbarboza, atishp, vincent.chen, greentime.hu,
frank.chang, jim.shu, Yong-Xuan Wang, Michael S. Tsirkin,
Cornelia Huck, Paolo Bonzini, Juan Quintela, Avihai Horon,
Alex Williamson, Thomas Huth, kvm
Update the linux headers to get the latest KVM RISC-V headers with AIA support
by the scripts/update-linux-headers.sh.
The linux headers is comes from the riscv_aia_v1 branch available at
https://github.com/avpatel/linux.git. It hasn't merged into the mainline kernel.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
---
| 105 +++++++++++++++++++++++++++++++++-
| 2 +
2 files changed, 106 insertions(+), 1 deletion(-)
--git a/linux-headers/asm-riscv/kvm.h b/linux-headers/asm-riscv/kvm.h
index 92af6f3f05..deba7ff304 100644
--- a/linux-headers/asm-riscv/kvm.h
+++ b/linux-headers/asm-riscv/kvm.h
@@ -12,8 +12,10 @@
#ifndef __ASSEMBLY__
#include <linux/types.h>
+#include <asm/bitsperlong.h>
#include <asm/ptrace.h>
+#define __KVM_HAVE_IRQ_LINE
#define __KVM_HAVE_READONLY_MEM
#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
@@ -64,7 +66,7 @@ struct kvm_riscv_core {
#define KVM_RISCV_MODE_S 1
#define KVM_RISCV_MODE_U 0
-/* CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
+/* General CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
struct kvm_riscv_csr {
unsigned long sstatus;
unsigned long sie;
@@ -78,6 +80,17 @@ struct kvm_riscv_csr {
unsigned long scounteren;
};
+/* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
+struct kvm_riscv_aia_csr {
+ unsigned long siselect;
+ unsigned long siprio1;
+ unsigned long siprio2;
+ unsigned long sieh;
+ unsigned long siph;
+ unsigned long siprio1h;
+ unsigned long siprio2h;
+};
+
/* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
struct kvm_riscv_timer {
__u64 frequency;
@@ -105,9 +118,28 @@ enum KVM_RISCV_ISA_EXT_ID {
KVM_RISCV_ISA_EXT_SVINVAL,
KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
KVM_RISCV_ISA_EXT_ZICBOM,
+ KVM_RISCV_ISA_EXT_ZBB,
+ KVM_RISCV_ISA_EXT_SSAIA,
KVM_RISCV_ISA_EXT_MAX,
};
+/*
+ * SBI extension IDs specific to KVM. This is not the same as the SBI
+ * extension IDs defined by the RISC-V SBI specification.
+ */
+enum KVM_RISCV_SBI_EXT_ID {
+ KVM_RISCV_SBI_EXT_V01 = 0,
+ KVM_RISCV_SBI_EXT_TIME,
+ KVM_RISCV_SBI_EXT_IPI,
+ KVM_RISCV_SBI_EXT_RFENCE,
+ KVM_RISCV_SBI_EXT_SRST,
+ KVM_RISCV_SBI_EXT_HSM,
+ KVM_RISCV_SBI_EXT_PMU,
+ KVM_RISCV_SBI_EXT_EXPERIMENTAL,
+ KVM_RISCV_SBI_EXT_VENDOR,
+ KVM_RISCV_SBI_EXT_MAX,
+};
+
/* Possible states for kvm_riscv_timer */
#define KVM_RISCV_TIMER_STATE_OFF 0
#define KVM_RISCV_TIMER_STATE_ON 1
@@ -118,6 +150,8 @@ enum KVM_RISCV_ISA_EXT_ID {
/* If you need to interpret the index values, here is the key: */
#define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000
#define KVM_REG_RISCV_TYPE_SHIFT 24
+#define KVM_REG_RISCV_SUBTYPE_MASK 0x0000000000FF0000
+#define KVM_REG_RISCV_SUBTYPE_SHIFT 16
/* Config registers are mapped as type 1 */
#define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT)
@@ -131,8 +165,12 @@ enum KVM_RISCV_ISA_EXT_ID {
/* Control and status registers are mapped as type 3 */
#define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
+#define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
#define KVM_REG_RISCV_CSR_REG(name) \
(offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
+#define KVM_REG_RISCV_CSR_AIA_REG(name) \
+ (offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long))
/* Timer registers are mapped as type 4 */
#define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT)
@@ -152,6 +190,71 @@ enum KVM_RISCV_ISA_EXT_ID {
/* ISA Extension registers are mapped as type 7 */
#define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT)
+/* SBI extension registers are mapped as type 8 */
+#define KVM_REG_RISCV_SBI_EXT (0x08 << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_SBI_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
+#define KVM_REG_RISCV_SBI_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
+#define KVM_REG_RISCV_SBI_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
+#define KVM_REG_RISCV_SBI_MULTI_REG(__ext_id) \
+ ((__ext_id) / __BITS_PER_LONG)
+#define KVM_REG_RISCV_SBI_MULTI_MASK(__ext_id) \
+ (1UL << ((__ext_id) % __BITS_PER_LONG))
+#define KVM_REG_RISCV_SBI_MULTI_REG_LAST \
+ KVM_REG_RISCV_SBI_MULTI_REG(KVM_RISCV_SBI_EXT_MAX - 1)
+
+/* Device Control API: RISC-V AIA */
+#define KVM_DEV_RISCV_APLIC_ALIGN 0x1000
+#define KVM_DEV_RISCV_APLIC_SIZE 0x4000
+#define KVM_DEV_RISCV_APLIC_MAX_HARTS 0x4000
+#define KVM_DEV_RISCV_IMSIC_ALIGN 0x1000
+#define KVM_DEV_RISCV_IMSIC_SIZE 0x1000
+
+#define KVM_DEV_RISCV_AIA_GRP_CONFIG 0
+#define KVM_DEV_RISCV_AIA_CONFIG_MODE 0
+#define KVM_DEV_RISCV_AIA_CONFIG_IDS 1
+#define KVM_DEV_RISCV_AIA_CONFIG_SRCS 2
+#define KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS 3
+#define KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT 4
+#define KVM_DEV_RISCV_AIA_CONFIG_HART_BITS 5
+#define KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS 6
+#define KVM_DEV_RISCV_AIA_MODE_EMUL 0
+#define KVM_DEV_RISCV_AIA_MODE_HWACCEL 1
+#define KVM_DEV_RISCV_AIA_MODE_AUTO 2
+#define KVM_DEV_RISCV_AIA_IDS_MIN 63
+#define KVM_DEV_RISCV_AIA_IDS_MAX 2048
+#define KVM_DEV_RISCV_AIA_SRCS_MAX 1024
+#define KVM_DEV_RISCV_AIA_GROUP_BITS_MAX 8
+#define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN 24
+#define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MAX 56
+#define KVM_DEV_RISCV_AIA_HART_BITS_MAX 16
+#define KVM_DEV_RISCV_AIA_GUEST_BITS_MAX 8
+
+#define KVM_DEV_RISCV_AIA_GRP_ADDR 1
+#define KVM_DEV_RISCV_AIA_ADDR_APLIC 0
+#define KVM_DEV_RISCV_AIA_ADDR_IMSIC(__vcpu) (1 + (__vcpu))
+#define KVM_DEV_RISCV_AIA_ADDR_MAX \
+ (1 + KVM_DEV_RISCV_APLIC_MAX_HARTS)
+
+#define KVM_DEV_RISCV_AIA_GRP_CTRL 2
+#define KVM_DEV_RISCV_AIA_CTRL_INIT 0
+
+#define KVM_DEV_RISCV_AIA_GRP_APLIC 3
+
+#define KVM_DEV_RISCV_AIA_GRP_IMSIC 4
+#define KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS 12
+#define KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK \
+ ((1U << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) - 1)
+#define KVM_DEV_RISCV_AIA_IMSIC_MKATTR(__vcpu, __isel) \
+ (((__vcpu) << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) | \
+ ((__isel) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK))
+#define KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(__attr) \
+ ((__attr) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK)
+#define KVM_DEV_RISCV_AIA_IMSIC_GET_VCPU(__attr) \
+ ((__attr) >> KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS)
+
+/* One single KVM irqchip, ie. the AIA */
+#define KVM_NR_IRQCHIPS 1
+
#endif
#endif /* __LINUX_KVM_RISCV_H */
--git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index 599de3c6e3..a9a4f5791d 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -1434,6 +1434,8 @@ enum kvm_device_type {
#define KVM_DEV_TYPE_XIVE KVM_DEV_TYPE_XIVE
KVM_DEV_TYPE_ARM_PV_TIME,
#define KVM_DEV_TYPE_ARM_PV_TIME KVM_DEV_TYPE_ARM_PV_TIME
+ KVM_DEV_TYPE_RISCV_AIA,
+#define KVM_DEV_TYPE_RISCV_AIA KVM_DEV_TYPE_RISCV_AIA
KVM_DEV_TYPE_MAX,
};
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PTACH v2 3/6] target/riscv: check the in-kernel irqchip support
[not found] <20230505113946.23433-1-yongxuan.wang@sifive.com>
2023-05-05 11:39 ` [PTACH v2 1/6] update-linux-headers: sync-up header with Linux for KVM AIA support Yong-Xuan Wang
@ 2023-05-05 11:39 ` Yong-Xuan Wang
2023-05-05 11:39 ` [PTACH v2 4/6] target/riscv: Create an KVM AIA irqchip Yong-Xuan Wang
2 siblings, 0 replies; 7+ messages in thread
From: Yong-Xuan Wang @ 2023-05-05 11:39 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: rkanwal, anup, dbarboza, atishp, vincent.chen, greentime.hu,
frank.chang, jim.shu, Yong-Xuan Wang, Palmer Dabbelt,
Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei, Paolo Bonzini,
kvm
We check the in-kernel irqchip support when using KVM acceleration.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
---
target/riscv/kvm.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 0f932a5b96..eb469e8ca5 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -433,7 +433,18 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
int kvm_arch_irqchip_create(KVMState *s)
{
- return 0;
+ if (kvm_kernel_irqchip_split()) {
+ error_report("-machine kernel_irqchip=split is not supported "
+ "on RISC-V.");
+ exit(1);
+ }
+
+ /*
+ * If we can create the VAIA using the newer device control API, we
+ * let the device do this when it initializes itself, otherwise we
+ * fall back to the old API
+ */
+ return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL);
}
int kvm_arch_process_async_events(CPUState *cs)
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PTACH v2 4/6] target/riscv: Create an KVM AIA irqchip
[not found] <20230505113946.23433-1-yongxuan.wang@sifive.com>
2023-05-05 11:39 ` [PTACH v2 1/6] update-linux-headers: sync-up header with Linux for KVM AIA support Yong-Xuan Wang
2023-05-05 11:39 ` [PTACH v2 3/6] target/riscv: check the in-kernel irqchip support Yong-Xuan Wang
@ 2023-05-05 11:39 ` Yong-Xuan Wang
2 siblings, 0 replies; 7+ messages in thread
From: Yong-Xuan Wang @ 2023-05-05 11:39 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: rkanwal, anup, dbarboza, atishp, vincent.chen, greentime.hu,
frank.chang, jim.shu, Yong-Xuan Wang, Palmer Dabbelt,
Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei, Paolo Bonzini,
kvm
implement a function to create an KVM AIA chip
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
---
target/riscv/kvm.c | 83 ++++++++++++++++++++++++++++++++++++++++
target/riscv/kvm_riscv.h | 3 ++
2 files changed, 86 insertions(+)
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index eb469e8ca5..ead121154f 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -34,6 +34,7 @@
#include "exec/address-spaces.h"
#include "hw/boards.h"
#include "hw/irq.h"
+#include "hw/intc/riscv_imsic.h"
#include "qemu/log.h"
#include "hw/loader.h"
#include "kvm_riscv.h"
@@ -548,3 +549,85 @@ bool kvm_arch_cpu_check_are_resettable(void)
void kvm_arch_accel_class_init(ObjectClass *oc)
{
}
+
+void kvm_riscv_aia_create(DeviceState *aplic_s, bool msimode, int socket,
+ uint64_t aia_irq_num, uint64_t hart_count,
+ uint64_t aplic_base, uint64_t imsic_base)
+{
+ int ret;
+ int aia_fd = -1;
+ uint64_t aia_mode;
+ uint64_t aia_nr_ids;
+ uint64_t aia_hart_bits = find_last_bit(&hart_count, BITS_PER_LONG) + 1;
+
+ if (!msimode) {
+ error_report("Currently KVM AIA only supports aplic_imsic mode");
+ exit(1);
+ }
+
+ aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false);
+
+ if (aia_fd < 0) {
+ error_report("Unable to create in-kernel irqchip");
+ exit(1);
+ }
+
+ ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
+ KVM_DEV_RISCV_AIA_CONFIG_MODE,
+ &aia_mode, false, NULL);
+
+ ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
+ KVM_DEV_RISCV_AIA_CONFIG_IDS,
+ &aia_nr_ids, false, NULL);
+
+ ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
+ KVM_DEV_RISCV_AIA_CONFIG_SRCS,
+ &aia_irq_num, true, NULL);
+ if (ret < 0) {
+ error_report("KVM AIA: fail to set number input irq lines");
+ exit(1);
+ }
+
+ ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
+ KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
+ &aia_hart_bits, true, NULL);
+ if (ret < 0) {
+ error_report("KVM AIA: fail to set number of harts");
+ exit(1);
+ }
+
+ ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR,
+ KVM_DEV_RISCV_AIA_ADDR_APLIC,
+ &aplic_base, true, NULL);
+ if (ret < 0) {
+ error_report("KVM AIA: fail to set the base address of APLIC");
+ exit(1);
+ }
+
+ for (int i = 0; i < hart_count; i++) {
+ uint64_t imsic_addr = imsic_base + i * IMSIC_HART_SIZE(0);
+ ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR,
+ KVM_DEV_RISCV_AIA_ADDR_IMSIC(i),
+ &imsic_addr, true, NULL);
+ if (ret < 0) {
+ error_report("KVM AIA: fail to set the base address of IMSICs");
+ exit(1);
+ }
+ }
+
+ if (kvm_has_gsi_routing()) {
+ for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) {
+ kvm_irqchip_add_irq_route(kvm_state, idx, socket, idx);
+ }
+ kvm_gsi_routing_allowed = true;
+ kvm_irqchip_commit_routes(kvm_state);
+ }
+
+ ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL,
+ KVM_DEV_RISCV_AIA_CTRL_INIT,
+ NULL, true, NULL);
+ if (ret < 0) {
+ error_report("KVM AIA: initialized fail");
+ exit(1);
+ }
+}
diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index ed281bdce0..d8d7256852 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -21,5 +21,8 @@
void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
+void kvm_riscv_aia_create(DeviceState *aplic_s, bool msimode, int socket,
+ uint64_t aia_irq_num, uint64_t hart_count,
+ uint64_t aplic_base, uint64_t imsic_base);
#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PTACH v2 1/6] update-linux-headers: sync-up header with Linux for KVM AIA support
2023-05-05 11:39 ` [PTACH v2 1/6] update-linux-headers: sync-up header with Linux for KVM AIA support Yong-Xuan Wang
@ 2023-05-05 16:17 ` Alex Williamson
2023-05-08 7:39 ` Cornelia Huck
0 siblings, 1 reply; 7+ messages in thread
From: Alex Williamson @ 2023-05-05 16:17 UTC (permalink / raw)
To: Yong-Xuan Wang
Cc: qemu-devel, qemu-riscv, rkanwal, anup, dbarboza, atishp,
vincent.chen, greentime.hu, frank.chang, jim.shu,
Michael S. Tsirkin, Cornelia Huck, Paolo Bonzini, Juan Quintela,
Avihai Horon, Thomas Huth, kvm
On Fri, 5 May 2023 11:39:36 +0000
Yong-Xuan Wang <yongxuan.wang@sifive.com> wrote:
> Update the linux headers to get the latest KVM RISC-V headers with AIA support
> by the scripts/update-linux-headers.sh.
> The linux headers is comes from the riscv_aia_v1 branch available at
> https://github.com/avpatel/linux.git. It hasn't merged into the mainline kernel.
Updating linux-headers outside of code accepted to mainline gets a down
vote from me. This sets a poor precedent and can potentially lead to
complicated compatibility issues. Thanks,
Alex
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PTACH v2 1/6] update-linux-headers: sync-up header with Linux for KVM AIA support
2023-05-05 16:17 ` Alex Williamson
@ 2023-05-08 7:39 ` Cornelia Huck
2023-05-23 9:38 ` Yong-Xuan Wang
0 siblings, 1 reply; 7+ messages in thread
From: Cornelia Huck @ 2023-05-08 7:39 UTC (permalink / raw)
To: Alex Williamson, Yong-Xuan Wang
Cc: qemu-devel, qemu-riscv, rkanwal, anup, dbarboza, atishp,
vincent.chen, greentime.hu, frank.chang, jim.shu,
Michael S. Tsirkin, Paolo Bonzini, Juan Quintela, Avihai Horon,
Thomas Huth, kvm
On Fri, May 05 2023, Alex Williamson <alex.williamson@redhat.com> wrote:
> On Fri, 5 May 2023 11:39:36 +0000
> Yong-Xuan Wang <yongxuan.wang@sifive.com> wrote:
>
>> Update the linux headers to get the latest KVM RISC-V headers with AIA support
>> by the scripts/update-linux-headers.sh.
>> The linux headers is comes from the riscv_aia_v1 branch available at
>> https://github.com/avpatel/linux.git. It hasn't merged into the mainline kernel.
>
> Updating linux-headers outside of code accepted to mainline gets a down
> vote from me. This sets a poor precedent and can potentially lead to
> complicated compatibility issues. Thanks,
>
> Alex
Indeed, this needs to be clearly marked as a placeholder patch, and
replaced with a proper header sync after the changes hit the mainline
kernel.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PTACH v2 1/6] update-linux-headers: sync-up header with Linux for KVM AIA support
2023-05-08 7:39 ` Cornelia Huck
@ 2023-05-23 9:38 ` Yong-Xuan Wang
2023-05-23 9:51 ` Cornelia Huck
0 siblings, 1 reply; 7+ messages in thread
From: Yong-Xuan Wang @ 2023-05-23 9:38 UTC (permalink / raw)
To: Cornelia Huck
Cc: Alex Williamson, qemu-devel, qemu-riscv, rkanwal, anup, dbarboza,
atishp, vincent.chen, greentime.hu, frank.chang, jim.shu,
Michael S. Tsirkin, Paolo Bonzini, Juan Quintela, Avihai Horon,
Thomas Huth, kvm
On Mon, May 8, 2023 at 3:39 PM Cornelia Huck <cohuck@redhat.com> wrote:
>
> On Fri, May 05 2023, Alex Williamson <alex.williamson@redhat.com> wrote:
>
> > On Fri, 5 May 2023 11:39:36 +0000
> > Yong-Xuan Wang <yongxuan.wang@sifive.com> wrote:
> >
> >> Update the linux headers to get the latest KVM RISC-V headers with AIA support
> >> by the scripts/update-linux-headers.sh.
> >> The linux headers is comes from the riscv_aia_v1 branch available at
> >> https://github.com/avpatel/linux.git. It hasn't merged into the mainline kernel.
> >
> > Updating linux-headers outside of code accepted to mainline gets a down
> > vote from me. This sets a poor precedent and can potentially lead to
> > complicated compatibility issues. Thanks,
> >
> > Alex
>
> Indeed, this needs to be clearly marked as a placeholder patch, and
> replaced with a proper header sync after the changes hit the mainline
> kernel.
>
Hi Alex and Cornelia,
We found that the changes are from 2 different patchsets.
[1] https://lore.kernel.org/lkml/20230404153452.2405681-1-apatel@ventanamicro.com/
[2] https://www.spinics.net/lists/kernel/msg4791872.html
Patchset 1 is already merged into mainline kernel in v6.4-rc1 and
patchset 2 is not.
Maybe we can split them into two placeholder patches?
Regards,
Yong-Xuan
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PTACH v2 1/6] update-linux-headers: sync-up header with Linux for KVM AIA support
2023-05-23 9:38 ` Yong-Xuan Wang
@ 2023-05-23 9:51 ` Cornelia Huck
0 siblings, 0 replies; 7+ messages in thread
From: Cornelia Huck @ 2023-05-23 9:51 UTC (permalink / raw)
To: Yong-Xuan Wang
Cc: Alex Williamson, qemu-devel, qemu-riscv, rkanwal, anup, dbarboza,
atishp, vincent.chen, greentime.hu, frank.chang, jim.shu,
Michael S. Tsirkin, Paolo Bonzini, Juan Quintela, Avihai Horon,
Thomas Huth, kvm
On Tue, May 23 2023, Yong-Xuan Wang <yongxuan.wang@sifive.com> wrote:
> On Mon, May 8, 2023 at 3:39 PM Cornelia Huck <cohuck@redhat.com> wrote:
>>
>> On Fri, May 05 2023, Alex Williamson <alex.williamson@redhat.com> wrote:
>>
>> > On Fri, 5 May 2023 11:39:36 +0000
>> > Yong-Xuan Wang <yongxuan.wang@sifive.com> wrote:
>> >
>> >> Update the linux headers to get the latest KVM RISC-V headers with AIA support
>> >> by the scripts/update-linux-headers.sh.
>> >> The linux headers is comes from the riscv_aia_v1 branch available at
>> >> https://github.com/avpatel/linux.git. It hasn't merged into the mainline kernel.
>> >
>> > Updating linux-headers outside of code accepted to mainline gets a down
>> > vote from me. This sets a poor precedent and can potentially lead to
>> > complicated compatibility issues. Thanks,
>> >
>> > Alex
>>
>> Indeed, this needs to be clearly marked as a placeholder patch, and
>> replaced with a proper header sync after the changes hit the mainline
>> kernel.
>>
>
> Hi Alex and Cornelia,
>
> We found that the changes are from 2 different patchsets.
>
> [1] https://lore.kernel.org/lkml/20230404153452.2405681-1-apatel@ventanamicro.com/
> [2] https://www.spinics.net/lists/kernel/msg4791872.html
>
> Patchset 1 is already merged into mainline kernel in v6.4-rc1 and
> patchset 2 is not.
> Maybe we can split them into two placeholder patches?
Please just keep this as a single placeholder patch; once you rebase on
top of a tree that includes a proper rebase to 6.4-rcX, the placeholder
patch will simply shrink to the bits in patchset 2. The important part
is that nobody tries to merge it by accident.
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-05-23 9:54 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <20230505113946.23433-1-yongxuan.wang@sifive.com>
2023-05-05 11:39 ` [PTACH v2 1/6] update-linux-headers: sync-up header with Linux for KVM AIA support Yong-Xuan Wang
2023-05-05 16:17 ` Alex Williamson
2023-05-08 7:39 ` Cornelia Huck
2023-05-23 9:38 ` Yong-Xuan Wang
2023-05-23 9:51 ` Cornelia Huck
2023-05-05 11:39 ` [PTACH v2 3/6] target/riscv: check the in-kernel irqchip support Yong-Xuan Wang
2023-05-05 11:39 ` [PTACH v2 4/6] target/riscv: Create an KVM AIA irqchip Yong-Xuan Wang
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).