From: Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>
To: Marc Zyngier <maz@kernel.org>,
linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org
Cc: Andre Przywara <andre.przywara@arm.com>,
Christoffer Dall <christoffer.dall@arm.com>,
Jintack Lim <jintack@cs.columbia.edu>,
Haibo Xu <haibo.xu@linaro.org>, James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
kernel-team@android.com
Subject: Re: [PATCH v5 14/69] KVM: arm64: nv: Support virtual EL2 exceptions
Date: Mon, 20 Dec 2021 12:27:33 +0530 [thread overview]
Message-ID: <6817416a-34b6-c987-c07e-e0d773fe1775@os.amperecomputing.com> (raw)
In-Reply-To: <20211129200150.351436-15-maz@kernel.org>
Hi Marc,
On 30-11-2021 01:30 am, Marc Zyngier wrote:
> From: Jintack Lim <jintack.lim@linaro.org>
>
> Support injecting exceptions and performing exception returns to and
> from virtual EL2. This must be done entirely in software except when
> taking an exception from vEL0 to vEL2 when the virtual HCR_EL2.{E2H,TGE}
> == {1,1} (a VHE guest hypervisor).
>
> Signed-off-by: Jintack Lim <jintack.lim@linaro.org>
> Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
> [maz: switch to common exception injection framework]
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> .mailmap | 1 +
> arch/arm64/include/asm/kvm_arm.h | 17 +++
> arch/arm64/include/asm/kvm_emulate.h | 10 ++
> arch/arm64/include/asm/kvm_host.h | 1 +
> arch/arm64/kvm/Makefile | 2 +-
> arch/arm64/kvm/emulate-nested.c | 176 +++++++++++++++++++++++++++
> arch/arm64/kvm/hyp/exception.c | 49 ++++++--
> arch/arm64/kvm/inject_fault.c | 68 +++++++++--
> arch/arm64/kvm/trace_arm.h | 59 +++++++++
> 9 files changed, 362 insertions(+), 21 deletions(-)
> create mode 100644 arch/arm64/kvm/emulate-nested.c
>
> diff --git a/.mailmap b/.mailmap
> index 14314e3c5d5e..491238a888cb 100644
> --- a/.mailmap
> +++ b/.mailmap
> @@ -167,6 +167,7 @@ Jeff Layton <jlayton@kernel.org> <jlayton@redhat.com>
> Jens Axboe <axboe@suse.de>
> Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
> Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
> +<jintack@cs.columbia.edu> <jintack.lim@linaro.org>
> Jiri Slaby <jirislaby@kernel.org> <jirislaby@gmail.com>
> Jiri Slaby <jirislaby@kernel.org> <jslaby@novell.com>
> Jiri Slaby <jirislaby@kernel.org> <jslaby@suse.com>
> diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
> index a39fcf318c77..589a6b92d741 100644
> --- a/arch/arm64/include/asm/kvm_arm.h
> +++ b/arch/arm64/include/asm/kvm_arm.h
> @@ -359,4 +359,21 @@
> #define CPACR_EL1_TTA (1 << 28)
> #define CPACR_EL1_DEFAULT (CPACR_EL1_FPEN | CPACR_EL1_ZEN_EL1EN)
>
> +#define kvm_mode_names \
> + { PSR_MODE_EL0t, "EL0t" }, \
> + { PSR_MODE_EL1t, "EL1t" }, \
> + { PSR_MODE_EL1h, "EL1h" }, \
> + { PSR_MODE_EL2t, "EL2t" }, \
> + { PSR_MODE_EL2h, "EL2h" }, \
> + { PSR_MODE_EL3t, "EL3t" }, \
> + { PSR_MODE_EL3h, "EL3h" }, \
> + { PSR_AA32_MODE_USR, "32-bit USR" }, \
> + { PSR_AA32_MODE_FIQ, "32-bit FIQ" }, \
> + { PSR_AA32_MODE_IRQ, "32-bit IRQ" }, \
> + { PSR_AA32_MODE_SVC, "32-bit SVC" }, \
> + { PSR_AA32_MODE_ABT, "32-bit ABT" }, \
> + { PSR_AA32_MODE_HYP, "32-bit HYP" }, \
> + { PSR_AA32_MODE_UND, "32-bit UND" }, \
> + { PSR_AA32_MODE_SYS, "32-bit SYS" }
> +
> #endif /* __ARM64_KVM_ARM_H__ */
> diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
> index f4b079945d0f..46c849ba281e 100644
> --- a/arch/arm64/include/asm/kvm_emulate.h
> +++ b/arch/arm64/include/asm/kvm_emulate.h
> @@ -33,6 +33,12 @@ enum exception_type {
> except_type_serror = 0x180,
> };
>
> +#define kvm_exception_type_names \
> + { except_type_sync, "SYNC" }, \
> + { except_type_irq, "IRQ" }, \
> + { except_type_fiq, "FIQ" }, \
> + { except_type_serror, "SERROR" }
> +
> bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
> void kvm_skip_instr32(struct kvm_vcpu *vcpu);
>
> @@ -41,6 +47,10 @@ void kvm_inject_vabt(struct kvm_vcpu *vcpu);
> void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
> void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
>
> +void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu);
> +int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2);
> +int kvm_inject_nested_irq(struct kvm_vcpu *vcpu);
> +
> static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
> {
> return !(vcpu->arch.hcr_el2 & HCR_RW);
> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
> index 4f642a2e9c34..7b6fe18ee450 100644
> --- a/arch/arm64/include/asm/kvm_host.h
> +++ b/arch/arm64/include/asm/kvm_host.h
> @@ -477,6 +477,7 @@ struct kvm_vcpu_arch {
> #define KVM_ARM64_EXCEPT_AA64_ELx_SERR (3 << 9)
> #define KVM_ARM64_EXCEPT_AA64_EL1 (0 << 11)
> #define KVM_ARM64_EXCEPT_AA64_EL2 (1 << 11)
> +#define KVM_ARM64_EXCEPT_AA64_EL_MASK (1 << 11)
>
> /*
> * Overlaps with KVM_ARM64_EXCEPT_MASK on purpose so that it can't be
> diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile
> index 989bb5dad2c8..1f602526e9a2 100644
> --- a/arch/arm64/kvm/Makefile
> +++ b/arch/arm64/kvm/Makefile
> @@ -16,7 +16,7 @@ kvm-y := $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o $(KVM)/eventfd.o \
> inject_fault.o va_layout.o handle_exit.o \
> guest.o debug.o reset.o sys_regs.o \
> vgic-sys-reg-v3.o fpsimd.o pmu.o \
> - arch_timer.o trng.o\
> + arch_timer.o trng.o emulate-nested.o \
> vgic/vgic.o vgic/vgic-init.o \
> vgic/vgic-irqfd.o vgic/vgic-v2.o \
> vgic/vgic-v3.o vgic/vgic-v4.o \
> diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
> new file mode 100644
> index 000000000000..339e8272b01e
> --- /dev/null
> +++ b/arch/arm64/kvm/emulate-nested.c
> @@ -0,0 +1,176 @@
> +/*
> + * Copyright (C) 2016 - Linaro and Columbia University
> + * Author: Jintack Lim <jintack.lim@linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/kvm.h>
> +#include <linux/kvm_host.h>
> +
> +#include <asm/kvm_emulate.h>
> +#include <asm/kvm_nested.h>
> +
> +#include "hyp/include/hyp/adjust_pc.h"
> +
> +#include "trace.h"
> +
> +void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu)
> +{
> + u64 spsr, elr, mode;
> + bool direct_eret;
> +
> + /*
> + * Going through the whole put/load motions is a waste of time
> + * if this is a VHE guest hypervisor returning to its own
> + * userspace, or the hypervisor performing a local exception
> + * return. No need to save/restore registers, no need to
> + * switch S2 MMU. Just do the canonical ERET.
> + */
> + spsr = vcpu_read_sys_reg(vcpu, SPSR_EL2);
> + mode = spsr & (PSR_MODE_MASK | PSR_MODE32_BIT);
> +
> + direct_eret = (mode == PSR_MODE_EL0t &&
> + vcpu_el2_e2h_is_set(vcpu) &&
> + vcpu_el2_tge_is_set(vcpu));
> + direct_eret |= (mode == PSR_MODE_EL2h || mode == PSR_MODE_EL2t);
> +
> + if (direct_eret) {
> + *vcpu_pc(vcpu) = vcpu_read_sys_reg(vcpu, ELR_EL2);
> + *vcpu_cpsr(vcpu) = spsr;
> + trace_kvm_nested_eret(vcpu, *vcpu_pc(vcpu), spsr);
> + return;
> + }
> +
> + preempt_disable();
> + kvm_arch_vcpu_put(vcpu);
> +
> + elr = __vcpu_sys_reg(vcpu, ELR_EL2);
> +
> + trace_kvm_nested_eret(vcpu, elr, spsr);
> +
> + /*
> + * Note that the current exception level is always the virtual EL2,
> + * since we set HCR_EL2.NV bit only when entering the virtual EL2.
> + */
> + *vcpu_pc(vcpu) = elr;
> + *vcpu_cpsr(vcpu) = spsr;
> +
> + kvm_arch_vcpu_load(vcpu, smp_processor_id());
> + preempt_enable();
> +}
> +
> +static void kvm_inject_el2_exception(struct kvm_vcpu *vcpu, u64 esr_el2,
> + enum exception_type type)
> +{
> + trace_kvm_inject_nested_exception(vcpu, esr_el2, type);
> +
> + switch (type) {
> + case except_type_sync:
> + vcpu->arch.flags |= KVM_ARM64_EXCEPT_AA64_ELx_SYNC;
> + break;
> + case except_type_irq:
> + vcpu->arch.flags |= KVM_ARM64_EXCEPT_AA64_ELx_IRQ;
> + break;
> + default:
> + WARN_ONCE(1, "Unsupported EL2 exception injection %d\n", type);
> + }
> +
> + vcpu->arch.flags |= (KVM_ARM64_EXCEPT_AA64_EL2 |
> + KVM_ARM64_PENDING_EXCEPTION);
> +
> + vcpu_write_sys_reg(vcpu, esr_el2, ESR_EL2);
> +}
> +
> +/*
> + * Emulate taking an exception to EL2.
> + * See ARM ARM J8.1.2 AArch64.TakeException()
> + */
> +static int kvm_inject_nested(struct kvm_vcpu *vcpu, u64 esr_el2,
> + enum exception_type type)
> +{
> + u64 pstate, mode;
> + bool direct_inject;
> +
> + if (!nested_virt_in_use(vcpu)) {
> + kvm_err("Unexpected call to %s for the non-nesting configuration\n",
> + __func__);
> + return -EINVAL;
> + }
> +
> + /*
> + * As for ERET, we can avoid doing too much on the injection path by
> + * checking that we either took the exception from a VHE host
> + * userspace or from vEL2. In these cases, there is no change in
> + * translation regime (or anything else), so let's do as little as
> + * possible.
> + */
> + pstate = *vcpu_cpsr(vcpu);
> + mode = pstate & (PSR_MODE_MASK | PSR_MODE32_BIT);
> +
> + direct_inject = (mode == PSR_MODE_EL0t &&
> + vcpu_el2_e2h_is_set(vcpu) &&
> + vcpu_el2_tge_is_set(vcpu));
> + direct_inject |= (mode == PSR_MODE_EL2h || mode == PSR_MODE_EL2t);
> +
> + if (direct_inject) {
> + kvm_inject_el2_exception(vcpu, esr_el2, type);
> + return 1;
> + }
> +
> + preempt_disable();
> + kvm_arch_vcpu_put(vcpu);
> +
> + kvm_inject_el2_exception(vcpu, esr_el2, type);
> +
> + /*
> + * A hard requirement is that a switch between EL1 and EL2
> + * contexts has to happen between a put/load, so that we can
> + * pick the correct timer and interrupt configuration, among
> + * other things.
> + *
> + * Make sure the exception actually took place before we load
> + * the new context.
> + */
> + __kvm_adjust_pc(vcpu);
> +
> + kvm_arch_vcpu_load(vcpu, smp_processor_id());
> + preempt_enable();
> +
> + return 1;
> +}
> +
> +int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2)
> +{
> + return kvm_inject_nested(vcpu, esr_el2, except_type_sync);
> +}
> +
> +int kvm_inject_nested_irq(struct kvm_vcpu *vcpu)
> +{
> + /*
> + * Do not inject an irq if the:
> + * - Current exception level is EL2, and
> + * - virtual HCR_EL2.TGE == 0
> + * - virtual HCR_EL2.IMO == 0
> + *
> + * See Table D1-17 "Physical interrupt target and masking when EL3 is
> + * not implemented and EL2 is implemented" in ARM DDI 0487C.a.
> + */
> +
> + if (vcpu_mode_el2(vcpu) && !vcpu_el2_tge_is_set(vcpu) &&
> + !(__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_IMO))
> + return 1;
> +
> + /* esr_el2 value doesn't matter for exits due to irqs. */
> + return kvm_inject_nested(vcpu, 0, except_type_irq);
> +}
> diff --git a/arch/arm64/kvm/hyp/exception.c b/arch/arm64/kvm/hyp/exception.c
> index 0418399e0a20..4ef5e86efd8b 100644
> --- a/arch/arm64/kvm/hyp/exception.c
> +++ b/arch/arm64/kvm/hyp/exception.c
> @@ -13,6 +13,7 @@
> #include <hyp/adjust_pc.h>
> #include <linux/kvm_host.h>
> #include <asm/kvm_emulate.h>
> +#include <asm/kvm_nested.h>
>
> #if !defined (__KVM_NVHE_HYPERVISOR__) && !defined (__KVM_VHE_HYPERVISOR__)
> #error Hypervisor code only!
> @@ -22,7 +23,9 @@ static inline u64 __vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
> {
> u64 val;
>
> - if (__vcpu_read_sys_reg_from_cpu(reg, &val))
> + if (unlikely(nested_virt_in_use(vcpu)))
> + return vcpu_read_sys_reg(vcpu, reg);
> + else if (__vcpu_read_sys_reg_from_cpu(reg, &val))
> return val;
>
> return __vcpu_sys_reg(vcpu, reg);
> @@ -30,14 +33,24 @@ static inline u64 __vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
>
> static inline void __vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
> {
> - if (__vcpu_write_sys_reg_to_cpu(val, reg))
> - return;
> -
> - __vcpu_sys_reg(vcpu, reg) = val;
> + if (unlikely(nested_virt_in_use(vcpu)))
> + vcpu_write_sys_reg(vcpu, val, reg);
> + else if (!__vcpu_write_sys_reg_to_cpu(val, reg))
> + __vcpu_sys_reg(vcpu, reg) = val;
> }
>
> -static void __vcpu_write_spsr(struct kvm_vcpu *vcpu, u64 val)
> +static void __vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long target_mode,
> + u64 val)
> {
> + if (unlikely(nested_virt_in_use(vcpu))) {
> + if (target_mode == PSR_MODE_EL1h)
> + vcpu_write_sys_reg(vcpu, val, SPSR_EL1);
> + else
> + vcpu_write_sys_reg(vcpu, val, SPSR_EL2);
> +
> + return;
> + }
> +
> write_sysreg_el1(val, SYS_SPSR);
> }
>
> @@ -97,6 +110,11 @@ static void enter_exception64(struct kvm_vcpu *vcpu, unsigned long target_mode,
> sctlr = __vcpu_read_sys_reg(vcpu, SCTLR_EL1);
> __vcpu_write_sys_reg(vcpu, *vcpu_pc(vcpu), ELR_EL1);
> break;
> + case PSR_MODE_EL2h:
> + vbar = __vcpu_read_sys_reg(vcpu, VBAR_EL2);
> + sctlr = __vcpu_read_sys_reg(vcpu, SCTLR_EL2);
> + __vcpu_write_sys_reg(vcpu, *vcpu_pc(vcpu), ELR_EL2);
> + break;
> default:
> /* Don't do that */
> BUG();
> @@ -149,7 +167,7 @@ static void enter_exception64(struct kvm_vcpu *vcpu, unsigned long target_mode,
> new |= target_mode;
>
> *vcpu_cpsr(vcpu) = new;
> - __vcpu_write_spsr(vcpu, old);
> + __vcpu_write_spsr(vcpu, target_mode, old);
> }
>
> /*
> @@ -320,11 +338,22 @@ static void kvm_inject_exception(struct kvm_vcpu *vcpu)
> KVM_ARM64_EXCEPT_AA64_EL1):
> enter_exception64(vcpu, PSR_MODE_EL1h, except_type_sync);
> break;
> +
> + case (KVM_ARM64_EXCEPT_AA64_ELx_SYNC |
> + KVM_ARM64_EXCEPT_AA64_EL2):
> + enter_exception64(vcpu, PSR_MODE_EL2h, except_type_sync);
> + break;
> +
> + case (KVM_ARM64_EXCEPT_AA64_ELx_IRQ |
> + KVM_ARM64_EXCEPT_AA64_EL2):
> + enter_exception64(vcpu, PSR_MODE_EL2h, except_type_irq);
> + break;
> +
> default:
> /*
> - * Only EL1_SYNC makes sense so far, EL2_{SYNC,IRQ}
> - * will be implemented at some point. Everything
> - * else gets silently ignored.
> + * Only EL1_SYNC and EL2_{SYNC,IRQ} makes
> + * sense so far. Everything else gets silently
> + * ignored.
> */
> break;
> }
> diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c
> index b47df73e98d7..5dcf3f8b08b8 100644
> --- a/arch/arm64/kvm/inject_fault.c
> +++ b/arch/arm64/kvm/inject_fault.c
> @@ -12,19 +12,58 @@
>
> #include <linux/kvm_host.h>
> #include <asm/kvm_emulate.h>
> +#include <asm/kvm_nested.h>
> #include <asm/esr.h>
>
> +static void pend_sync_exception(struct kvm_vcpu *vcpu)
> +{
> + vcpu->arch.flags |= (KVM_ARM64_EXCEPT_AA64_ELx_SYNC |
> + KVM_ARM64_PENDING_EXCEPTION);
> +
> + /* If not nesting, EL1 is the only possible exception target */
> + if (likely(!nested_virt_in_use(vcpu))) {
> + vcpu->arch.flags |= KVM_ARM64_EXCEPT_AA64_EL1;
> + return;
> + }
> +
> + /*
> + * With NV, we need to pick between EL1 and EL2. Note that we
> + * never deal with a nesting exception here, hence never
> + * changing context, and the exception itself can be delayed
> + * until the next entry.
> + */
> + switch(*vcpu_cpsr(vcpu) & PSR_MODE_MASK) {
> + case PSR_MODE_EL2h:
> + case PSR_MODE_EL2t:
> + vcpu->arch.flags |= KVM_ARM64_EXCEPT_AA64_EL2;
> + break;
> + case PSR_MODE_EL1h:
> + case PSR_MODE_EL1t:
> + vcpu->arch.flags |= KVM_ARM64_EXCEPT_AA64_EL1;
> + break;
> + case PSR_MODE_EL0t:
> + if (vcpu_el2_tge_is_set(vcpu) & HCR_TGE)
IMO, AND with HCR_TGE is not needed.
> + vcpu->arch.flags |= KVM_ARM64_EXCEPT_AA64_EL2;
> + else
> + vcpu->arch.flags |= KVM_ARM64_EXCEPT_AA64_EL1;
> + break;
> + default:
> + BUG();
> + }
> +}
> +
> +static bool match_target_el(struct kvm_vcpu *vcpu, unsigned long target)
> +{
> + return (vcpu->arch.flags & KVM_ARM64_EXCEPT_AA64_EL_MASK) == target;
> +}
> +
> static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr)
> {
> unsigned long cpsr = *vcpu_cpsr(vcpu);
> bool is_aarch32 = vcpu_mode_is_32bit(vcpu);
> u32 esr = 0;
>
> - vcpu->arch.flags |= (KVM_ARM64_EXCEPT_AA64_EL1 |
> - KVM_ARM64_EXCEPT_AA64_ELx_SYNC |
> - KVM_ARM64_PENDING_EXCEPTION);
> -
> - vcpu_write_sys_reg(vcpu, addr, FAR_EL1);
> + pend_sync_exception(vcpu);
>
> /*
> * Build an {i,d}abort, depending on the level and the
> @@ -45,16 +84,22 @@ static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr
> if (!is_iabt)
> esr |= ESR_ELx_EC_DABT_LOW << ESR_ELx_EC_SHIFT;
>
> - vcpu_write_sys_reg(vcpu, esr | ESR_ELx_FSC_EXTABT, ESR_EL1);
> + esr |= ESR_ELx_FSC_EXTABT;
> +
> + if (match_target_el(vcpu, KVM_ARM64_EXCEPT_AA64_EL1)) {
> + vcpu_write_sys_reg(vcpu, addr, FAR_EL1);
> + vcpu_write_sys_reg(vcpu, esr, ESR_EL1);
> + } else {
> + vcpu_write_sys_reg(vcpu, addr, FAR_EL2);
> + vcpu_write_sys_reg(vcpu, esr, ESR_EL2);
> + }
> }
>
> static void inject_undef64(struct kvm_vcpu *vcpu)
> {
> u32 esr = (ESR_ELx_EC_UNKNOWN << ESR_ELx_EC_SHIFT);
>
> - vcpu->arch.flags |= (KVM_ARM64_EXCEPT_AA64_EL1 |
> - KVM_ARM64_EXCEPT_AA64_ELx_SYNC |
> - KVM_ARM64_PENDING_EXCEPTION);
> + pend_sync_exception(vcpu);
>
> /*
> * Build an unknown exception, depending on the instruction
> @@ -63,7 +108,10 @@ static void inject_undef64(struct kvm_vcpu *vcpu)
> if (kvm_vcpu_trap_il_is32bit(vcpu))
> esr |= ESR_ELx_IL;
>
> - vcpu_write_sys_reg(vcpu, esr, ESR_EL1);
> + if (match_target_el(vcpu, KVM_ARM64_EXCEPT_AA64_EL1))
> + vcpu_write_sys_reg(vcpu, esr, ESR_EL1);
> + else
> + vcpu_write_sys_reg(vcpu, esr, ESR_EL2);
> }
>
> #define DFSR_FSC_EXTABT_LPAE 0x10
> diff --git a/arch/arm64/kvm/trace_arm.h b/arch/arm64/kvm/trace_arm.h
> index 33e4e7dd2719..f3e46a976125 100644
> --- a/arch/arm64/kvm/trace_arm.h
> +++ b/arch/arm64/kvm/trace_arm.h
> @@ -2,6 +2,7 @@
> #if !defined(_TRACE_ARM_ARM64_KVM_H) || defined(TRACE_HEADER_MULTI_READ)
> #define _TRACE_ARM_ARM64_KVM_H
>
> +#include <asm/kvm_emulate.h>
> #include <kvm/arm_arch_timer.h>
> #include <linux/tracepoint.h>
>
> @@ -301,6 +302,64 @@ TRACE_EVENT(kvm_timer_emulate,
> __entry->timer_idx, __entry->should_fire)
> );
>
> +TRACE_EVENT(kvm_nested_eret,
> + TP_PROTO(struct kvm_vcpu *vcpu, unsigned long elr_el2,
> + unsigned long spsr_el2),
> + TP_ARGS(vcpu, elr_el2, spsr_el2),
> +
> + TP_STRUCT__entry(
> + __field(struct kvm_vcpu *, vcpu)
> + __field(unsigned long, elr_el2)
> + __field(unsigned long, spsr_el2)
> + __field(unsigned long, target_mode)
> + __field(unsigned long, hcr_el2)
> + ),
> +
> + TP_fast_assign(
> + __entry->vcpu = vcpu;
> + __entry->elr_el2 = elr_el2;
> + __entry->spsr_el2 = spsr_el2;
> + __entry->target_mode = spsr_el2 & (PSR_MODE_MASK | PSR_MODE32_BIT);
> + __entry->hcr_el2 = __vcpu_sys_reg(vcpu, HCR_EL2);
> + ),
> +
> + TP_printk("elr_el2: 0x%lx spsr_el2: 0x%08lx (M: %s) hcr_el2: %lx",
> + __entry->elr_el2, __entry->spsr_el2,
> + __print_symbolic(__entry->target_mode, kvm_mode_names),
> + __entry->hcr_el2)
> +);
> +
> +TRACE_EVENT(kvm_inject_nested_exception,
> + TP_PROTO(struct kvm_vcpu *vcpu, u64 esr_el2, int type),
> + TP_ARGS(vcpu, esr_el2, type),
> +
> + TP_STRUCT__entry(
> + __field(struct kvm_vcpu *, vcpu)
> + __field(unsigned long, esr_el2)
> + __field(int, type)
> + __field(unsigned long, spsr_el2)
> + __field(unsigned long, pc)
> + __field(unsigned long, source_mode)
> + __field(unsigned long, hcr_el2)
> + ),
> +
> + TP_fast_assign(
> + __entry->vcpu = vcpu;
> + __entry->esr_el2 = esr_el2;
> + __entry->type = type;
> + __entry->spsr_el2 = *vcpu_cpsr(vcpu);
> + __entry->pc = *vcpu_pc(vcpu);
> + __entry->source_mode = *vcpu_cpsr(vcpu) & (PSR_MODE_MASK | PSR_MODE32_BIT);
> + __entry->hcr_el2 = __vcpu_sys_reg(vcpu, HCR_EL2);
> + ),
> +
> + TP_printk("%s: esr_el2 0x%lx elr_el2: 0x%lx spsr_el2: 0x%08lx (M: %s) hcr_el2: %lx",
> + __print_symbolic(__entry->type, kvm_exception_type_names),
> + __entry->esr_el2, __entry->pc, __entry->spsr_el2,
> + __print_symbolic(__entry->source_mode, kvm_mode_names),
> + __entry->hcr_el2)
> +);
> +
> #endif /* _TRACE_ARM_ARM64_KVM_H */
>
> #undef TRACE_INCLUDE_PATH
It looks good to me, please feel free to add.
Reviewed-by: Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>
Thanks,
Ganapat
next prev parent reply other threads:[~2021-12-20 6:57 UTC|newest]
Thread overview: 139+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-29 20:00 [PATCH v5 00/69] KVM: arm64: ARMv8.3/8.4 Nested Virtualization support Marc Zyngier
2021-11-29 20:00 ` [PATCH v5 01/69] KVM: arm64: Save PSTATE early on exit Marc Zyngier
2022-01-17 15:36 ` Russell King (Oracle)
2021-11-29 20:00 ` [PATCH v5 02/69] KVM: arm64: Move pkvm's special 32bit handling into a generic infrastructure Marc Zyngier
2022-01-17 15:34 ` Russell King (Oracle)
2021-11-29 20:00 ` [PATCH v5 03/69] KVM: arm64: Add minimal handling for the ARMv8.7 PMU Marc Zyngier
2022-01-17 15:40 ` Russell King (Oracle)
2021-11-29 20:00 ` [PATCH v5 04/69] KVM: arm64: Rework kvm_pgtable initialisation Marc Zyngier
2022-01-17 15:43 ` Russell King (Oracle)
2021-11-29 20:00 ` [PATCH v5 05/69] KVM: arm64: Allow preservation of the S2 SW bits Marc Zyngier
2022-01-13 12:12 ` Alexandru Elisei
2022-01-13 13:14 ` Marc Zyngier
2022-01-17 15:51 ` Russell King (Oracle)
2021-11-29 20:00 ` [PATCH v5 06/69] arm64: Add ARM64_HAS_NESTED_VIRT cpufeature Marc Zyngier
2021-11-29 20:00 ` [PATCH v5 07/69] KVM: arm64: nv: Introduce nested virtualization VCPU feature Marc Zyngier
2021-12-20 6:45 ` Ganapatrao Kulkarni
2022-01-13 14:10 ` Alexandru Elisei
2022-01-13 14:24 ` Marc Zyngier
2022-01-17 16:57 ` Russell King (Oracle)
2021-11-29 20:00 ` [PATCH v5 08/69] KVM: arm64: nv: Reset VCPU to EL2 registers if VCPU nested virt is set Marc Zyngier
2022-01-07 21:54 ` Chase Conklin
2022-01-27 12:42 ` Marc Zyngier
2022-01-17 17:06 ` Russell King (Oracle)
2022-01-27 12:43 ` Marc Zyngier
2021-11-29 20:00 ` [PATCH v5 09/69] KVM: arm64: nv: Allow userspace to set PSR_MODE_EL2x Marc Zyngier
2022-01-17 17:07 ` Russell King (Oracle)
2021-11-29 20:00 ` [PATCH v5 10/69] KVM: arm64: nv: Add EL2 system registers to vcpu context Marc Zyngier
2022-01-17 17:14 ` Russell King (Oracle)
2021-11-29 20:00 ` [PATCH v5 11/69] KVM: arm64: nv: Add nested virt VCPU primitives for vEL2 VCPU state Marc Zyngier
2022-01-14 17:42 ` Alexandru Elisei
2022-01-15 12:19 ` Marc Zyngier
2022-01-17 10:19 ` Alexandru Elisei
2022-01-18 15:45 ` Russell King (Oracle)
2021-11-29 20:00 ` [PATCH v5 12/69] KVM: arm64: nv: Handle HCR_EL2.NV system register traps Marc Zyngier
2022-01-17 11:31 ` Alexandru Elisei
2022-01-26 16:08 ` Marc Zyngier
2022-01-18 15:51 ` Russell King (Oracle)
2022-01-26 16:01 ` Marc Zyngier
2021-11-29 20:00 ` [PATCH v5 13/69] KVM: arm64: nv: Reset VMPIDR_EL2 and VPIDR_EL2 to sane values Marc Zyngier
2022-01-18 15:52 ` Russell King (Oracle)
2021-11-29 20:00 ` [PATCH v5 14/69] KVM: arm64: nv: Support virtual EL2 exceptions Marc Zyngier
2021-12-20 6:57 ` Ganapatrao Kulkarni [this message]
2022-01-18 14:11 ` Alexandru Elisei
2022-01-26 20:11 ` Marc Zyngier
2022-01-18 16:02 ` Russell King (Oracle)
2022-01-26 20:32 ` Marc Zyngier
2022-01-20 13:58 ` Alexandru Elisei
2022-01-27 11:08 ` Marc Zyngier
2021-11-29 20:00 ` [PATCH v5 15/69] KVM: arm64: nv: Inject HVC exceptions to the virtual EL2 Marc Zyngier
2022-01-18 16:04 ` Russell King (Oracle)
2022-01-18 16:35 ` Alexandru Elisei
2021-11-29 20:00 ` [PATCH v5 16/69] KVM: arm64: nv: Handle trapped ERET from " Marc Zyngier
2022-01-18 16:05 ` Russell King (Oracle)
2022-01-18 16:36 ` Alexandru Elisei
2022-01-27 11:50 ` Marc Zyngier
2021-11-29 20:00 ` [PATCH v5 17/69] KVM: arm64: nv: Add non-VHE-EL2->EL1 translation helpers Marc Zyngier
2022-01-20 11:52 ` Alexandru Elisei
2022-01-27 17:22 ` Marc Zyngier
2021-11-29 20:00 ` [PATCH v5 18/69] KVM: arm64: nv: Handle virtual EL2 registers in vcpu_read/write_sys_reg() Marc Zyngier
2021-12-20 7:04 ` Ganapatrao Kulkarni
2021-12-20 9:10 ` Marc Zyngier
2021-12-21 7:12 ` Ganapatrao Kulkarni
2021-12-21 8:39 ` Marc Zyngier
2021-12-21 10:12 ` Ganapatrao Kulkarni
2022-01-20 15:12 ` Alexandru Elisei
2021-11-29 20:01 ` [PATCH v5 19/69] KVM: arm64: nv: Handle SPSR_EL2 specially Marc Zyngier
2022-01-20 16:28 ` Alexandru Elisei
2021-11-29 20:01 ` [PATCH v5 20/69] KVM: arm64: nv: Handle HCR_EL2.E2H specially Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 21/69] KVM: arm64: nv: Save/Restore vEL2 sysregs Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 22/69] KVM: arm64: nv: Emulate PSTATE.M for a guest hypervisor Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 23/69] KVM: arm64: nv: Trap EL1 VM register accesses in virtual EL2 Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 24/69] KVM: arm64: nv: Trap SPSR_EL1, ELR_EL1 and VBAR_EL1 from " Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 25/69] KVM: arm64: nv: Trap CPACR_EL1 access in " Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 26/69] KVM: arm64: nv: Handle PSCI call via smc from the guest Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 27/69] KVM: arm64: nv: Respect virtual HCR_EL2.TWX setting Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 28/69] KVM: arm64: nv: Respect virtual CPTR_EL2.{TFP,FPEN} settings Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 29/69] KVM: arm64: nv: Respect the virtual HCR_EL2.NV bit setting Marc Zyngier
2021-12-20 7:11 ` Ganapatrao Kulkarni
2021-12-20 9:18 ` Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 30/69] KVM: arm64: nv: Respect virtual HCR_EL2.TVM and TRVM settings Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 31/69] KVM: arm64: nv: Respect the virtual HCR_EL2.NV1 bit setting Marc Zyngier
2021-12-20 7:18 ` Ganapatrao Kulkarni
2021-12-20 9:39 ` Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 32/69] KVM: arm64: nv: Emulate EL12 register accesses from the virtual EL2 Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 33/69] KVM: arm64: nv: Forward debug traps to the nested guest Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 34/69] KVM: arm64: nv: Configure HCR_EL2 for nested virtualization Marc Zyngier
2022-01-04 8:53 ` Ganapatrao Kulkarni
2022-01-04 9:39 ` Marc Zyngier
2022-01-04 9:53 ` Ganapatrao Kulkarni
2021-11-29 20:01 ` [PATCH v5 35/69] KVM: arm64: nv: Only toggle cache for virtual EL2 when SCTLR_EL2 changes Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 36/69] KVM: arm64: nv: Filter out unsupported features from ID regs Marc Zyngier
2021-12-20 7:26 ` Ganapatrao Kulkarni
2021-12-20 9:56 ` Marc Zyngier
2021-12-21 6:03 ` Ganapatrao Kulkarni
2021-12-21 9:10 ` Marc Zyngier
2021-12-21 10:07 ` Ganapatrao Kulkarni
2022-01-21 11:33 ` Ganapatrao Kulkarni
2022-01-27 13:04 ` Marc Zyngier
2022-01-04 10:24 ` Ganapatrao Kulkarni
2021-11-29 20:01 ` [PATCH v5 37/69] KVM: arm64: nv: Hide RAS from nested guests Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 38/69] KVM: arm64: nv: Support multiple nested Stage-2 mmu structures Marc Zyngier
2022-01-18 11:24 ` Ganapatrao Kulkarni
2022-01-27 11:50 ` Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 39/69] KVM: arm64: nv: Implement nested Stage-2 page table walk logic Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 40/69] KVM: arm64: nv: Handle shadow stage 2 page faults Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 41/69] KVM: arm64: nv: Restrict S2 RD/WR permissions to match the guest's Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 42/69] KVM: arm64: nv: Unmap/flush shadow stage 2 page tables Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 43/69] KVM: arm64: nv: Introduce sys_reg_desc.forward_trap Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 44/69] KVM: arm64: nv: Set a handler for the system instruction traps Marc Zyngier
2022-01-18 11:29 ` Ganapatrao Kulkarni
2021-11-29 20:01 ` [PATCH v5 45/69] KVM: arm64: nv: Trap and emulate AT instructions from virtual EL2 Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 46/69] KVM: arm64: nv: Trap and emulate TLBI " Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 47/69] KVM: arm64: nv: Fold guest's HCR_EL2 configuration into the host's Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 48/69] KVM: arm64: nv: arch_timer: Support hyp timer emulation Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 49/69] KVM: arm64: nv: Add handling of EL2-specific timer registers Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 50/69] KVM: arm64: nv: Load timer before the GIC Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 51/69] KVM: arm64: nv: Nested GICv3 Support Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 52/69] KVM: arm64: nv: Don't load the GICv4 context on entering a nested guest Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 53/69] KVM: arm64: nv: vgic: Emulate the HW bit in software Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 54/69] KVM: arm64: nv: vgic: Allow userland to set VGIC maintenance IRQ Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 55/69] KVM: arm64: nv: Implement maintenance interrupt forwarding Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 56/69] KVM: arm64: nv: Add nested GICv3 tracepoints Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 57/69] KVM: arm64: nv: Allow userspace to request KVM_ARM_VCPU_NESTED_VIRT Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 58/69] KVM: arm64: nv: Add handling of ARMv8.4-TTL TLB invalidation Marc Zyngier
2022-01-18 11:35 ` Ganapatrao Kulkarni
2021-11-29 20:01 ` [PATCH v5 59/69] KVM: arm64: nv: Invalidate TLBs based on shadow S2 TTL-like information Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 60/69] KVM: arm64: nv: Tag shadow S2 entries with nested level Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 61/69] KVM: arm64: nv: Add include containing the VNCR_EL2 offsets Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 62/69] KVM: arm64: nv: Map VNCR-capable registers to a separate page Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 63/69] KVM: arm64: nv: Move nested vgic state into the sysreg file Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 64/69] KVM: arm64: Add ARMv8.4 Enhanced Nested Virt cpufeature Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 65/69] KVM: arm64: nv: Sync nested timer state with ARMv8.4 Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 66/69] KVM: arm64: nv: Allocate VNCR page when required Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 67/69] KVM: arm64: nv: Enable ARMv8.4-NV support Marc Zyngier
2022-01-18 11:50 ` Ganapatrao Kulkarni
2022-01-27 11:48 ` Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 68/69] KVM: arm64: nv: Fast-track 'InHost' exception returns Marc Zyngier
2021-11-29 20:01 ` [PATCH v5 69/69] KVM: arm64: nv: Fast-track EL1 TLBIs for VHE guests Marc Zyngier
2021-12-16 17:19 ` (subset) [PATCH v5 00/69] KVM: arm64: ARMv8.3/8.4 Nested Virtualization support Marc Zyngier
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