From: Paolo Bonzini <pbonzini@redhat.com>
To: Anup Patel <Anup.Patel@wdc.com>,
Palmer Dabbelt <palmer@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Radim K <rkrcmar@redhat.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Alexander Graf <graf@amazon.com>,
Atish Patra <Atish.Patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Damien Le Moal <Damien.LeMoal@wdc.com>,
Christoph Hellwig <hch@infradead.org>,
Anup Patel <anup@brainfault.org>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v9 19/22] RISC-V: KVM: Remove per-CPU vsip_shadow variable
Date: Mon, 21 Oct 2019 19:28:48 +0200 [thread overview]
Message-ID: <7381057d-a3f3-e79a-bb2c-b078fc918b1f@redhat.com> (raw)
In-Reply-To: <20191016160649.24622-20-anup.patel@wdc.com>
On 16/10/19 18:12, Anup Patel wrote:
> Currently, we track last value wrote to VSIP CSR using per-CPU
> vsip_shadow variable but this easily goes out-of-sync because
> Guest can update VSIP.SSIP bit directly.
>
> To simplify things, we remove per-CPU vsip_shadow variable and
> unconditionally write vcpu->arch.guest_csr.vsip to VSIP CSR in
> run-loop.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
Please squash this and patch 20 into the corresponding patches earlier
in the series.
Paolo
> ---
> arch/riscv/include/asm/kvm_host.h | 3 ---
> arch/riscv/kvm/main.c | 6 ------
> arch/riscv/kvm/vcpu.c | 24 +-----------------------
> 3 files changed, 1 insertion(+), 32 deletions(-)
>
> diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
> index ec1ca4bc98f2..cd86acaed055 100644
> --- a/arch/riscv/include/asm/kvm_host.h
> +++ b/arch/riscv/include/asm/kvm_host.h
> @@ -202,9 +202,6 @@ static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
> static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
> static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
>
> -int kvm_riscv_setup_vsip(void);
> -void kvm_riscv_cleanup_vsip(void);
> -
> #define KVM_ARCH_WANT_MMU_NOTIFIER
> int kvm_unmap_hva_range(struct kvm *kvm,
> unsigned long start, unsigned long end);
> diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c
> index 55df85184241..002301a27d29 100644
> --- a/arch/riscv/kvm/main.c
> +++ b/arch/riscv/kvm/main.c
> @@ -61,17 +61,11 @@ void kvm_arch_hardware_disable(void)
>
> int kvm_arch_init(void *opaque)
> {
> - int ret;
> -
> if (!riscv_isa_extension_available(NULL, h)) {
> kvm_info("hypervisor extension not available\n");
> return -ENODEV;
> }
>
> - ret = kvm_riscv_setup_vsip();
> - if (ret)
> - return ret;
> -
> kvm_riscv_stage2_vmid_detect();
>
> kvm_info("hypervisor extension available\n");
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index fd77cd39dd8c..f1a218d3a8cf 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -111,8 +111,6 @@ static void kvm_riscv_vcpu_host_fp_restore(struct kvm_cpu_context *cntx) {}
> riscv_isa_extension_mask(s) | \
> riscv_isa_extension_mask(u))
>
> -static unsigned long __percpu *vsip_shadow;
> -
> static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu)
> {
> struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
> @@ -765,7 +763,6 @@ int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
> void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
> {
> struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
> - unsigned long *vsip = raw_cpu_ptr(vsip_shadow);
>
> csr_write(CSR_VSSTATUS, csr->vsstatus);
> csr_write(CSR_VSIE, csr->vsie);
> @@ -775,7 +772,6 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
> csr_write(CSR_VSCAUSE, csr->vscause);
> csr_write(CSR_VSTVAL, csr->vstval);
> csr_write(CSR_VSIP, csr->vsip);
> - *vsip = csr->vsip;
> csr_write(CSR_VSATP, csr->vsatp);
>
> kvm_riscv_stage2_update_hgatp(vcpu);
> @@ -843,26 +839,8 @@ static void kvm_riscv_check_vcpu_requests(struct kvm_vcpu *vcpu)
> static void kvm_riscv_update_vsip(struct kvm_vcpu *vcpu)
> {
> struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
> - unsigned long *vsip = raw_cpu_ptr(vsip_shadow);
> -
> - if (*vsip != csr->vsip) {
> - csr_write(CSR_VSIP, csr->vsip);
> - *vsip = csr->vsip;
> - }
> -}
> -
> -int kvm_riscv_setup_vsip(void)
> -{
> - vsip_shadow = alloc_percpu(unsigned long);
> - if (!vsip_shadow)
> - return -ENOMEM;
>
> - return 0;
> -}
> -
> -void kvm_riscv_cleanup_vsip(void)
> -{
> - free_percpu(vsip_shadow);
> + csr_write(CSR_VSIP, csr->vsip);
> }
>
> int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
>
next prev parent reply other threads:[~2019-10-21 17:29 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-16 16:08 [PATCH v9 00/22] KVM RISC-V Support Anup Patel
2019-10-16 16:08 ` [PATCH v9 01/22] RISC-V: Add bitmap reprensenting ISA features common across CPUs Anup Patel
2019-10-17 8:48 ` Anup Patel
2019-10-25 23:30 ` Paul Walmsley
2019-10-16 16:08 ` [PATCH v9 02/22] RISC-V: Add hypervisor extension related CSR defines Anup Patel
2019-10-16 16:08 ` [PATCH v9 03/22] RISC-V: Add initial skeletal KVM support Anup Patel
2019-11-20 8:04 ` Paul Walmsley
2019-10-16 16:08 ` [PATCH v9 04/22] RISC-V: KVM: Implement VCPU create, init and destroy functions Anup Patel
2019-10-16 16:09 ` [PATCH v9 05/22] RISC-V: KVM: Implement VCPU interrupts and requests handling Anup Patel
2019-10-16 16:09 ` [PATCH v9 06/22] RISC-V: KVM: Implement KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls Anup Patel
2019-10-16 16:09 ` [PATCH v9 07/22] RISC-V: KVM: Implement VCPU world-switch Anup Patel
2019-10-16 16:09 ` [PATCH v9 08/22] RISC-V: KVM: Handle MMIO exits for VCPU Anup Patel
2019-10-16 16:10 ` [PATCH v9 09/22] RISC-V: KVM: Handle WFI " Anup Patel
2019-10-16 16:10 ` [PATCH v9 10/22] RISC-V: KVM: Implement VMID allocator Anup Patel
2019-10-16 16:10 ` [PATCH v9 11/22] RISC-V: KVM: Implement stage2 page table programming Anup Patel
2019-10-16 16:10 ` [PATCH v9 12/22] RISC-V: KVM: Implement MMU notifiers Anup Patel
2019-10-16 16:10 ` [PATCH v9 13/22] RISC-V: KVM: Add timer functionality Anup Patel
2019-12-04 16:08 ` Daniel Lezcano
2019-10-16 16:10 ` [PATCH v9 14/22] RISC-V: KVM: FP lazy save/restore Anup Patel
2019-10-16 16:11 ` [PATCH v9 15/22] RISC-V: KVM: Implement ONE REG interface for FP registers Anup Patel
2019-10-16 16:11 ` [PATCH v9 16/22] RISC-V: KVM: Add SBI v0.1 support Anup Patel
2019-10-16 16:11 ` [PATCH v9 17/22] RISC-V: KVM: Forward unhandled SBI calls to userspace Anup Patel
2019-10-16 16:11 ` [PATCH v9 18/22] RISC-V: KVM: Simplify stage2 page table programming Anup Patel
2019-10-21 17:31 ` Paolo Bonzini
2019-10-22 5:12 ` Anup Patel
2019-10-16 16:12 ` [PATCH v9 19/22] RISC-V: KVM: Remove per-CPU vsip_shadow variable Anup Patel
2019-10-21 17:28 ` Paolo Bonzini [this message]
2019-10-22 5:09 ` Anup Patel
2019-10-16 16:12 ` [PATCH v9 20/22] RISC-V: KVM: Fix race-condition in kvm_riscv_vcpu_sync_interrupts() Anup Patel
2019-10-21 17:27 ` Paolo Bonzini
2019-10-22 5:07 ` Anup Patel
2019-10-16 16:12 ` [PATCH v9 21/22] RISC-V: KVM: Document RISC-V specific parts of KVM API Anup Patel
2019-10-16 16:12 ` [PATCH v9 22/22] RISC-V: KVM: Add MAINTAINERS entry Anup Patel
2019-10-25 23:10 ` [PATCH v9 00/22] KVM RISC-V Support Paul Walmsley
2019-10-26 3:22 ` Anup Patel
2019-10-26 5:33 ` Christoph Hellwig
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=7381057d-a3f3-e79a-bb2c-b078fc918b1f@redhat.com \
--to=pbonzini@redhat.com \
--cc=Alistair.Francis@wdc.com \
--cc=Anup.Patel@wdc.com \
--cc=Atish.Patra@wdc.com \
--cc=Damien.LeMoal@wdc.com \
--cc=anup@brainfault.org \
--cc=daniel.lezcano@linaro.org \
--cc=graf@amazon.com \
--cc=hch@infradead.org \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@sifive.com \
--cc=paul.walmsley@sifive.com \
--cc=rkrcmar@redhat.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).