* [PATCH v18 0/6] Add ARMv8 RAS virtualization support in QEMU
@ 2019-09-06 8:31 Xiang Zheng
2019-09-06 8:31 ` [PATCH v18 1/6] hw/arm/virt: Introduce RAS platform version and RAS machine option Xiang Zheng
` (7 more replies)
0 siblings, 8 replies; 26+ messages in thread
From: Xiang Zheng @ 2019-09-06 8:31 UTC (permalink / raw)
To: pbonzini, mst, imammedo, shannon.zhaosl, peter.maydell, lersek,
james.morse, gengdongjiu, mtosatti, rth, ehabkost,
jonathan.cameron, xuwei5, kvm, qemu-devel, qemu-arm, linuxarm
Cc: zhengxiang9, wanghaibin.wang
In the ARMv8 platform, the CPU error types are synchronous external abort(SEA)
and SError Interrupt (SEI). If exception happens in guest, sometimes it's better
for guest to perform the recovery, because host does not know the detailed
information of guest. For example, if an exception happens in a user-space
application within guest, host does not know which application encounters
errors.
For the ARMv8 SEA/SEI, KVM or host kernel delivers SIGBUS to notify userspace.
After user space gets the notification, it will record the CPER into guest GHES
buffer and inject an exception or IRQ into guest.
In the current implementation, if the type of SIGBUS is BUS_MCEERR_AR, we will
treat it as a synchronous exception, and notify guest with ARMv8 SEA
notification type after recording CPER into guest.
This series of patches are based on Qemu 4.1, which include two parts:
1. Generate APEI/GHES table.
2. Handle the SIGBUS signal, record the CPER in runtime and fill it into guest
memory, then notify guest according to the type of SIGBUS.
The whole solution was suggested by James(james.morse@arm.com); The solution of
APEI section was suggested by Laszlo(lersek@redhat.com).
Show some discussions in [1].
This series of patches have already been tested on ARM64 platform with RAS
feature enabled:
Show the APEI part verification result in [2].
Show the BUS_MCEERR_AR SIGBUS handling verification result in [3].
---
Since Dongjiu is too busy to do this work, I will finish the rest work on behalf
of him.
---
Change since v17:
1. Improve some commit messages and comments.
2. Fix some code-style problems.
3. Add a *ras* machine option.
4. Move HEST/GHES related structures and macros into "hw/acpi/acpi_ghes.*".
5. Move HWPoison page functions into "include/sysemu/kvm_int.h".
6. Fix some bugs.
7. Improve the design document.
Change since v16:
1. check whether ACPI table is enabled when handling the memory error in the SIGBUS handler.
Change since v15:
1. Add a doc-comment in the proper format for 'include/exec/ram_addr.h'
2. Remove write_part_cpustate_to_list() because there is another bug fix patch
has been merged "arm: Allow system registers for KVM guests to be changed by QEMU code"
3. Add some comments for kvm_inject_arm_sea() in 'target/arm/kvm64.c'
4. Compare the arm_current_el() return value to 0,1,2,3, not to PSTATE_MODE_* constants.
5. Change the RAS support wasn't introduced before 4.1 QEMU version.
6. Move the no_ras flag patch to begin in this series
Change since v14:
1. Remove the BUS_MCEERR_AO handling logic because this asynchronous signal was masked by main thread
2. Address some Igor Mammedov's comments(ACPI part)
1) change the comments for the enum AcpiHestNotifyType definition and remove ditto in patch 1
2) change some patch commit messages and separate "APEI GHES table generation" patch to more patches.
3. Address some peter's comments(arm64 Synchronous External Abort injection)
1) change some code notes
2) using arm_current_el() for current EL
2) use the helper functions for those (syn_data_abort_*).
Change since v13:
1. Move the patches that set guest ESR and inject virtual SError out of this series
2. Clean and optimize the APEI part patches
3. Update the commit messages and add some comments for the code
Change since v12:
1. Address Paolo's comments to move HWPoisonPage definition to accel/kvm/kvm-all.c
2. Only call kvm_cpu_synchronize_state() when get the BUS_MCEERR_AR signal
3. Only add and enable GPIO-Signal and ARMv8 SEA two hardware error sources
4. Address Michael's comments to not sync SPDX from Linux kernel header file
Change since v11:
Address James's comments(james.morse@arm.com)
1. Check whether KVM has the capability to to set ESR instead of detecting host CPU RAS capability
2. For SIGBUS_MCEERR_AR SIGBUS, use Synchronous-External-Abort(SEA) notification type
for SIGBUS_MCEERR_AO SIGBUS, use GPIO-Signal notification
Address Shannon's comments(for ACPI part):
1. Unify hest_ghes.c and hest_ghes.h license declaration
2. Remove unnecessary including "qmp-commands.h" in hest_ghes.c
3. Unconditionally add guest APEI table based on James's comments(james.morse@arm.com)
4. Add a option to virt machine for migration compatibility. On new virt machine it's on
by default while off for old ones, we enabled it since 2.12
5. Refer to the ACPI spec version which introduces Hardware Error Notification first time
6. Add ACPI_HEST_NOTIFY_RESERVED notification type
Address Igor's comments(for ACPI part):
1. Add doc patch first which will describe how it's supposed to work between QEMU/firmware/guest
OS with expected flows.
2. Move APEI diagrams into doc/spec patch
3. Remove redundant g_malloc in ghes_record_cper()
4. Use build_append_int_noprefix() API to compose whole error status block and whole APEI table,
and try to get rid of most structures in patch 1, as they will be left unused after that
5. Reuse something like https://github.com/imammedo/qemu/commit/3d2fd6d13a3ea298d2ee814835495ce6241d085c
to build GAS
6. Remove much offsetof() in the function
7. Build independent tables first and only then build dependent tables passing to it pointers
to previously build table if necessary.
8. Redefine macro GHES_ACPI_HEST_NOTIFY_RESERVED to ACPI_HEST_ERROR_SOURCE_COUNT to avoid confusion
Address Peter Maydell's comments
1. linux-headers is done as a patch of their own created using scripts/update-linux-headers.sh run against a
mainline kernel tree
2. Tested whether this patchset builds OK on aarch32
3. Abstract Hwpoison page adding code out properly into a cpu-independent source file from target/i386/kvm.c,
such as kvm-all.c
4. Add doc-comment formatted documentation comment for new globally-visible function prototype in a header
---
[1]:
https://lkml.org/lkml/2017/2/27/246
https://patchwork.kernel.org/patch/9633105/
https://patchwork.kernel.org/patch/9925227/
[2]:
Note: the UEFI(QEMU_EFI.fd) is needed if guest want to use ACPI table.
After guest boot up, dump the APEI table, then can see the initialized table
(1) # iasl -p ./HEST -d /sys/firmware/acpi/tables/HEST
(2) # cat HEST.dsl
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20170728 (64-bit version)
* Copyright (c) 2000 - 2017 Intel Corporation
*
* Disassembly of /sys/firmware/acpi/tables/HEST, Mon Sep 5 07:59:17 2016
*
* ACPI Data Table [HEST]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
..................................................................................
[308h 0776 2] Subtable Type : 000A [Generic Hardware Error Source V2]
[30Ah 0778 2] Source Id : 0001
[30Ch 0780 2] Related Source Id : FFFF
[30Eh 0782 1] Reserved : 00
[30Fh 0783 1] Enabled : 01
[310h 0784 4] Records To Preallocate : 00000001
[314h 0788 4] Max Sections Per Record : 00000001
[318h 0792 4] Max Raw Data Length : 00001000
[31Ch 0796 12] Error Status Address : [Generic Address Structure]
[31Ch 0796 1] Space ID : 00 [SystemMemory]
[31Dh 0797 1] Bit Width : 40
[31Eh 0798 1] Bit Offset : 00
[31Fh 0799 1] Encoded Access Width : 04 [QWord Access:64]
[320h 0800 8] Address : 00000000785D0040
[328h 0808 28] Notify : [Hardware Error Notification Structure]
[328h 0808 1] Notify Type : 08 [SEA]
[329h 0809 1] Notify Length : 1C
[32Ah 0810 2] Configuration Write Enable : 0000
[32Ch 0812 4] PollInterval : 00000000
[330h 0816 4] Vector : 00000000
[334h 0820 4] Polling Threshold Value : 00000000
[338h 0824 4] Polling Threshold Window : 00000000
[33Ch 0828 4] Error Threshold Value : 00000000
[340h 0832 4] Error Threshold Window : 00000000
[344h 0836 4] Error Status Block Length : 00001000
[348h 0840 12] Read Ack Register : [Generic Address Structure]
[348h 0840 1] Space ID : 00 [SystemMemory]
[349h 0841 1] Bit Width : 40
[34Ah 0842 1] Bit Offset : 00
[34Bh 0843 1] Encoded Access Width : 04 [QWord Access:64]
[34Ch 0844 8] Address : 00000000785D0098
[354h 0852 8] Read Ack Preserve : 00000000FFFFFFFE
[35Ch 0860 8] Read Ack Write : 0000000000000001
.....................................................................................
(3) After a synchronous external abort(SEA) happen, Qemu receive a SIGBUS and
filled the CPER into guest GHES memory. For example, according to above table,
the address that contains the physical address of a block of memory that holds
the error status data for this abort is 0x00000000785D0040
(4) the address for SEA notification error source is 0x785d80b0
(qemu) xp /1 0x00000000785D0040
00000000785d0040: 0x785d80b0
(5) check the content of generic error status block and generic error data entry
(qemu) xp /100x 0x785d80b0
00000000785d80b0: 0x00000001 0x00000000 0x00000000 0x00000098
00000000785d80c0: 0x00000000 0xa5bc1114 0x4ede6f64 0x833e63b8
00000000785d80d0: 0xb1837ced 0x00000000 0x00000300 0x00000050
00000000785d80e0: 0x00000000 0x00000000 0x00000000 0x00000000
00000000785d80f0: 0x00000000 0x00000000 0x00000000 0x00000000
00000000785d8100: 0x00000000 0x00000000 0x00000000 0x00004002
(6) check the OSPM's ACK value(for example SEA)
/* Before OSPM acknowledges the error, check the ACK value */
(qemu) xp /1 0x00000000785D0098
00000000785d00f0: 0x00000000
/* After OSPM acknowledges the error, check the ACK value, it change to 1 from 0 */
(qemu) xp /1 0x00000000785D0098
00000000785d00f0: 0x00000001
[3]: KVM deliver "BUS_MCEERR_AR" to Qemu, Qemu record the guest CPER and inject
synchronous external abort to notify guest, then guest do the recovery.
[ 1552.516170] Synchronous External Abort: synchronous external abort (0x92000410) at 0x000000003751c6b4
[ 1553.074073] {1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 8
[ 1553.081654] {1}[Hardware Error]: event severity: recoverable
[ 1554.034191] {1}[Hardware Error]: Error 0, type: recoverable
[ 1554.037934] {1}[Hardware Error]: section_type: memory error
[ 1554.513261] {1}[Hardware Error]: physical_address: 0x0000000040fa6000
[ 1554.513944] {1}[Hardware Error]: error_type: 0, unknown
[ 1555.041451] Memory failure: 0x40fa6: Killing mca-recover:1296 due to hardware memory corruption
[ 1555.373116] Memory failure: 0x40fa6: recovery action for dirty LRU page: Recovered
Dongjiu Geng (6):
hw/arm/virt: Introduce RAS platform version and RAS machine option
docs: APEI GHES generation and CPER record description
ACPI: Add APEI GHES table generation support
KVM: Move hwpoison page related functions into
include/sysemu/kvm_int.h
target-arm: kvm64: inject synchronous External Abort
target-arm: kvm64: handle SIGBUS signal from kernel or KVM
accel/kvm/kvm-all.c | 33 +++
default-configs/arm-softmmu.mak | 1 +
docs/specs/acpi_hest_ghes.txt | 88 ++++++
hw/acpi/Kconfig | 4 +
hw/acpi/Makefile.objs | 1 +
hw/acpi/acpi_ghes.c | 462 ++++++++++++++++++++++++++++++++
hw/acpi/aml-build.c | 2 +
hw/arm/virt-acpi-build.c | 12 +
hw/arm/virt.c | 33 +++
include/hw/acpi/acpi_ghes.h | 143 ++++++++++
include/hw/acpi/aml-build.h | 1 +
include/hw/arm/virt.h | 2 +
include/sysemu/kvm.h | 2 +-
include/sysemu/kvm_int.h | 23 ++
target/arm/helper.c | 2 +-
target/arm/internals.h | 5 +-
target/arm/kvm.c | 3 +
target/arm/kvm64.c | 73 +++++
target/arm/tlb_helper.c | 2 +-
target/i386/kvm.c | 34 ---
20 files changed, 887 insertions(+), 39 deletions(-)
create mode 100644 docs/specs/acpi_hest_ghes.txt
create mode 100644 hw/acpi/acpi_ghes.c
create mode 100644 include/hw/acpi/acpi_ghes.h
--
2.19.1
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v18 1/6] hw/arm/virt: Introduce RAS platform version and RAS machine option
2019-09-06 8:31 [PATCH v18 0/6] Add ARMv8 RAS virtualization support in QEMU Xiang Zheng
@ 2019-09-06 8:31 ` Xiang Zheng
2019-09-27 14:02 ` Peter Maydell
2019-09-06 8:31 ` [PATCH v18 2/6] docs: APEI GHES generation and CPER record description Xiang Zheng
` (6 subsequent siblings)
7 siblings, 1 reply; 26+ messages in thread
From: Xiang Zheng @ 2019-09-06 8:31 UTC (permalink / raw)
To: pbonzini, mst, imammedo, shannon.zhaosl, peter.maydell, lersek,
james.morse, gengdongjiu, mtosatti, rth, ehabkost,
jonathan.cameron, xuwei5, kvm, qemu-devel, qemu-arm, linuxarm
Cc: zhengxiang9, wanghaibin.wang
From: Dongjiu Geng <gengdongjiu@huawei.com>
Support RAS Virtualization feature since version 4.2, disable it by
default in the old versions. Also add a machine option which allows user
to enable it explicitly.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
---
hw/arm/virt.c | 33 +++++++++++++++++++++++++++++++++
include/hw/arm/virt.h | 2 ++
2 files changed, 35 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index d74538b021..e0451433c8 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1783,6 +1783,20 @@ static void virt_set_its(Object *obj, bool value, Error **errp)
vms->its = value;
}
+static bool virt_get_ras(Object *obj, Error **errp)
+{
+ VirtMachineState *vms = VIRT_MACHINE(obj);
+
+ return vms->ras;
+}
+
+static void virt_set_ras(Object *obj, bool value, Error **errp)
+{
+ VirtMachineState *vms = VIRT_MACHINE(obj);
+
+ vms->ras = value;
+}
+
static char *virt_get_gic_version(Object *obj, Error **errp)
{
VirtMachineState *vms = VIRT_MACHINE(obj);
@@ -2026,6 +2040,19 @@ static void virt_instance_init(Object *obj)
"Valid values are none and smmuv3",
NULL);
+ if (vmc->no_ras) {
+ vms->ras = false;
+ } else {
+ /* Default disallows RAS instantiation */
+ vms->ras = false;
+ object_property_add_bool(obj, "ras", virt_get_ras,
+ virt_set_ras, NULL);
+ object_property_set_description(obj, "ras",
+ "Set on/off to enable/disable "
+ "RAS instantiation",
+ NULL);
+ }
+
vms->irqmap = a15irqmap;
virt_flash_create(vms);
@@ -2058,8 +2085,14 @@ DEFINE_VIRT_MACHINE_AS_LATEST(4, 2)
static void virt_machine_4_1_options(MachineClass *mc)
{
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
+
virt_machine_4_2_options(mc);
compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
+ /* Disable memory recovery feature for 4.1 as RAS support was
+ * introduced with 4.2.
+ */
+ vmc->no_ras = true;
}
DEFINE_VIRT_MACHINE(4, 1)
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index a72094204e..04ab42ca42 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -103,6 +103,7 @@ typedef struct {
bool disallow_affinity_adjustment;
bool no_its;
bool no_pmu;
+ bool no_ras;
bool claim_edge_triggered_timers;
bool smbios_old_sys_ver;
bool no_highmem_ecam;
@@ -119,6 +120,7 @@ typedef struct {
bool highmem_ecam;
bool its;
bool virt;
+ bool ras;
int32_t gic_version;
VirtIOMMUType iommu;
struct arm_boot_info bootinfo;
--
2.19.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v18 2/6] docs: APEI GHES generation and CPER record description
2019-09-06 8:31 [PATCH v18 0/6] Add ARMv8 RAS virtualization support in QEMU Xiang Zheng
2019-09-06 8:31 ` [PATCH v18 1/6] hw/arm/virt: Introduce RAS platform version and RAS machine option Xiang Zheng
@ 2019-09-06 8:31 ` Xiang Zheng
2019-09-19 13:25 ` Peter Maydell
2019-10-04 8:20 ` [Qemu-devel] " Igor Mammedov
2019-09-06 8:31 ` [PATCH v18 3/6] ACPI: Add APEI GHES table generation support Xiang Zheng
` (5 subsequent siblings)
7 siblings, 2 replies; 26+ messages in thread
From: Xiang Zheng @ 2019-09-06 8:31 UTC (permalink / raw)
To: pbonzini, mst, imammedo, shannon.zhaosl, peter.maydell, lersek,
james.morse, gengdongjiu, mtosatti, rth, ehabkost,
jonathan.cameron, xuwei5, kvm, qemu-devel, qemu-arm, linuxarm
Cc: zhengxiang9, wanghaibin.wang
From: Dongjiu Geng <gengdongjiu@huawei.com>
Add APEI/GHES detailed design document
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
---
docs/specs/acpi_hest_ghes.txt | 88 +++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
create mode 100644 docs/specs/acpi_hest_ghes.txt
diff --git a/docs/specs/acpi_hest_ghes.txt b/docs/specs/acpi_hest_ghes.txt
new file mode 100644
index 0000000000..690d4b2bd0
--- /dev/null
+++ b/docs/specs/acpi_hest_ghes.txt
@@ -0,0 +1,88 @@
+APEI tables generating and CPER record
+=============================
+
+Copyright (C) 2019 Huawei Corporation.
+
+Design Details:
+-------------------
+
+ etc/acpi/tables etc/hardware_errors
+ ==================== ==========================================
++ +--------------------------+ +-----------------------+
+| | HEST | | address | +--------------+
+| +--------------------------+ | registers | | Error Status |
+| | GHES1 | | +---------------------+ | Data Block 1 |
+| +--------------------------+ +--------->| |error_block_address1 |----------->| +------------+
+| | ................. | | | +---------------------+ | | CPER |
+| | error_status_address-----+-+ +------->| |error_block_address2 |--------+ | | CPER |
+| | ................. | | | +---------------------+ | | | .... |
+| | read_ack_register--------+-+ | | | .............. | | | | CPER |
+| | read_ack_preserve | | | +-----------------------+ | | +------------+
+| | read_ack_write | | | +----->| |error_block_addressN |------+ | | Error Status |
++ +--------------------------+ | | | | +---------------------+ | | | Data Block 2 |
+| | GHES2 | +-+-+----->| |read_ack_register1 | | +-->| +------------+
++ +--------------------------+ | | | +---------------------+ | | | CPER |
+| | ................. | | | +--->| |read_ack_register2 | | | | CPER |
+| | error_status_address-----+---+ | | | +---------------------+ | | | .... |
+| | ................. | | | | | ............. | | | | CPER |
+| | read_ack_register--------+-----+-+ | +---------------------+ | +-+------------+
+| | read_ack_preserve | | +->| |read_ack_registerN | | | |.......... |
+| | read_ack_write | | | | +---------------------+ | | +------------+
++ +--------------------------| | | | | Error Status |
+| | ............... | | | | | Data Block N |
++ +--------------------------+ | | +---->| +------------+
+| | GHESN | | | | | CPER |
++ +--------------------------+ | | | | CPER |
+| | ................. | | | | | .... |
+| | error_status_address-----+-----+ | | | CPER |
+| | ................. | | +-+------------+
+| | read_ack_register--------+---------+
+| | read_ack_preserve |
+| | read_ack_write |
++ +--------------------------+
+
+(1) QEMU generates the ACPI HEST table. This table goes in the current
+ "etc/acpi/tables" fw_cfg blob. Each error source has different
+ notification types.
+
+(2) A new fw_cfg blob called "etc/hardware_errors" is introduced. QEMU
+ also need to populate this blob. The "etc/hardwre_errors" fw_cfg blob
+ contains an address registers table and an Error Status Data Block table.
+
+(3) The address registers table contains N Error Block Address entries
+ and N Read Ack Register entries, the size for each entry is 8-byte.
+ The Error Status Data Block table contains N Error Status Data Block
+ entries, the size for each entry is 4096(0x1000) bytes. The total size
+ for "etc/hardware_errors" fw_cfg blob is (N * 8 * 2 + N * 4096) bytes.
+ N is the kinds of hardware error sources.
+
+(4) QEMU generates the ACPI linker/loader script for the firmware, the
+ firmware pre-allocates memory for "etc/acpi/tables", "etc/hardware_errors"
+ and copies blobs content there.
+
+(5) QEMU generates N ADD_POINTER commands, which patch address in the
+ "error_status_address" fields of the HEST table with a pointer to the
+ corresponding "address registers" in "etc/hardware_errors" blob.
+
+(6) QEMU generates N ADD_POINTER commands, which patch address in the
+ "read_ack_register" fields of the HEST table with a pointer to the
+ corresponding "address registers" in "etc/hardware_errors" blob.
+
+(7) QEMU generates N ADD_POINTER commands for the firmware, which patch
+ address in the " error_block_address" fields with a pointer to the
+ respective "Error Status Data Block" in "etc/hardware_errors" blob.
+
+(8) QEMU defines a third and write-only fw_cfg blob which is called
+ "etc/hardware_errors_addr". Through that blob, the firmware can send back
+ the guest-side allocation addresses to QEMU. The "etc/hardware_errors_addr"
+ blob contains a 8-byte entry. QEMU generates a single WRITE_POINTER commands
+ for the firmware, the firmware will write back the start address of
+ "etc/hardware_errors" blob to fw_cfg file "etc/hardware_errors_addr".
+
+(9) When QEMU gets SIGBUS from the kernel, QEMU formats the CPER right into
+ guest memory, and then injects whatever interrupt (or assert whatever GPIO
+ line) as a notification which is necessary for notifying the guest.
+
+(10) This notification (in virtual hardware) will be handled by guest kernel,
+ guest APEI driver will read the CPER which is recorded by QEMU and do the
+ recovery.
--
2.19.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v18 3/6] ACPI: Add APEI GHES table generation support
2019-09-06 8:31 [PATCH v18 0/6] Add ARMv8 RAS virtualization support in QEMU Xiang Zheng
2019-09-06 8:31 ` [PATCH v18 1/6] hw/arm/virt: Introduce RAS platform version and RAS machine option Xiang Zheng
2019-09-06 8:31 ` [PATCH v18 2/6] docs: APEI GHES generation and CPER record description Xiang Zheng
@ 2019-09-06 8:31 ` Xiang Zheng
2019-09-27 15:43 ` Michael S. Tsirkin
2019-09-06 8:31 ` [PATCH v18 4/6] KVM: Move hwpoison page related functions into include/sysemu/kvm_int.h Xiang Zheng
` (4 subsequent siblings)
7 siblings, 1 reply; 26+ messages in thread
From: Xiang Zheng @ 2019-09-06 8:31 UTC (permalink / raw)
To: pbonzini, mst, imammedo, shannon.zhaosl, peter.maydell, lersek,
james.morse, gengdongjiu, mtosatti, rth, ehabkost,
jonathan.cameron, xuwei5, kvm, qemu-devel, qemu-arm, linuxarm
Cc: zhengxiang9, wanghaibin.wang
From: Dongjiu Geng <gengdongjiu@huawei.com>
This patch implements APEI GHES Table generation via fw_cfg blobs. Now
it only supports ARMv8 SEA, a type of GHESv2 error source. Afterwards,
we can extend the supported types if needed. For the CPER section,
currently it is memory section because kernel mainly wants userspace to
handle the memory errors.
This patch follows the spec ACPI 6.2 to build the Hardware Error Source
table. For more detailed information, please refer to document:
docs/specs/acpi_hest_ghes.txt
Suggested-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
---
default-configs/arm-softmmu.mak | 1 +
hw/acpi/Kconfig | 4 +
hw/acpi/Makefile.objs | 1 +
hw/acpi/acpi_ghes.c | 210 ++++++++++++++++++++++++++++++++
hw/acpi/aml-build.c | 2 +
hw/arm/virt-acpi-build.c | 12 ++
include/hw/acpi/acpi_ghes.h | 103 ++++++++++++++++
include/hw/acpi/aml-build.h | 1 +
8 files changed, 334 insertions(+)
create mode 100644 hw/acpi/acpi_ghes.c
create mode 100644 include/hw/acpi/acpi_ghes.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 1f2e0e7fde..5722f3130e 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -40,3 +40,4 @@ CONFIG_FSL_IMX25=y
CONFIG_FSL_IMX7=y
CONFIG_FSL_IMX6UL=y
CONFIG_SEMIHOSTING=y
+CONFIG_ACPI_APEI=y
diff --git a/hw/acpi/Kconfig b/hw/acpi/Kconfig
index 7c59cf900b..2c4d0b9826 100644
--- a/hw/acpi/Kconfig
+++ b/hw/acpi/Kconfig
@@ -23,6 +23,10 @@ config ACPI_NVDIMM
bool
depends on ACPI
+config ACPI_APEI
+ bool
+ depends on ACPI
+
config ACPI_PCI
bool
depends on ACPI && PCI
diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs
index 9bb2101e3b..93fd8e8f64 100644
--- a/hw/acpi/Makefile.objs
+++ b/hw/acpi/Makefile.objs
@@ -5,6 +5,7 @@ common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu_hotplug.o
common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o
common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu.o
common-obj-$(CONFIG_ACPI_NVDIMM) += nvdimm.o
+common-obj-$(CONFIG_ACPI_APEI) += acpi_ghes.o
common-obj-$(CONFIG_ACPI_VMGENID) += vmgenid.o
common-obj-$(call lnot,$(CONFIG_ACPI_X86)) += acpi-stub.o
diff --git a/hw/acpi/acpi_ghes.c b/hw/acpi/acpi_ghes.c
new file mode 100644
index 0000000000..20c45179ff
--- /dev/null
+++ b/hw/acpi/acpi_ghes.c
@@ -0,0 +1,210 @@
+/* Support for generating APEI tables and record CPER for Guests
+ *
+ * Copyright (C) 2019 Huawei Corporation.
+ *
+ * Author: Dongjiu Geng <gengdongjiu@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/acpi/acpi.h"
+#include "hw/acpi/aml-build.h"
+#include "hw/acpi/acpi_ghes.h"
+#include "hw/nvram/fw_cfg.h"
+#include "sysemu/sysemu.h"
+#include "qemu/error-report.h"
+
+/* Hardware Error Notification
+ * ACPI 4.0: 17.3.2.7 Hardware Error Notification
+ */
+static void acpi_ghes_build_notify(GArray *table, const uint8_t type,
+ uint8_t length, uint16_t config_write_enable,
+ uint32_t poll_interval, uint32_t vector,
+ uint32_t polling_threshold_value,
+ uint32_t polling_threshold_window,
+ uint32_t error_threshold_value,
+ uint32_t error_threshold_window)
+{
+ /* Type */
+ build_append_int_noprefix(table, type, 1);
+ /* Length */
+ build_append_int_noprefix(table, length, 1);
+ /* Configuration Write Enable */
+ build_append_int_noprefix(table, config_write_enable, 2);
+ /* Poll Interval */
+ build_append_int_noprefix(table, poll_interval, 4);
+ /* Vector */
+ build_append_int_noprefix(table, vector, 4);
+ /* Switch To Polling Threshold Value */
+ build_append_int_noprefix(table, polling_threshold_value, 4);
+ /* Switch To Polling Threshold Window */
+ build_append_int_noprefix(table, polling_threshold_window, 4);
+ /* Error Threshold Value */
+ build_append_int_noprefix(table, error_threshold_value, 4);
+ /* Error Threshold Window */
+ build_append_int_noprefix(table, error_threshold_window, 4);
+}
+
+/* Build table for the hardware error fw_cfg blob */
+void acpi_ghes_build_error_table(GArray *hardware_errors, BIOSLinker *linker)
+{
+ int i, error_status_block_offset;
+
+ /*
+ * | +--------------------------+
+ * | | error_block_address |
+ * | | .......... |
+ * | +--------------------------+
+ * | | read_ack_register |
+ * | | ........... |
+ * | +--------------------------+
+ * | | Error Status Data Block |
+ * | | ........ |
+ * | +--------------------------+
+ */
+
+ /* Build error_block_address */
+ build_append_int_noprefix(hardware_errors, 0,
+ ACPI_GHES_ADDRESS_SIZE * ACPI_GHES_ERROR_SOURCE_COUNT);
+
+ /* Build read_ack_register */
+ for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) {
+ /* Initialize the value of read_ack_register to 1, so GHES can be
+ * writeable in the first time.
+ * ACPI 6.2: 18.3.2.8 Generic Hardware Error Source version 2
+ * (GHESv2 - Type 10)
+ */
+ build_append_int_noprefix(hardware_errors, 1, ACPI_GHES_ADDRESS_SIZE);
+ }
+
+ /* Build Error Status Data Block */
+ build_append_int_noprefix(hardware_errors, 0,
+ ACPI_GHES_MAX_RAW_DATA_LENGTH * ACPI_GHES_ERROR_SOURCE_COUNT);
+
+ /* Allocate guest memory for the hardware error fw_cfg blob */
+ bios_linker_loader_alloc(linker, ACPI_GHES_ERRORS_FW_CFG_FILE,
+ hardware_errors, 1, false);
+
+ /* Generic Error Status Block offset in the hardware error fw_cfg blob */
+ error_status_block_offset = ACPI_GHES_ADDRESS_SIZE * 2 *
+ ACPI_GHES_ERROR_SOURCE_COUNT;
+
+ for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) {
+ /* Patch address of Error Status Data Block into
+ * the error_block_address of hardware_errors fw_cfg blob
+ */
+ bios_linker_loader_add_pointer(linker,
+ ACPI_GHES_ERRORS_FW_CFG_FILE, ACPI_GHES_ADDRESS_SIZE * i,
+ ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE,
+ error_status_block_offset + i * ACPI_GHES_MAX_RAW_DATA_LENGTH);
+ }
+
+ /* Write address of hardware_errors fw_cfg blob into the
+ * hardware_errors_addr fw_cfg blob.
+ */
+ bios_linker_loader_write_pointer(linker, ACPI_GHES_DATA_ADDR_FW_CFG_FILE,
+ 0, ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE, 0);
+}
+
+/* Build Hardware Error Source Table */
+void acpi_ghes_build_hest(GArray *table_data, GArray *hardware_errors,
+ BIOSLinker *linker)
+{
+ uint32_t i, hest_start = table_data->len;
+
+ /* Reserve Hardware Error Source Table header size */
+ acpi_data_push(table_data, sizeof(AcpiTableHeader));
+
+ /* Error Source Count */
+ build_append_int_noprefix(table_data, ACPI_GHES_ERROR_SOURCE_COUNT, 4);
+
+ /* Generic Hardware Error Source version 2(GHESv2 - Type 10) */
+ for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) {
+ /* Type */
+ build_append_int_noprefix(table_data,
+ ACPI_GHES_SOURCE_GENERIC_ERROR_V2, 2);
+ /* Source Id */
+ build_append_int_noprefix(table_data, i, 2);
+ /* Related Source Id */
+ build_append_int_noprefix(table_data, 0xffff, 2);
+ /* Flags */
+ build_append_int_noprefix(table_data, 0, 1);
+ /* Enabled */
+ build_append_int_noprefix(table_data, 1, 1);
+
+ /* Number of Records To Pre-allocate */
+ build_append_int_noprefix(table_data, 1, 4);
+ /* Max Sections Per Record */
+ build_append_int_noprefix(table_data, 1, 4);
+ /* Max Raw Data Length */
+ build_append_int_noprefix(table_data, ACPI_GHES_MAX_RAW_DATA_LENGTH, 4);
+
+ /* Error Status Address */
+ build_append_gas(table_data, AML_SYSTEM_MEMORY, 0x40, 0,
+ 4 /* QWord access */, 0);
+ bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
+ ACPI_GHES_ERROR_STATUS_ADDRESS_OFFSET(hest_start, i),
+ ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE,
+ i * ACPI_GHES_ADDRESS_SIZE);
+
+ if (i == 0) {
+ /* Notification Structure
+ * Now only enable ARMv8 SEA notification type
+ */
+ acpi_ghes_build_notify(table_data, ACPI_GHES_NOTIFY_SEA, 28, 0,
+ 0, 0, 0, 0, 0, 0);
+ } else {
+ g_assert_not_reached();
+ }
+
+ /* Error Status Block Length */
+ build_append_int_noprefix(table_data, ACPI_GHES_MAX_RAW_DATA_LENGTH, 4);
+
+ /* Read Ack Register
+ * ACPI 6.1: 18.3.2.8 Generic Hardware Error Source
+ * version 2 (GHESv2 - Type 10)
+ */
+ build_append_gas(table_data, AML_SYSTEM_MEMORY, 0x40, 0,
+ 4 /* QWord access */, 0);
+ bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
+ ACPI_GHES_READ_ACK_REGISTER_ADDRESS_OFFSET(hest_start, i),
+ ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE,
+ (ACPI_GHES_ERROR_SOURCE_COUNT + i) * ACPI_GHES_ADDRESS_SIZE);
+
+ /* Read Ack Preserve */
+ build_append_int_noprefix(table_data, 0xfffffffffffffffe, 8);
+ /* Read Ack Write */
+ build_append_int_noprefix(table_data, 0x1, 8);
+ }
+
+ build_header(linker, table_data, (void *)(table_data->data + hest_start),
+ "HEST", table_data->len - hest_start, 1, NULL, "GHES");
+}
+
+static AcpiGhesState ges;
+void acpi_ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error)
+{
+
+ size_t size = 2 * ACPI_GHES_ADDRESS_SIZE + ACPI_GHES_MAX_RAW_DATA_LENGTH;
+ size_t request_block_size = ACPI_GHES_ERROR_SOURCE_COUNT * size;
+
+ /* Create a read-only fw_cfg file for GHES */
+ fw_cfg_add_file(s, ACPI_GHES_ERRORS_FW_CFG_FILE, hardware_error->data,
+ request_block_size);
+
+ /* Create a read-write fw_cfg file for Address */
+ fw_cfg_add_file_callback(s, ACPI_GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL,
+ NULL, &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false);
+}
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 78aee1a2f9..bfdb84c517 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -1578,6 +1578,7 @@ void acpi_build_tables_init(AcpiBuildTables *tables)
tables->table_data = g_array_new(false, true /* clear */, 1);
tables->tcpalog = g_array_new(false, true /* clear */, 1);
tables->vmgenid = g_array_new(false, true /* clear */, 1);
+ tables->hardware_errors = g_array_new(false, true /* clear */, 1);
tables->linker = bios_linker_loader_init();
}
@@ -1588,6 +1589,7 @@ void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre)
g_array_free(tables->table_data, true);
g_array_free(tables->tcpalog, mfre);
g_array_free(tables->vmgenid, mfre);
+ g_array_free(tables->hardware_errors, mfre);
}
/*
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 6cdf156cf5..c74e178aa0 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -46,6 +46,7 @@
#include "sysemu/reset.h"
#include "kvm_arm.h"
#include "migration/vmstate.h"
+#include "hw/acpi/acpi_ghes.h"
#define ARM_SPI_BASE 32
#define ACPI_POWER_BUTTON_DEVICE "PWRB"
@@ -796,6 +797,13 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_spcr(tables_blob, tables->linker, vms);
+ if (vms->ras) {
+ acpi_add_table(table_offsets, tables_blob);
+ acpi_ghes_build_error_table(tables->hardware_errors, tables->linker);
+ acpi_ghes_build_hest(tables_blob, tables->hardware_errors,
+ tables->linker);
+ }
+
if (ms->numa_state->num_nodes > 0) {
acpi_add_table(table_offsets, tables_blob);
build_srat(tables_blob, tables->linker, vms);
@@ -913,6 +921,10 @@ void virt_acpi_setup(VirtMachineState *vms)
fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
acpi_data_len(tables.tcpalog));
+ if (vms->ras) {
+ acpi_ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors);
+ }
+
build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update,
build_state, tables.rsdp,
ACPI_BUILD_RSDP_FILE, 0);
diff --git a/include/hw/acpi/acpi_ghes.h b/include/hw/acpi/acpi_ghes.h
new file mode 100644
index 0000000000..69747ba3d7
--- /dev/null
+++ b/include/hw/acpi/acpi_ghes.h
@@ -0,0 +1,103 @@
+/* Support for generating APEI tables and record CPER for Guests
+ *
+ * Copyright (C) 2019 Huawei Corporation.
+ *
+ * Author: Dongjiu Geng <gengdongjiu@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef ACPI_GHES_H
+#define ACPI_GHES_H
+
+#include "hw/acpi/bios-linker-loader.h"
+
+#define ACPI_GHES_ERRORS_FW_CFG_FILE "etc/hardware_errors"
+#define ACPI_GHES_DATA_ADDR_FW_CFG_FILE "etc/hardware_errors_addr"
+
+/* The size of Address field in Generic Address Structure,
+ * ACPI 2.0/3.0: 5.2.3.1 Generic Address Structure.
+ */
+#define ACPI_GHES_ADDRESS_SIZE 8
+
+/* The max size in bytes for one error block */
+#define ACPI_GHES_MAX_RAW_DATA_LENGTH 0x1000
+
+/* Now only support ARMv8 SEA notification type error source
+ */
+#define ACPI_GHES_ERROR_SOURCE_COUNT 1
+
+/*
+ * Generic Hardware Error Source version 2
+ */
+#define ACPI_GHES_SOURCE_GENERIC_ERROR_V2 10
+
+/*
+ * Values for Hardware Error Notification Type field
+ */
+enum AcpiGhesNotifyType {
+ ACPI_GHES_NOTIFY_POLLED = 0, /* Polled */
+ ACPI_GHES_NOTIFY_EXTERNAL = 1, /* External Interrupt */
+ ACPI_GHES_NOTIFY_LOCAL = 2, /* Local Interrupt */
+ ACPI_GHES_NOTIFY_SCI = 3, /* SCI */
+ ACPI_GHES_NOTIFY_NMI = 4, /* NMI */
+ ACPI_GHES_NOTIFY_CMCI = 5, /* CMCI, ACPI 5.0: 18.3.2.7, Table 18-290 */
+ ACPI_GHES_NOTIFY_MCE = 6, /* MCE, ACPI 5.0: 18.3.2.7, Table 18-290 */
+ /* GPIO-Signal, ACPI 6.0: 18.3.2.7, Table 18-332 */
+ ACPI_GHES_NOTIFY_GPIO = 7,
+ /* ARMv8 SEA, ACPI 6.1: 18.3.2.9, Table 18-345 */
+ ACPI_GHES_NOTIFY_SEA = 8,
+ /* ARMv8 SEI, ACPI 6.1: 18.3.2.9, Table 18-345 */
+ ACPI_GHES_NOTIFY_SEI = 9,
+ /* External Interrupt - GSIV, ACPI 6.1: 18.3.2.9, Table 18-345 */
+ ACPI_GHES_NOTIFY_GSIV = 10,
+ /* Software Delegated Exception, ACPI 6.2: 18.3.2.9, Table 18-383 */
+ ACPI_GHES_NOTIFY_SDEI = 11,
+ ACPI_GHES_NOTIFY_RESERVED = 12 /* 12 and greater are reserved */
+};
+
+/*
+ * | +--------------------------+ 0
+ * | | Header |
+ * | +--------------------------+ 40---+-
+ * | | ................. | |
+ * | | error_status_address-----+ 60 |
+ * | | ................. | |
+ * | | read_ack_register--------+ 104 92
+ * | | read_ack_preserve | |
+ * | | read_ack_write | |
+ * + +--------------------------+ 132--+-
+ *
+ * From above GHES definition, the error status address offset is 60;
+ * the Read ack register offset is 104, the whole size of GHESv2 is 92
+ */
+
+/* The error status address offset in GHES */
+#define ACPI_GHES_ERROR_STATUS_ADDRESS_OFFSET(start_addr, n) (start_addr + \
+ 60 + offsetof(struct AcpiGenericAddress, address) + n * 92)
+
+/* The read Ack register offset in GHES */
+#define ACPI_GHES_READ_ACK_REGISTER_ADDRESS_OFFSET(start_addr, n) (start_addr +\
+ 104 + offsetof(struct AcpiGenericAddress, address) + n * 92)
+
+typedef struct AcpiGhesState {
+ uint64_t ghes_addr_le;
+} AcpiGhesState;
+
+void acpi_ghes_build_hest(GArray *table_data, GArray *hardware_error,
+ BIOSLinker *linker);
+
+void acpi_ghes_build_error_table(GArray *hardware_errors, BIOSLinker *linker);
+void acpi_ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_errors);
+#endif
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 991cf05134..2cc61712fd 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -220,6 +220,7 @@ struct AcpiBuildTables {
GArray *rsdp;
GArray *tcpalog;
GArray *vmgenid;
+ GArray *hardware_errors;
BIOSLinker *linker;
} AcpiBuildTables;
--
2.19.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v18 4/6] KVM: Move hwpoison page related functions into include/sysemu/kvm_int.h
2019-09-06 8:31 [PATCH v18 0/6] Add ARMv8 RAS virtualization support in QEMU Xiang Zheng
` (2 preceding siblings ...)
2019-09-06 8:31 ` [PATCH v18 3/6] ACPI: Add APEI GHES table generation support Xiang Zheng
@ 2019-09-06 8:31 ` Xiang Zheng
2019-09-27 13:19 ` [Qemu-arm] " Peter Maydell
2019-09-06 8:31 ` [PATCH v18 5/6] target-arm: kvm64: inject synchronous External Abort Xiang Zheng
` (3 subsequent siblings)
7 siblings, 1 reply; 26+ messages in thread
From: Xiang Zheng @ 2019-09-06 8:31 UTC (permalink / raw)
To: pbonzini, mst, imammedo, shannon.zhaosl, peter.maydell, lersek,
james.morse, gengdongjiu, mtosatti, rth, ehabkost,
jonathan.cameron, xuwei5, kvm, qemu-devel, qemu-arm, linuxarm
Cc: zhengxiang9, wanghaibin.wang
From: Dongjiu Geng <gengdongjiu@huawei.com>
kvm_hwpoison_page_add() and kvm_unpoison_all() will both be used by X86
and ARM platforms, so moving them into "include/sysemu/kvm_int.h" to
avoid duplicate code.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
---
accel/kvm/kvm-all.c | 33 +++++++++++++++++++++++++++++++++
include/sysemu/kvm_int.h | 23 +++++++++++++++++++++++
target/arm/kvm.c | 3 +++
target/i386/kvm.c | 34 ----------------------------------
4 files changed, 59 insertions(+), 34 deletions(-)
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index b09bad0804..c6c052ba57 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
@@ -821,6 +821,39 @@ int kvm_vm_check_extension(KVMState *s, unsigned int extension)
return ret;
}
+typedef struct HWPoisonPage {
+ ram_addr_t ram_addr;
+ QLIST_ENTRY(HWPoisonPage) list;
+} HWPoisonPage;
+
+static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
+ QLIST_HEAD_INITIALIZER(hwpoison_page_list);
+
+void kvm_unpoison_all(void *param)
+{
+ HWPoisonPage *page, *next_page;
+
+ QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
+ QLIST_REMOVE(page, list);
+ qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
+ g_free(page);
+ }
+}
+
+void kvm_hwpoison_page_add(ram_addr_t ram_addr)
+{
+ HWPoisonPage *page;
+
+ QLIST_FOREACH(page, &hwpoison_page_list, list) {
+ if (page->ram_addr == ram_addr) {
+ return;
+ }
+ }
+ page = g_new(HWPoisonPage, 1);
+ page->ram_addr = ram_addr;
+ QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
+}
+
static uint32_t adjust_ioeventfd_endianness(uint32_t val, uint32_t size)
{
#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
diff --git a/include/sysemu/kvm_int.h b/include/sysemu/kvm_int.h
index 72b2d1b3ae..3ad49f9a28 100644
--- a/include/sysemu/kvm_int.h
+++ b/include/sysemu/kvm_int.h
@@ -41,4 +41,27 @@ typedef struct KVMMemoryListener {
void kvm_memory_listener_register(KVMState *s, KVMMemoryListener *kml,
AddressSpace *as, int as_id);
+/**
+ * kvm_hwpoison_page_add:
+ *
+ * Parameters:
+ * @ram_addr: the address in the RAM for the poisoned page
+ *
+ * Add a poisoned page to the list
+ *
+ * Return: None.
+ */
+void kvm_hwpoison_page_add(ram_addr_t ram_addr);
+
+/**
+ * kvm_unpoison_all:
+ *
+ * Parameters:
+ * @param: some data may be passed to this function
+ *
+ * Free and remove all the poisoned pages in the list
+ *
+ * Return: None.
+ */
+void kvm_unpoison_all(void *param);
#endif
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index b2eaa50b8d..3a110be7b8 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -20,6 +20,7 @@
#include "sysemu/sysemu.h"
#include "sysemu/kvm.h"
#include "sysemu/kvm_int.h"
+#include "sysemu/reset.h"
#include "kvm_arm.h"
#include "cpu.h"
#include "trace.h"
@@ -195,6 +196,8 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE);
+ qemu_register_reset(kvm_unpoison_all, NULL);
+
return 0;
}
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 8023c679ea..4f9f3682ee 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -476,40 +476,6 @@ uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
return msr_data.entries[0].data;
}
-
-typedef struct HWPoisonPage {
- ram_addr_t ram_addr;
- QLIST_ENTRY(HWPoisonPage) list;
-} HWPoisonPage;
-
-static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
- QLIST_HEAD_INITIALIZER(hwpoison_page_list);
-
-static void kvm_unpoison_all(void *param)
-{
- HWPoisonPage *page, *next_page;
-
- QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
- QLIST_REMOVE(page, list);
- qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
- g_free(page);
- }
-}
-
-static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
-{
- HWPoisonPage *page;
-
- QLIST_FOREACH(page, &hwpoison_page_list, list) {
- if (page->ram_addr == ram_addr) {
- return;
- }
- }
- page = g_new(HWPoisonPage, 1);
- page->ram_addr = ram_addr;
- QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
-}
-
static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
int *max_banks)
{
--
2.19.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v18 5/6] target-arm: kvm64: inject synchronous External Abort
2019-09-06 8:31 [PATCH v18 0/6] Add ARMv8 RAS virtualization support in QEMU Xiang Zheng
` (3 preceding siblings ...)
2019-09-06 8:31 ` [PATCH v18 4/6] KVM: Move hwpoison page related functions into include/sysemu/kvm_int.h Xiang Zheng
@ 2019-09-06 8:31 ` Xiang Zheng
2019-09-27 13:33 ` Peter Maydell
2019-09-06 8:31 ` [PATCH v18 6/6] target-arm: kvm64: handle SIGBUS signal from kernel or KVM Xiang Zheng
` (2 subsequent siblings)
7 siblings, 1 reply; 26+ messages in thread
From: Xiang Zheng @ 2019-09-06 8:31 UTC (permalink / raw)
To: pbonzini, mst, imammedo, shannon.zhaosl, peter.maydell, lersek,
james.morse, gengdongjiu, mtosatti, rth, ehabkost,
jonathan.cameron, xuwei5, kvm, qemu-devel, qemu-arm, linuxarm
Cc: zhengxiang9, wanghaibin.wang
From: Dongjiu Geng <gengdongjiu@huawei.com>
Introduce kvm_inject_arm_sea() function in which we will setup the type
of exception and the syndrome information in order to inject a virtual
synchronous external abort. When switching to guest, it will jump to the
synchronous external abort vector table entry.
The ESR_ELx.DFSC is set to synchronous external abort(0x10), and
ESR_ELx.FnV is set to not valid(0x1), which will tell guest that FAR is
not valid and hold an UNKNOWN value. These values will be set to KVM
register structures through KVM_SET_ONE_REG IOCTL.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
---
target/arm/helper.c | 2 +-
target/arm/internals.h | 5 +++--
target/arm/kvm64.c | 34 ++++++++++++++++++++++++++++++++++
target/arm/tlb_helper.c | 2 +-
4 files changed, 39 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 507026c915..a13baeb085 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3005,7 +3005,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
* Report exception with ESR indicating a fault due to a
* translation table walk for a cache maintenance instruction.
*/
- syn = syn_data_abort_no_iss(current_el == target_el,
+ syn = syn_data_abort_no_iss(current_el == target_el, 0,
fi.ea, 1, fi.s1ptw, 1, fsc);
env->exception.vaddress = value;
env->exception.fsr = fsr;
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 232d963875..98cde702ad 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -451,13 +451,14 @@ static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
| ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc;
}
-static inline uint32_t syn_data_abort_no_iss(int same_el,
+static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv,
int ea, int cm, int s1ptw,
int wnr, int fsc)
{
return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
| ARM_EL_IL
- | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
+ | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7)
+ | (wnr << 6) | fsc;
}
static inline uint32_t syn_data_abort_with_iss(int same_el,
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 28f6db57d5..bf6edaa3f6 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -710,6 +710,40 @@ int kvm_arm_cpreg_level(uint64_t regidx)
return KVM_PUT_RUNTIME_STATE;
}
+/* Inject synchronous external abort */
+static void kvm_inject_arm_sea(CPUState *c)
+{
+ ARMCPU *cpu = ARM_CPU(c);
+ CPUARMState *env = &cpu->env;
+ CPUClass *cc = CPU_GET_CLASS(c);
+ uint32_t esr;
+ bool same_el;
+
+ /**
+ * Set the exception type to synchronous data abort
+ * and the target exception Level to EL1.
+ */
+ c->exception_index = EXCP_DATA_ABORT;
+ env->exception.target_el = 1;
+
+ /*
+ * Set the DFSC to synchronous external abort and set FnV to not valid,
+ * this will tell guest the FAR_ELx is UNKNOWN for this abort.
+ */
+
+ /* This exception comes from lower or current exception level. */
+ same_el = arm_current_el(env) == env->exception.target_el;
+ esr = syn_data_abort_no_iss(same_el, 1, 0, 0, 0, 0, 0x10);
+
+ env->exception.syndrome = esr;
+
+ /**
+ * The vcpu thread already hold BQL, so no need hold again when
+ * calling do_interrupt
+ */
+ cc->do_interrupt(c);
+}
+
#define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index 5feb312941..499672ebbc 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -33,7 +33,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
* ISV field.
*/
if (!(template_syn & ARM_EL_ISV) || target_el != 2 || s1ptw) {
- syn = syn_data_abort_no_iss(same_el,
+ syn = syn_data_abort_no_iss(same_el, 0,
ea, 0, s1ptw, is_write, fsc);
} else {
/*
--
2.19.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v18 6/6] target-arm: kvm64: handle SIGBUS signal from kernel or KVM
2019-09-06 8:31 [PATCH v18 0/6] Add ARMv8 RAS virtualization support in QEMU Xiang Zheng
` (4 preceding siblings ...)
2019-09-06 8:31 ` [PATCH v18 5/6] target-arm: kvm64: inject synchronous External Abort Xiang Zheng
@ 2019-09-06 8:31 ` Xiang Zheng
2019-09-27 13:57 ` Peter Maydell
2019-09-17 12:39 ` [PATCH v18 0/6] Add ARMv8 RAS virtualization support in QEMU Xiang Zheng
2019-09-27 14:03 ` [Qemu-arm] " Peter Maydell
7 siblings, 1 reply; 26+ messages in thread
From: Xiang Zheng @ 2019-09-06 8:31 UTC (permalink / raw)
To: pbonzini, mst, imammedo, shannon.zhaosl, peter.maydell, lersek,
james.morse, gengdongjiu, mtosatti, rth, ehabkost,
jonathan.cameron, xuwei5, kvm, qemu-devel, qemu-arm, linuxarm
Cc: zhengxiang9, wanghaibin.wang
From: Dongjiu Geng <gengdongjiu@huawei.com>
Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type,
translates the host VA delivered by host to guest PA, then fills this PA
to guest APEI GHES memory, then notifies guest according to the SIGBUS
type.
If guest accesses the poisoned memory, it generates Synchronous External
Abort(SEA). Then host kernel gets an APEI notification and calls
memory_failure() to unmapped the affected page in stage 2, finally
returns to guest.
Guest continues to access PG_hwpoison page, it will trap to KVM as
stage2 fault, then a SIGBUS_MCEERR_AR synchronous signal is delivered to
Qemu, Qemu records this error address into guest APEI GHES memory and
notifes guest using Synchronous-External-Abort(SEA).
Suggested-by: James Morse <james.morse@arm.com>
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
---
hw/acpi/acpi_ghes.c | 252 ++++++++++++++++++++++++++++++++++++
include/hw/acpi/acpi_ghes.h | 40 ++++++
include/sysemu/kvm.h | 2 +-
target/arm/kvm64.c | 39 ++++++
4 files changed, 332 insertions(+), 1 deletion(-)
diff --git a/hw/acpi/acpi_ghes.c b/hw/acpi/acpi_ghes.c
index 20c45179ff..2d17c88045 100644
--- a/hw/acpi/acpi_ghes.c
+++ b/hw/acpi/acpi_ghes.c
@@ -26,6 +26,168 @@
#include "sysemu/sysemu.h"
#include "qemu/error-report.h"
+/* Total size for Generic Error Status Block
+ * ACPI 6.2: 18.3.2.7.1 Generic Error Data,
+ * Table 18-380 Generic Error Status Block
+ */
+#define ACPI_GHES_GESB_SIZE 20
+/* The offset of Data Length in Generic Error Status Block */
+#define ACPI_GHES_GESB_DATA_LENGTH_OFFSET 12
+
+/* Record the value of data length for each error status block to avoid getting
+ * this value from guest.
+ */
+static uint32_t acpi_ghes_data_length[ACPI_GHES_ERROR_SOURCE_COUNT];
+
+/* Generic Error Data Entry
+ * ACPI 6.1: 18.3.2.7.1 Generic Error Data
+ */
+static void acpi_ghes_generic_error_data(GArray *table, QemuUUID section_type,
+ uint32_t error_severity, uint16_t revision,
+ uint8_t validation_bits, uint8_t flags,
+ uint32_t error_data_length, QemuUUID fru_id,
+ uint8_t *fru_text, uint64_t time_stamp)
+{
+ QemuUUID uuid_le;
+
+ /* Section Type */
+ uuid_le = qemu_uuid_bswap(section_type);
+ g_array_append_vals(table, uuid_le.data, ARRAY_SIZE(uuid_le.data));
+
+ /* Error Severity */
+ build_append_int_noprefix(table, error_severity, 4);
+ /* Revision */
+ build_append_int_noprefix(table, revision, 2);
+ /* Validation Bits */
+ build_append_int_noprefix(table, validation_bits, 1);
+ /* Flags */
+ build_append_int_noprefix(table, flags, 1);
+ /* Error Data Length */
+ build_append_int_noprefix(table, error_data_length, 4);
+
+ /* FRU Id */
+ uuid_le = qemu_uuid_bswap(fru_id);
+ g_array_append_vals(table, uuid_le.data, ARRAY_SIZE(uuid_le.data));
+
+ /* FRU Text */
+ g_array_append_vals(table, fru_text, 20);
+ /* Timestamp */
+ build_append_int_noprefix(table, time_stamp, 8);
+}
+
+/* Generic Error Status Block
+ * ACPI 6.1: 18.3.2.7.1 Generic Error Data
+ */
+static void acpi_ghes_generic_error_status(GArray *table, uint32_t block_status,
+ uint32_t raw_data_offset, uint32_t raw_data_length,
+ uint32_t data_length, uint32_t error_severity)
+{
+ /* Block Status */
+ build_append_int_noprefix(table, block_status, 4);
+ /* Raw Data Offset */
+ build_append_int_noprefix(table, raw_data_offset, 4);
+ /* Raw Data Length */
+ build_append_int_noprefix(table, raw_data_length, 4);
+ /* Data Length */
+ build_append_int_noprefix(table, data_length, 4);
+ /* Error Severity */
+ build_append_int_noprefix(table, error_severity, 4);
+}
+
+/* UEFI 2.6: N.2.5 Memory Error Section */
+static void acpi_ghes_build_append_mem_cper(GArray *table,
+ uint64_t error_physical_addr)
+{
+ /*
+ * Memory Error Record
+ */
+
+ /* Validation Bits */
+ build_append_int_noprefix(table,
+ (1UL << 14) | /* Type Valid */
+ (1UL << 1) /* Physical Address Valid */,
+ 8);
+ /* Error Status */
+ build_append_int_noprefix(table, 0, 8);
+ /* Physical Address */
+ build_append_int_noprefix(table, error_physical_addr, 8);
+ /* Skip all the detailed information normally found in such a record */
+ build_append_int_noprefix(table, 0, 48);
+ /* Memory Error Type */
+ build_append_int_noprefix(table, 0 /* Unknown error */, 1);
+ /* Skip all the detailed information normally found in such a record */
+ build_append_int_noprefix(table, 0, 7);
+}
+
+static int acpi_ghes_record_mem_error(uint64_t error_block_address,
+ uint64_t error_physical_addr,
+ uint32_t data_length)
+{
+ GArray *block;
+ uint64_t current_block_length;
+ /* Memory Error Section Type */
+ QemuUUID mem_section_id_le = UEFI_CPER_SEC_PLATFORM_MEM;
+ QemuUUID fru_id = {0};
+ uint8_t fru_text[20] = {0};
+
+ /* Generic Error Status Block
+ * | +---------------------+
+ * | | block_status |
+ * | +---------------------+
+ * | | raw_data_offset |
+ * | +---------------------+
+ * | | raw_data_length |
+ * | +---------------------+
+ * | | data_length |
+ * | +---------------------+
+ * | | error_severity |
+ * | +---------------------+
+ */
+ block = g_array_new(false, true /* clear */, 1);
+
+ /* The current whole length of the generic error status block */
+ current_block_length = ACPI_GHES_GESB_SIZE + data_length;
+
+ /* This is the length if adding a new generic error data entry*/
+ data_length += ACPI_GHES_DATA_LENGTH;
+ data_length += ACPI_GHES_MEM_CPER_LENGTH;
+
+ /* Check whether it will run out of the preallocated memory if adding a new
+ * generic error data entry
+ */
+ if ((data_length + ACPI_GHES_GESB_SIZE) > ACPI_GHES_MAX_RAW_DATA_LENGTH) {
+ error_report("Record CPER out of boundary!!!");
+ return ACPI_GHES_CPER_FAIL;
+ }
+
+ /* Build the new generic error status block header */
+ acpi_ghes_generic_error_status(block, cpu_to_le32(ACPI_GEBS_UNCORRECTABLE),
+ 0, 0, cpu_to_le32(data_length), cpu_to_le32(ACPI_CPER_SEV_RECOVERABLE));
+
+ /* Write back above generic error status block header to guest memory */
+ cpu_physical_memory_write(error_block_address, block->data,
+ block->len);
+
+ /* Add a new generic error data entry */
+
+ data_length = block->len;
+ /* Build this new generic error data entry header */
+ acpi_ghes_generic_error_data(block, mem_section_id_le,
+ cpu_to_le32(ACPI_CPER_SEV_RECOVERABLE), cpu_to_le32(0x300), 0, 0,
+ cpu_to_le32(ACPI_GHES_MEM_CPER_LENGTH), fru_id, fru_text, 0);
+
+ /* Build the memory section CPER for above new generic error data entry */
+ acpi_ghes_build_append_mem_cper(block, error_physical_addr);
+
+ /* Write back above this new generic error data entry to guest memory */
+ cpu_physical_memory_write(error_block_address + current_block_length,
+ block->data + data_length, block->len - data_length);
+
+ g_array_free(block, true);
+
+ return ACPI_GHES_CPER_OK;
+}
+
/* Hardware Error Notification
* ACPI 4.0: 17.3.2.7 Hardware Error Notification
*/
@@ -208,3 +370,93 @@ void acpi_ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error)
fw_cfg_add_file_callback(s, ACPI_GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL,
NULL, &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false);
}
+
+bool acpi_ghes_record_errors(uint32_t notify, uint64_t physical_address)
+{
+ uint64_t error_block_addr, read_ack_register_addr, read_ack_register = 0;
+ int loop = 0;
+ uint64_t start_addr = le64_to_cpu(ges.ghes_addr_le);
+ bool ret = ACPI_GHES_CPER_FAIL;
+ uint8_t source_id;
+ const uint8_t error_source_id[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0, 0xff, 0xff, 0xff};
+
+ /*
+ * | +---------------------+ ges.ghes_addr_le
+ * | |error_block_address0 |
+ * | +---------------------+ --+--
+ * | | ............. | ACPI_GHES_ADDRESS_SIZE
+ * | +---------------------+ --+--
+ * | |error_block_addressN |
+ * | +---------------------+
+ * | | read_ack_register0 |
+ * | +---------------------+ --+--
+ * | | ............. | ACPI_GHES_ADDRESS_SIZE
+ * | +---------------------+ --+--
+ * | | read_ack_registerN |
+ * | +---------------------+ --+--
+ * | | CPER | |
+ * | | .... | ACPI_GHES_MAX_RAW_DATA_LENGT
+ * | | CPER | |
+ * | +---------------------+ --+--
+ * | | .......... |
+ * | +---------------------+
+ * | | CPER |
+ * | | .... |
+ * | | CPER |
+ * | +---------------------+
+ */
+ if (physical_address && notify < ACPI_GHES_NOTIFY_RESERVED) {
+ /* Find and check the source id for this new CPER */
+ source_id = error_source_id[notify];
+ if (source_id != 0xff) {
+ start_addr += source_id * ACPI_GHES_ADDRESS_SIZE;
+ } else {
+ goto out;
+ }
+
+ cpu_physical_memory_read(start_addr, &error_block_addr,
+ ACPI_GHES_ADDRESS_SIZE);
+
+ read_ack_register_addr = start_addr +
+ ACPI_GHES_ERROR_SOURCE_COUNT * ACPI_GHES_ADDRESS_SIZE;
+retry:
+ cpu_physical_memory_read(read_ack_register_addr,
+ &read_ack_register, ACPI_GHES_ADDRESS_SIZE);
+
+ /* zero means OSPM does not acknowledge the error */
+ if (!read_ack_register) {
+ if (loop < 3) {
+ usleep(100 * 1000);
+ loop++;
+ goto retry;
+ } else {
+ error_report("OSPM does not acknowledge previous error,"
+ " so can not record CPER for current error, forcibly"
+ " acknowledge previous error to avoid blocking next time"
+ " CPER record! Exit");
+ read_ack_register = 1;
+ cpu_physical_memory_write(read_ack_register_addr,
+ &read_ack_register, ACPI_GHES_ADDRESS_SIZE);
+ }
+ } else {
+ if (error_block_addr) {
+ read_ack_register = 0;
+ /* Clear the Read Ack Register, OSPM will write it to 1 when
+ * acknowledge this error.
+ */
+ cpu_physical_memory_write(read_ack_register_addr,
+ &read_ack_register, ACPI_GHES_ADDRESS_SIZE);
+ ret = acpi_ghes_record_mem_error(error_block_addr,
+ physical_address, acpi_ghes_data_length[source_id]);
+ if (ret == ACPI_GHES_CPER_OK) {
+ acpi_ghes_data_length[source_id] +=
+ (ACPI_GHES_DATA_LENGTH + ACPI_GHES_MEM_CPER_LENGTH);
+ }
+ }
+ }
+ }
+
+out:
+ return ret;
+}
diff --git a/include/hw/acpi/acpi_ghes.h b/include/hw/acpi/acpi_ghes.h
index 69747ba3d7..96f932c207 100644
--- a/include/hw/acpi/acpi_ghes.h
+++ b/include/hw/acpi/acpi_ghes.h
@@ -34,6 +34,35 @@
/* The max size in bytes for one error block */
#define ACPI_GHES_MAX_RAW_DATA_LENGTH 0x1000
+/* The total size of Generic Error Data Entry
+ * ACPI 6.1/6.2: 18.3.2.7.1 Generic Error Data,
+ * Table 18-343 Generic Error Data Entry
+ */
+#define ACPI_GHES_DATA_LENGTH 72
+
+/* The memory section CPER size,
+ * UEFI 2.6: N.2.5 Memory Error Section
+ */
+#define ACPI_GHES_MEM_CPER_LENGTH 80
+
+#define ACPI_GHES_CPER_OK 1
+#define ACPI_GHES_CPER_FAIL 0
+
+/*
+ * Masks for block_status flags above
+ */
+#define ACPI_GEBS_UNCORRECTABLE 1
+
+/*
+ * Values for error_severity field above
+ */
+enum AcpiGenericErrorSeverity {
+ ACPI_CPER_SEV_RECOVERABLE,
+ ACPI_CPER_SEV_FATAL,
+ ACPI_CPER_SEV_CORRECTED,
+ ACPI_CPER_SEV_NONE,
+};
+
/* Now only support ARMv8 SEA notification type error source
*/
#define ACPI_GHES_ERROR_SOURCE_COUNT 1
@@ -67,6 +96,16 @@ enum AcpiGhesNotifyType {
ACPI_GHES_NOTIFY_RESERVED = 12 /* 12 and greater are reserved */
};
+#define UUID_BE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
+ {{{ ((a) >> 24) & 0xff, ((a) >> 16) & 0xff, ((a) >> 8) & 0xff, (a) & 0xff, \
+ ((b) >> 8) & 0xff, (b) & 0xff, \
+ ((c) >> 8) & 0xff, (c) & 0xff, \
+ (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } } }
+
+#define UEFI_CPER_SEC_PLATFORM_MEM \
+ UUID_BE(0xA5BC1114, 0x6F64, 0x4EDE, 0xB8, 0x63, 0x3E, 0x83, \
+ 0xED, 0x7C, 0x83, 0xB1)
+
/*
* | +--------------------------+ 0
* | | Header |
@@ -100,4 +139,5 @@ void acpi_ghes_build_hest(GArray *table_data, GArray *hardware_error,
void acpi_ghes_build_error_table(GArray *hardware_errors, BIOSLinker *linker);
void acpi_ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_errors);
+bool acpi_ghes_record_errors(uint32_t notify, uint64_t error_physical_addr);
#endif
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 909bcd77cf..5f57e4ed43 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -378,7 +378,7 @@ bool kvm_vcpu_id_is_valid(int vcpu_id);
/* Returns VCPU ID to be used on KVM_CREATE_VCPU ioctl() */
unsigned long kvm_arch_vcpu_id(CPUState *cpu);
-#ifdef TARGET_I386
+#if defined(TARGET_I386) || defined(TARGET_AARCH64)
#define KVM_HAVE_MCE_INJECTION 1
void kvm_arch_on_sigbus_vcpu(CPUState *cpu, int code, void *addr);
#endif
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index bf6edaa3f6..186d855522 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -28,6 +28,8 @@
#include "kvm_arm.h"
#include "hw/boards.h"
#include "internals.h"
+#include "hw/acpi/acpi.h"
+#include "hw/acpi/acpi_ghes.h"
static bool have_guest_debug;
@@ -1070,6 +1072,43 @@ int kvm_arch_get_registers(CPUState *cs)
return ret;
}
+void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
+{
+ ram_addr_t ram_addr;
+ hwaddr paddr;
+
+ assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
+
+ if (acpi_enabled && addr &&
+ object_property_get_bool(qdev_get_machine(), "ras", NULL)) {
+ ram_addr = qemu_ram_addr_from_host(addr);
+ if (ram_addr != RAM_ADDR_INVALID &&
+ kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
+ kvm_hwpoison_page_add(ram_addr);
+ /* Asynchronous signal will be masked by main thread, so
+ * only handle synchronous signal.
+ */
+ if (code == BUS_MCEERR_AR) {
+ kvm_cpu_synchronize_state(c);
+ if (ACPI_GHES_CPER_FAIL !=
+ acpi_ghes_record_errors(ACPI_GHES_NOTIFY_SEA, paddr)) {
+ kvm_inject_arm_sea(c);
+ } else {
+ fprintf(stderr, "failed to record the error\n");
+ }
+ }
+ return;
+ }
+ fprintf(stderr, "Hardware memory error for memory used by "
+ "QEMU itself instead of guest system!\n");
+ }
+
+ if (code == BUS_MCEERR_AR) {
+ fprintf(stderr, "Hardware memory error!\n");
+ exit(1);
+ }
+}
+
/* C6.6.29 BRK instruction */
static const uint32_t brk_insn = 0xd4200000;
--
2.19.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH v18 0/6] Add ARMv8 RAS virtualization support in QEMU
2019-09-06 8:31 [PATCH v18 0/6] Add ARMv8 RAS virtualization support in QEMU Xiang Zheng
` (5 preceding siblings ...)
2019-09-06 8:31 ` [PATCH v18 6/6] target-arm: kvm64: handle SIGBUS signal from kernel or KVM Xiang Zheng
@ 2019-09-17 12:39 ` Xiang Zheng
2019-09-20 2:07 ` gengdongjiu
2019-09-27 14:03 ` [Qemu-arm] " Peter Maydell
7 siblings, 1 reply; 26+ messages in thread
From: Xiang Zheng @ 2019-09-17 12:39 UTC (permalink / raw)
To: pbonzini, mst, imammedo, shannon.zhaosl, peter.maydell, lersek,
james.morse, gengdongjiu, mtosatti, rth, ehabkost,
jonathan.cameron, xuwei5, kvm, qemu-devel, qemu-arm, linuxarm
Cc: wanghaibin.wang
Hi all,
This patch series has been tested for both TCG and KVM scenes.
1) Test for TCG:
- Re-compile qemu after applying the patch refered to https://patchwork.kernel.org/cover/10942757/#22640271).
- Use command line shown below to start qemu:
./qemu-system-aarch64 \
-name guest=ras \
-machine virt,gic-version=3,ras=on \
-cpu cortex-a57 \
-bios /usr/share/edk2/aarch64/QEMU_EFI.fd \
-nodefaults \
-kernel ${GUEST_KERNEL} \
-initrd ${GUEST_FS} \
-append "rdinit=init console=ttyAMA0 earlycon=pl011,0x9000000" \
-m 8192 \
-smp 4 \
-serial stdio \
- Send a signal to one of the VCPU threads:
kill -s SIGBUS 71571
- The result of test is shown below:
[ 41.194753] {1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 0
[ 41.197329] {1}[Hardware Error]: event severity: recoverable
[ 41.199078] {1}[Hardware Error]: Error 0, type: recoverable
[ 41.200829] {1}[Hardware Error]: section_type: memory error
[ 41.202603] {1}[Hardware Error]: physical_address: 0x00000000400a1000
[ 41.204649] {1}[Hardware Error]: error_type: 0, unknown
[ 41.206328] EDAC MC0: 1 UE Unknown on unknown label ( page:0x400a1 offset:0x0 grain:0)
[ 41.208788] Internal error: synchronous external abort: 96000410 [#1] SMP
[ 41.210879] Modules linked in:
[ 41.211823] CPU: 2 PID: 0 Comm: swapper/2 Not tainted 4.19.0+ #8
[ 41.213698] Hardware name: QEMU KVM Virtual Machine, BIOS 0.0.0 02/06/2015
[ 41.215812] pstate: 60c00085 (nZCv daIf +PAN +UAO)
[ 41.217296] pc : cpu_do_idle+0x8/0xc
[ 41.218400] lr : arch_cpu_idle+0x2c/0x1b8
[ 41.219629] sp : ffff000009f9bf00
[ 41.220649] x29: ffff000009f9bf00 x28: 0000000000000000
[ 41.222310] x27: 0000000000000000 x26: ffff8001fe471d80
[ 41.223945] x25: 0000000000000000 x24: ffff00000937ba38
[ 41.225581] x23: ffff0000090b3338 x22: ffff000009379000
[ 41.227220] x21: ffff00000937b000 x20: 0000000000000004
[ 41.228871] x19: ffff0000090a6000 x18: 0000000000000000
[ 41.230517] x17: 0000000000000000 x16: 0000000000000000
[ 41.232165] x15: 0000000000000000 x14: 0000000000000000
[ 41.233810] x13: ffff0000089f4da8 x12: 000000000000000e
[ 41.235448] x11: ffff0000089f4d80 x10: 0000000000000af0
[ 41.237101] x9 : ffff000009f9be80 x8 : ffff8001fe4728d0
[ 41.238738] x7 : 0000000000000004 x6 : ffff8001fffbaf30
[ 41.240380] x5 : ffff00000c43b940 x4 : 00008001f6f0c000
[ 41.242030] x3 : 0000000000000001 x2 : ffff000009f9bf00
[ 41.243666] x1 : ffff8001fffb82c8 x0 : ffff0000090a6018
[ 41.245306] Process swapper/2 (pid: 0, stack limit = 0x(____ptrval____))
[ 41.247378] Call trace:
[ 41.248117] cpu_do_idle+0x8/0xc
[ 41.249111] do_idle+0x1dc/0x2a8
[ 41.250111] cpu_startup_entry+0x28/0x30
[ 41.251319] secondary_start_kernel+0x180/0x1c8
[ 41.252725] Code: a8c17bfd d65f03c0 d5033f9f d503207f (d65f03c0)
[ 41.254606] ---[ end trace 221bc8a614fb5a1d ]---
[ 41.256030] Kernel panic - not syncing: Fatal exception
[ 41.257644] SMP: stopping secondary CPUs
[ 41.258912] Kernel Offset: disabled
[ 41.260011] CPU features: 0x0,22a00238
[ 41.261178] Memory Limit: none
[ 41.262122] ---[ end Kernel panic - not syncing: Fatal exception ]---
2) Test for KVM:
- Use command line shown below to start qemu:
./qemu-system-aarch64 \
-name guest=ras \
-machine virt,accel=kvm,gic-version=3,ras=on \
-cpu host \
-bios /usr/share/edk2/aarch64/QEMU_EFI.fd \
-nodefaults \
-kernel ${GUEST_KERNEL} \
-initrd ${GUEST_FS} \
-append "rdinit=init console=ttyAMA0 earlycon=pl011,0x9000000" \
-m 8192 \
-smp 4 \
-serial stdio \
- Run mca-recover and get the GPA(IPA) of allocated page which would be corrupted on the later.
- Convert the GPA to HPA and corrupt this HPA via APEI/EINJ.
- Go back to guest and continue to read this page.
- The result of test is shown below:
root@genericarmv8:~/tools# ./mca-recover
pagesize: 0x1000
before clear cache
flags for page 0x2317b2: uptodate active mmap anon swapbacked
vtop(0xffff9c9e8000) = 0x2317b2000
Hit any key to access: before read
after read
Access at Tue Sep 17 01:41:14 2019
flags for page 0x2317b2: uptodate active mmap anon swapbacked
[ 403.298539] {1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 0
[ 403.301421] {1}[Hardware Error]: event severity: recoverable
[ 403.303217] {1}[Hardware Error]: Error 0, type: recoverable
[ 403.304920] {1}[Hardware Error]: section_type: memory error
[ 403.306645] {1}[Hardware Error]: physical_address: 0x00000002317b2000
[ 403.308947] {1}[Hardware Error]: error_type: 0, unknown
[ 403.310630] WARNING: CPU: 0 PID: 510 at drivers/edac/ghes_edac.c:202 ghes_edac_report_mem_error+0x648/0xb20
[ 403.310630] Modules linked in:
[ 403.310631] CPU: 0 PID: 510 Comm: mca-recover Not tainted 4.19.0+ #8
[ 403.310632] Hardware name: QEMU KVM Virtual Machine, BIOS 0.0.0 02/06/2015
[ 403.310632] pstate: 60000005 (nZCv daif -PAN -UAO)
[ 403.310632] pc : ghes_edac_report_mem_error+0x648/0xb20
[ 403.310633] lr : ghes_proc+0x3d8/0x950
[ 403.310633] sp : ffff00000c543b20
[ 403.310633] x29: ffff00000c543b50 x28: ffff8001f5918014
[ 403.310634] x27: 0000000000000000 x26: b1837ced833e63b8
[ 403.310635] x25: 430fbbc1d995e954 x24: 0000000000000002
[ 403.310636] x23: 0000000000000002 x22: ffff0000096ec000
[ 403.310637] x21: ffff000009379000 x20: ffff8001f591805c
[ 403.310638] x19: ffff8001f591e71c x18: ffffffffffffffff
[ 403.310638] x17: 0000000000000000 x16: 0000000000000000
[ 403.310639] x15: ffff000009379708 x14: 0000000000000000
[ 403.310640] x13: 0000000000000002 x12: 317b200000000000
[ 403.310641] x11: 0000000000000000 x10: 0000400200000000
[ 403.310642] x9 : 0000000000000000 x8 : 00000002540be3ff
[ 403.310642] x7 : 0000000000000000 x6 : ffff0000096dce30
[ 403.310643] x5 : 4ede6f64a5bc1114 x4 : 0000000000000000
[ 403.310644] x3 : ffff0000096ec4f0 x2 : ffff8001f591805c
[ 403.310645] x1 : 0000000000000000 x0 : 0000000000110000
[ 403.310646] Call trace:
[ 403.310646] ghes_edac_report_mem_error+0x648/0xb20
[ 403.310646] ghes_proc+0x3d8/0x950
[ 403.310647] ghes_notify_sea+0x3c/0x68
[ 403.310647] do_sea+0x9c/0x188
[ 403.310647] do_mem_abort+0x74/0x140
[ 403.310648] el0_da+0x24/0x28
[ 403.310648] ---[ end trace 651f1abaa6b1de2d ]---
Recover: sig=7 si=0xffffc9bc5640 v=0xffffc9bc56c0[ 403.364295] Memory failure: 0x2317b2: recovery action for dirty LRU page: Recovered
[ 403.364295] Memory failure: 0x2317b2: recovery action for dirty LRU page: Recovered
Platform memory error at 0x(nil)
Addr = (nil) lsb=0
Recovery allocated new page at physical 0x232563000
Got 2a2a2a2a
--
Thanks,
Xiang
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v18 2/6] docs: APEI GHES generation and CPER record description
2019-09-06 8:31 ` [PATCH v18 2/6] docs: APEI GHES generation and CPER record description Xiang Zheng
@ 2019-09-19 13:25 ` Peter Maydell
2019-09-20 1:45 ` Xiang Zheng
2019-10-04 8:20 ` [Qemu-devel] " Igor Mammedov
1 sibling, 1 reply; 26+ messages in thread
From: Peter Maydell @ 2019-09-19 13:25 UTC (permalink / raw)
To: Xiang Zheng
Cc: Paolo Bonzini, Michael S. Tsirkin, Igor Mammedov, Shannon Zhao,
Laszlo Ersek, James Morse, gengdongjiu, Marcelo Tosatti,
Richard Henderson, Eduardo Habkost, Jonathan Cameron, xuwei (O),
kvm-devel, QEMU Developers, qemu-arm, Linuxarm, wanghaibin.wang
On Fri, 6 Sep 2019 at 09:33, Xiang Zheng <zhengxiang9@huawei.com> wrote:
>
> From: Dongjiu Geng <gengdongjiu@huawei.com>
>
> Add APEI/GHES detailed design document
>
> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
> Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
> ---
> docs/specs/acpi_hest_ghes.txt | 88 +++++++++++++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
> create mode 100644 docs/specs/acpi_hest_ghes.txt
Hi; new documentation in docs/specs should be in rst format and
listed in the contents page for the manual at docs/specs/index.rst,
please. Conversion from plain text should hopefully be fairly
straightforward.
I've also provided some minor typo/grammar fixes below.
> diff --git a/docs/specs/acpi_hest_ghes.txt b/docs/specs/acpi_hest_ghes.txt
> new file mode 100644
> index 0000000000..690d4b2bd0
> --- /dev/null
> +++ b/docs/specs/acpi_hest_ghes.txt
> @@ -0,0 +1,88 @@
> +APEI tables generating and CPER record
> +=============================
> +
> +Copyright (C) 2019 Huawei Corporation.
> +
> +Design Details:
> +-------------------
> +
> + etc/acpi/tables etc/hardware_errors
> + ==================== ==========================================
> ++ +--------------------------+ +-----------------------+
> +| | HEST | | address | +--------------+
> +| +--------------------------+ | registers | | Error Status |
> +| | GHES1 | | +---------------------+ | Data Block 1 |
> +| +--------------------------+ +--------->| |error_block_address1 |----------->| +------------+
> +| | ................. | | | +---------------------+ | | CPER |
> +| | error_status_address-----+-+ +------->| |error_block_address2 |--------+ | | CPER |
> +| | ................. | | | +---------------------+ | | | .... |
> +| | read_ack_register--------+-+ | | | .............. | | | | CPER |
> +| | read_ack_preserve | | | +-----------------------+ | | +------------+
> +| | read_ack_write | | | +----->| |error_block_addressN |------+ | | Error Status |
> ++ +--------------------------+ | | | | +---------------------+ | | | Data Block 2 |
> +| | GHES2 | +-+-+----->| |read_ack_register1 | | +-->| +------------+
> ++ +--------------------------+ | | | +---------------------+ | | | CPER |
> +| | ................. | | | +--->| |read_ack_register2 | | | | CPER |
> +| | error_status_address-----+---+ | | | +---------------------+ | | | .... |
> +| | ................. | | | | | ............. | | | | CPER |
> +| | read_ack_register--------+-----+-+ | +---------------------+ | +-+------------+
> +| | read_ack_preserve | | +->| |read_ack_registerN | | | |.......... |
> +| | read_ack_write | | | | +---------------------+ | | +------------+
> ++ +--------------------------| | | | | Error Status |
> +| | ............... | | | | | Data Block N |
> ++ +--------------------------+ | | +---->| +------------+
> +| | GHESN | | | | | CPER |
> ++ +--------------------------+ | | | | CPER |
> +| | ................. | | | | | .... |
> +| | error_status_address-----+-----+ | | | CPER |
> +| | ................. | | +-+------------+
> +| | read_ack_register--------+---------+
> +| | read_ack_preserve |
> +| | read_ack_write |
> ++ +--------------------------+
> +
> +(1) QEMU generates the ACPI HEST table. This table goes in the current
> + "etc/acpi/tables" fw_cfg blob. Each error source has different
> + notification types.
> +
> +(2) A new fw_cfg blob called "etc/hardware_errors" is introduced. QEMU
> + also need to populate this blob. The "etc/hardwre_errors" fw_cfg blob
"needs". "hardware_errors".
> + contains an address registers table and an Error Status Data Block table.
> +
> +(3) The address registers table contains N Error Block Address entries
> + and N Read Ack Register entries, the size for each entry is 8-byte.
". The size".
> + The Error Status Data Block table contains N Error Status Data Block
> + entries, the size for each entry is 4096(0x1000) bytes. The total size
". The size"
> + for "etc/hardware_errors" fw_cfg blob is (N * 8 * 2 + N * 4096) bytes.
"for the"
> + N is the kinds of hardware error sources.
Not sure what you had in mind here. Possibly either "N is the number of kinds of
hardware error sources" or "N is the number of hardware error sources" ?
> +
> +(4) QEMU generates the ACPI linker/loader script for the firmware, the
". The"
> + firmware pre-allocates memory for "etc/acpi/tables", "etc/hardware_errors"
> + and copies blobs content there.
"blob contents"
> +
> +(5) QEMU generates N ADD_POINTER commands, which patch address in the
"addresses"
> + "error_status_address" fields of the HEST table with a pointer to the
> + corresponding "address registers" in "etc/hardware_errors" blob.
"in the"
> +
> +(6) QEMU generates N ADD_POINTER commands, which patch address in the
"addresses"
> + "read_ack_register" fields of the HEST table with a pointer to the
> + corresponding "address registers" in "etc/hardware_errors" blob.
"in the"
> +
> +(7) QEMU generates N ADD_POINTER commands for the firmware, which patch
> + address in the " error_block_address" fields with a pointer to the
"addresses". Stray extra space after open-quote.
> + respective "Error Status Data Block" in "etc/hardware_errors" blob.
"in the"
> +
> +(8) QEMU defines a third and write-only fw_cfg blob which is called
> + "etc/hardware_errors_addr". Through that blob, the firmware can send back
> + the guest-side allocation addresses to QEMU. The "etc/hardware_errors_addr"
> + blob contains a 8-byte entry. QEMU generates a single WRITE_POINTER commands
"command"
> + for the firmware, the firmware will write back the start address of
". The"
> + "etc/hardware_errors" blob to fw_cfg file "etc/hardware_errors_addr".
"to the fw_cfg file"
> +
> +(9) When QEMU gets SIGBUS from the kernel, QEMU formats the CPER right into
"a SIGBUS"
> + guest memory, and then injects whatever interrupt (or assert whatever GPIO
"or asserts"
> + line) as a notification which is necessary for notifying the guest.
> +
> +(10) This notification (in virtual hardware) will be handled by guest kernel,
"the guest kernel"
> + guest APEI driver will read the CPER which is recorded by QEMU and do the
"and the guest APEI driver"
> + recovery.
thanks
-- PMM
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v18 2/6] docs: APEI GHES generation and CPER record description
2019-09-19 13:25 ` Peter Maydell
@ 2019-09-20 1:45 ` Xiang Zheng
0 siblings, 0 replies; 26+ messages in thread
From: Xiang Zheng @ 2019-09-20 1:45 UTC (permalink / raw)
To: Peter Maydell
Cc: Paolo Bonzini, Michael S. Tsirkin, Igor Mammedov, Shannon Zhao,
Laszlo Ersek, James Morse, gengdongjiu, Marcelo Tosatti,
Richard Henderson, Eduardo Habkost, Jonathan Cameron, xuwei (O),
kvm-devel, QEMU Developers, qemu-arm, Linuxarm, wanghaibin.wang
Hi Peter, thanks for your review!
On 2019/9/19 21:25, Peter Maydell wrote:
> On Fri, 6 Sep 2019 at 09:33, Xiang Zheng <zhengxiang9@huawei.com> wrote:
>>
>> From: Dongjiu Geng <gengdongjiu@huawei.com>
>>
>> Add APEI/GHES detailed design document
>>
>> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
>> Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
>> ---
>> docs/specs/acpi_hest_ghes.txt | 88 +++++++++++++++++++++++++++++++++++
>> 1 file changed, 88 insertions(+)
>> create mode 100644 docs/specs/acpi_hest_ghes.txt
>
> Hi; new documentation in docs/specs should be in rst format and
> listed in the contents page for the manual at docs/specs/index.rst,
> please. Conversion from plain text should hopefully be fairly
> straightforward.
>
Got it!
>
> I've also provided some minor typo/grammar fixes below.
>
Thanks, I will fix them soon.
>
>> diff --git a/docs/specs/acpi_hest_ghes.txt b/docs/specs/acpi_hest_ghes.txt
>> new file mode 100644
>> index 0000000000..690d4b2bd0
>> --- /dev/null
>> +++ b/docs/specs/acpi_hest_ghes.txt
>> @@ -0,0 +1,88 @@
>> +APEI tables generating and CPER record
>> +=============================
>> +
>> +Copyright (C) 2019 Huawei Corporation.
>> +
>> +Design Details:
>> +-------------------
>> +
>> + etc/acpi/tables etc/hardware_errors
>> + ==================== ==========================================
>> ++ +--------------------------+ +-----------------------+
>> +| | HEST | | address | +--------------+
>> +| +--------------------------+ | registers | | Error Status |
>> +| | GHES1 | | +---------------------+ | Data Block 1 |
>> +| +--------------------------+ +--------->| |error_block_address1 |----------->| +------------+
>> +| | ................. | | | +---------------------+ | | CPER |
>> +| | error_status_address-----+-+ +------->| |error_block_address2 |--------+ | | CPER |
>> +| | ................. | | | +---------------------+ | | | .... |
>> +| | read_ack_register--------+-+ | | | .............. | | | | CPER |
>> +| | read_ack_preserve | | | +-----------------------+ | | +------------+
>> +| | read_ack_write | | | +----->| |error_block_addressN |------+ | | Error Status |
>> ++ +--------------------------+ | | | | +---------------------+ | | | Data Block 2 |
>> +| | GHES2 | +-+-+----->| |read_ack_register1 | | +-->| +------------+
>> ++ +--------------------------+ | | | +---------------------+ | | | CPER |
>> +| | ................. | | | +--->| |read_ack_register2 | | | | CPER |
>> +| | error_status_address-----+---+ | | | +---------------------+ | | | .... |
>> +| | ................. | | | | | ............. | | | | CPER |
>> +| | read_ack_register--------+-----+-+ | +---------------------+ | +-+------------+
>> +| | read_ack_preserve | | +->| |read_ack_registerN | | | |.......... |
>> +| | read_ack_write | | | | +---------------------+ | | +------------+
>> ++ +--------------------------| | | | | Error Status |
>> +| | ............... | | | | | Data Block N |
>> ++ +--------------------------+ | | +---->| +------------+
>> +| | GHESN | | | | | CPER |
>> ++ +--------------------------+ | | | | CPER |
>> +| | ................. | | | | | .... |
>> +| | error_status_address-----+-----+ | | | CPER |
>> +| | ................. | | +-+------------+
>> +| | read_ack_register--------+---------+
>> +| | read_ack_preserve |
>> +| | read_ack_write |
>> ++ +--------------------------+
>> +
>> +(1) QEMU generates the ACPI HEST table. This table goes in the current
>> + "etc/acpi/tables" fw_cfg blob. Each error source has different
>> + notification types.
>> +
>> +(2) A new fw_cfg blob called "etc/hardware_errors" is introduced. QEMU
>> + also need to populate this blob. The "etc/hardwre_errors" fw_cfg blob
>
> "needs". "hardware_errors".
>
>> + contains an address registers table and an Error Status Data Block table.
>> +
>> +(3) The address registers table contains N Error Block Address entries
>> + and N Read Ack Register entries, the size for each entry is 8-byte.
>
> ". The size".
>
>> + The Error Status Data Block table contains N Error Status Data Block
>> + entries, the size for each entry is 4096(0x1000) bytes. The total size
>
>
> ". The size"
>
>> + for "etc/hardware_errors" fw_cfg blob is (N * 8 * 2 + N * 4096) bytes.
>
> "for the"
>
>> + N is the kinds of hardware error sources.
>
> Not sure what you had in mind here. Possibly either "N is the number of kinds of
> hardware error sources" or "N is the number of hardware error sources" ?
Yes, I mean "N is the number of kinds of hardware error sources".
>
>> +
>> +(4) QEMU generates the ACPI linker/loader script for the firmware, the
>
> ". The"
>
>> + firmware pre-allocates memory for "etc/acpi/tables", "etc/hardware_errors"
>> + and copies blobs content there.
>
> "blob contents"
>
>> +
>> +(5) QEMU generates N ADD_POINTER commands, which patch address in the
>
> "addresses"
>
>> + "error_status_address" fields of the HEST table with a pointer to the
>> + corresponding "address registers" in "etc/hardware_errors" blob.
>
> "in the"
>
>> +
>> +(6) QEMU generates N ADD_POINTER commands, which patch address in the
>
> "addresses"
>
>> + "read_ack_register" fields of the HEST table with a pointer to the
>> + corresponding "address registers" in "etc/hardware_errors" blob.
>
> "in the"
>
>> +
>> +(7) QEMU generates N ADD_POINTER commands for the firmware, which patch
>> + address in the " error_block_address" fields with a pointer to the
>
> "addresses". Stray extra space after open-quote.
>
>> + respective "Error Status Data Block" in "etc/hardware_errors" blob.
>
> "in the"
>
>> +
>> +(8) QEMU defines a third and write-only fw_cfg blob which is called
>> + "etc/hardware_errors_addr". Through that blob, the firmware can send back
>> + the guest-side allocation addresses to QEMU. The "etc/hardware_errors_addr"
>> + blob contains a 8-byte entry. QEMU generates a single WRITE_POINTER commands
>
> "command"
>
>> + for the firmware, the firmware will write back the start address of
>
> ". The"
>
>> + "etc/hardware_errors" blob to fw_cfg file "etc/hardware_errors_addr".
>
> "to the fw_cfg file"
>
>> +
>> +(9) When QEMU gets SIGBUS from the kernel, QEMU formats the CPER right into
>
> "a SIGBUS"
>
>> + guest memory, and then injects whatever interrupt (or assert whatever GPIO
>
> "or asserts"
>
>> + line) as a notification which is necessary for notifying the guest.
>> +
>> +(10) This notification (in virtual hardware) will be handled by guest kernel,
>
> "the guest kernel"
>
>> + guest APEI driver will read the CPER which is recorded by QEMU and do the
>
> "and the guest APEI driver"
>
>> + recovery.
>
> thanks
> -- PMM
>
> .
>
--
Thanks,
Xiang
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v18 0/6] Add ARMv8 RAS virtualization support in QEMU
2019-09-17 12:39 ` [PATCH v18 0/6] Add ARMv8 RAS virtualization support in QEMU Xiang Zheng
@ 2019-09-20 2:07 ` gengdongjiu
0 siblings, 0 replies; 26+ messages in thread
From: gengdongjiu @ 2019-09-20 2:07 UTC (permalink / raw)
To: Xiang Zheng, pbonzini, mst, imammedo, shannon.zhaosl,
peter.maydell, lersek, james.morse, mtosatti, rth, ehabkost,
jonathan.cameron, xuwei5, kvm, qemu-devel, qemu-arm, linuxarm
Cc: wanghaibin.wang
Thanks xiang's continue upstream and test.
Hope maintainer can review it.
On 2019/9/17 20:39, Xiang Zheng wrote:
> Hi all,
>
> This patch series has been tested for both TCG and KVM scenes.
>
> 1) Test for TCG:
> - Re-compile qemu after applying the patch refered to https://patchwork.kernel.org/cover/10942757/#22640271).
> - Use command line shown below to start qemu:
> ./qemu-system-aarch64 \
> -name guest=ras \
> -machine virt,gic-version=3,ras=on \
> -cpu cortex-a57 \
> -bios /usr/share/edk2/aarch64/QEMU_EFI.fd \
> -nodefaults \
> -kernel ${GUEST_KERNEL} \
> -initrd ${GUEST_FS} \
> -append "rdinit=init console=ttyAMA0 earlycon=pl011,0x9000000" \
> -m 8192 \
> -smp 4 \
> -serial stdio \
>
> - Send a signal to one of the VCPU threads:
> kill -s SIGBUS 71571
>
> - The result of test is shown below:
>
> [ 41.194753] {1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 0
> [ 41.197329] {1}[Hardware Error]: event severity: recoverable
> [ 41.199078] {1}[Hardware Error]: Error 0, type: recoverable
> [ 41.200829] {1}[Hardware Error]: section_type: memory error
> [ 41.202603] {1}[Hardware Error]: physical_address: 0x00000000400a1000
> [ 41.204649] {1}[Hardware Error]: error_type: 0, unknown
> [ 41.206328] EDAC MC0: 1 UE Unknown on unknown label ( page:0x400a1 offset:0x0 grain:0)
> [ 41.208788] Internal error: synchronous external abort: 96000410 [#1] SMP
> [ 41.210879] Modules linked in:
> [ 41.211823] CPU: 2 PID: 0 Comm: swapper/2 Not tainted 4.19.0+ #8
> [ 41.213698] Hardware name: QEMU KVM Virtual Machine, BIOS 0.0.0 02/06/2015
> [ 41.215812] pstate: 60c00085 (nZCv daIf +PAN +UAO)
> [ 41.217296] pc : cpu_do_idle+0x8/0xc
> [ 41.218400] lr : arch_cpu_idle+0x2c/0x1b8
> [ 41.219629] sp : ffff000009f9bf00
> [ 41.220649] x29: ffff000009f9bf00 x28: 0000000000000000
> [ 41.222310] x27: 0000000000000000 x26: ffff8001fe471d80
> [ 41.223945] x25: 0000000000000000 x24: ffff00000937ba38
> [ 41.225581] x23: ffff0000090b3338 x22: ffff000009379000
> [ 41.227220] x21: ffff00000937b000 x20: 0000000000000004
> [ 41.228871] x19: ffff0000090a6000 x18: 0000000000000000
> [ 41.230517] x17: 0000000000000000 x16: 0000000000000000
> [ 41.232165] x15: 0000000000000000 x14: 0000000000000000
> [ 41.233810] x13: ffff0000089f4da8 x12: 000000000000000e
> [ 41.235448] x11: ffff0000089f4d80 x10: 0000000000000af0
> [ 41.237101] x9 : ffff000009f9be80 x8 : ffff8001fe4728d0
> [ 41.238738] x7 : 0000000000000004 x6 : ffff8001fffbaf30
> [ 41.240380] x5 : ffff00000c43b940 x4 : 00008001f6f0c000
> [ 41.242030] x3 : 0000000000000001 x2 : ffff000009f9bf00
> [ 41.243666] x1 : ffff8001fffb82c8 x0 : ffff0000090a6018
> [ 41.245306] Process swapper/2 (pid: 0, stack limit = 0x(____ptrval____))
> [ 41.247378] Call trace:
> [ 41.248117] cpu_do_idle+0x8/0xc
> [ 41.249111] do_idle+0x1dc/0x2a8
> [ 41.250111] cpu_startup_entry+0x28/0x30
> [ 41.251319] secondary_start_kernel+0x180/0x1c8
> [ 41.252725] Code: a8c17bfd d65f03c0 d5033f9f d503207f (d65f03c0)
> [ 41.254606] ---[ end trace 221bc8a614fb5a1d ]---
> [ 41.256030] Kernel panic - not syncing: Fatal exception
> [ 41.257644] SMP: stopping secondary CPUs
> [ 41.258912] Kernel Offset: disabled
> [ 41.260011] CPU features: 0x0,22a00238
> [ 41.261178] Memory Limit: none
> [ 41.262122] ---[ end Kernel panic - not syncing: Fatal exception ]---
>
> 2) Test for KVM:
> - Use command line shown below to start qemu:
> ./qemu-system-aarch64 \
> -name guest=ras \
> -machine virt,accel=kvm,gic-version=3,ras=on \
> -cpu host \
> -bios /usr/share/edk2/aarch64/QEMU_EFI.fd \
> -nodefaults \
> -kernel ${GUEST_KERNEL} \
> -initrd ${GUEST_FS} \
> -append "rdinit=init console=ttyAMA0 earlycon=pl011,0x9000000" \
> -m 8192 \
> -smp 4 \
> -serial stdio \
>
> - Run mca-recover and get the GPA(IPA) of allocated page which would be corrupted on the later.
> - Convert the GPA to HPA and corrupt this HPA via APEI/EINJ.
> - Go back to guest and continue to read this page.
>
> - The result of test is shown below:
>
> root@genericarmv8:~/tools# ./mca-recover
> pagesize: 0x1000
> before clear cache
> flags for page 0x2317b2: uptodate active mmap anon swapbacked
> vtop(0xffff9c9e8000) = 0x2317b2000
> Hit any key to access: before read
>
> after read
> Access at Tue Sep 17 01:41:14 2019
>
> flags for page 0x2317b2: uptodate active mmap anon swapbacked
> [ 403.298539] {1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 0
> [ 403.301421] {1}[Hardware Error]: event severity: recoverable
> [ 403.303217] {1}[Hardware Error]: Error 0, type: recoverable
> [ 403.304920] {1}[Hardware Error]: section_type: memory error
> [ 403.306645] {1}[Hardware Error]: physical_address: 0x00000002317b2000
> [ 403.308947] {1}[Hardware Error]: error_type: 0, unknown
> [ 403.310630] WARNING: CPU: 0 PID: 510 at drivers/edac/ghes_edac.c:202 ghes_edac_report_mem_error+0x648/0xb20
> [ 403.310630] Modules linked in:
> [ 403.310631] CPU: 0 PID: 510 Comm: mca-recover Not tainted 4.19.0+ #8
> [ 403.310632] Hardware name: QEMU KVM Virtual Machine, BIOS 0.0.0 02/06/2015
> [ 403.310632] pstate: 60000005 (nZCv daif -PAN -UAO)
> [ 403.310632] pc : ghes_edac_report_mem_error+0x648/0xb20
> [ 403.310633] lr : ghes_proc+0x3d8/0x950
> [ 403.310633] sp : ffff00000c543b20
> [ 403.310633] x29: ffff00000c543b50 x28: ffff8001f5918014
> [ 403.310634] x27: 0000000000000000 x26: b1837ced833e63b8
> [ 403.310635] x25: 430fbbc1d995e954 x24: 0000000000000002
> [ 403.310636] x23: 0000000000000002 x22: ffff0000096ec000
> [ 403.310637] x21: ffff000009379000 x20: ffff8001f591805c
> [ 403.310638] x19: ffff8001f591e71c x18: ffffffffffffffff
> [ 403.310638] x17: 0000000000000000 x16: 0000000000000000
> [ 403.310639] x15: ffff000009379708 x14: 0000000000000000
> [ 403.310640] x13: 0000000000000002 x12: 317b200000000000
> [ 403.310641] x11: 0000000000000000 x10: 0000400200000000
> [ 403.310642] x9 : 0000000000000000 x8 : 00000002540be3ff
> [ 403.310642] x7 : 0000000000000000 x6 : ffff0000096dce30
> [ 403.310643] x5 : 4ede6f64a5bc1114 x4 : 0000000000000000
> [ 403.310644] x3 : ffff0000096ec4f0 x2 : ffff8001f591805c
> [ 403.310645] x1 : 0000000000000000 x0 : 0000000000110000
> [ 403.310646] Call trace:
> [ 403.310646] ghes_edac_report_mem_error+0x648/0xb20
> [ 403.310646] ghes_proc+0x3d8/0x950
> [ 403.310647] ghes_notify_sea+0x3c/0x68
> [ 403.310647] do_sea+0x9c/0x188
> [ 403.310647] do_mem_abort+0x74/0x140
> [ 403.310648] el0_da+0x24/0x28
> [ 403.310648] ---[ end trace 651f1abaa6b1de2d ]---
> Recover: sig=7 si=0xffffc9bc5640 v=0xffffc9bc56c0[ 403.364295] Memory failure: 0x2317b2: recovery action for dirty LRU page: Recovered
> [ 403.364295] Memory failure: 0x2317b2: recovery action for dirty LRU page: Recovered
>
> Platform memory error at 0x(nil)
> Addr = (nil) lsb=0
> Recovery allocated new page at physical 0x232563000
> Got 2a2a2a2a
>
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Qemu-arm] [PATCH v18 4/6] KVM: Move hwpoison page related functions into include/sysemu/kvm_int.h
2019-09-06 8:31 ` [PATCH v18 4/6] KVM: Move hwpoison page related functions into include/sysemu/kvm_int.h Xiang Zheng
@ 2019-09-27 13:19 ` Peter Maydell
2019-10-08 7:01 ` Xiang Zheng
0 siblings, 1 reply; 26+ messages in thread
From: Peter Maydell @ 2019-09-27 13:19 UTC (permalink / raw)
To: Xiang Zheng
Cc: Paolo Bonzini, Michael S. Tsirkin, Igor Mammedov, Shannon Zhao,
Laszlo Ersek, James Morse, gengdongjiu, Marcelo Tosatti,
Richard Henderson, Eduardo Habkost, Jonathan Cameron, xuwei (O),
kvm-devel, QEMU Developers, qemu-arm, Linuxarm, wanghaibin.wang
On Fri, 6 Sep 2019 at 09:33, Xiang Zheng <zhengxiang9@huawei.com> wrote:
>
> From: Dongjiu Geng <gengdongjiu@huawei.com>
>
> kvm_hwpoison_page_add() and kvm_unpoison_all() will both be used by X86
> and ARM platforms, so moving them into "include/sysemu/kvm_int.h" to
> avoid duplicate code.
>
> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
> Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
> ---
> accel/kvm/kvm-all.c | 33 +++++++++++++++++++++++++++++++++
> include/sysemu/kvm_int.h | 23 +++++++++++++++++++++++
> target/arm/kvm.c | 3 +++
> target/i386/kvm.c | 34 ----------------------------------
> 4 files changed, 59 insertions(+), 34 deletions(-)
> static uint32_t adjust_ioeventfd_endianness(uint32_t val, uint32_t size)
> {
> #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
> diff --git a/include/sysemu/kvm_int.h b/include/sysemu/kvm_int.h
> index 72b2d1b3ae..3ad49f9a28 100644
> --- a/include/sysemu/kvm_int.h
> +++ b/include/sysemu/kvm_int.h
> @@ -41,4 +41,27 @@ typedef struct KVMMemoryListener {
> void kvm_memory_listener_register(KVMState *s, KVMMemoryListener *kml,
> AddressSpace *as, int as_id);
>
> +/**
> + * kvm_hwpoison_page_add:
> + *
> + * Parameters:
> + * @ram_addr: the address in the RAM for the poisoned page
> + *
> + * Add a poisoned page to the list
> + *
> + * Return: None.
> + */
> +void kvm_hwpoison_page_add(ram_addr_t ram_addr);
> +
> +/**
> + * kvm_unpoison_all:
> + *
> + * Parameters:
> + * @param: some data may be passed to this function
> + *
> + * Free and remove all the poisoned pages in the list
> + *
> + * Return: None.
> + */
> +void kvm_unpoison_all(void *param);
> #endif
> diff --git a/target/arm/kvm.c b/target/arm/kvm.c
> index b2eaa50b8d..3a110be7b8 100644
> --- a/target/arm/kvm.c
> +++ b/target/arm/kvm.c
> @@ -20,6 +20,7 @@
> #include "sysemu/sysemu.h"
> #include "sysemu/kvm.h"
> #include "sysemu/kvm_int.h"
> +#include "sysemu/reset.h"
> #include "kvm_arm.h"
> #include "cpu.h"
> #include "trace.h"
> @@ -195,6 +196,8 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
>
> cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE);
>
> + qemu_register_reset(kvm_unpoison_all, NULL);
> +
Rather than registering the same reset handler in
all the architectures, we could register it in the
generic kvm_init() function. (For architectures that
don't use the poison-list functionality the reset handler
will harmlessly do nothing, because there will be nothing
in the list.)
This would allow you to not have to make the
kvm_unpoison_all() function global -- it can be static
in accel/tcg/kvm-all.c.
> return 0;
> }
thanks
-- PMM
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v18 5/6] target-arm: kvm64: inject synchronous External Abort
2019-09-06 8:31 ` [PATCH v18 5/6] target-arm: kvm64: inject synchronous External Abort Xiang Zheng
@ 2019-09-27 13:33 ` Peter Maydell
2019-10-08 8:05 ` Xiang Zheng
0 siblings, 1 reply; 26+ messages in thread
From: Peter Maydell @ 2019-09-27 13:33 UTC (permalink / raw)
To: Xiang Zheng
Cc: Paolo Bonzini, Michael S. Tsirkin, Igor Mammedov, Shannon Zhao,
Laszlo Ersek, James Morse, gengdongjiu, Marcelo Tosatti,
Richard Henderson, Eduardo Habkost, Jonathan Cameron, xuwei (O),
kvm-devel, QEMU Developers, qemu-arm, Linuxarm, wanghaibin.wang
On Fri, 6 Sep 2019 at 09:33, Xiang Zheng <zhengxiang9@huawei.com> wrote:
>
> From: Dongjiu Geng <gengdongjiu@huawei.com>
>
> Introduce kvm_inject_arm_sea() function in which we will setup the type
> of exception and the syndrome information in order to inject a virtual
> synchronous external abort. When switching to guest, it will jump to the
> synchronous external abort vector table entry.
>
> The ESR_ELx.DFSC is set to synchronous external abort(0x10), and
> ESR_ELx.FnV is set to not valid(0x1), which will tell guest that FAR is
> not valid and hold an UNKNOWN value. These values will be set to KVM
> register structures through KVM_SET_ONE_REG IOCTL.
>
> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
> Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
> +/* Inject synchronous external abort */
> +static void kvm_inject_arm_sea(CPUState *c)
This will cause a compilation failure at this point in
the patch series, because the compiler will complain about
a static function which is defined but never used.
To avoid breaking bisection, we need to put the definition
of the function in the same patch where it's used.
> +{
> + ARMCPU *cpu = ARM_CPU(c);
> + CPUARMState *env = &cpu->env;
> + CPUClass *cc = CPU_GET_CLASS(c);
> + uint32_t esr;
> + bool same_el;
> +
> + /**
> + * Set the exception type to synchronous data abort
> + * and the target exception Level to EL1.
> + */
This comment doesn't really tell us anything that's not obvious
from the two lines of code that it's commenting on:
> + c->exception_index = EXCP_DATA_ABORT;
> + env->exception.target_el = 1;
> +
> + /*
> + * Set the DFSC to synchronous external abort and set FnV to not valid,
> + * this will tell guest the FAR_ELx is UNKNOWN for this abort.
> + */
> +
> + /* This exception comes from lower or current exception level. */
This comment too is stating the obvious I think.
> + same_el = arm_current_el(env) == env->exception.target_el;
> + esr = syn_data_abort_no_iss(same_el, 1, 0, 0, 0, 0, 0x10);
> +
> + env->exception.syndrome = esr;
> +
> + /**
There's a stray second '*' in this comment-start.
> + * The vcpu thread already hold BQL, so no need hold again when
> + * calling do_interrupt
I think this requirement would be better placed as a
comment at the top of the function noting that callers
must hold the iothread lock.
> + */
> + cc->do_interrupt(c);
> +}
> +
> #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
> KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
>
> diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
> index 5feb312941..499672ebbc 100644
> --- a/target/arm/tlb_helper.c
> +++ b/target/arm/tlb_helper.c
> @@ -33,7 +33,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
> * ISV field.
> */
> if (!(template_syn & ARM_EL_ISV) || target_el != 2 || s1ptw) {
> - syn = syn_data_abort_no_iss(same_el,
> + syn = syn_data_abort_no_iss(same_el, 0,
> ea, 0, s1ptw, is_write, fsc);
> } else {
> /*
> --
> 2.19.1
thanks
-- PMM
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v18 6/6] target-arm: kvm64: handle SIGBUS signal from kernel or KVM
2019-09-06 8:31 ` [PATCH v18 6/6] target-arm: kvm64: handle SIGBUS signal from kernel or KVM Xiang Zheng
@ 2019-09-27 13:57 ` Peter Maydell
2019-10-08 12:42 ` Xiang Zheng
0 siblings, 1 reply; 26+ messages in thread
From: Peter Maydell @ 2019-09-27 13:57 UTC (permalink / raw)
To: Xiang Zheng
Cc: Paolo Bonzini, Michael S. Tsirkin, Igor Mammedov, Shannon Zhao,
Laszlo Ersek, James Morse, gengdongjiu, Marcelo Tosatti,
Richard Henderson, Eduardo Habkost, Jonathan Cameron, xuwei (O),
kvm-devel, QEMU Developers, qemu-arm, Linuxarm, wanghaibin.wang
On Fri, 6 Sep 2019 at 09:33, Xiang Zheng <zhengxiang9@huawei.com> wrote:
>
> From: Dongjiu Geng <gengdongjiu@huawei.com>
>
> Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type,
> translates the host VA delivered by host to guest PA, then fills this PA
> to guest APEI GHES memory, then notifies guest according to the SIGBUS
> type.
>
> If guest accesses the poisoned memory, it generates Synchronous External
> Abort(SEA). Then host kernel gets an APEI notification and calls
> memory_failure() to unmapped the affected page in stage 2, finally
> returns to guest.
>
> Guest continues to access PG_hwpoison page, it will trap to KVM as
> stage2 fault, then a SIGBUS_MCEERR_AR synchronous signal is delivered to
> Qemu, Qemu records this error address into guest APEI GHES memory and
> notifes guest using Synchronous-External-Abort(SEA).
>
> Suggested-by: James Morse <james.morse@arm.com>
> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
> Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
> ---
> hw/acpi/acpi_ghes.c | 252 ++++++++++++++++++++++++++++++++++++
> include/hw/acpi/acpi_ghes.h | 40 ++++++
> include/sysemu/kvm.h | 2 +-
> target/arm/kvm64.c | 39 ++++++
> 4 files changed, 332 insertions(+), 1 deletion(-)
I'll let somebody else review the ACPI parts as that's not my
area of expertise, but I'll look at the target/arm parts below:
> diff --git a/hw/acpi/acpi_ghes.c b/hw/acpi/acpi_ghes.c
> index 20c45179ff..2d17c88045 100644
> --- a/hw/acpi/acpi_ghes.c
> +++ b/hw/acpi/acpi_ghes.c
> @@ -26,6 +26,168 @@
> #include "sysemu/sysemu.h"
> #include "qemu/error-report.h"
>
> +/* Total size for Generic Error Status Block
This block comment should start with '/*' on a line of its own
(as should others in this patch). Usually checkpatch catches these
but it's not infallible.
> diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
> index 909bcd77cf..5f57e4ed43 100644
> --- a/include/sysemu/kvm.h
> +++ b/include/sysemu/kvm.h
> @@ -378,7 +378,7 @@ bool kvm_vcpu_id_is_valid(int vcpu_id);
> /* Returns VCPU ID to be used on KVM_CREATE_VCPU ioctl() */
> unsigned long kvm_arch_vcpu_id(CPUState *cpu);
>
> -#ifdef TARGET_I386
> +#if defined(TARGET_I386) || defined(TARGET_AARCH64)
> #define KVM_HAVE_MCE_INJECTION 1
> void kvm_arch_on_sigbus_vcpu(CPUState *cpu, int code, void *addr);
> #endif
Rather than introducing a new ifdef with lots of TARGET_*,
I think it would be better to have target/i386/cpu.h and
target/arm/cpu.h do "#define KVM_HAVE_MCE_INJECTION 1"
(nb that the arm cpu.h needs to define it only for aarch64,
not for 32-bit arm host compiles).
and then kvm.h can just do
#ifdef KVM_HAVE_MCE_INJECTION
void kvm_arch_on_sigbus_vcpu(CPUState *cpu, int code, void *addr);
#endif
> diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
> index bf6edaa3f6..186d855522 100644
> --- a/target/arm/kvm64.c
> +++ b/target/arm/kvm64.c
> @@ -28,6 +28,8 @@
> #include "kvm_arm.h"
> #include "hw/boards.h"
> #include "internals.h"
> +#include "hw/acpi/acpi.h"
> +#include "hw/acpi/acpi_ghes.h"
>
> static bool have_guest_debug;
>
> @@ -1070,6 +1072,43 @@ int kvm_arch_get_registers(CPUState *cs)
> return ret;
> }
>
> +void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
> +{
> + ram_addr_t ram_addr;
> + hwaddr paddr;
> +
> + assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
> +
> + if (acpi_enabled && addr &&
> + object_property_get_bool(qdev_get_machine(), "ras", NULL)) {
> + ram_addr = qemu_ram_addr_from_host(addr);
> + if (ram_addr != RAM_ADDR_INVALID &&
> + kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
> + kvm_hwpoison_page_add(ram_addr);
> + /* Asynchronous signal will be masked by main thread, so
> + * only handle synchronous signal.
> + */
I don't entirely understand this comment. The x86 version
of this function says:
/* If we get an action required MCE, it has been injected by KVM
* while the VM was running. An action optional MCE instead should
* be coming from the main thread, which qemu_init_sigbus identifies
* as the "early kill" thread.
*/
so we can be called for action-optional MCE here (not on the vcpu
thread). We obviously can't deliver those as a synchronous exception
to a particular CPU, but is there no mechanism for reporting them
to the guest at all?
> + if (code == BUS_MCEERR_AR) {
> + kvm_cpu_synchronize_state(c);
> + if (ACPI_GHES_CPER_FAIL !=
> + acpi_ghes_record_errors(ACPI_GHES_NOTIFY_SEA, paddr)) {
> + kvm_inject_arm_sea(c);
> + } else {
> + fprintf(stderr, "failed to record the error\n");
> + }
> + }
> + return;
> + }
> + fprintf(stderr, "Hardware memory error for memory used by "
> + "QEMU itself instead of guest system!\n");
> + }
> +
> + if (code == BUS_MCEERR_AR) {
> + fprintf(stderr, "Hardware memory error!\n");
> + exit(1);
> + }
> +}
> +
> /* C6.6.29 BRK instruction */
> static const uint32_t brk_insn = 0xd4200000;
>
thanks
-- PMM
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v18 1/6] hw/arm/virt: Introduce RAS platform version and RAS machine option
2019-09-06 8:31 ` [PATCH v18 1/6] hw/arm/virt: Introduce RAS platform version and RAS machine option Xiang Zheng
@ 2019-09-27 14:02 ` Peter Maydell
2019-09-29 2:04 ` Xiang Zheng
0 siblings, 1 reply; 26+ messages in thread
From: Peter Maydell @ 2019-09-27 14:02 UTC (permalink / raw)
To: Xiang Zheng
Cc: Paolo Bonzini, Michael S. Tsirkin, Igor Mammedov, Shannon Zhao,
Laszlo Ersek, James Morse, gengdongjiu, Marcelo Tosatti,
Richard Henderson, Eduardo Habkost, Jonathan Cameron, xuwei (O),
kvm-devel, QEMU Developers, qemu-arm, Linuxarm, wanghaibin.wang
On Fri, 6 Sep 2019 at 09:33, Xiang Zheng <zhengxiang9@huawei.com> wrote:
>
> From: Dongjiu Geng <gengdongjiu@huawei.com>
>
> Support RAS Virtualization feature since version 4.2, disable it by
> default in the old versions. Also add a machine option which allows user
> to enable it explicitly.
>
> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
> Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
> ---
> hw/arm/virt.c | 33 +++++++++++++++++++++++++++++++++
> include/hw/arm/virt.h | 2 ++
> 2 files changed, 35 insertions(+)
>
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index d74538b021..e0451433c8 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -1783,6 +1783,20 @@ static void virt_set_its(Object *obj, bool value, Error **errp)
> vms->its = value;
> }
>
> +static bool virt_get_ras(Object *obj, Error **errp)
> +{
> + VirtMachineState *vms = VIRT_MACHINE(obj);
> +
> + return vms->ras;
> +}
> +
> +static void virt_set_ras(Object *obj, bool value, Error **errp)
> +{
> + VirtMachineState *vms = VIRT_MACHINE(obj);
> +
> + vms->ras = value;
> +}
> +
> static char *virt_get_gic_version(Object *obj, Error **errp)
> {
> VirtMachineState *vms = VIRT_MACHINE(obj);
> @@ -2026,6 +2040,19 @@ static void virt_instance_init(Object *obj)
> "Valid values are none and smmuv3",
> NULL);
>
> + if (vmc->no_ras) {
> + vms->ras = false;
> + } else {
> + /* Default disallows RAS instantiation */
> + vms->ras = false;
> + object_property_add_bool(obj, "ras", virt_get_ras,
> + virt_set_ras, NULL);
> + object_property_set_description(obj, "ras",
> + "Set on/off to enable/disable "
> + "RAS instantiation",
> + NULL);
> + }
For a property which is disabled by default, you don't need
to have a separate flag in the VirtMachineClass struct.
Those are only needed for properties where we need the old machine
types to have the property be 'off' but new machine types
need to default to it be 'on'. Since vms->ras is false
by default anyway, you can just have this part:
> + /* Default disallows RAS instantiation */
> + vms->ras = false;
> + object_property_add_bool(obj, "ras", virt_get_ras,
> + virt_set_ras, NULL);
> + object_property_set_description(obj, "ras",
> + "Set on/off to enable/disable "
> + "RAS instantiation",
> + NULL);
Compare the 'vms->secure' flag and associated property
for an example of this.
> vms->irqmap = a15irqmap;
>
> virt_flash_create(vms);
> @@ -2058,8 +2085,14 @@ DEFINE_VIRT_MACHINE_AS_LATEST(4, 2)
>
> static void virt_machine_4_1_options(MachineClass *mc)
> {
> + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
> +
> virt_machine_4_2_options(mc);
> compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
> + /* Disable memory recovery feature for 4.1 as RAS support was
> + * introduced with 4.2.
> + */
> + vmc->no_ras = true;
> }
> DEFINE_VIRT_MACHINE(4, 1)
thanks
-- PMM
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Qemu-arm] [PATCH v18 0/6] Add ARMv8 RAS virtualization support in QEMU
2019-09-06 8:31 [PATCH v18 0/6] Add ARMv8 RAS virtualization support in QEMU Xiang Zheng
` (6 preceding siblings ...)
2019-09-17 12:39 ` [PATCH v18 0/6] Add ARMv8 RAS virtualization support in QEMU Xiang Zheng
@ 2019-09-27 14:03 ` Peter Maydell
7 siblings, 0 replies; 26+ messages in thread
From: Peter Maydell @ 2019-09-27 14:03 UTC (permalink / raw)
To: Xiang Zheng
Cc: Paolo Bonzini, Michael S. Tsirkin, Igor Mammedov, Shannon Zhao,
Laszlo Ersek, James Morse, gengdongjiu, Marcelo Tosatti,
Richard Henderson, Eduardo Habkost, Jonathan Cameron, xuwei (O),
kvm-devel, QEMU Developers, qemu-arm, Linuxarm, wanghaibin.wang
On Fri, 6 Sep 2019 at 09:33, Xiang Zheng <zhengxiang9@huawei.com> wrote:
>
> In the ARMv8 platform, the CPU error types are synchronous external abort(SEA)
> and SError Interrupt (SEI). If exception happens in guest, sometimes it's better
> for guest to perform the recovery, because host does not know the detailed
> information of guest. For example, if an exception happens in a user-space
> application within guest, host does not know which application encounters
> errors.
>
> For the ARMv8 SEA/SEI, KVM or host kernel delivers SIGBUS to notify userspace.
> After user space gets the notification, it will record the CPER into guest GHES
> buffer and inject an exception or IRQ into guest.
>
> In the current implementation, if the type of SIGBUS is BUS_MCEERR_AR, we will
> treat it as a synchronous exception, and notify guest with ARMv8 SEA
> notification type after recording CPER into guest.
>
> This series of patches are based on Qemu 4.1, which include two parts:
> 1. Generate APEI/GHES table.
> 2. Handle the SIGBUS signal, record the CPER in runtime and fill it into guest
> memory, then notify guest according to the type of SIGBUS.
>
> The whole solution was suggested by James(james.morse@arm.com); The solution of
> APEI section was suggested by Laszlo(lersek@redhat.com).
> Show some discussions in [1].
>
> This series of patches have already been tested on ARM64 platform with RAS
> feature enabled:
> Show the APEI part verification result in [2].
> Show the BUS_MCEERR_AR SIGBUS handling verification result in [3].
>
> ---
>
> Since Dongjiu is too busy to do this work, I will finish the rest work on behalf
> of him.
Thanks for picking up the work on this patchset, and sorry it's taken me
a while to get to reviewing it. I've now given review comments on the
arm parts of this, which are looking in generally good shape (my comments
are all pretty minor stuff I think). I'll have to leave the ACPI parts
to somebody else to review as that is definitely not my speciality.
thanks
-- PMM
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v18 3/6] ACPI: Add APEI GHES table generation support
2019-09-06 8:31 ` [PATCH v18 3/6] ACPI: Add APEI GHES table generation support Xiang Zheng
@ 2019-09-27 15:43 ` Michael S. Tsirkin
2019-10-08 6:00 ` Xiang Zheng
0 siblings, 1 reply; 26+ messages in thread
From: Michael S. Tsirkin @ 2019-09-27 15:43 UTC (permalink / raw)
To: Xiang Zheng
Cc: pbonzini, imammedo, shannon.zhaosl, peter.maydell, lersek,
james.morse, gengdongjiu, mtosatti, rth, ehabkost,
jonathan.cameron, xuwei5, kvm, qemu-devel, qemu-arm, linuxarm,
wanghaibin.wang
On Fri, Sep 06, 2019 at 04:31:49PM +0800, Xiang Zheng wrote:
> From: Dongjiu Geng <gengdongjiu@huawei.com>
>
> This patch implements APEI GHES Table generation via fw_cfg blobs. Now
> it only supports ARMv8 SEA, a type of GHESv2 error source. Afterwards,
> we can extend the supported types if needed. For the CPER section,
> currently it is memory section because kernel mainly wants userspace to
> handle the memory errors.
>
> This patch follows the spec ACPI 6.2 to build the Hardware Error Source
> table. For more detailed information, please refer to document:
> docs/specs/acpi_hest_ghes.txt
>
> Suggested-by: Laszlo Ersek <lersek@redhat.com>
> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
> Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
> ---
> default-configs/arm-softmmu.mak | 1 +
> hw/acpi/Kconfig | 4 +
> hw/acpi/Makefile.objs | 1 +
> hw/acpi/acpi_ghes.c | 210 ++++++++++++++++++++++++++++++++
> hw/acpi/aml-build.c | 2 +
> hw/arm/virt-acpi-build.c | 12 ++
> include/hw/acpi/acpi_ghes.h | 103 ++++++++++++++++
> include/hw/acpi/aml-build.h | 1 +
> 8 files changed, 334 insertions(+)
> create mode 100644 hw/acpi/acpi_ghes.c
> create mode 100644 include/hw/acpi/acpi_ghes.h
>
> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
> index 1f2e0e7fde..5722f3130e 100644
> --- a/default-configs/arm-softmmu.mak
> +++ b/default-configs/arm-softmmu.mak
> @@ -40,3 +40,4 @@ CONFIG_FSL_IMX25=y
> CONFIG_FSL_IMX7=y
> CONFIG_FSL_IMX6UL=y
> CONFIG_SEMIHOSTING=y
> +CONFIG_ACPI_APEI=y
> diff --git a/hw/acpi/Kconfig b/hw/acpi/Kconfig
> index 7c59cf900b..2c4d0b9826 100644
> --- a/hw/acpi/Kconfig
> +++ b/hw/acpi/Kconfig
> @@ -23,6 +23,10 @@ config ACPI_NVDIMM
> bool
> depends on ACPI
>
> +config ACPI_APEI
> + bool
> + depends on ACPI
> +
> config ACPI_PCI
> bool
> depends on ACPI && PCI
> diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs
> index 9bb2101e3b..93fd8e8f64 100644
> --- a/hw/acpi/Makefile.objs
> +++ b/hw/acpi/Makefile.objs
> @@ -5,6 +5,7 @@ common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu_hotplug.o
> common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o
> common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu.o
> common-obj-$(CONFIG_ACPI_NVDIMM) += nvdimm.o
> +common-obj-$(CONFIG_ACPI_APEI) += acpi_ghes.o
> common-obj-$(CONFIG_ACPI_VMGENID) += vmgenid.o
> common-obj-$(call lnot,$(CONFIG_ACPI_X86)) += acpi-stub.o
>
> diff --git a/hw/acpi/acpi_ghes.c b/hw/acpi/acpi_ghes.c
> new file mode 100644
> index 0000000000..20c45179ff
> --- /dev/null
> +++ b/hw/acpi/acpi_ghes.c
> @@ -0,0 +1,210 @@
> +/* Support for generating APEI tables and record CPER for Guests
> + *
> + * Copyright (C) 2019 Huawei Corporation.
> + *
> + * Author: Dongjiu Geng <gengdongjiu@huawei.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> +
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> +
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/acpi/acpi.h"
> +#include "hw/acpi/aml-build.h"
> +#include "hw/acpi/acpi_ghes.h"
> +#include "hw/nvram/fw_cfg.h"
> +#include "sysemu/sysemu.h"
> +#include "qemu/error-report.h"
> +
> +/* Hardware Error Notification
> + * ACPI 4.0: 17.3.2.7 Hardware Error Notification
> + */
> +static void acpi_ghes_build_notify(GArray *table, const uint8_t type,
> + uint8_t length, uint16_t config_write_enable,
> + uint32_t poll_interval, uint32_t vector,
> + uint32_t polling_threshold_value,
> + uint32_t polling_threshold_window,
> + uint32_t error_threshold_value,
> + uint32_t error_threshold_window)
This function has too many arguments.
How about we just hard code all the 0's until we need to set them
to something else?
> +{
> + /* Type */
> + build_append_int_noprefix(table, type, 1);
> + /* Length */
> + build_append_int_noprefix(table, length, 1);
> + /* Configuration Write Enable */
> + build_append_int_noprefix(table, config_write_enable, 2);
> + /* Poll Interval */
> + build_append_int_noprefix(table, poll_interval, 4);
> + /* Vector */
> + build_append_int_noprefix(table, vector, 4);
> + /* Switch To Polling Threshold Value */
> + build_append_int_noprefix(table, polling_threshold_value, 4);
> + /* Switch To Polling Threshold Window */
> + build_append_int_noprefix(table, polling_threshold_window, 4);
> + /* Error Threshold Value */
> + build_append_int_noprefix(table, error_threshold_value, 4);
> + /* Error Threshold Window */
> + build_append_int_noprefix(table, error_threshold_window, 4);
> +}
> +
> +/* Build table for the hardware error fw_cfg blob */
> +void acpi_ghes_build_error_table(GArray *hardware_errors, BIOSLinker *linker)
> +{
> + int i, error_status_block_offset;
> +
> + /*
> + * | +--------------------------+
> + * | | error_block_address |
> + * | | .......... |
> + * | +--------------------------+
> + * | | read_ack_register |
> + * | | ........... |
> + * | +--------------------------+
> + * | | Error Status Data Block |
> + * | | ........ |
> + * | +--------------------------+
> + */
> +
> + /* Build error_block_address */
> + build_append_int_noprefix(hardware_errors, 0,
> + ACPI_GHES_ADDRESS_SIZE * ACPI_GHES_ERROR_SOURCE_COUNT);
This works for adding more than 8 bytes but it's a bit of a hack,
only works when value is 0. A loop would be a bit cleaner imho.
> +
> + /* Build read_ack_register */
> + for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) {
> + /* Initialize the value of read_ack_register to 1, so GHES can be
> + * writeable in the first time.
> + * ACPI 6.2: 18.3.2.8 Generic Hardware Error Source version 2
> + * (GHESv2 - Type 10)
> + */
> + build_append_int_noprefix(hardware_errors, 1, ACPI_GHES_ADDRESS_SIZE);
> + }
> +
> + /* Build Error Status Data Block */
> + build_append_int_noprefix(hardware_errors, 0,
> + ACPI_GHES_MAX_RAW_DATA_LENGTH * ACPI_GHES_ERROR_SOURCE_COUNT);
> +
> + /* Allocate guest memory for the hardware error fw_cfg blob */
> + bios_linker_loader_alloc(linker, ACPI_GHES_ERRORS_FW_CFG_FILE,
> + hardware_errors, 1, false);
> +
> + /* Generic Error Status Block offset in the hardware error fw_cfg blob */
> + error_status_block_offset = ACPI_GHES_ADDRESS_SIZE * 2 *
> + ACPI_GHES_ERROR_SOURCE_COUNT;
a better way to get this is to save hardware_errors->len just before
you append the padding where the value should be.
> +
> + for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) {
> + /* Patch address of Error Status Data Block into
> + * the error_block_address of hardware_errors fw_cfg blob
> + */
> + bios_linker_loader_add_pointer(linker,
> + ACPI_GHES_ERRORS_FW_CFG_FILE, ACPI_GHES_ADDRESS_SIZE * i,
> + ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE,
> + error_status_block_offset + i * ACPI_GHES_MAX_RAW_DATA_LENGTH);
> + }
> +
> + /* Write address of hardware_errors fw_cfg blob into the
> + * hardware_errors_addr fw_cfg blob.
> + */
> + bios_linker_loader_write_pointer(linker, ACPI_GHES_DATA_ADDR_FW_CFG_FILE,
> + 0, ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE, 0);
> +}
> +
> +/* Build Hardware Error Source Table */
> +void acpi_ghes_build_hest(GArray *table_data, GArray *hardware_errors,
> + BIOSLinker *linker)
> +{
> + uint32_t i, hest_start = table_data->len;
> +
> + /* Reserve Hardware Error Source Table header size */
> + acpi_data_push(table_data, sizeof(AcpiTableHeader));
> +
> + /* Error Source Count */
> + build_append_int_noprefix(table_data, ACPI_GHES_ERROR_SOURCE_COUNT, 4);
> +
> + /* Generic Hardware Error Source version 2(GHESv2 - Type 10) */
> + for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) {
> + /* Type */
> + build_append_int_noprefix(table_data,
> + ACPI_GHES_SOURCE_GENERIC_ERROR_V2, 2);
> + /* Source Id */
> + build_append_int_noprefix(table_data, i, 2);
> + /* Related Source Id */
> + build_append_int_noprefix(table_data, 0xffff, 2);
> + /* Flags */
> + build_append_int_noprefix(table_data, 0, 1);
> + /* Enabled */
> + build_append_int_noprefix(table_data, 1, 1);
> +
> + /* Number of Records To Pre-allocate */
> + build_append_int_noprefix(table_data, 1, 4);
> + /* Max Sections Per Record */
> + build_append_int_noprefix(table_data, 1, 4);
> + /* Max Raw Data Length */
> + build_append_int_noprefix(table_data, ACPI_GHES_MAX_RAW_DATA_LENGTH, 4);
> +
> + /* Error Status Address */
> + build_append_gas(table_data, AML_SYSTEM_MEMORY, 0x40, 0,
> + 4 /* QWord access */, 0);
> + bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
> + ACPI_GHES_ERROR_STATUS_ADDRESS_OFFSET(hest_start, i),
> + ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE,
> + i * ACPI_GHES_ADDRESS_SIZE);
> +
> + if (i == 0) {
> + /* Notification Structure
> + * Now only enable ARMv8 SEA notification type
> + */
> + acpi_ghes_build_notify(table_data, ACPI_GHES_NOTIFY_SEA, 28,
what's the magic 28? generally acpi_ghes_build_notify isn't self
contained.
> 0,
> + 0, 0, 0, 0, 0, 0);
> + } else {
> + g_assert_not_reached();
OK so how about we just drop all these loops for
ACPI_GHES_ERROR_SOURCE_COUNT?
> + }
> +
> + /* Error Status Block Length */
> + build_append_int_noprefix(table_data, ACPI_GHES_MAX_RAW_DATA_LENGTH, 4);
> +
> + /* Read Ack Register
> + * ACPI 6.1: 18.3.2.8 Generic Hardware Error Source
> + * version 2 (GHESv2 - Type 10)
> + */
> + build_append_gas(table_data, AML_SYSTEM_MEMORY, 0x40, 0,
> + 4 /* QWord access */, 0);
> + bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
> + ACPI_GHES_READ_ACK_REGISTER_ADDRESS_OFFSET(hest_start, i),
> + ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE,
> + (ACPI_GHES_ERROR_SOURCE_COUNT + i) * ACPI_GHES_ADDRESS_SIZE);
> +
> + /* Read Ack Preserve */
> + build_append_int_noprefix(table_data, 0xfffffffffffffffe, 8);
don't we need to specify ULL? Also isn't this just ~0x1ULL?
you should try to document values not just field names.
e.g. why is ~0x1ULL specifically? which bits are clear?
> + /* Read Ack Write */
> + build_append_int_noprefix(table_data, 0x1, 8);
> + }
> +
> + build_header(linker, table_data, (void *)(table_data->data + hest_start),
> + "HEST", table_data->len - hest_start, 1, NULL, "GHES");
> +}
> +
> +static AcpiGhesState ges;
> +void acpi_ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error)
> +{
> +
> + size_t size = 2 * ACPI_GHES_ADDRESS_SIZE + ACPI_GHES_MAX_RAW_DATA_LENGTH;
> + size_t request_block_size = ACPI_GHES_ERROR_SOURCE_COUNT * size;
> +
> + /* Create a read-only fw_cfg file for GHES */
> + fw_cfg_add_file(s, ACPI_GHES_ERRORS_FW_CFG_FILE, hardware_error->data,
> + request_block_size);
> +
> + /* Create a read-write fw_cfg file for Address */
> + fw_cfg_add_file_callback(s, ACPI_GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL,
> + NULL, &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false);
> +}
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index 78aee1a2f9..bfdb84c517 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -1578,6 +1578,7 @@ void acpi_build_tables_init(AcpiBuildTables *tables)
> tables->table_data = g_array_new(false, true /* clear */, 1);
> tables->tcpalog = g_array_new(false, true /* clear */, 1);
> tables->vmgenid = g_array_new(false, true /* clear */, 1);
> + tables->hardware_errors = g_array_new(false, true /* clear */, 1);
> tables->linker = bios_linker_loader_init();
> }
>
> @@ -1588,6 +1589,7 @@ void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre)
> g_array_free(tables->table_data, true);
> g_array_free(tables->tcpalog, mfre);
> g_array_free(tables->vmgenid, mfre);
> + g_array_free(tables->hardware_errors, mfre);
> }
>
> /*
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 6cdf156cf5..c74e178aa0 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -46,6 +46,7 @@
> #include "sysemu/reset.h"
> #include "kvm_arm.h"
> #include "migration/vmstate.h"
> +#include "hw/acpi/acpi_ghes.h"
>
> #define ARM_SPI_BASE 32
> #define ACPI_POWER_BUTTON_DEVICE "PWRB"
> @@ -796,6 +797,13 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
> acpi_add_table(table_offsets, tables_blob);
> build_spcr(tables_blob, tables->linker, vms);
>
> + if (vms->ras) {
> + acpi_add_table(table_offsets, tables_blob);
> + acpi_ghes_build_error_table(tables->hardware_errors, tables->linker);
> + acpi_ghes_build_hest(tables_blob, tables->hardware_errors,
> + tables->linker);
> + }
> +
> if (ms->numa_state->num_nodes > 0) {
> acpi_add_table(table_offsets, tables_blob);
> build_srat(tables_blob, tables->linker, vms);
> @@ -913,6 +921,10 @@ void virt_acpi_setup(VirtMachineState *vms)
> fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
> acpi_data_len(tables.tcpalog));
>
> + if (vms->ras) {
> + acpi_ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors);
> + }
> +
> build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update,
> build_state, tables.rsdp,
> ACPI_BUILD_RSDP_FILE, 0);
> diff --git a/include/hw/acpi/acpi_ghes.h b/include/hw/acpi/acpi_ghes.h
> new file mode 100644
> index 0000000000..69747ba3d7
> --- /dev/null
> +++ b/include/hw/acpi/acpi_ghes.h
> @@ -0,0 +1,103 @@
> +/* Support for generating APEI tables and record CPER for Guests
> + *
> + * Copyright (C) 2019 Huawei Corporation.
> + *
> + * Author: Dongjiu Geng <gengdongjiu@huawei.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> +
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> +
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef ACPI_GHES_H
> +#define ACPI_GHES_H
> +
> +#include "hw/acpi/bios-linker-loader.h"
> +
> +#define ACPI_GHES_ERRORS_FW_CFG_FILE "etc/hardware_errors"
> +#define ACPI_GHES_DATA_ADDR_FW_CFG_FILE "etc/hardware_errors_addr"
> +
> +/* The size of Address field in Generic Address Structure,
> + * ACPI 2.0/3.0: 5.2.3.1 Generic Address Structure.
> + */
> +#define ACPI_GHES_ADDRESS_SIZE 8
> +
> +/* The max size in bytes for one error block */
> +#define ACPI_GHES_MAX_RAW_DATA_LENGTH 0x1000
> +
> +/* Now only support ARMv8 SEA notification type error source
> + */
> +#define ACPI_GHES_ERROR_SOURCE_COUNT 1
> +
> +/*
> + * Generic Hardware Error Source version 2
> + */
> +#define ACPI_GHES_SOURCE_GENERIC_ERROR_V2 10
> +
> +/*
> + * Values for Hardware Error Notification Type field
> + */
> +enum AcpiGhesNotifyType {
> + ACPI_GHES_NOTIFY_POLLED = 0, /* Polled */
> + ACPI_GHES_NOTIFY_EXTERNAL = 1, /* External Interrupt */
> + ACPI_GHES_NOTIFY_LOCAL = 2, /* Local Interrupt */
> + ACPI_GHES_NOTIFY_SCI = 3, /* SCI */
> + ACPI_GHES_NOTIFY_NMI = 4, /* NMI */
> + ACPI_GHES_NOTIFY_CMCI = 5, /* CMCI, ACPI 5.0: 18.3.2.7, Table 18-290 */
> + ACPI_GHES_NOTIFY_MCE = 6, /* MCE, ACPI 5.0: 18.3.2.7, Table 18-290 */
> + /* GPIO-Signal, ACPI 6.0: 18.3.2.7, Table 18-332 */
> + ACPI_GHES_NOTIFY_GPIO = 7,
> + /* ARMv8 SEA, ACPI 6.1: 18.3.2.9, Table 18-345 */
> + ACPI_GHES_NOTIFY_SEA = 8,
> + /* ARMv8 SEI, ACPI 6.1: 18.3.2.9, Table 18-345 */
> + ACPI_GHES_NOTIFY_SEI = 9,
> + /* External Interrupt - GSIV, ACPI 6.1: 18.3.2.9, Table 18-345 */
> + ACPI_GHES_NOTIFY_GSIV = 10,
> + /* Software Delegated Exception, ACPI 6.2: 18.3.2.9, Table 18-383 */
> + ACPI_GHES_NOTIFY_SDEI = 11,
> + ACPI_GHES_NOTIFY_RESERVED = 12 /* 12 and greater are reserved */
> +};
> +
> +/*
> + * | +--------------------------+ 0
> + * | | Header |
> + * | +--------------------------+ 40---+-
> + * | | ................. | |
> + * | | error_status_address-----+ 60 |
> + * | | ................. | |
> + * | | read_ack_register--------+ 104 92
> + * | | read_ack_preserve | |
> + * | | read_ack_write | |
> + * + +--------------------------+ 132--+-
> + *
> + * From above GHES definition, the error status address offset is 60;
> + * the Read ack register offset is 104, the whole size of GHESv2 is 92
> + */
> +
> +/* The error status address offset in GHES */
> +#define ACPI_GHES_ERROR_STATUS_ADDRESS_OFFSET(start_addr, n) (start_addr + \
> + 60 + offsetof(struct AcpiGenericAddress, address) + n * 92)
> +
> +/* The read Ack register offset in GHES */
> +#define ACPI_GHES_READ_ACK_REGISTER_ADDRESS_OFFSET(start_addr, n) (start_addr +\
> + 104 + offsetof(struct AcpiGenericAddress, address) + n * 92)
> +
> +typedef struct AcpiGhesState {
> + uint64_t ghes_addr_le;
> +} AcpiGhesState;
> +
> +void acpi_ghes_build_hest(GArray *table_data, GArray *hardware_error,
> + BIOSLinker *linker);
> +
> +void acpi_ghes_build_error_table(GArray *hardware_errors, BIOSLinker *linker);
> +void acpi_ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_errors);
> +#endif
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index 991cf05134..2cc61712fd 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -220,6 +220,7 @@ struct AcpiBuildTables {
> GArray *rsdp;
> GArray *tcpalog;
> GArray *vmgenid;
> + GArray *hardware_errors;
> BIOSLinker *linker;
> } AcpiBuildTables;
>
> --
> 2.19.1
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v18 1/6] hw/arm/virt: Introduce RAS platform version and RAS machine option
2019-09-27 14:02 ` Peter Maydell
@ 2019-09-29 2:04 ` Xiang Zheng
0 siblings, 0 replies; 26+ messages in thread
From: Xiang Zheng @ 2019-09-29 2:04 UTC (permalink / raw)
To: Peter Maydell
Cc: Paolo Bonzini, Michael S. Tsirkin, Igor Mammedov, Shannon Zhao,
Laszlo Ersek, James Morse, gengdongjiu, Marcelo Tosatti,
Richard Henderson, Eduardo Habkost, Jonathan Cameron, xuwei (O),
kvm-devel, QEMU Developers, qemu-arm, Linuxarm, wanghaibin.wang
On 2019/9/27 22:02, Peter Maydell wrote:
> On Fri, 6 Sep 2019 at 09:33, Xiang Zheng <zhengxiang9@huawei.com> wrote:
>>
>> From: Dongjiu Geng <gengdongjiu@huawei.com>
>>
>> Support RAS Virtualization feature since version 4.2, disable it by
>> default in the old versions. Also add a machine option which allows user
>> to enable it explicitly.
>>
>> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
>> Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
>> ---
>> hw/arm/virt.c | 33 +++++++++++++++++++++++++++++++++
>> include/hw/arm/virt.h | 2 ++
>> 2 files changed, 35 insertions(+)
>>
>> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
>> index d74538b021..e0451433c8 100644
>> --- a/hw/arm/virt.c
>> +++ b/hw/arm/virt.c
>> @@ -1783,6 +1783,20 @@ static void virt_set_its(Object *obj, bool value, Error **errp)
>> vms->its = value;
>> }
>>
>> +static bool virt_get_ras(Object *obj, Error **errp)
>> +{
>> + VirtMachineState *vms = VIRT_MACHINE(obj);
>> +
>> + return vms->ras;
>> +}
>> +
>> +static void virt_set_ras(Object *obj, bool value, Error **errp)
>> +{
>> + VirtMachineState *vms = VIRT_MACHINE(obj);
>> +
>> + vms->ras = value;
>> +}
>> +
>> static char *virt_get_gic_version(Object *obj, Error **errp)
>> {
>> VirtMachineState *vms = VIRT_MACHINE(obj);
>> @@ -2026,6 +2040,19 @@ static void virt_instance_init(Object *obj)
>> "Valid values are none and smmuv3",
>> NULL);
>>
>> + if (vmc->no_ras) {
>> + vms->ras = false;
>> + } else {
>> + /* Default disallows RAS instantiation */
>> + vms->ras = false;
>> + object_property_add_bool(obj, "ras", virt_get_ras,
>> + virt_set_ras, NULL);
>> + object_property_set_description(obj, "ras",
>> + "Set on/off to enable/disable "
>> + "RAS instantiation",
>> + NULL);
>> + }
>
> For a property which is disabled by default, you don't need
> to have a separate flag in the VirtMachineClass struct.
> Those are only needed for properties where we need the old machine
> types to have the property be 'off' but new machine types
> need to default to it be 'on'. Since vms->ras is false
> by default anyway, you can just have this part:
>
>> + /* Default disallows RAS instantiation */
>> + vms->ras = false;
>> + object_property_add_bool(obj, "ras", virt_get_ras,
>> + virt_set_ras, NULL);
>> + object_property_set_description(obj, "ras",
>> + "Set on/off to enable/disable "
>> + "RAS instantiation",
>> + NULL);
>
> Compare the 'vms->secure' flag and associated property
> for an example of this.
Thanks for pointing it out, I will remove the no_ras in the VirtMachineClass struct.
>
>> vms->irqmap = a15irqmap;
>>
>> virt_flash_create(vms);
>> @@ -2058,8 +2085,14 @@ DEFINE_VIRT_MACHINE_AS_LATEST(4, 2)
>>
>> static void virt_machine_4_1_options(MachineClass *mc)
>> {
>> + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
>> +
>> virt_machine_4_2_options(mc);
>> compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
>> + /* Disable memory recovery feature for 4.1 as RAS support was
>> + * introduced with 4.2.
>> + */
>> + vmc->no_ras = true;
>> }
>> DEFINE_VIRT_MACHINE(4, 1)
>
> thanks
> -- PMM
>
> .
>
--
Thanks,
Xiang
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Qemu-devel] [PATCH v18 2/6] docs: APEI GHES generation and CPER record description
2019-09-06 8:31 ` [PATCH v18 2/6] docs: APEI GHES generation and CPER record description Xiang Zheng
2019-09-19 13:25 ` Peter Maydell
@ 2019-10-04 8:20 ` Igor Mammedov
2019-10-08 13:25 ` Xiang Zheng
1 sibling, 1 reply; 26+ messages in thread
From: Igor Mammedov @ 2019-10-04 8:20 UTC (permalink / raw)
To: Xiang Zheng
Cc: pbonzini, mst, shannon.zhaosl, peter.maydell, lersek,
james.morse, gengdongjiu, mtosatti, rth, ehabkost,
jonathan.cameron, xuwei5, kvm, qemu-devel, qemu-arm, linuxarm,
wanghaibin.wang
On Fri, 6 Sep 2019 16:31:48 +0800
Xiang Zheng <zhengxiang9@huawei.com> wrote:
> From: Dongjiu Geng <gengdongjiu@huawei.com>
>
[...]
> +
> +(9) When QEMU gets SIGBUS from the kernel, QEMU formats the CPER right into
> + guest memory, and then injects whatever interrupt (or assert whatever GPIO
s/whatever .../platform specific/
and add concrete impl info like:
"in case of arm/virt machine it's ..."
> + line) as a notification which is necessary for notifying the guest.
[...]
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v18 3/6] ACPI: Add APEI GHES table generation support
2019-09-27 15:43 ` Michael S. Tsirkin
@ 2019-10-08 6:00 ` Xiang Zheng
2019-10-08 7:45 ` Michael S. Tsirkin
0 siblings, 1 reply; 26+ messages in thread
From: Xiang Zheng @ 2019-10-08 6:00 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: pbonzini, imammedo, shannon.zhaosl, peter.maydell, lersek,
james.morse, gengdongjiu, mtosatti, rth, ehabkost,
jonathan.cameron, xuwei5, kvm, qemu-devel, qemu-arm, linuxarm,
wanghaibin.wang
Hi Michael,
Thanks for your review!
On 2019/9/27 23:43, Michael S. Tsirkin wrote:
> On Fri, Sep 06, 2019 at 04:31:49PM +0800, Xiang Zheng wrote:
>> From: Dongjiu Geng <gengdongjiu@huawei.com>
>>
>> This patch implements APEI GHES Table generation via fw_cfg blobs. Now
>> it only supports ARMv8 SEA, a type of GHESv2 error source. Afterwards,
>> we can extend the supported types if needed. For the CPER section,
>> currently it is memory section because kernel mainly wants userspace to
>> handle the memory errors.
>>
>> This patch follows the spec ACPI 6.2 to build the Hardware Error Source
>> table. For more detailed information, please refer to document:
>> docs/specs/acpi_hest_ghes.txt
>>
>> Suggested-by: Laszlo Ersek <lersek@redhat.com>
>> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
>> Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
>> ---
>> default-configs/arm-softmmu.mak | 1 +
>> hw/acpi/Kconfig | 4 +
>> hw/acpi/Makefile.objs | 1 +
>> hw/acpi/acpi_ghes.c | 210 ++++++++++++++++++++++++++++++++
>> hw/acpi/aml-build.c | 2 +
>> hw/arm/virt-acpi-build.c | 12 ++
>> include/hw/acpi/acpi_ghes.h | 103 ++++++++++++++++
>> include/hw/acpi/aml-build.h | 1 +
>> 8 files changed, 334 insertions(+)
>> create mode 100644 hw/acpi/acpi_ghes.c
>> create mode 100644 include/hw/acpi/acpi_ghes.h
>>
>> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
>> index 1f2e0e7fde..5722f3130e 100644
>> --- a/default-configs/arm-softmmu.mak
>> +++ b/default-configs/arm-softmmu.mak
>> @@ -40,3 +40,4 @@ CONFIG_FSL_IMX25=y
>> CONFIG_FSL_IMX7=y
>> CONFIG_FSL_IMX6UL=y
>> CONFIG_SEMIHOSTING=y
>> +CONFIG_ACPI_APEI=y
>> diff --git a/hw/acpi/Kconfig b/hw/acpi/Kconfig
>> index 7c59cf900b..2c4d0b9826 100644
>> --- a/hw/acpi/Kconfig
>> +++ b/hw/acpi/Kconfig
>> @@ -23,6 +23,10 @@ config ACPI_NVDIMM
>> bool
>> depends on ACPI
>>
>> +config ACPI_APEI
>> + bool
>> + depends on ACPI
>> +
>> config ACPI_PCI
>> bool
>> depends on ACPI && PCI
>> diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs
>> index 9bb2101e3b..93fd8e8f64 100644
>> --- a/hw/acpi/Makefile.objs
>> +++ b/hw/acpi/Makefile.objs
>> @@ -5,6 +5,7 @@ common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu_hotplug.o
>> common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o
>> common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu.o
>> common-obj-$(CONFIG_ACPI_NVDIMM) += nvdimm.o
>> +common-obj-$(CONFIG_ACPI_APEI) += acpi_ghes.o
>> common-obj-$(CONFIG_ACPI_VMGENID) += vmgenid.o
>> common-obj-$(call lnot,$(CONFIG_ACPI_X86)) += acpi-stub.o
>>
>> diff --git a/hw/acpi/acpi_ghes.c b/hw/acpi/acpi_ghes.c
>> new file mode 100644
>> index 0000000000..20c45179ff
>> --- /dev/null
>> +++ b/hw/acpi/acpi_ghes.c
>> @@ -0,0 +1,210 @@
>> +/* Support for generating APEI tables and record CPER for Guests
>> + *
>> + * Copyright (C) 2019 Huawei Corporation.
>> + *
>> + * Author: Dongjiu Geng <gengdongjiu@huawei.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> +
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> +
>> + * You should have received a copy of the GNU General Public License along
>> + * with this program; if not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "hw/acpi/acpi.h"
>> +#include "hw/acpi/aml-build.h"
>> +#include "hw/acpi/acpi_ghes.h"
>> +#include "hw/nvram/fw_cfg.h"
>> +#include "sysemu/sysemu.h"
>> +#include "qemu/error-report.h"
>> +
>> +/* Hardware Error Notification
>> + * ACPI 4.0: 17.3.2.7 Hardware Error Notification
>> + */
>> +static void acpi_ghes_build_notify(GArray *table, const uint8_t type,
>> + uint8_t length, uint16_t config_write_enable,
>> + uint32_t poll_interval, uint32_t vector,
>> + uint32_t polling_threshold_value,
>> + uint32_t polling_threshold_window,
>> + uint32_t error_threshold_value,
>> + uint32_t error_threshold_window)
>
>
> This function has too many arguments.
> How about we just hard code all the 0's until we need to set them
> to something else?
Yes, and we can also hard code the value of length which is always 28 and
indicates the total length of the structure in bytes.
>
>> +{
>> + /* Type */
>> + build_append_int_noprefix(table, type, 1);
>> + /* Length */
>> + build_append_int_noprefix(table, length, 1);
>> + /* Configuration Write Enable */
>> + build_append_int_noprefix(table, config_write_enable, 2);
>> + /* Poll Interval */
>> + build_append_int_noprefix(table, poll_interval, 4);
>> + /* Vector */
>> + build_append_int_noprefix(table, vector, 4);
>> + /* Switch To Polling Threshold Value */
>> + build_append_int_noprefix(table, polling_threshold_value, 4);
>> + /* Switch To Polling Threshold Window */
>> + build_append_int_noprefix(table, polling_threshold_window, 4);
>> + /* Error Threshold Value */
>> + build_append_int_noprefix(table, error_threshold_value, 4);
>> + /* Error Threshold Window */
>> + build_append_int_noprefix(table, error_threshold_window, 4);
>> +}
>> +
>> +/* Build table for the hardware error fw_cfg blob */
>> +void acpi_ghes_build_error_table(GArray *hardware_errors, BIOSLinker *linker)
>> +{
>> + int i, error_status_block_offset;
>> +
>> + /*
>> + * | +--------------------------+
>> + * | | error_block_address |
>> + * | | .......... |
>> + * | +--------------------------+
>> + * | | read_ack_register |
>> + * | | ........... |
>> + * | +--------------------------+
>> + * | | Error Status Data Block |
>> + * | | ........ |
>> + * | +--------------------------+
>> + */
>> +
>> + /* Build error_block_address */
>> + build_append_int_noprefix(hardware_errors, 0,
>> + ACPI_GHES_ADDRESS_SIZE * ACPI_GHES_ERROR_SOURCE_COUNT);
>
> This works for adding more than 8 bytes but it's a bit of a hack,
> only works when value is 0. A loop would be a bit cleaner imho.
Yes, this might confuse someone and it's better to use a loop instead.
>
>> +
>> + /* Build read_ack_register */
>> + for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) {
>> + /* Initialize the value of read_ack_register to 1, so GHES can be
>> + * writeable in the first time.
>> + * ACPI 6.2: 18.3.2.8 Generic Hardware Error Source version 2
>> + * (GHESv2 - Type 10)
>> + */
>> + build_append_int_noprefix(hardware_errors, 1, ACPI_GHES_ADDRESS_SIZE);
>> + }
>> +
>> + /* Build Error Status Data Block */
>> + build_append_int_noprefix(hardware_errors, 0,
>> + ACPI_GHES_MAX_RAW_DATA_LENGTH * ACPI_GHES_ERROR_SOURCE_COUNT);
>> +
>> + /* Allocate guest memory for the hardware error fw_cfg blob */
>> + bios_linker_loader_alloc(linker, ACPI_GHES_ERRORS_FW_CFG_FILE,
>> + hardware_errors, 1, false);
>> +
>> + /* Generic Error Status Block offset in the hardware error fw_cfg blob */
>> + error_status_block_offset = ACPI_GHES_ADDRESS_SIZE * 2 *
>> + ACPI_GHES_ERROR_SOURCE_COUNT;
>
> a better way to get this is to save hardware_errors->len just before
> you append the padding where the value should be.
Thanks, this really makes it better.
>
>> +
>> + for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) {
>> + /* Patch address of Error Status Data Block into
>> + * the error_block_address of hardware_errors fw_cfg blob
>> + */
>> + bios_linker_loader_add_pointer(linker,
>> + ACPI_GHES_ERRORS_FW_CFG_FILE, ACPI_GHES_ADDRESS_SIZE * i,
>> + ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE,
>> + error_status_block_offset + i * ACPI_GHES_MAX_RAW_DATA_LENGTH);
>> + }
>> +
>> + /* Write address of hardware_errors fw_cfg blob into the
>> + * hardware_errors_addr fw_cfg blob.
>> + */
>> + bios_linker_loader_write_pointer(linker, ACPI_GHES_DATA_ADDR_FW_CFG_FILE,
>> + 0, ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE, 0);
>> +}
>> +
>> +/* Build Hardware Error Source Table */
>> +void acpi_ghes_build_hest(GArray *table_data, GArray *hardware_errors,
>> + BIOSLinker *linker)
>> +{
>> + uint32_t i, hest_start = table_data->len;
>> +
>> + /* Reserve Hardware Error Source Table header size */
>> + acpi_data_push(table_data, sizeof(AcpiTableHeader));
>> +
>> + /* Error Source Count */
>> + build_append_int_noprefix(table_data, ACPI_GHES_ERROR_SOURCE_COUNT, 4);
>> +
>> + /* Generic Hardware Error Source version 2(GHESv2 - Type 10) */
>> + for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) {
>> + /* Type */
>> + build_append_int_noprefix(table_data,
>> + ACPI_GHES_SOURCE_GENERIC_ERROR_V2, 2);
>> + /* Source Id */
>> + build_append_int_noprefix(table_data, i, 2);
>> + /* Related Source Id */
>> + build_append_int_noprefix(table_data, 0xffff, 2);
>> + /* Flags */
>> + build_append_int_noprefix(table_data, 0, 1);
>> + /* Enabled */
>> + build_append_int_noprefix(table_data, 1, 1);
>> +
>> + /* Number of Records To Pre-allocate */
>> + build_append_int_noprefix(table_data, 1, 4);
>> + /* Max Sections Per Record */
>> + build_append_int_noprefix(table_data, 1, 4);
>> + /* Max Raw Data Length */
>> + build_append_int_noprefix(table_data, ACPI_GHES_MAX_RAW_DATA_LENGTH, 4);
>> +
>> + /* Error Status Address */
>> + build_append_gas(table_data, AML_SYSTEM_MEMORY, 0x40, 0,
>> + 4 /* QWord access */, 0);
>> + bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
>> + ACPI_GHES_ERROR_STATUS_ADDRESS_OFFSET(hest_start, i),
>> + ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE,
>> + i * ACPI_GHES_ADDRESS_SIZE);
>> +
>> + if (i == 0) {
>> + /* Notification Structure
>> + * Now only enable ARMv8 SEA notification type
>> + */
>> + acpi_ghes_build_notify(table_data, ACPI_GHES_NOTIFY_SEA, 28,
>
>
> what's the magic 28? generally acpi_ghes_build_notify isn't self
> contained.
>
According to "ACPI 6.2: 18.3.2.9 Hardware Error Notification", the number "28" indicates
the total length of the hardware error notifaction structure in bytes. I will add a new
macro such as ACPI_GHES_HW_ERROR_NOTIF_LENGTH.
>
>> 0,
>> + 0, 0, 0, 0, 0, 0);
>> + } else {
>> + g_assert_not_reached();
>
> OK so how about we just drop all these loops for
> ACPI_GHES_ERROR_SOURCE_COUNT?
Even though we only support ARMv8 SEA notification type now, we still use these loops for
scalability. Maybe we need to add a new staic array for these loops, like below:
static uint8_t acpi_ghes_hw_srouces[ACPI_GHES_ERROR_SOURCE_COUNT] = {
ACPI_GHES_NOTIFY_SEA
};
>
>
>> + }
>> +
>> + /* Error Status Block Length */
>> + build_append_int_noprefix(table_data, ACPI_GHES_MAX_RAW_DATA_LENGTH, 4);
>> +
>> + /* Read Ack Register
>> + * ACPI 6.1: 18.3.2.8 Generic Hardware Error Source
>> + * version 2 (GHESv2 - Type 10)
>> + */
>> + build_append_gas(table_data, AML_SYSTEM_MEMORY, 0x40, 0,
>> + 4 /* QWord access */, 0);
>> + bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
>> + ACPI_GHES_READ_ACK_REGISTER_ADDRESS_OFFSET(hest_start, i),
>> + ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE,
>> + (ACPI_GHES_ERROR_SOURCE_COUNT + i) * ACPI_GHES_ADDRESS_SIZE);
>> +
>> + /* Read Ack Preserve */
>> + build_append_int_noprefix(table_data, 0xfffffffffffffffe, 8);
>
> don't we need to specify ULL? Also isn't this just ~0x1ULL?
Yes, I will use ~0x1ULL instead.
>
> you should try to document values not just field names.
> e.g. why is ~0x1ULL specifically? which bits are clear?
OK, I will document it. According to "ACPI 6.2: 18.3.2.8 Generic Hardware Error
Source version 2 (GHESv2 - Type 10)", we only provide the first bit to OSPM while
the other bits are preserved. That's why we initialize the value of Read Ack Register
to 1.
>
>> + /* Read Ack Write */
>> + build_append_int_noprefix(table_data, 0x1, 8);
>> + }
>> +
>> + build_header(linker, table_data, (void *)(table_data->data + hest_start),
>> + "HEST", table_data->len - hest_start, 1, NULL, "GHES");
>> +}
>> +
>> +static AcpiGhesState ges;
>> +void acpi_ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error)
>> +{
>> +
>> + size_t size = 2 * ACPI_GHES_ADDRESS_SIZE + ACPI_GHES_MAX_RAW_DATA_LENGTH;
>> + size_t request_block_size = ACPI_GHES_ERROR_SOURCE_COUNT * size;
>> +
>> + /* Create a read-only fw_cfg file for GHES */
>> + fw_cfg_add_file(s, ACPI_GHES_ERRORS_FW_CFG_FILE, hardware_error->data,
>> + request_block_size);
>> +
>> + /* Create a read-write fw_cfg file for Address */
>> + fw_cfg_add_file_callback(s, ACPI_GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL,
>> + NULL, &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false);
>> +}
>> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
>> index 78aee1a2f9..bfdb84c517 100644
>> --- a/hw/acpi/aml-build.c
>> +++ b/hw/acpi/aml-build.c
>> @@ -1578,6 +1578,7 @@ void acpi_build_tables_init(AcpiBuildTables *tables)
>> tables->table_data = g_array_new(false, true /* clear */, 1);
>> tables->tcpalog = g_array_new(false, true /* clear */, 1);
>> tables->vmgenid = g_array_new(false, true /* clear */, 1);
>> + tables->hardware_errors = g_array_new(false, true /* clear */, 1);
>> tables->linker = bios_linker_loader_init();
>> }
>>
>> @@ -1588,6 +1589,7 @@ void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre)
>> g_array_free(tables->table_data, true);
>> g_array_free(tables->tcpalog, mfre);
>> g_array_free(tables->vmgenid, mfre);
>> + g_array_free(tables->hardware_errors, mfre);
>> }
>>
>> /*
>> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
>> index 6cdf156cf5..c74e178aa0 100644
>> --- a/hw/arm/virt-acpi-build.c
>> +++ b/hw/arm/virt-acpi-build.c
>> @@ -46,6 +46,7 @@
>> #include "sysemu/reset.h"
>> #include "kvm_arm.h"
>> #include "migration/vmstate.h"
>> +#include "hw/acpi/acpi_ghes.h"
>>
>> #define ARM_SPI_BASE 32
>> #define ACPI_POWER_BUTTON_DEVICE "PWRB"
>> @@ -796,6 +797,13 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
>> acpi_add_table(table_offsets, tables_blob);
>> build_spcr(tables_blob, tables->linker, vms);
>>
>> + if (vms->ras) {
>> + acpi_add_table(table_offsets, tables_blob);
>> + acpi_ghes_build_error_table(tables->hardware_errors, tables->linker);
>> + acpi_ghes_build_hest(tables_blob, tables->hardware_errors,
>> + tables->linker);
>> + }
>> +
>> if (ms->numa_state->num_nodes > 0) {
>> acpi_add_table(table_offsets, tables_blob);
>> build_srat(tables_blob, tables->linker, vms);
>> @@ -913,6 +921,10 @@ void virt_acpi_setup(VirtMachineState *vms)
>> fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
>> acpi_data_len(tables.tcpalog));
>>
>> + if (vms->ras) {
>> + acpi_ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors);
>> + }
>> +
>> build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update,
>> build_state, tables.rsdp,
>> ACPI_BUILD_RSDP_FILE, 0);
>> diff --git a/include/hw/acpi/acpi_ghes.h b/include/hw/acpi/acpi_ghes.h
>> new file mode 100644
>> index 0000000000..69747ba3d7
>> --- /dev/null
>> +++ b/include/hw/acpi/acpi_ghes.h
>> @@ -0,0 +1,103 @@
>> +/* Support for generating APEI tables and record CPER for Guests
>> + *
>> + * Copyright (C) 2019 Huawei Corporation.
>> + *
>> + * Author: Dongjiu Geng <gengdongjiu@huawei.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> +
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> +
>> + * You should have received a copy of the GNU General Public License along
>> + * with this program; if not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#ifndef ACPI_GHES_H
>> +#define ACPI_GHES_H
>> +
>> +#include "hw/acpi/bios-linker-loader.h"
>> +
>> +#define ACPI_GHES_ERRORS_FW_CFG_FILE "etc/hardware_errors"
>> +#define ACPI_GHES_DATA_ADDR_FW_CFG_FILE "etc/hardware_errors_addr"
>> +
>> +/* The size of Address field in Generic Address Structure,
>> + * ACPI 2.0/3.0: 5.2.3.1 Generic Address Structure.
>> + */
>> +#define ACPI_GHES_ADDRESS_SIZE 8
>> +
>> +/* The max size in bytes for one error block */
>> +#define ACPI_GHES_MAX_RAW_DATA_LENGTH 0x1000
>> +
>> +/* Now only support ARMv8 SEA notification type error source
>> + */
>> +#define ACPI_GHES_ERROR_SOURCE_COUNT 1
>> +
>> +/*
>> + * Generic Hardware Error Source version 2
>> + */
>> +#define ACPI_GHES_SOURCE_GENERIC_ERROR_V2 10
>> +
>> +/*
>> + * Values for Hardware Error Notification Type field
>> + */
>> +enum AcpiGhesNotifyType {
>> + ACPI_GHES_NOTIFY_POLLED = 0, /* Polled */
>> + ACPI_GHES_NOTIFY_EXTERNAL = 1, /* External Interrupt */
>> + ACPI_GHES_NOTIFY_LOCAL = 2, /* Local Interrupt */
>> + ACPI_GHES_NOTIFY_SCI = 3, /* SCI */
>> + ACPI_GHES_NOTIFY_NMI = 4, /* NMI */
>> + ACPI_GHES_NOTIFY_CMCI = 5, /* CMCI, ACPI 5.0: 18.3.2.7, Table 18-290 */
>> + ACPI_GHES_NOTIFY_MCE = 6, /* MCE, ACPI 5.0: 18.3.2.7, Table 18-290 */
>> + /* GPIO-Signal, ACPI 6.0: 18.3.2.7, Table 18-332 */
>> + ACPI_GHES_NOTIFY_GPIO = 7,
>> + /* ARMv8 SEA, ACPI 6.1: 18.3.2.9, Table 18-345 */
>> + ACPI_GHES_NOTIFY_SEA = 8,
>> + /* ARMv8 SEI, ACPI 6.1: 18.3.2.9, Table 18-345 */
>> + ACPI_GHES_NOTIFY_SEI = 9,
>> + /* External Interrupt - GSIV, ACPI 6.1: 18.3.2.9, Table 18-345 */
>> + ACPI_GHES_NOTIFY_GSIV = 10,
>> + /* Software Delegated Exception, ACPI 6.2: 18.3.2.9, Table 18-383 */
>> + ACPI_GHES_NOTIFY_SDEI = 11,
>> + ACPI_GHES_NOTIFY_RESERVED = 12 /* 12 and greater are reserved */
>> +};
>> +
>> +/*
>> + * | +--------------------------+ 0
>> + * | | Header |
>> + * | +--------------------------+ 40---+-
>> + * | | ................. | |
>> + * | | error_status_address-----+ 60 |
>> + * | | ................. | |
>> + * | | read_ack_register--------+ 104 92
>> + * | | read_ack_preserve | |
>> + * | | read_ack_write | |
>> + * + +--------------------------+ 132--+-
>> + *
>> + * From above GHES definition, the error status address offset is 60;
>> + * the Read ack register offset is 104, the whole size of GHESv2 is 92
>> + */
>> +
>> +/* The error status address offset in GHES */
>> +#define ACPI_GHES_ERROR_STATUS_ADDRESS_OFFSET(start_addr, n) (start_addr + \
>> + 60 + offsetof(struct AcpiGenericAddress, address) + n * 92)
>> +
>> +/* The read Ack register offset in GHES */
>> +#define ACPI_GHES_READ_ACK_REGISTER_ADDRESS_OFFSET(start_addr, n) (start_addr +\
>> + 104 + offsetof(struct AcpiGenericAddress, address) + n * 92)
>> +
>> +typedef struct AcpiGhesState {
>> + uint64_t ghes_addr_le;
>> +} AcpiGhesState;
>> +
>> +void acpi_ghes_build_hest(GArray *table_data, GArray *hardware_error,
>> + BIOSLinker *linker);
>> +
>> +void acpi_ghes_build_error_table(GArray *hardware_errors, BIOSLinker *linker);
>> +void acpi_ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_errors);
>> +#endif
>> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
>> index 991cf05134..2cc61712fd 100644
>> --- a/include/hw/acpi/aml-build.h
>> +++ b/include/hw/acpi/aml-build.h
>> @@ -220,6 +220,7 @@ struct AcpiBuildTables {
>> GArray *rsdp;
>> GArray *tcpalog;
>> GArray *vmgenid;
>> + GArray *hardware_errors;
>> BIOSLinker *linker;
>> } AcpiBuildTables;
>>
>> --
>> 2.19.1
>>
>
> .
>
--
Thanks,
Xiang
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Qemu-arm] [PATCH v18 4/6] KVM: Move hwpoison page related functions into include/sysemu/kvm_int.h
2019-09-27 13:19 ` [Qemu-arm] " Peter Maydell
@ 2019-10-08 7:01 ` Xiang Zheng
0 siblings, 0 replies; 26+ messages in thread
From: Xiang Zheng @ 2019-10-08 7:01 UTC (permalink / raw)
To: Peter Maydell
Cc: Paolo Bonzini, Michael S. Tsirkin, Igor Mammedov, Shannon Zhao,
Laszlo Ersek, James Morse, gengdongjiu, Marcelo Tosatti,
Richard Henderson, Eduardo Habkost, Jonathan Cameron, xuwei (O),
kvm-devel, QEMU Developers, qemu-arm, Linuxarm, wanghaibin.wang
On 2019/9/27 21:19, Peter Maydell wrote:
> On Fri, 6 Sep 2019 at 09:33, Xiang Zheng <zhengxiang9@huawei.com> wrote:
>>
>> From: Dongjiu Geng <gengdongjiu@huawei.com>
>>
>> kvm_hwpoison_page_add() and kvm_unpoison_all() will both be used by X86
>> and ARM platforms, so moving them into "include/sysemu/kvm_int.h" to
>> avoid duplicate code.
>>
>> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
>> Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
>> ---
>> accel/kvm/kvm-all.c | 33 +++++++++++++++++++++++++++++++++
>> include/sysemu/kvm_int.h | 23 +++++++++++++++++++++++
>> target/arm/kvm.c | 3 +++
>> target/i386/kvm.c | 34 ----------------------------------
>> 4 files changed, 59 insertions(+), 34 deletions(-)
>
>> static uint32_t adjust_ioeventfd_endianness(uint32_t val, uint32_t size)
>> {
>> #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
>> diff --git a/include/sysemu/kvm_int.h b/include/sysemu/kvm_int.h
>> index 72b2d1b3ae..3ad49f9a28 100644
>> --- a/include/sysemu/kvm_int.h
>> +++ b/include/sysemu/kvm_int.h
>> @@ -41,4 +41,27 @@ typedef struct KVMMemoryListener {
>> void kvm_memory_listener_register(KVMState *s, KVMMemoryListener *kml,
>> AddressSpace *as, int as_id);
>>
>> +/**
>> + * kvm_hwpoison_page_add:
>> + *
>> + * Parameters:
>> + * @ram_addr: the address in the RAM for the poisoned page
>> + *
>> + * Add a poisoned page to the list
>> + *
>> + * Return: None.
>> + */
>> +void kvm_hwpoison_page_add(ram_addr_t ram_addr);
>> +
>> +/**
>> + * kvm_unpoison_all:
>> + *
>> + * Parameters:
>> + * @param: some data may be passed to this function
>> + *
>> + * Free and remove all the poisoned pages in the list
>> + *
>> + * Return: None.
>> + */
>> +void kvm_unpoison_all(void *param);
>> #endif
>> diff --git a/target/arm/kvm.c b/target/arm/kvm.c
>> index b2eaa50b8d..3a110be7b8 100644
>> --- a/target/arm/kvm.c
>> +++ b/target/arm/kvm.c
>> @@ -20,6 +20,7 @@
>> #include "sysemu/sysemu.h"
>> #include "sysemu/kvm.h"
>> #include "sysemu/kvm_int.h"
>> +#include "sysemu/reset.h"
>> #include "kvm_arm.h"
>> #include "cpu.h"
>> #include "trace.h"
>> @@ -195,6 +196,8 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
>>
>> cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE);
>>
>> + qemu_register_reset(kvm_unpoison_all, NULL);
>> +
>
> Rather than registering the same reset handler in
> all the architectures, we could register it in the
> generic kvm_init() function. (For architectures that
> don't use the poison-list functionality the reset handler
> will harmlessly do nothing, because there will be nothing
> in the list.)
>
> This would allow you to not have to make the
> kvm_unpoison_all() function global -- it can be static
> in accel/tcg/kvm-all.c.
OK, I will move the register code into the kvm_init() function.
>
>> return 0;
>> }
>
> thanks
> -- PMM
>
> .
>
--
Thanks,
Xiang
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v18 3/6] ACPI: Add APEI GHES table generation support
2019-10-08 6:00 ` Xiang Zheng
@ 2019-10-08 7:45 ` Michael S. Tsirkin
2019-10-08 12:48 ` Xiang Zheng
0 siblings, 1 reply; 26+ messages in thread
From: Michael S. Tsirkin @ 2019-10-08 7:45 UTC (permalink / raw)
To: Xiang Zheng
Cc: pbonzini, imammedo, shannon.zhaosl, peter.maydell, lersek,
james.morse, gengdongjiu, mtosatti, rth, ehabkost,
jonathan.cameron, xuwei5, kvm, qemu-devel, qemu-arm, linuxarm,
wanghaibin.wang
On Tue, Oct 08, 2019 at 02:00:56PM +0800, Xiang Zheng wrote:
> Hi Michael,
>
> Thanks for your review!
>
> On 2019/9/27 23:43, Michael S. Tsirkin wrote:
> > On Fri, Sep 06, 2019 at 04:31:49PM +0800, Xiang Zheng wrote:
> >> From: Dongjiu Geng <gengdongjiu@huawei.com>
> >>
> >> This patch implements APEI GHES Table generation via fw_cfg blobs. Now
> >> it only supports ARMv8 SEA, a type of GHESv2 error source. Afterwards,
> >> we can extend the supported types if needed. For the CPER section,
> >> currently it is memory section because kernel mainly wants userspace to
> >> handle the memory errors.
> >>
> >> This patch follows the spec ACPI 6.2 to build the Hardware Error Source
> >> table. For more detailed information, please refer to document:
> >> docs/specs/acpi_hest_ghes.txt
> >>
> >> Suggested-by: Laszlo Ersek <lersek@redhat.com>
> >> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
> >> Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
> >> ---
> >> default-configs/arm-softmmu.mak | 1 +
> >> hw/acpi/Kconfig | 4 +
> >> hw/acpi/Makefile.objs | 1 +
> >> hw/acpi/acpi_ghes.c | 210 ++++++++++++++++++++++++++++++++
> >> hw/acpi/aml-build.c | 2 +
> >> hw/arm/virt-acpi-build.c | 12 ++
> >> include/hw/acpi/acpi_ghes.h | 103 ++++++++++++++++
> >> include/hw/acpi/aml-build.h | 1 +
> >> 8 files changed, 334 insertions(+)
> >> create mode 100644 hw/acpi/acpi_ghes.c
> >> create mode 100644 include/hw/acpi/acpi_ghes.h
> >>
> >> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
> >> index 1f2e0e7fde..5722f3130e 100644
> >> --- a/default-configs/arm-softmmu.mak
> >> +++ b/default-configs/arm-softmmu.mak
> >> @@ -40,3 +40,4 @@ CONFIG_FSL_IMX25=y
> >> CONFIG_FSL_IMX7=y
> >> CONFIG_FSL_IMX6UL=y
> >> CONFIG_SEMIHOSTING=y
> >> +CONFIG_ACPI_APEI=y
> >> diff --git a/hw/acpi/Kconfig b/hw/acpi/Kconfig
> >> index 7c59cf900b..2c4d0b9826 100644
> >> --- a/hw/acpi/Kconfig
> >> +++ b/hw/acpi/Kconfig
> >> @@ -23,6 +23,10 @@ config ACPI_NVDIMM
> >> bool
> >> depends on ACPI
> >>
> >> +config ACPI_APEI
> >> + bool
> >> + depends on ACPI
> >> +
> >> config ACPI_PCI
> >> bool
> >> depends on ACPI && PCI
> >> diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs
> >> index 9bb2101e3b..93fd8e8f64 100644
> >> --- a/hw/acpi/Makefile.objs
> >> +++ b/hw/acpi/Makefile.objs
> >> @@ -5,6 +5,7 @@ common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu_hotplug.o
> >> common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o
> >> common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu.o
> >> common-obj-$(CONFIG_ACPI_NVDIMM) += nvdimm.o
> >> +common-obj-$(CONFIG_ACPI_APEI) += acpi_ghes.o
> >> common-obj-$(CONFIG_ACPI_VMGENID) += vmgenid.o
> >> common-obj-$(call lnot,$(CONFIG_ACPI_X86)) += acpi-stub.o
> >>
> >> diff --git a/hw/acpi/acpi_ghes.c b/hw/acpi/acpi_ghes.c
> >> new file mode 100644
> >> index 0000000000..20c45179ff
> >> --- /dev/null
> >> +++ b/hw/acpi/acpi_ghes.c
> >> @@ -0,0 +1,210 @@
> >> +/* Support for generating APEI tables and record CPER for Guests
> >> + *
> >> + * Copyright (C) 2019 Huawei Corporation.
> >> + *
> >> + * Author: Dongjiu Geng <gengdongjiu@huawei.com>
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify
> >> + * it under the terms of the GNU General Public License as published by
> >> + * the Free Software Foundation; either version 2 of the License, or
> >> + * (at your option) any later version.
> >> +
> >> + * This program is distributed in the hope that it will be useful,
> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> >> + * GNU General Public License for more details.
> >> +
> >> + * You should have received a copy of the GNU General Public License along
> >> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> >> + */
> >> +
> >> +#include "qemu/osdep.h"
> >> +#include "hw/acpi/acpi.h"
> >> +#include "hw/acpi/aml-build.h"
> >> +#include "hw/acpi/acpi_ghes.h"
> >> +#include "hw/nvram/fw_cfg.h"
> >> +#include "sysemu/sysemu.h"
> >> +#include "qemu/error-report.h"
> >> +
> >> +/* Hardware Error Notification
> >> + * ACPI 4.0: 17.3.2.7 Hardware Error Notification
> >> + */
> >> +static void acpi_ghes_build_notify(GArray *table, const uint8_t type,
> >> + uint8_t length, uint16_t config_write_enable,
> >> + uint32_t poll_interval, uint32_t vector,
> >> + uint32_t polling_threshold_value,
> >> + uint32_t polling_threshold_window,
> >> + uint32_t error_threshold_value,
> >> + uint32_t error_threshold_window)
> >
> >
> > This function has too many arguments.
> > How about we just hard code all the 0's until we need to set them
> > to something else?
>
> Yes, and we can also hard code the value of length which is always 28 and
> indicates the total length of the structure in bytes.
>
> >
> >> +{
> >> + /* Type */
> >> + build_append_int_noprefix(table, type, 1);
> >> + /* Length */
> >> + build_append_int_noprefix(table, length, 1);
> >> + /* Configuration Write Enable */
> >> + build_append_int_noprefix(table, config_write_enable, 2);
> >> + /* Poll Interval */
> >> + build_append_int_noprefix(table, poll_interval, 4);
> >> + /* Vector */
> >> + build_append_int_noprefix(table, vector, 4);
> >> + /* Switch To Polling Threshold Value */
> >> + build_append_int_noprefix(table, polling_threshold_value, 4);
> >> + /* Switch To Polling Threshold Window */
> >> + build_append_int_noprefix(table, polling_threshold_window, 4);
> >> + /* Error Threshold Value */
> >> + build_append_int_noprefix(table, error_threshold_value, 4);
> >> + /* Error Threshold Window */
> >> + build_append_int_noprefix(table, error_threshold_window, 4);
> >> +}
> >> +
> >> +/* Build table for the hardware error fw_cfg blob */
> >> +void acpi_ghes_build_error_table(GArray *hardware_errors, BIOSLinker *linker)
> >> +{
> >> + int i, error_status_block_offset;
> >> +
> >> + /*
> >> + * | +--------------------------+
> >> + * | | error_block_address |
> >> + * | | .......... |
> >> + * | +--------------------------+
> >> + * | | read_ack_register |
> >> + * | | ........... |
> >> + * | +--------------------------+
> >> + * | | Error Status Data Block |
> >> + * | | ........ |
> >> + * | +--------------------------+
> >> + */
> >> +
> >> + /* Build error_block_address */
> >> + build_append_int_noprefix(hardware_errors, 0,
> >> + ACPI_GHES_ADDRESS_SIZE * ACPI_GHES_ERROR_SOURCE_COUNT);
> >
> > This works for adding more than 8 bytes but it's a bit of a hack,
> > only works when value is 0. A loop would be a bit cleaner imho.
>
> Yes, this might confuse someone and it's better to use a loop instead.
>
> >
> >> +
> >> + /* Build read_ack_register */
> >> + for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) {
> >> + /* Initialize the value of read_ack_register to 1, so GHES can be
> >> + * writeable in the first time.
> >> + * ACPI 6.2: 18.3.2.8 Generic Hardware Error Source version 2
> >> + * (GHESv2 - Type 10)
> >> + */
> >> + build_append_int_noprefix(hardware_errors, 1, ACPI_GHES_ADDRESS_SIZE);
> >> + }
> >> +
> >> + /* Build Error Status Data Block */
> >> + build_append_int_noprefix(hardware_errors, 0,
> >> + ACPI_GHES_MAX_RAW_DATA_LENGTH * ACPI_GHES_ERROR_SOURCE_COUNT);
> >> +
> >> + /* Allocate guest memory for the hardware error fw_cfg blob */
> >> + bios_linker_loader_alloc(linker, ACPI_GHES_ERRORS_FW_CFG_FILE,
> >> + hardware_errors, 1, false);
> >> +
> >> + /* Generic Error Status Block offset in the hardware error fw_cfg blob */
> >> + error_status_block_offset = ACPI_GHES_ADDRESS_SIZE * 2 *
> >> + ACPI_GHES_ERROR_SOURCE_COUNT;
> >
> > a better way to get this is to save hardware_errors->len just before
> > you append the padding where the value should be.
>
> Thanks, this really makes it better.
>
> >
> >> +
> >> + for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) {
> >> + /* Patch address of Error Status Data Block into
> >> + * the error_block_address of hardware_errors fw_cfg blob
> >> + */
> >> + bios_linker_loader_add_pointer(linker,
> >> + ACPI_GHES_ERRORS_FW_CFG_FILE, ACPI_GHES_ADDRESS_SIZE * i,
> >> + ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE,
> >> + error_status_block_offset + i * ACPI_GHES_MAX_RAW_DATA_LENGTH);
> >> + }
> >> +
> >> + /* Write address of hardware_errors fw_cfg blob into the
> >> + * hardware_errors_addr fw_cfg blob.
> >> + */
> >> + bios_linker_loader_write_pointer(linker, ACPI_GHES_DATA_ADDR_FW_CFG_FILE,
> >> + 0, ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE, 0);
> >> +}
> >> +
> >> +/* Build Hardware Error Source Table */
> >> +void acpi_ghes_build_hest(GArray *table_data, GArray *hardware_errors,
> >> + BIOSLinker *linker)
> >> +{
> >> + uint32_t i, hest_start = table_data->len;
> >> +
> >> + /* Reserve Hardware Error Source Table header size */
> >> + acpi_data_push(table_data, sizeof(AcpiTableHeader));
> >> +
> >> + /* Error Source Count */
> >> + build_append_int_noprefix(table_data, ACPI_GHES_ERROR_SOURCE_COUNT, 4);
> >> +
> >> + /* Generic Hardware Error Source version 2(GHESv2 - Type 10) */
> >> + for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) {
> >> + /* Type */
> >> + build_append_int_noprefix(table_data,
> >> + ACPI_GHES_SOURCE_GENERIC_ERROR_V2, 2);
> >> + /* Source Id */
> >> + build_append_int_noprefix(table_data, i, 2);
> >> + /* Related Source Id */
> >> + build_append_int_noprefix(table_data, 0xffff, 2);
> >> + /* Flags */
> >> + build_append_int_noprefix(table_data, 0, 1);
> >> + /* Enabled */
> >> + build_append_int_noprefix(table_data, 1, 1);
> >> +
> >> + /* Number of Records To Pre-allocate */
> >> + build_append_int_noprefix(table_data, 1, 4);
> >> + /* Max Sections Per Record */
> >> + build_append_int_noprefix(table_data, 1, 4);
> >> + /* Max Raw Data Length */
> >> + build_append_int_noprefix(table_data, ACPI_GHES_MAX_RAW_DATA_LENGTH, 4);
> >> +
> >> + /* Error Status Address */
> >> + build_append_gas(table_data, AML_SYSTEM_MEMORY, 0x40, 0,
> >> + 4 /* QWord access */, 0);
> >> + bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
> >> + ACPI_GHES_ERROR_STATUS_ADDRESS_OFFSET(hest_start, i),
> >> + ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE,
> >> + i * ACPI_GHES_ADDRESS_SIZE);
> >> +
> >> + if (i == 0) {
> >> + /* Notification Structure
> >> + * Now only enable ARMv8 SEA notification type
> >> + */
> >> + acpi_ghes_build_notify(table_data, ACPI_GHES_NOTIFY_SEA, 28,
> >
> >
> > what's the magic 28? generally acpi_ghes_build_notify isn't self
> > contained.
> >
>
> According to "ACPI 6.2: 18.3.2.9 Hardware Error Notification", the number "28" indicates
> the total length of the hardware error notifaction structure in bytes. I will add a new
> macro such as ACPI_GHES_HW_ERROR_NOTIF_LENGTH.
no need - just write a comment near where you use it.
> >
> >> 0,
> >> + 0, 0, 0, 0, 0, 0);
> >> + } else {
> >> + g_assert_not_reached();
> >
> > OK so how about we just drop all these loops for
> > ACPI_GHES_ERROR_SOURCE_COUNT?
>
> Even though we only support ARMv8 SEA notification type now, we still use these loops for
> scalability. Maybe we need to add a new staic array for these loops, like below:
>
> static uint8_t acpi_ghes_hw_srouces[ACPI_GHES_ERROR_SOURCE_COUNT] = {
> ACPI_GHES_NOTIFY_SEA
> };
just keep code simple, it won't be hard to add loops when needed.
> >
> >
> >> + }
> >> +
> >> + /* Error Status Block Length */
> >> + build_append_int_noprefix(table_data, ACPI_GHES_MAX_RAW_DATA_LENGTH, 4);
> >> +
> >> + /* Read Ack Register
> >> + * ACPI 6.1: 18.3.2.8 Generic Hardware Error Source
> >> + * version 2 (GHESv2 - Type 10)
> >> + */
> >> + build_append_gas(table_data, AML_SYSTEM_MEMORY, 0x40, 0,
> >> + 4 /* QWord access */, 0);
> >> + bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
> >> + ACPI_GHES_READ_ACK_REGISTER_ADDRESS_OFFSET(hest_start, i),
> >> + ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE,
> >> + (ACPI_GHES_ERROR_SOURCE_COUNT + i) * ACPI_GHES_ADDRESS_SIZE);
> >> +
> >> + /* Read Ack Preserve */
> >> + build_append_int_noprefix(table_data, 0xfffffffffffffffe, 8);
> >
> > don't we need to specify ULL? Also isn't this just ~0x1ULL?
>
> Yes, I will use ~0x1ULL instead.
>
> >
> > you should try to document values not just field names.
> > e.g. why is ~0x1ULL specifically? which bits are clear?
>
> OK, I will document it. According to "ACPI 6.2: 18.3.2.8 Generic Hardware Error
> Source version 2 (GHESv2 - Type 10)", we only provide the first bit to OSPM while
> the other bits are preserved. That's why we initialize the value of Read Ack Register
> to 1.
so write comments near each value.
> >
> >> + /* Read Ack Write */
> >> + build_append_int_noprefix(table_data, 0x1, 8);
> >> + }
> >> +
> >> + build_header(linker, table_data, (void *)(table_data->data + hest_start),
> >> + "HEST", table_data->len - hest_start, 1, NULL, "GHES");
> >> +}
> >> +
> >> +static AcpiGhesState ges;
> >> +void acpi_ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error)
> >> +{
> >> +
> >> + size_t size = 2 * ACPI_GHES_ADDRESS_SIZE + ACPI_GHES_MAX_RAW_DATA_LENGTH;
> >> + size_t request_block_size = ACPI_GHES_ERROR_SOURCE_COUNT * size;
> >> +
> >> + /* Create a read-only fw_cfg file for GHES */
> >> + fw_cfg_add_file(s, ACPI_GHES_ERRORS_FW_CFG_FILE, hardware_error->data,
> >> + request_block_size);
> >> +
> >> + /* Create a read-write fw_cfg file for Address */
> >> + fw_cfg_add_file_callback(s, ACPI_GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL,
> >> + NULL, &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false);
> >> +}
> >> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> >> index 78aee1a2f9..bfdb84c517 100644
> >> --- a/hw/acpi/aml-build.c
> >> +++ b/hw/acpi/aml-build.c
> >> @@ -1578,6 +1578,7 @@ void acpi_build_tables_init(AcpiBuildTables *tables)
> >> tables->table_data = g_array_new(false, true /* clear */, 1);
> >> tables->tcpalog = g_array_new(false, true /* clear */, 1);
> >> tables->vmgenid = g_array_new(false, true /* clear */, 1);
> >> + tables->hardware_errors = g_array_new(false, true /* clear */, 1);
> >> tables->linker = bios_linker_loader_init();
> >> }
> >>
> >> @@ -1588,6 +1589,7 @@ void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre)
> >> g_array_free(tables->table_data, true);
> >> g_array_free(tables->tcpalog, mfre);
> >> g_array_free(tables->vmgenid, mfre);
> >> + g_array_free(tables->hardware_errors, mfre);
> >> }
> >>
> >> /*
> >> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> >> index 6cdf156cf5..c74e178aa0 100644
> >> --- a/hw/arm/virt-acpi-build.c
> >> +++ b/hw/arm/virt-acpi-build.c
> >> @@ -46,6 +46,7 @@
> >> #include "sysemu/reset.h"
> >> #include "kvm_arm.h"
> >> #include "migration/vmstate.h"
> >> +#include "hw/acpi/acpi_ghes.h"
> >>
> >> #define ARM_SPI_BASE 32
> >> #define ACPI_POWER_BUTTON_DEVICE "PWRB"
> >> @@ -796,6 +797,13 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
> >> acpi_add_table(table_offsets, tables_blob);
> >> build_spcr(tables_blob, tables->linker, vms);
> >>
> >> + if (vms->ras) {
> >> + acpi_add_table(table_offsets, tables_blob);
> >> + acpi_ghes_build_error_table(tables->hardware_errors, tables->linker);
> >> + acpi_ghes_build_hest(tables_blob, tables->hardware_errors,
> >> + tables->linker);
> >> + }
> >> +
> >> if (ms->numa_state->num_nodes > 0) {
> >> acpi_add_table(table_offsets, tables_blob);
> >> build_srat(tables_blob, tables->linker, vms);
> >> @@ -913,6 +921,10 @@ void virt_acpi_setup(VirtMachineState *vms)
> >> fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
> >> acpi_data_len(tables.tcpalog));
> >>
> >> + if (vms->ras) {
> >> + acpi_ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors);
> >> + }
> >> +
> >> build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update,
> >> build_state, tables.rsdp,
> >> ACPI_BUILD_RSDP_FILE, 0);
> >> diff --git a/include/hw/acpi/acpi_ghes.h b/include/hw/acpi/acpi_ghes.h
> >> new file mode 100644
> >> index 0000000000..69747ba3d7
> >> --- /dev/null
> >> +++ b/include/hw/acpi/acpi_ghes.h
> >> @@ -0,0 +1,103 @@
> >> +/* Support for generating APEI tables and record CPER for Guests
> >> + *
> >> + * Copyright (C) 2019 Huawei Corporation.
> >> + *
> >> + * Author: Dongjiu Geng <gengdongjiu@huawei.com>
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify
> >> + * it under the terms of the GNU General Public License as published by
> >> + * the Free Software Foundation; either version 2 of the License, or
> >> + * (at your option) any later version.
> >> +
> >> + * This program is distributed in the hope that it will be useful,
> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> >> + * GNU General Public License for more details.
> >> +
> >> + * You should have received a copy of the GNU General Public License along
> >> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> >> + */
> >> +
> >> +#ifndef ACPI_GHES_H
> >> +#define ACPI_GHES_H
> >> +
> >> +#include "hw/acpi/bios-linker-loader.h"
> >> +
> >> +#define ACPI_GHES_ERRORS_FW_CFG_FILE "etc/hardware_errors"
> >> +#define ACPI_GHES_DATA_ADDR_FW_CFG_FILE "etc/hardware_errors_addr"
> >> +
> >> +/* The size of Address field in Generic Address Structure,
> >> + * ACPI 2.0/3.0: 5.2.3.1 Generic Address Structure.
> >> + */
> >> +#define ACPI_GHES_ADDRESS_SIZE 8
> >> +
> >> +/* The max size in bytes for one error block */
> >> +#define ACPI_GHES_MAX_RAW_DATA_LENGTH 0x1000
> >> +
> >> +/* Now only support ARMv8 SEA notification type error source
> >> + */
> >> +#define ACPI_GHES_ERROR_SOURCE_COUNT 1
> >> +
> >> +/*
> >> + * Generic Hardware Error Source version 2
> >> + */
> >> +#define ACPI_GHES_SOURCE_GENERIC_ERROR_V2 10
> >> +
> >> +/*
> >> + * Values for Hardware Error Notification Type field
> >> + */
> >> +enum AcpiGhesNotifyType {
> >> + ACPI_GHES_NOTIFY_POLLED = 0, /* Polled */
> >> + ACPI_GHES_NOTIFY_EXTERNAL = 1, /* External Interrupt */
> >> + ACPI_GHES_NOTIFY_LOCAL = 2, /* Local Interrupt */
> >> + ACPI_GHES_NOTIFY_SCI = 3, /* SCI */
> >> + ACPI_GHES_NOTIFY_NMI = 4, /* NMI */
> >> + ACPI_GHES_NOTIFY_CMCI = 5, /* CMCI, ACPI 5.0: 18.3.2.7, Table 18-290 */
> >> + ACPI_GHES_NOTIFY_MCE = 6, /* MCE, ACPI 5.0: 18.3.2.7, Table 18-290 */
> >> + /* GPIO-Signal, ACPI 6.0: 18.3.2.7, Table 18-332 */
> >> + ACPI_GHES_NOTIFY_GPIO = 7,
> >> + /* ARMv8 SEA, ACPI 6.1: 18.3.2.9, Table 18-345 */
> >> + ACPI_GHES_NOTIFY_SEA = 8,
> >> + /* ARMv8 SEI, ACPI 6.1: 18.3.2.9, Table 18-345 */
> >> + ACPI_GHES_NOTIFY_SEI = 9,
> >> + /* External Interrupt - GSIV, ACPI 6.1: 18.3.2.9, Table 18-345 */
> >> + ACPI_GHES_NOTIFY_GSIV = 10,
> >> + /* Software Delegated Exception, ACPI 6.2: 18.3.2.9, Table 18-383 */
> >> + ACPI_GHES_NOTIFY_SDEI = 11,
> >> + ACPI_GHES_NOTIFY_RESERVED = 12 /* 12 and greater are reserved */
> >> +};
> >> +
> >> +/*
> >> + * | +--------------------------+ 0
> >> + * | | Header |
> >> + * | +--------------------------+ 40---+-
> >> + * | | ................. | |
> >> + * | | error_status_address-----+ 60 |
> >> + * | | ................. | |
> >> + * | | read_ack_register--------+ 104 92
> >> + * | | read_ack_preserve | |
> >> + * | | read_ack_write | |
> >> + * + +--------------------------+ 132--+-
> >> + *
> >> + * From above GHES definition, the error status address offset is 60;
> >> + * the Read ack register offset is 104, the whole size of GHESv2 is 92
> >> + */
> >> +
> >> +/* The error status address offset in GHES */
> >> +#define ACPI_GHES_ERROR_STATUS_ADDRESS_OFFSET(start_addr, n) (start_addr + \
> >> + 60 + offsetof(struct AcpiGenericAddress, address) + n * 92)
> >> +
> >> +/* The read Ack register offset in GHES */
> >> +#define ACPI_GHES_READ_ACK_REGISTER_ADDRESS_OFFSET(start_addr, n) (start_addr +\
> >> + 104 + offsetof(struct AcpiGenericAddress, address) + n * 92)
> >> +
> >> +typedef struct AcpiGhesState {
> >> + uint64_t ghes_addr_le;
> >> +} AcpiGhesState;
> >> +
> >> +void acpi_ghes_build_hest(GArray *table_data, GArray *hardware_error,
> >> + BIOSLinker *linker);
> >> +
> >> +void acpi_ghes_build_error_table(GArray *hardware_errors, BIOSLinker *linker);
> >> +void acpi_ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_errors);
> >> +#endif
> >> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> >> index 991cf05134..2cc61712fd 100644
> >> --- a/include/hw/acpi/aml-build.h
> >> +++ b/include/hw/acpi/aml-build.h
> >> @@ -220,6 +220,7 @@ struct AcpiBuildTables {
> >> GArray *rsdp;
> >> GArray *tcpalog;
> >> GArray *vmgenid;
> >> + GArray *hardware_errors;
> >> BIOSLinker *linker;
> >> } AcpiBuildTables;
> >>
> >> --
> >> 2.19.1
> >>
> >
> > .
> >
>
> --
>
> Thanks,
> Xiang
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v18 5/6] target-arm: kvm64: inject synchronous External Abort
2019-09-27 13:33 ` Peter Maydell
@ 2019-10-08 8:05 ` Xiang Zheng
0 siblings, 0 replies; 26+ messages in thread
From: Xiang Zheng @ 2019-10-08 8:05 UTC (permalink / raw)
To: Peter Maydell
Cc: Paolo Bonzini, Michael S. Tsirkin, Igor Mammedov, Shannon Zhao,
Laszlo Ersek, James Morse, gengdongjiu, Marcelo Tosatti,
Richard Henderson, Eduardo Habkost, Jonathan Cameron, xuwei (O),
kvm-devel, QEMU Developers, qemu-arm, Linuxarm, wanghaibin.wang
On 2019/9/27 21:33, Peter Maydell wrote:
> On Fri, 6 Sep 2019 at 09:33, Xiang Zheng <zhengxiang9@huawei.com> wrote:
>>
>> From: Dongjiu Geng <gengdongjiu@huawei.com>
>>
>> Introduce kvm_inject_arm_sea() function in which we will setup the type
>> of exception and the syndrome information in order to inject a virtual
>> synchronous external abort. When switching to guest, it will jump to the
>> synchronous external abort vector table entry.
>>
>> The ESR_ELx.DFSC is set to synchronous external abort(0x10), and
>> ESR_ELx.FnV is set to not valid(0x1), which will tell guest that FAR is
>> not valid and hold an UNKNOWN value. These values will be set to KVM
>> register structures through KVM_SET_ONE_REG IOCTL.
>>
>> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
>> Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
>
>> +/* Inject synchronous external abort */
>> +static void kvm_inject_arm_sea(CPUState *c)
>
> This will cause a compilation failure at this point in
> the patch series, because the compiler will complain about
> a static function which is defined but never used.
> To avoid breaking bisection, we need to put the definition
> of the function in the same patch where it's used.
Thanks, I will merge this patch with the next patch.
>
>> +{
>> + ARMCPU *cpu = ARM_CPU(c);
>> + CPUARMState *env = &cpu->env;
>> + CPUClass *cc = CPU_GET_CLASS(c);
>> + uint32_t esr;
>> + bool same_el;
>> +
>> + /**
>> + * Set the exception type to synchronous data abort
>> + * and the target exception Level to EL1.
>> + */
>
> This comment doesn't really tell us anything that's not obvious
> from the two lines of code that it's commenting on:
Yes, I will remove this comment.
>
>> + c->exception_index = EXCP_DATA_ABORT;
>> + env->exception.target_el = 1;
>> +
>> + /*
>> + * Set the DFSC to synchronous external abort and set FnV to not valid,
>> + * this will tell guest the FAR_ELx is UNKNOWN for this abort.
>> + */
>> +
>> + /* This exception comes from lower or current exception level. */
>
> This comment too is stating the obvious I think.
I will remove it too.
>
>> + same_el = arm_current_el(env) == env->exception.target_el;
>> + esr = syn_data_abort_no_iss(same_el, 1, 0, 0, 0, 0, 0x10);
>> +
>> + env->exception.syndrome = esr;
>> +
>> + /**
>
> There's a stray second '*' in this comment-start.
OK, I will remove this stray '*'.
>
>
>> + * The vcpu thread already hold BQL, so no need hold again when
>> + * calling do_interrupt
>
> I think this requirement would be better placed as a
> comment at the top of the function noting that callers
> must hold the iothread lock.
OK, I will add the comment at the top of the function.
>
>> + */
>> + cc->do_interrupt(c);
>> +}
>> +
>> #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
>> KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
>>
>> diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
>> index 5feb312941..499672ebbc 100644
>> --- a/target/arm/tlb_helper.c
>> +++ b/target/arm/tlb_helper.c
>> @@ -33,7 +33,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
>> * ISV field.
>> */
>> if (!(template_syn & ARM_EL_ISV) || target_el != 2 || s1ptw) {
>> - syn = syn_data_abort_no_iss(same_el,
>> + syn = syn_data_abort_no_iss(same_el, 0,
>> ea, 0, s1ptw, is_write, fsc);
>> } else {
>> /*
>> --
>> 2.19.1
>
> thanks
> -- PMM
>
> .
>
--
Thanks,
Xiang
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v18 6/6] target-arm: kvm64: handle SIGBUS signal from kernel or KVM
2019-09-27 13:57 ` Peter Maydell
@ 2019-10-08 12:42 ` Xiang Zheng
0 siblings, 0 replies; 26+ messages in thread
From: Xiang Zheng @ 2019-10-08 12:42 UTC (permalink / raw)
To: Peter Maydell
Cc: Paolo Bonzini, Michael S. Tsirkin, Igor Mammedov, Shannon Zhao,
Laszlo Ersek, James Morse, gengdongjiu, Marcelo Tosatti,
Richard Henderson, Eduardo Habkost, Jonathan Cameron, xuwei (O),
kvm-devel, QEMU Developers, qemu-arm, Linuxarm, wanghaibin.wang
On 2019/9/27 21:57, Peter Maydell wrote:
> On Fri, 6 Sep 2019 at 09:33, Xiang Zheng <zhengxiang9@huawei.com> wrote:
>>
>> From: Dongjiu Geng <gengdongjiu@huawei.com>
>>
>> Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type,
>> translates the host VA delivered by host to guest PA, then fills this PA
>> to guest APEI GHES memory, then notifies guest according to the SIGBUS
>> type.
>>
>> If guest accesses the poisoned memory, it generates Synchronous External
>> Abort(SEA). Then host kernel gets an APEI notification and calls
>> memory_failure() to unmapped the affected page in stage 2, finally
>> returns to guest.
>>
>> Guest continues to access PG_hwpoison page, it will trap to KVM as
>> stage2 fault, then a SIGBUS_MCEERR_AR synchronous signal is delivered to
>> Qemu, Qemu records this error address into guest APEI GHES memory and
>> notifes guest using Synchronous-External-Abort(SEA).
>>
>> Suggested-by: James Morse <james.morse@arm.com>
>> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
>> Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
>> ---
>> hw/acpi/acpi_ghes.c | 252 ++++++++++++++++++++++++++++++++++++
>> include/hw/acpi/acpi_ghes.h | 40 ++++++
>> include/sysemu/kvm.h | 2 +-
>> target/arm/kvm64.c | 39 ++++++
>> 4 files changed, 332 insertions(+), 1 deletion(-)
>
> I'll let somebody else review the ACPI parts as that's not my
> area of expertise, but I'll look at the target/arm parts below:
>
>> diff --git a/hw/acpi/acpi_ghes.c b/hw/acpi/acpi_ghes.c
>> index 20c45179ff..2d17c88045 100644
>> --- a/hw/acpi/acpi_ghes.c
>> +++ b/hw/acpi/acpi_ghes.c
>> @@ -26,6 +26,168 @@
>> #include "sysemu/sysemu.h"
>> #include "qemu/error-report.h"
>>
>> +/* Total size for Generic Error Status Block
>
> This block comment should start with '/*' on a line of its own
> (as should others in this patch). Usually checkpatch catches these
> but it's not infallible.
Yes, checkpatch catches these and reports 'WARNING' informations. I will
clean up all these 'WARINIG's.
>
>> diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
>> index 909bcd77cf..5f57e4ed43 100644
>> --- a/include/sysemu/kvm.h
>> +++ b/include/sysemu/kvm.h
>> @@ -378,7 +378,7 @@ bool kvm_vcpu_id_is_valid(int vcpu_id);
>> /* Returns VCPU ID to be used on KVM_CREATE_VCPU ioctl() */
>> unsigned long kvm_arch_vcpu_id(CPUState *cpu);
>>
>> -#ifdef TARGET_I386
>> +#if defined(TARGET_I386) || defined(TARGET_AARCH64)
>> #define KVM_HAVE_MCE_INJECTION 1
>> void kvm_arch_on_sigbus_vcpu(CPUState *cpu, int code, void *addr);
>> #endif
>
> Rather than introducing a new ifdef with lots of TARGET_*,
> I think it would be better to have target/i386/cpu.h and
> target/arm/cpu.h do "#define KVM_HAVE_MCE_INJECTION 1"
> (nb that the arm cpu.h needs to define it only for aarch64,
> not for 32-bit arm host compiles).
>
> and then kvm.h can just do
> #ifdef KVM_HAVE_MCE_INJECTION
> void kvm_arch_on_sigbus_vcpu(CPUState *cpu, int code, void *addr);
> #endif
Yes, it's much better.
>
>> diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
>> index bf6edaa3f6..186d855522 100644
>> --- a/target/arm/kvm64.c
>> +++ b/target/arm/kvm64.c
>> @@ -28,6 +28,8 @@
>> #include "kvm_arm.h"
>> #include "hw/boards.h"
>> #include "internals.h"
>> +#include "hw/acpi/acpi.h"
>> +#include "hw/acpi/acpi_ghes.h"
>>
>> static bool have_guest_debug;
>>
>> @@ -1070,6 +1072,43 @@ int kvm_arch_get_registers(CPUState *cs)
>> return ret;
>> }
>>
>> +void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
>> +{
>> + ram_addr_t ram_addr;
>> + hwaddr paddr;
>> +
>> + assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
>> +
>> + if (acpi_enabled && addr &&
>> + object_property_get_bool(qdev_get_machine(), "ras", NULL)) {
>> + ram_addr = qemu_ram_addr_from_host(addr);
>> + if (ram_addr != RAM_ADDR_INVALID &&
>> + kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
>> + kvm_hwpoison_page_add(ram_addr);
>> + /* Asynchronous signal will be masked by main thread, so
>> + * only handle synchronous signal.
>> + */
>
> I don't entirely understand this comment. The x86 version
> of this function says:
>
> /* If we get an action required MCE, it has been injected by KVM
> * while the VM was running. An action optional MCE instead should
> * be coming from the main thread, which qemu_init_sigbus identifies
> * as the "early kill" thread.
> */
This comment also applies to the Arm KVM.
>
> so we can be called for action-optional MCE here (not on the vcpu
> thread). We obviously can't deliver those as a synchronous exception
> to a particular CPU, but is there no mechanism for reporting them
> to the guest at all?
On the one hand, the AO MCE/SEI cannot be recovered by the guest. On the other hand,
the SIGBUS signal is masked by qemu main thread[1]. Thus we only deliver a SEA to the
target vCPU.
[1] https://lists.gnu.org/archive/html/qemu-devel/2017-11/msg03575.html.
>
>> + if (code == BUS_MCEERR_AR) {
>> + kvm_cpu_synchronize_state(c);
>> + if (ACPI_GHES_CPER_FAIL !=
>> + acpi_ghes_record_errors(ACPI_GHES_NOTIFY_SEA, paddr)) {
>> + kvm_inject_arm_sea(c);
>> + } else {
>> + fprintf(stderr, "failed to record the error\n");
>> + }
>> + }
>> + return;
>> + }
>> + fprintf(stderr, "Hardware memory error for memory used by "
>> + "QEMU itself instead of guest system!\n");
>> + }
>> +
>> + if (code == BUS_MCEERR_AR) {
>> + fprintf(stderr, "Hardware memory error!\n");
>> + exit(1);
>> + }
>> +}
>> +
>> /* C6.6.29 BRK instruction */
>> static const uint32_t brk_insn = 0xd4200000;
>>
>
> thanks
> -- PMM
>
> .
>
--
Thanks,
Xiang
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v18 3/6] ACPI: Add APEI GHES table generation support
2019-10-08 7:45 ` Michael S. Tsirkin
@ 2019-10-08 12:48 ` Xiang Zheng
0 siblings, 0 replies; 26+ messages in thread
From: Xiang Zheng @ 2019-10-08 12:48 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: peter.maydell, ehabkost, kvm, wanghaibin.wang, mtosatti,
linuxarm, qemu-devel, gengdongjiu, shannon.zhaosl, qemu-arm,
james.morse, jonathan.cameron, imammedo, pbonzini, xuwei5,
lersek, rth
On 2019/10/8 15:45, Michael S. Tsirkin wrote:
> On Tue, Oct 08, 2019 at 02:00:56PM +0800, Xiang Zheng wrote:
>> Hi Michael,
>>
>> Thanks for your review!
>>
>> On 2019/9/27 23:43, Michael S. Tsirkin wrote:
>>> On Fri, Sep 06, 2019 at 04:31:49PM +0800, Xiang Zheng wrote:
>>>> From: Dongjiu Geng <gengdongjiu@huawei.com>
>>>>
>>>> This patch implements APEI GHES Table generation via fw_cfg blobs. Now
>>>> it only supports ARMv8 SEA, a type of GHESv2 error source. Afterwards,
>>>> we can extend the supported types if needed. For the CPER section,
>>>> currently it is memory section because kernel mainly wants userspace to
>>>> handle the memory errors.
>>>>
>>>> This patch follows the spec ACPI 6.2 to build the Hardware Error Source
>>>> table. For more detailed information, please refer to document:
>>>> docs/specs/acpi_hest_ghes.txt
>>>>
>>>> Suggested-by: Laszlo Ersek <lersek@redhat.com>
>>>> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
>>>> Signed-off-by: Xiang Zheng <zhengxiang9@huawei.com>
>>>> ---
>>>> default-configs/arm-softmmu.mak | 1 +
>>>> hw/acpi/Kconfig | 4 +
>>>> hw/acpi/Makefile.objs | 1 +
>>>> hw/acpi/acpi_ghes.c | 210 ++++++++++++++++++++++++++++++++
>>>> hw/acpi/aml-build.c | 2 +
>>>> hw/arm/virt-acpi-build.c | 12 ++
>>>> include/hw/acpi/acpi_ghes.h | 103 ++++++++++++++++
>>>> include/hw/acpi/aml-build.h | 1 +
>>>> 8 files changed, 334 insertions(+)
>>>> create mode 100644 hw/acpi/acpi_ghes.c
>>>> create mode 100644 include/hw/acpi/acpi_ghes.h
>>>>
>>>> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
>>>> index 1f2e0e7fde..5722f3130e 100644
>>>> --- a/default-configs/arm-softmmu.mak
>>>> +++ b/default-configs/arm-softmmu.mak
>>>> @@ -40,3 +40,4 @@ CONFIG_FSL_IMX25=y
>>>> CONFIG_FSL_IMX7=y
>>>> CONFIG_FSL_IMX6UL=y
>>>> CONFIG_SEMIHOSTING=y
>>>> +CONFIG_ACPI_APEI=y
>>>> diff --git a/hw/acpi/Kconfig b/hw/acpi/Kconfig
>>>> index 7c59cf900b..2c4d0b9826 100644
>>>> --- a/hw/acpi/Kconfig
>>>> +++ b/hw/acpi/Kconfig
>>>> @@ -23,6 +23,10 @@ config ACPI_NVDIMM
>>>> bool
>>>> depends on ACPI
>>>>
>>>> +config ACPI_APEI
>>>> + bool
>>>> + depends on ACPI
>>>> +
>>>> config ACPI_PCI
>>>> bool
>>>> depends on ACPI && PCI
>>>> diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs
>>>> index 9bb2101e3b..93fd8e8f64 100644
>>>> --- a/hw/acpi/Makefile.objs
>>>> +++ b/hw/acpi/Makefile.objs
>>>> @@ -5,6 +5,7 @@ common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu_hotplug.o
>>>> common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o
>>>> common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu.o
>>>> common-obj-$(CONFIG_ACPI_NVDIMM) += nvdimm.o
>>>> +common-obj-$(CONFIG_ACPI_APEI) += acpi_ghes.o
>>>> common-obj-$(CONFIG_ACPI_VMGENID) += vmgenid.o
>>>> common-obj-$(call lnot,$(CONFIG_ACPI_X86)) += acpi-stub.o
>>>>
>>>> diff --git a/hw/acpi/acpi_ghes.c b/hw/acpi/acpi_ghes.c
>>>> new file mode 100644
>>>> index 0000000000..20c45179ff
>>>> --- /dev/null
>>>> +++ b/hw/acpi/acpi_ghes.c
>>>> @@ -0,0 +1,210 @@
>>>> +/* Support for generating APEI tables and record CPER for Guests
>>>> + *
>>>> + * Copyright (C) 2019 Huawei Corporation.
>>>> + *
>>>> + * Author: Dongjiu Geng <gengdongjiu@huawei.com>
>>>> + *
>>>> + * This program is free software; you can redistribute it and/or modify
>>>> + * it under the terms of the GNU General Public License as published by
>>>> + * the Free Software Foundation; either version 2 of the License, or
>>>> + * (at your option) any later version.
>>>> +
>>>> + * This program is distributed in the hope that it will be useful,
>>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>>>> + * GNU General Public License for more details.
>>>> +
>>>> + * You should have received a copy of the GNU General Public License along
>>>> + * with this program; if not, see <http://www.gnu.org/licenses/>.
>>>> + */
>>>> +
>>>> +#include "qemu/osdep.h"
>>>> +#include "hw/acpi/acpi.h"
>>>> +#include "hw/acpi/aml-build.h"
>>>> +#include "hw/acpi/acpi_ghes.h"
>>>> +#include "hw/nvram/fw_cfg.h"
>>>> +#include "sysemu/sysemu.h"
>>>> +#include "qemu/error-report.h"
>>>> +
>>>> +/* Hardware Error Notification
>>>> + * ACPI 4.0: 17.3.2.7 Hardware Error Notification
>>>> + */
>>>> +static void acpi_ghes_build_notify(GArray *table, const uint8_t type,
>>>> + uint8_t length, uint16_t config_write_enable,
>>>> + uint32_t poll_interval, uint32_t vector,
>>>> + uint32_t polling_threshold_value,
>>>> + uint32_t polling_threshold_window,
>>>> + uint32_t error_threshold_value,
>>>> + uint32_t error_threshold_window)
>>>
>>>
>>> This function has too many arguments.
>>> How about we just hard code all the 0's until we need to set them
>>> to something else?
>>
>> Yes, and we can also hard code the value of length which is always 28 and
>> indicates the total length of the structure in bytes.
>>
>>>
>>>> +{
>>>> + /* Type */
>>>> + build_append_int_noprefix(table, type, 1);
>>>> + /* Length */
>>>> + build_append_int_noprefix(table, length, 1);
>>>> + /* Configuration Write Enable */
>>>> + build_append_int_noprefix(table, config_write_enable, 2);
>>>> + /* Poll Interval */
>>>> + build_append_int_noprefix(table, poll_interval, 4);
>>>> + /* Vector */
>>>> + build_append_int_noprefix(table, vector, 4);
>>>> + /* Switch To Polling Threshold Value */
>>>> + build_append_int_noprefix(table, polling_threshold_value, 4);
>>>> + /* Switch To Polling Threshold Window */
>>>> + build_append_int_noprefix(table, polling_threshold_window, 4);
>>>> + /* Error Threshold Value */
>>>> + build_append_int_noprefix(table, error_threshold_value, 4);
>>>> + /* Error Threshold Window */
>>>> + build_append_int_noprefix(table, error_threshold_window, 4);
>>>> +}
>>>> +
>>>> +/* Build table for the hardware error fw_cfg blob */
>>>> +void acpi_ghes_build_error_table(GArray *hardware_errors, BIOSLinker *linker)
>>>> +{
>>>> + int i, error_status_block_offset;
>>>> +
>>>> + /*
>>>> + * | +--------------------------+
>>>> + * | | error_block_address |
>>>> + * | | .......... |
>>>> + * | +--------------------------+
>>>> + * | | read_ack_register |
>>>> + * | | ........... |
>>>> + * | +--------------------------+
>>>> + * | | Error Status Data Block |
>>>> + * | | ........ |
>>>> + * | +--------------------------+
>>>> + */
>>>> +
>>>> + /* Build error_block_address */
>>>> + build_append_int_noprefix(hardware_errors, 0,
>>>> + ACPI_GHES_ADDRESS_SIZE * ACPI_GHES_ERROR_SOURCE_COUNT);
>>>
>>> This works for adding more than 8 bytes but it's a bit of a hack,
>>> only works when value is 0. A loop would be a bit cleaner imho.
>>
>> Yes, this might confuse someone and it's better to use a loop instead.
>>
>>>
>>>> +
>>>> + /* Build read_ack_register */
>>>> + for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) {
>>>> + /* Initialize the value of read_ack_register to 1, so GHES can be
>>>> + * writeable in the first time.
>>>> + * ACPI 6.2: 18.3.2.8 Generic Hardware Error Source version 2
>>>> + * (GHESv2 - Type 10)
>>>> + */
>>>> + build_append_int_noprefix(hardware_errors, 1, ACPI_GHES_ADDRESS_SIZE);
>>>> + }
>>>> +
>>>> + /* Build Error Status Data Block */
>>>> + build_append_int_noprefix(hardware_errors, 0,
>>>> + ACPI_GHES_MAX_RAW_DATA_LENGTH * ACPI_GHES_ERROR_SOURCE_COUNT);
>>>> +
>>>> + /* Allocate guest memory for the hardware error fw_cfg blob */
>>>> + bios_linker_loader_alloc(linker, ACPI_GHES_ERRORS_FW_CFG_FILE,
>>>> + hardware_errors, 1, false);
>>>> +
>>>> + /* Generic Error Status Block offset in the hardware error fw_cfg blob */
>>>> + error_status_block_offset = ACPI_GHES_ADDRESS_SIZE * 2 *
>>>> + ACPI_GHES_ERROR_SOURCE_COUNT;
>>>
>>> a better way to get this is to save hardware_errors->len just before
>>> you append the padding where the value should be.
>>
>> Thanks, this really makes it better.
>>
>>>
>>>> +
>>>> + for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) {
>>>> + /* Patch address of Error Status Data Block into
>>>> + * the error_block_address of hardware_errors fw_cfg blob
>>>> + */
>>>> + bios_linker_loader_add_pointer(linker,
>>>> + ACPI_GHES_ERRORS_FW_CFG_FILE, ACPI_GHES_ADDRESS_SIZE * i,
>>>> + ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE,
>>>> + error_status_block_offset + i * ACPI_GHES_MAX_RAW_DATA_LENGTH);
>>>> + }
>>>> +
>>>> + /* Write address of hardware_errors fw_cfg blob into the
>>>> + * hardware_errors_addr fw_cfg blob.
>>>> + */
>>>> + bios_linker_loader_write_pointer(linker, ACPI_GHES_DATA_ADDR_FW_CFG_FILE,
>>>> + 0, ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE, 0);
>>>> +}
>>>> +
>>>> +/* Build Hardware Error Source Table */
>>>> +void acpi_ghes_build_hest(GArray *table_data, GArray *hardware_errors,
>>>> + BIOSLinker *linker)
>>>> +{
>>>> + uint32_t i, hest_start = table_data->len;
>>>> +
>>>> + /* Reserve Hardware Error Source Table header size */
>>>> + acpi_data_push(table_data, sizeof(AcpiTableHeader));
>>>> +
>>>> + /* Error Source Count */
>>>> + build_append_int_noprefix(table_data, ACPI_GHES_ERROR_SOURCE_COUNT, 4);
>>>> +
>>>> + /* Generic Hardware Error Source version 2(GHESv2 - Type 10) */
>>>> + for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) {
>>>> + /* Type */
>>>> + build_append_int_noprefix(table_data,
>>>> + ACPI_GHES_SOURCE_GENERIC_ERROR_V2, 2);
>>>> + /* Source Id */
>>>> + build_append_int_noprefix(table_data, i, 2);
>>>> + /* Related Source Id */
>>>> + build_append_int_noprefix(table_data, 0xffff, 2);
>>>> + /* Flags */
>>>> + build_append_int_noprefix(table_data, 0, 1);
>>>> + /* Enabled */
>>>> + build_append_int_noprefix(table_data, 1, 1);
>>>> +
>>>> + /* Number of Records To Pre-allocate */
>>>> + build_append_int_noprefix(table_data, 1, 4);
>>>> + /* Max Sections Per Record */
>>>> + build_append_int_noprefix(table_data, 1, 4);
>>>> + /* Max Raw Data Length */
>>>> + build_append_int_noprefix(table_data, ACPI_GHES_MAX_RAW_DATA_LENGTH, 4);
>>>> +
>>>> + /* Error Status Address */
>>>> + build_append_gas(table_data, AML_SYSTEM_MEMORY, 0x40, 0,
>>>> + 4 /* QWord access */, 0);
>>>> + bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
>>>> + ACPI_GHES_ERROR_STATUS_ADDRESS_OFFSET(hest_start, i),
>>>> + ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE,
>>>> + i * ACPI_GHES_ADDRESS_SIZE);
>>>> +
>>>> + if (i == 0) {
>>>> + /* Notification Structure
>>>> + * Now only enable ARMv8 SEA notification type
>>>> + */
>>>> + acpi_ghes_build_notify(table_data, ACPI_GHES_NOTIFY_SEA, 28,
>>>
>>>
>>> what's the magic 28? generally acpi_ghes_build_notify isn't self
>>> contained.
>>>
>>
>> According to "ACPI 6.2: 18.3.2.9 Hardware Error Notification", the number "28" indicates
>> the total length of the hardware error notifaction structure in bytes. I will add a new
>> macro such as ACPI_GHES_HW_ERROR_NOTIF_LENGTH.
>
>
> no need - just write a comment near where you use it.
OK, thanks.
>
>>>
>>>> 0,
>>>> + 0, 0, 0, 0, 0, 0);
>>>> + } else {
>>>> + g_assert_not_reached();
>>>
>>> OK so how about we just drop all these loops for
>>> ACPI_GHES_ERROR_SOURCE_COUNT?
>>
>> Even though we only support ARMv8 SEA notification type now, we still use these loops for
>> scalability. Maybe we need to add a new staic array for these loops, like below:
>>
>> static uint8_t acpi_ghes_hw_srouces[ACPI_GHES_ERROR_SOURCE_COUNT] = {
>> ACPI_GHES_NOTIFY_SEA
>> };
>
> just keep code simple, it won't be hard to add loops when needed.
>
OK, I will drop these loops.
>
>>>
>>>
>>>> + }
>>>> +
>>>> + /* Error Status Block Length */
>>>> + build_append_int_noprefix(table_data, ACPI_GHES_MAX_RAW_DATA_LENGTH, 4);
>>>> +
>>>> + /* Read Ack Register
>>>> + * ACPI 6.1: 18.3.2.8 Generic Hardware Error Source
>>>> + * version 2 (GHESv2 - Type 10)
>>>> + */
>>>> + build_append_gas(table_data, AML_SYSTEM_MEMORY, 0x40, 0,
>>>> + 4 /* QWord access */, 0);
>>>> + bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
>>>> + ACPI_GHES_READ_ACK_REGISTER_ADDRESS_OFFSET(hest_start, i),
>>>> + ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE,
>>>> + (ACPI_GHES_ERROR_SOURCE_COUNT + i) * ACPI_GHES_ADDRESS_SIZE);
>>>> +
>>>> + /* Read Ack Preserve */
>>>> + build_append_int_noprefix(table_data, 0xfffffffffffffffe, 8);
>>>
>>> don't we need to specify ULL? Also isn't this just ~0x1ULL?
>>
>> Yes, I will use ~0x1ULL instead.
>>
>>>
>>> you should try to document values not just field names.
>>> e.g. why is ~0x1ULL specifically? which bits are clear?
>>
>> OK, I will document it. According to "ACPI 6.2: 18.3.2.8 Generic Hardware Error
>> Source version 2 (GHESv2 - Type 10)", we only provide the first bit to OSPM while
>> the other bits are preserved. That's why we initialize the value of Read Ack Register
>> to 1.
>
> so write comments near each value.
>
Got it.
--
Thanks,
Xiang
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Qemu-devel] [PATCH v18 2/6] docs: APEI GHES generation and CPER record description
2019-10-04 8:20 ` [Qemu-devel] " Igor Mammedov
@ 2019-10-08 13:25 ` Xiang Zheng
0 siblings, 0 replies; 26+ messages in thread
From: Xiang Zheng @ 2019-10-08 13:25 UTC (permalink / raw)
To: Igor Mammedov
Cc: pbonzini, mst, shannon.zhaosl, peter.maydell, lersek,
james.morse, gengdongjiu, mtosatti, rth, ehabkost,
jonathan.cameron, xuwei5, kvm, qemu-devel, qemu-arm, linuxarm,
wanghaibin.wang
Hi Igor,
Thanks for your review!
On 2019/10/4 16:20, Igor Mammedov wrote:
> On Fri, 6 Sep 2019 16:31:48 +0800
> Xiang Zheng <zhengxiang9@huawei.com> wrote:
>
>> From: Dongjiu Geng <gengdongjiu@huawei.com>
>>
> [...]
>> +
>> +(9) When QEMU gets SIGBUS from the kernel, QEMU formats the CPER right into
>> + guest memory, and then injects whatever interrupt (or assert whatever GPIO
> s/whatever .../platform specific/
>
> and add concrete impl info like:
> "in case of arm/virt machine it's ..."
OK, I will add the concrete impl info.
>
>> + line) as a notification which is necessary for notifying the guest.
> [...]
>
> .
>
--
Thanks,
Xiang
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2019-10-08 13:25 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-09-06 8:31 [PATCH v18 0/6] Add ARMv8 RAS virtualization support in QEMU Xiang Zheng
2019-09-06 8:31 ` [PATCH v18 1/6] hw/arm/virt: Introduce RAS platform version and RAS machine option Xiang Zheng
2019-09-27 14:02 ` Peter Maydell
2019-09-29 2:04 ` Xiang Zheng
2019-09-06 8:31 ` [PATCH v18 2/6] docs: APEI GHES generation and CPER record description Xiang Zheng
2019-09-19 13:25 ` Peter Maydell
2019-09-20 1:45 ` Xiang Zheng
2019-10-04 8:20 ` [Qemu-devel] " Igor Mammedov
2019-10-08 13:25 ` Xiang Zheng
2019-09-06 8:31 ` [PATCH v18 3/6] ACPI: Add APEI GHES table generation support Xiang Zheng
2019-09-27 15:43 ` Michael S. Tsirkin
2019-10-08 6:00 ` Xiang Zheng
2019-10-08 7:45 ` Michael S. Tsirkin
2019-10-08 12:48 ` Xiang Zheng
2019-09-06 8:31 ` [PATCH v18 4/6] KVM: Move hwpoison page related functions into include/sysemu/kvm_int.h Xiang Zheng
2019-09-27 13:19 ` [Qemu-arm] " Peter Maydell
2019-10-08 7:01 ` Xiang Zheng
2019-09-06 8:31 ` [PATCH v18 5/6] target-arm: kvm64: inject synchronous External Abort Xiang Zheng
2019-09-27 13:33 ` Peter Maydell
2019-10-08 8:05 ` Xiang Zheng
2019-09-06 8:31 ` [PATCH v18 6/6] target-arm: kvm64: handle SIGBUS signal from kernel or KVM Xiang Zheng
2019-09-27 13:57 ` Peter Maydell
2019-10-08 12:42 ` Xiang Zheng
2019-09-17 12:39 ` [PATCH v18 0/6] Add ARMv8 RAS virtualization support in QEMU Xiang Zheng
2019-09-20 2:07 ` gengdongjiu
2019-09-27 14:03 ` [Qemu-arm] " Peter Maydell
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