Re: [PATCH v2 1/3] KVM: x86: Allow CPU to force vendor-specific TDP level

From: Jim Mattson <jmattson@google.com>
To: Sean Christopherson <seanjc@google.com>
Cc: Yu Zhang <yu.c.zhang@linux.intel.com>,
	Wei Huang <wei.huang2@amd.com>,
	kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
	pbonzini@redhat.com, vkuznets@redhat.com, wanpengli@tencent.com,
	joro@8bytes.org, tglx@linutronix.de, mingo@redhat.com,
	bp@alien8.de, x86@kernel.org, hpa@zytor.com
Subject: Re: [PATCH v2 1/3] KVM: x86: Allow CPU to force vendor-specific TDP level
Date: Mon, 9 Aug 2021 14:49:47 -0700	[thread overview]
Message-ID: <CALMp9eRfuntBFz=gnsvEuTXAXZorWJFAPq0ZdwZePxxQYGzdQA@mail.gmail.com> (raw)
In-Reply-To: <YRFKABg2MOJxcq+y@google.com>

On Mon, Aug 9, 2021 at 8:30 AM Sean Christopherson <seanjc@google.com> wrote:
>
> On Mon, Aug 09, 2021, Yu Zhang wrote:
> > On Sun, Aug 08, 2021 at 11:33:44PM -0500, Wei Huang wrote:
> > >
> > > On 8/8/21 11:27 PM, Yu Zhang wrote:
> > > > On Sun, Aug 08, 2021 at 11:11:40PM -0500, Wei Huang wrote:
> > > > >
> > > > >
> > > > > On 8/8/21 10:58 PM, Yu Zhang wrote:
> > > > > > On Sun, Aug 08, 2021 at 02:26:56PM -0500, Wei Huang wrote:
> > > > > > > AMD future CPUs will require a 5-level NPT if host CR4.LA57 is set.
> > > > > >
> > > > > > Sorry, but why? NPT is not indexed by HVA.
> > > > >
> > > > > NPT is not indexed by HVA - it is always indexed by GPA. What I meant is NPT
> > > > > page table level has to be the same as the host OS page table: if 5-level
> > > > > page table is enabled in host OS (CR4.LA57=1), guest NPT has to 5-level too.
> > > >
> > > > I know what you meant. But may I ask why?
> > >
> > > I don't have a good answer for it. From what I know, VMCB doesn't have a
> > > field to indicate guest page table level. As a result, hardware relies on
> > > host CR4 to infer NPT level.
> >
> > I guess you mean not even in the N_CR3 field of VMCB?
>
> Correct, nCR3 is a basically a pure representation of a regular CR3.
>
> > Then it's not a broken design - it's a limitation of SVM. :)
>
> That's just a polite way of saying it's a broken design ;-)

Doesn't this break legacy type 2 hypervisors that don't know anything
about 5-level NPT and don't have any control over whether or not the
host uses 5-level paging?

> Joking aside, NPT opted for a semblance of backwards compatibility at the cost of
> having to carry all the baggage that comes with a legacy design.  Keeping the core
> functionality from IA32 paging presumably miminizes design and hardware costs, and
> required minimal enabling in hypervisors.  The downside is that it's less flexible
> than EPT and has a few warts, e.g. shadowing NPT is gross because the host can't
> easily mirror L1's desired paging mode.