RE: [PATCH v2 1/5] iommufd: Add nesting related data structures for Intel VT-d

["Liu, Yi L" <yi.l.liu@intel.com>]

> From: Liu, Jingqi <jingqi.liu@intel.com>
> Sent: Wednesday, March 15, 2023 9:51 PM
> 
> 
> On 3/9/2023 4:22 PM, Yi Liu wrote:
> > Add the following data structures for corresponding ioctls:
> >                 iommu_hwpt_intel_vtd => IOMMU_HWPT_ALLOC
> >                iommu_hw_info_vtd => IOMMU_DEVICE_GET_HW_INFO
> >      iommu_hwpt_invalidate_intel_vtd => IOMMU_HWPT_INVALIDATE
> >
> > Also, add IOMMU_HW_INFO_TYPE_INTEL_VTD and
> IOMMU_HWPT_TYPE_VTD_S1 to the
> > header and corresponding type/size arrays.
> >
> > Signed-off-by: Yi Liu <yi.l.liu@intel.com>
> > ---
> >   drivers/iommu/iommufd/hw_pagetable.c |   7 +-
> >   drivers/iommu/iommufd/main.c         |   5 +
> >   include/uapi/linux/iommufd.h         | 136
> +++++++++++++++++++++++++++
> >   3 files changed, 147 insertions(+), 1 deletion(-)
> >
> [...]
> 
> > +
> > +/**
> > + * struct iommu_hwpt_intel_vtd - Intel VT-d specific user-managed
> > + *                               stage-1 page table info
> > + * @flags: Combination of enum iommu_hwpt_intel_vtd_flags
> > + * @pgtbl_addr: The base address of the user-managed stage-1 page
> table.
> > + * @pat: Page attribute table data to compute effective memory type
> > + * @emt: Extended memory type
> > + * @addr_width: The address width of the untranslated addresses that
> are
> > + *              subjected to the user-managed stage-1 page table.
> > + * @__reserved: Must be 0
> > + *
> > + * The Intel VT-d specific data for creating hw_pagetable to represent
> > + * the user-managed stage-1 page table that is used in nested translation.
> > + *
> > + * In nested translation, the stage-1 page table locates in the address
> > + * space that defined by the corresponding stage-2 page table. Hence
> the
> > + * stage-1 page table base address value should not be higher than the
> > + * maximum untranslated address of stage-2 page table.
> > + *
> > + * The paging level of the stage-1 page table should be compataible with
> 
> s/compataible/compatible
> 
> > + * the hardware iommu. Otherwise, the allocation would be failed.
> > + */
> > +struct iommu_hwpt_intel_vtd {
> > +	__u64 flags;
> > +	__u64 pgtbl_addr;
> > +	__u32 pat;
> > +	__u32 emt;
> > +	__u32 addr_width;
> > +	__u32 __reserved;
> >   };
> >
> 
> [...]
> 
> > +
> > +/**
> > + * struct iommu_hwpt_invalidate_intel_vtd - Intel VT-d cache
> invalidation info
> > + * @granularity: One of enum iommu_vtd_qi_granularity.
> > + * @flags: Combination of enum
> iommu_hwpt_intel_vtd_invalidate_flags
> > + * @__reserved: Must be 0
> > + * @addr: The start address of the addresses to be invalidated.
> > + * @granule_size: Page/block size of the mapping in bytes. It is used to
> > + *                compute the invalidation range togehter with @nb_granules.
> 
> s/togehter/together
> 

All above received. Thanks.

Regards,
Yi Liu