* [PATCH] KVM: SVM: Fix x2APIC MSRs interception
@ 2022-07-18 8:38 Suravee Suthikulpanit
2022-07-18 9:38 ` Maxim Levitsky
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Suravee Suthikulpanit @ 2022-07-18 8:38 UTC (permalink / raw)
To: linux-kernel, kvm
Cc: pbonzini, mlevitsk, seanjc, jon.grimm, Suravee Suthikulpanit
The index for svm_direct_access_msrs was incorrectly initialized with
the APIC MMIO register macros. Fix by introducing a macro for calculating
x2APIC MSRs.
Fixes: 5c127c85472c ("KVM: SVM: Adding support for configuring x2APIC MSRs interception")
Cc: Maxim Levitsky <mlevitsk@redhat.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
arch/x86/kvm/svm/svm.c | 52 ++++++++++++++++++++++--------------------
1 file changed, 27 insertions(+), 25 deletions(-)
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index ba81a7e58f75..aef63aae922d 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -74,6 +74,8 @@ static uint64_t osvw_len = 4, osvw_status;
static DEFINE_PER_CPU(u64, current_tsc_ratio);
+#define X2APIC_MSR(x) (APIC_BASE_MSR + (x >> 4))
+
static const struct svm_direct_access_msrs {
u32 index; /* Index of the MSR */
bool always; /* True if intercept is initially cleared */
@@ -100,31 +102,31 @@ static const struct svm_direct_access_msrs {
{ .index = MSR_IA32_CR_PAT, .always = false },
{ .index = MSR_AMD64_SEV_ES_GHCB, .always = true },
{ .index = MSR_TSC_AUX, .always = false },
- { .index = (APIC_BASE_MSR + APIC_ID), .always = false },
- { .index = (APIC_BASE_MSR + APIC_LVR), .always = false },
- { .index = (APIC_BASE_MSR + APIC_TASKPRI), .always = false },
- { .index = (APIC_BASE_MSR + APIC_ARBPRI), .always = false },
- { .index = (APIC_BASE_MSR + APIC_PROCPRI), .always = false },
- { .index = (APIC_BASE_MSR + APIC_EOI), .always = false },
- { .index = (APIC_BASE_MSR + APIC_RRR), .always = false },
- { .index = (APIC_BASE_MSR + APIC_LDR), .always = false },
- { .index = (APIC_BASE_MSR + APIC_DFR), .always = false },
- { .index = (APIC_BASE_MSR + APIC_SPIV), .always = false },
- { .index = (APIC_BASE_MSR + APIC_ISR), .always = false },
- { .index = (APIC_BASE_MSR + APIC_TMR), .always = false },
- { .index = (APIC_BASE_MSR + APIC_IRR), .always = false },
- { .index = (APIC_BASE_MSR + APIC_ESR), .always = false },
- { .index = (APIC_BASE_MSR + APIC_ICR), .always = false },
- { .index = (APIC_BASE_MSR + APIC_ICR2), .always = false },
- { .index = (APIC_BASE_MSR + APIC_LVTT), .always = false },
- { .index = (APIC_BASE_MSR + APIC_LVTTHMR), .always = false },
- { .index = (APIC_BASE_MSR + APIC_LVTPC), .always = false },
- { .index = (APIC_BASE_MSR + APIC_LVT0), .always = false },
- { .index = (APIC_BASE_MSR + APIC_LVT1), .always = false },
- { .index = (APIC_BASE_MSR + APIC_LVTERR), .always = false },
- { .index = (APIC_BASE_MSR + APIC_TMICT), .always = false },
- { .index = (APIC_BASE_MSR + APIC_TMCCT), .always = false },
- { .index = (APIC_BASE_MSR + APIC_TDCR), .always = false },
+ { .index = X2APIC_MSR(APIC_ID), .always = false },
+ { .index = X2APIC_MSR(APIC_LVR), .always = false },
+ { .index = X2APIC_MSR(APIC_TASKPRI), .always = false },
+ { .index = X2APIC_MSR(APIC_ARBPRI), .always = false },
+ { .index = X2APIC_MSR(APIC_PROCPRI), .always = false },
+ { .index = X2APIC_MSR(APIC_EOI), .always = false },
+ { .index = X2APIC_MSR(APIC_RRR), .always = false },
+ { .index = X2APIC_MSR(APIC_LDR), .always = false },
+ { .index = X2APIC_MSR(APIC_DFR), .always = false },
+ { .index = X2APIC_MSR(APIC_SPIV), .always = false },
+ { .index = X2APIC_MSR(APIC_ISR), .always = false },
+ { .index = X2APIC_MSR(APIC_TMR), .always = false },
+ { .index = X2APIC_MSR(APIC_IRR), .always = false },
+ { .index = X2APIC_MSR(APIC_ESR), .always = false },
+ { .index = X2APIC_MSR(APIC_ICR), .always = false },
+ { .index = X2APIC_MSR(APIC_ICR2), .always = false },
+ { .index = X2APIC_MSR(APIC_LVTT), .always = false },
+ { .index = X2APIC_MSR(APIC_LVTTHMR), .always = false },
+ { .index = X2APIC_MSR(APIC_LVTPC), .always = false },
+ { .index = X2APIC_MSR(APIC_LVT0), .always = false },
+ { .index = X2APIC_MSR(APIC_LVT1), .always = false },
+ { .index = X2APIC_MSR(APIC_LVTERR), .always = false },
+ { .index = X2APIC_MSR(APIC_TMICT), .always = false },
+ { .index = X2APIC_MSR(APIC_TMCCT), .always = false },
+ { .index = X2APIC_MSR(APIC_TDCR), .always = false },
{ .index = MSR_INVALID, .always = false },
};
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] KVM: SVM: Fix x2APIC MSRs interception
2022-07-18 8:38 [PATCH] KVM: SVM: Fix x2APIC MSRs interception Suravee Suthikulpanit
@ 2022-07-18 9:38 ` Maxim Levitsky
2022-07-19 13:21 ` Paolo Bonzini
2022-07-19 19:11 ` Sean Christopherson
2 siblings, 0 replies; 4+ messages in thread
From: Maxim Levitsky @ 2022-07-18 9:38 UTC (permalink / raw)
To: Suravee Suthikulpanit, linux-kernel, kvm; +Cc: pbonzini, seanjc, jon.grimm
On Mon, 2022-07-18 at 03:38 -0500, Suravee Suthikulpanit wrote:
> The index for svm_direct_access_msrs was incorrectly initialized with
> the APIC MMIO register macros. Fix by introducing a macro for calculating
> x2APIC MSRs.
>
> Fixes: 5c127c85472c ("KVM: SVM: Adding support for configuring x2APIC MSRs interception")
> Cc: Maxim Levitsky <mlevitsk@redhat.com>
> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> ---
> arch/x86/kvm/svm/svm.c | 52 ++++++++++++++++++++++--------------------
> 1 file changed, 27 insertions(+), 25 deletions(-)
>
> diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
> index ba81a7e58f75..aef63aae922d 100644
> --- a/arch/x86/kvm/svm/svm.c
> +++ b/arch/x86/kvm/svm/svm.c
> @@ -74,6 +74,8 @@ static uint64_t osvw_len = 4, osvw_status;
>
> static DEFINE_PER_CPU(u64, current_tsc_ratio);
>
> +#define X2APIC_MSR(x) (APIC_BASE_MSR + (x >> 4))
> +
> static const struct svm_direct_access_msrs {
> u32 index; /* Index of the MSR */
> bool always; /* True if intercept is initially cleared */
> @@ -100,31 +102,31 @@ static const struct svm_direct_access_msrs {
> { .index = MSR_IA32_CR_PAT, .always = false },
> { .index = MSR_AMD64_SEV_ES_GHCB, .always = true },
> { .index = MSR_TSC_AUX, .always = false },
> - { .index = (APIC_BASE_MSR + APIC_ID), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_LVR), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_TASKPRI), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_ARBPRI), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_PROCPRI), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_EOI), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_RRR), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_LDR), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_DFR), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_SPIV), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_ISR), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_TMR), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_IRR), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_ESR), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_ICR), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_ICR2), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_LVTT), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_LVTTHMR), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_LVTPC), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_LVT0), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_LVT1), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_LVTERR), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_TMICT), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_TMCCT), .always = false },
> - { .index = (APIC_BASE_MSR + APIC_TDCR), .always = false },
> + { .index = X2APIC_MSR(APIC_ID), .always = false },
> + { .index = X2APIC_MSR(APIC_LVR), .always = false },
> + { .index = X2APIC_MSR(APIC_TASKPRI), .always = false },
> + { .index = X2APIC_MSR(APIC_ARBPRI), .always = false },
> + { .index = X2APIC_MSR(APIC_PROCPRI), .always = false },
> + { .index = X2APIC_MSR(APIC_EOI), .always = false },
> + { .index = X2APIC_MSR(APIC_RRR), .always = false },
> + { .index = X2APIC_MSR(APIC_LDR), .always = false },
> + { .index = X2APIC_MSR(APIC_DFR), .always = false },
> + { .index = X2APIC_MSR(APIC_SPIV), .always = false },
> + { .index = X2APIC_MSR(APIC_ISR), .always = false },
> + { .index = X2APIC_MSR(APIC_TMR), .always = false },
> + { .index = X2APIC_MSR(APIC_IRR), .always = false },
> + { .index = X2APIC_MSR(APIC_ESR), .always = false },
> + { .index = X2APIC_MSR(APIC_ICR), .always = false },
> + { .index = X2APIC_MSR(APIC_ICR2), .always = false },
> + { .index = X2APIC_MSR(APIC_LVTT), .always = false },
> + { .index = X2APIC_MSR(APIC_LVTTHMR), .always = false },
> + { .index = X2APIC_MSR(APIC_LVTPC), .always = false },
> + { .index = X2APIC_MSR(APIC_LVT0), .always = false },
> + { .index = X2APIC_MSR(APIC_LVT1), .always = false },
> + { .index = X2APIC_MSR(APIC_LVTERR), .always = false },
> + { .index = X2APIC_MSR(APIC_TMICT), .always = false },
> + { .index = X2APIC_MSR(APIC_TMCCT), .always = false },
> + { .index = X2APIC_MSR(APIC_TDCR), .always = false },
> { .index = MSR_INVALID, .always = false },
Ouch.
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
Best regards,
Maxim Levitsky
> };
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] KVM: SVM: Fix x2APIC MSRs interception
2022-07-18 8:38 [PATCH] KVM: SVM: Fix x2APIC MSRs interception Suravee Suthikulpanit
2022-07-18 9:38 ` Maxim Levitsky
@ 2022-07-19 13:21 ` Paolo Bonzini
2022-07-19 19:11 ` Sean Christopherson
2 siblings, 0 replies; 4+ messages in thread
From: Paolo Bonzini @ 2022-07-19 13:21 UTC (permalink / raw)
To: Suravee Suthikulpanit
Cc: linux-kernel, kvm, pbonzini, mlevitsk, seanjc, jon.grimm
Queued, thanks.
Paolo
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] KVM: SVM: Fix x2APIC MSRs interception
2022-07-18 8:38 [PATCH] KVM: SVM: Fix x2APIC MSRs interception Suravee Suthikulpanit
2022-07-18 9:38 ` Maxim Levitsky
2022-07-19 13:21 ` Paolo Bonzini
@ 2022-07-19 19:11 ` Sean Christopherson
2 siblings, 0 replies; 4+ messages in thread
From: Sean Christopherson @ 2022-07-19 19:11 UTC (permalink / raw)
To: Suravee Suthikulpanit; +Cc: linux-kernel, kvm, pbonzini, mlevitsk, jon.grimm
On Mon, Jul 18, 2022, Suravee Suthikulpanit wrote:
> The index for svm_direct_access_msrs was incorrectly initialized with
> the APIC MMIO register macros. Fix by introducing a macro for calculating
> x2APIC MSRs.
>
> Fixes: 5c127c85472c ("KVM: SVM: Adding support for configuring x2APIC MSRs interception")
> Cc: Maxim Levitsky <mlevitsk@redhat.com>
> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> ---
> arch/x86/kvm/svm/svm.c | 52 ++++++++++++++++++++++--------------------
> 1 file changed, 27 insertions(+), 25 deletions(-)
>
> diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
> index ba81a7e58f75..aef63aae922d 100644
> --- a/arch/x86/kvm/svm/svm.c
> +++ b/arch/x86/kvm/svm/svm.c
> @@ -74,6 +74,8 @@ static uint64_t osvw_len = 4, osvw_status;
>
> static DEFINE_PER_CPU(u64, current_tsc_ratio);
>
> +#define X2APIC_MSR(x) (APIC_BASE_MSR + (x >> 4))
Once this hits kvm/queue, I'll send a follow-up series to move X2APIC_MSR() to
arch/x86/include/asm/apicdef.h. Non-KVM APIC support open code the calculation
in multiple places, and both VMX and SVM now have their own definitions.
^ permalink raw reply [flat|nested] 4+ messages in thread
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2022-07-18 9:38 ` Maxim Levitsky
2022-07-19 13:21 ` Paolo Bonzini
2022-07-19 19:11 ` Sean Christopherson
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