* [PATCH 00/19] target/mips: Boring code reordering
@ 2020-12-06 23:39 Philippe Mathieu-Daudé
2020-12-06 23:39 ` [PATCH 01/19] hw/mips: Move address translation helpers to target/mips/ Philippe Mathieu-Daudé
` (19 more replies)
0 siblings, 20 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-06 23:39 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Philippe Mathieu-Daudé,
Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
Hi,
This is not what I had plan to finish this WE but well...
at least it is done, and the following series will be
clearer/easier to review.
There are now less dependencies on the big translate.c,
and we can almost build a KVM-only binary (without TCG).
Yet another very boring patch series, sorry.
Regards,
Phil.
Philippe Mathieu-Daudé (19):
hw/mips: Move address translation helpers to target/mips/
target/mips: Remove unused headers from translate.c
target/mips: Remove unused headers from fpu_helper.c
target/mips: Remove unused headers from cp0_helper.c
target/mips: Remove unused headers from op_helper.c
target/mips: Remove unused headers from kvm.c
target/mips: Include "exec/memattrs.h" in 'internal.h'
target/mips: Extract cpu_supports*/cpu_set* translate.c
target/mips: Move mips_cpu_add_definition() from helper.c to cpu.c
target/mips: Add !CONFIG_USER_ONLY comment after #endif
target/mips: Extract common helpers from helper.c to common_helper.c
target/mips: Rename helper.c as tlb_helper.c
target/mips: Fix code style for checkpatch.pl
target/mips: Move mmu_init() functions to tlb_helper.c
target/mips: Move cpu definitions, reset() and realize() to cpu.c
target/mips: Inline cpu_mips_realize_env() in mips_cpu_realizefn()
target/mips: Rename translate_init.c as cpu-defs.c
target/mips: Restrict some TCG specific CPUClass handlers
target/mips: Only build TCG code when CONFIG_TCG is set
include/hw/mips/cpudevs.h | 7 -
target/mips/cpu.h | 8 +
target/mips/internal.h | 6 +-
hw/mips/boston.c | 1 -
{hw => target}/mips/addr.c | 2 +-
target/mips/common_helper.c | 178 ++++++++++
target/mips/cp0_helper.c | 4 +-
target/mips/cpu.c | 309 +++++++++++++++++-
target/mips/fpu_helper.c | 4 -
target/mips/kvm.c | 3 -
target/mips/op_helper.c | 4 -
target/mips/{helper.c => tlb_helper.c} | 244 +++-----------
target/mips/translate.c | 262 ---------------
hw/mips/meson.build | 2 +-
.../{translate_init.c.inc => cpu-defs.c.inc} | 57 ----
target/mips/meson.build | 10 +-
16 files changed, 556 insertions(+), 545 deletions(-)
rename {hw => target}/mips/addr.c (98%)
create mode 100644 target/mips/common_helper.c
rename target/mips/{helper.c => tlb_helper.c} (89%)
rename target/mips/{translate_init.c.inc => cpu-defs.c.inc} (96%)
--
2.26.2
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH 01/19] hw/mips: Move address translation helpers to target/mips/
2020-12-06 23:39 [PATCH 00/19] target/mips: Boring code reordering Philippe Mathieu-Daudé
@ 2020-12-06 23:39 ` Philippe Mathieu-Daudé
2020-12-08 21:46 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 02/19] target/mips: Remove unused headers from translate.c Philippe Mathieu-Daudé
` (18 subsequent siblings)
19 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-06 23:39 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Philippe Mathieu-Daudé,
Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
Address translation is an architectural thing (not hardware
related). Move the helpers from hw/ to target/.
As physical address and KVM are specific to system mode
emulation, restrict this file to softmmu, so it doesn't
get compiled for user-mode emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/mips/cpudevs.h | 7 -------
target/mips/cpu.h | 8 ++++++++
hw/mips/boston.c | 1 -
{hw => target}/mips/addr.c | 2 +-
target/mips/translate.c | 2 --
hw/mips/meson.build | 2 +-
target/mips/meson.build | 1 +
7 files changed, 11 insertions(+), 12 deletions(-)
rename {hw => target}/mips/addr.c (98%)
diff --git a/include/hw/mips/cpudevs.h b/include/hw/mips/cpudevs.h
index 291f59281a0..f7c9728fa9f 100644
--- a/include/hw/mips/cpudevs.h
+++ b/include/hw/mips/cpudevs.h
@@ -5,13 +5,6 @@
/* Definitions for MIPS CPU internal devices. */
-/* addr.c */
-uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr);
-uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr);
-uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr);
-bool mips_um_ksegs_enabled(void);
-void mips_um_ksegs_enable(void);
-
/* mips_int.c */
void cpu_mips_irq_init_cpu(MIPSCPU *cpu);
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 23f8c6f96cd..313e3252cbb 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1290,6 +1290,14 @@ bool cpu_supports_cps_smp(const char *cpu_type);
bool cpu_supports_isa(const char *cpu_type, uint64_t isa);
void cpu_set_exception_base(int vp_index, target_ulong address);
+/* addr.c */
+uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr);
+uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr);
+
+uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr);
+bool mips_um_ksegs_enabled(void);
+void mips_um_ksegs_enable(void);
+
/* mips_int.c */
void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 3d40867dc4c..91183363ff3 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -28,7 +28,6 @@
#include "hw/loader.h"
#include "hw/loader-fit.h"
#include "hw/mips/cps.h"
-#include "hw/mips/cpudevs.h"
#include "hw/pci-host/xilinx-pcie.h"
#include "hw/qdev-clock.h"
#include "hw/qdev-properties.h"
diff --git a/hw/mips/addr.c b/target/mips/addr.c
similarity index 98%
rename from hw/mips/addr.c
rename to target/mips/addr.c
index 2f138fe1ea8..27a6036c451 100644
--- a/hw/mips/addr.c
+++ b/target/mips/addr.c
@@ -21,7 +21,7 @@
*/
#include "qemu/osdep.h"
-#include "hw/mips/cpudevs.h"
+#include "cpu.h"
static int mips_um_ksegs;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c64a1bc42e1..87dc38c0683 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28,8 +28,6 @@
#include "exec/exec-all.h"
#include "tcg/tcg-op.h"
#include "exec/cpu_ldst.h"
-#include "hw/mips/cpudevs.h"
-
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
#include "hw/semihosting/semihost.h"
diff --git a/hw/mips/meson.build b/hw/mips/meson.build
index bcdf96be69f..77b4d8f365e 100644
--- a/hw/mips/meson.build
+++ b/hw/mips/meson.build
@@ -1,5 +1,5 @@
mips_ss = ss.source_set()
-mips_ss.add(files('addr.c', 'mips_int.c'))
+mips_ss.add(files('mips_int.c'))
mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c'))
mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c'))
mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c'))
diff --git a/target/mips/meson.build b/target/mips/meson.build
index fa1f024e782..d980240f9e3 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -15,6 +15,7 @@
mips_softmmu_ss = ss.source_set()
mips_softmmu_ss.add(files(
+ 'addr.c',
'cp0_timer.c',
'machine.c',
'mips-semi.c',
--
2.26.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 02/19] target/mips: Remove unused headers from translate.c
2020-12-06 23:39 [PATCH 00/19] target/mips: Boring code reordering Philippe Mathieu-Daudé
2020-12-06 23:39 ` [PATCH 01/19] hw/mips: Move address translation helpers to target/mips/ Philippe Mathieu-Daudé
@ 2020-12-06 23:39 ` Philippe Mathieu-Daudé
2020-12-08 21:47 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 03/19] target/mips: Remove unused headers from fpu_helper.c Philippe Mathieu-Daudé
` (17 subsequent siblings)
19 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-06 23:39 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Philippe Mathieu-Daudé,
Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 87dc38c0683..346635370c4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24,8 +24,6 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "internal.h"
-#include "disas/disas.h"
-#include "exec/exec-all.h"
#include "tcg/tcg-op.h"
#include "exec/cpu_ldst.h"
#include "exec/helper-proto.h"
--
2.26.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 03/19] target/mips: Remove unused headers from fpu_helper.c
2020-12-06 23:39 [PATCH 00/19] target/mips: Boring code reordering Philippe Mathieu-Daudé
2020-12-06 23:39 ` [PATCH 01/19] hw/mips: Move address translation helpers to target/mips/ Philippe Mathieu-Daudé
2020-12-06 23:39 ` [PATCH 02/19] target/mips: Remove unused headers from translate.c Philippe Mathieu-Daudé
@ 2020-12-06 23:39 ` Philippe Mathieu-Daudé
2020-12-08 21:49 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 04/19] target/mips: Remove unused headers from cp0_helper.c Philippe Mathieu-Daudé
` (16 subsequent siblings)
19 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-06 23:39 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Philippe Mathieu-Daudé,
Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/fpu_helper.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index 020b768e87b..956e3417d0f 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -21,15 +21,11 @@
*/
#include "qemu/osdep.h"
-#include "qemu/main-loop.h"
#include "cpu.h"
#include "internal.h"
-#include "qemu/host-utils.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
-#include "exec/memop.h"
-#include "sysemu/kvm.h"
#include "fpu/softfloat.h"
--
2.26.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 04/19] target/mips: Remove unused headers from cp0_helper.c
2020-12-06 23:39 [PATCH 00/19] target/mips: Boring code reordering Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2020-12-06 23:39 ` [PATCH 03/19] target/mips: Remove unused headers from fpu_helper.c Philippe Mathieu-Daudé
@ 2020-12-06 23:39 ` Philippe Mathieu-Daudé
2020-12-08 21:50 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 05/19] target/mips: Remove unused headers from op_helper.c Philippe Mathieu-Daudé
` (15 subsequent siblings)
19 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-06 23:39 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Philippe Mathieu-Daudé,
Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
Remove unused headers and add missing "qemu/log.h" since
qemu_log() is called.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/cp0_helper.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c
index a1b5140ccaf..d8749658945 100644
--- a/target/mips/cp0_helper.c
+++ b/target/mips/cp0_helper.c
@@ -21,15 +21,13 @@
*/
#include "qemu/osdep.h"
+#include "qemu/log.h"
#include "qemu/main-loop.h"
#include "cpu.h"
#include "internal.h"
#include "qemu/host-utils.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
-#include "exec/memop.h"
-#include "sysemu/kvm.h"
#ifndef CONFIG_USER_ONLY
--
2.26.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 05/19] target/mips: Remove unused headers from op_helper.c
2020-12-06 23:39 [PATCH 00/19] target/mips: Boring code reordering Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2020-12-06 23:39 ` [PATCH 04/19] target/mips: Remove unused headers from cp0_helper.c Philippe Mathieu-Daudé
@ 2020-12-06 23:39 ` Philippe Mathieu-Daudé
2020-12-08 21:50 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 06/19] target/mips: Remove unused headers from kvm.c Philippe Mathieu-Daudé
` (14 subsequent siblings)
19 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-06 23:39 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Philippe Mathieu-Daudé,
Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/op_helper.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 5184a1838be..5aa97902e98 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -19,15 +19,11 @@
*/
#include "qemu/osdep.h"
-#include "qemu/main-loop.h"
#include "cpu.h"
#include "internal.h"
-#include "qemu/host-utils.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
#include "exec/memop.h"
-#include "sysemu/kvm.h"
/*****************************************************************************/
--
2.26.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 06/19] target/mips: Remove unused headers from kvm.c
2020-12-06 23:39 [PATCH 00/19] target/mips: Boring code reordering Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2020-12-06 23:39 ` [PATCH 05/19] target/mips: Remove unused headers from op_helper.c Philippe Mathieu-Daudé
@ 2020-12-06 23:39 ` Philippe Mathieu-Daudé
2020-12-08 21:50 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 07/19] target/mips: Include "exec/memattrs.h" in 'internal.h' Philippe Mathieu-Daudé
` (13 subsequent siblings)
19 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-06 23:39 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Philippe Mathieu-Daudé,
Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/kvm.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/mips/kvm.c b/target/mips/kvm.c
index 72637a1e021..b3f193f7764 100644
--- a/target/mips/kvm.c
+++ b/target/mips/kvm.c
@@ -19,11 +19,9 @@
#include "internal.h"
#include "qemu/error-report.h"
#include "qemu/main-loop.h"
-#include "qemu/timer.h"
#include "sysemu/kvm.h"
#include "sysemu/kvm_int.h"
#include "sysemu/runstate.h"
-#include "sysemu/cpus.h"
#include "kvm_mips.h"
#include "exec/memattrs.h"
#include "hw/boards.h"
--
2.26.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 07/19] target/mips: Include "exec/memattrs.h" in 'internal.h'
2020-12-06 23:39 [PATCH 00/19] target/mips: Boring code reordering Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2020-12-06 23:39 ` [PATCH 06/19] target/mips: Remove unused headers from kvm.c Philippe Mathieu-Daudé
@ 2020-12-06 23:39 ` Philippe Mathieu-Daudé
2020-12-08 21:51 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 08/19] target/mips: Extract cpu_supports*/cpu_set* translate.c Philippe Mathieu-Daudé
` (12 subsequent siblings)
19 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-06 23:39 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Philippe Mathieu-Daudé,
Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
mips_cpu_do_transaction_failed() requires MemTxAttrs
and MemTxResult declarations.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/internal.h | 1 +
target/mips/kvm.c | 1 -
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index dd8a7809b64..76b7a85cbb3 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -8,6 +8,7 @@
#ifndef MIPS_INTERNAL_H
#define MIPS_INTERNAL_H
+#include "exec/memattrs.h"
#include "fpu/softfloat-helpers.h"
/*
diff --git a/target/mips/kvm.c b/target/mips/kvm.c
index b3f193f7764..7a6ea5299fb 100644
--- a/target/mips/kvm.c
+++ b/target/mips/kvm.c
@@ -23,7 +23,6 @@
#include "sysemu/kvm_int.h"
#include "sysemu/runstate.h"
#include "kvm_mips.h"
-#include "exec/memattrs.h"
#include "hw/boards.h"
#define DEBUG_KVM 0
--
2.26.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 08/19] target/mips: Extract cpu_supports*/cpu_set* translate.c
2020-12-06 23:39 [PATCH 00/19] target/mips: Boring code reordering Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2020-12-06 23:39 ` [PATCH 07/19] target/mips: Include "exec/memattrs.h" in 'internal.h' Philippe Mathieu-Daudé
@ 2020-12-06 23:39 ` Philippe Mathieu-Daudé
2020-12-08 21:53 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 09/19] target/mips: Move mips_cpu_add_definition() from helper.c to cpu.c Philippe Mathieu-Daudé
` (11 subsequent siblings)
19 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-06 23:39 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Philippe Mathieu-Daudé,
Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
Move cpu_supports*() and cpu_set_exception_base() from
translate.c to cpu.c.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/cpu.c | 18 ++++++++++++++++++
target/mips/translate.c | 18 ------------------
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 76d50b00b42..8d9ef139f07 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -310,3 +310,21 @@ MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
return MIPS_CPU(cpu);
}
+
+bool cpu_supports_cps_smp(const char *cpu_type)
+{
+ const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
+ return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
+}
+
+bool cpu_supports_isa(const char *cpu_type, uint64_t isa)
+{
+ const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
+ return (mcc->cpu_def->insn_flags & isa) != 0;
+}
+
+void cpu_set_exception_base(int vp_index, target_ulong address)
+{
+ MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
+ vp->env.exception_base = address;
+}
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 346635370c4..dbb71fdaa5d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31766,24 +31766,6 @@ void cpu_mips_realize_env(CPUMIPSState *env)
mvp_init(env, env->cpu_model);
}
-bool cpu_supports_cps_smp(const char *cpu_type)
-{
- const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
- return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
-}
-
-bool cpu_supports_isa(const char *cpu_type, uint64_t isa)
-{
- const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
- return (mcc->cpu_def->insn_flags & isa) != 0;
-}
-
-void cpu_set_exception_base(int vp_index, target_ulong address)
-{
- MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
- vp->env.exception_base = address;
-}
-
void cpu_state_reset(CPUMIPSState *env)
{
CPUState *cs = env_cpu(env);
--
2.26.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 09/19] target/mips: Move mips_cpu_add_definition() from helper.c to cpu.c
2020-12-06 23:39 [PATCH 00/19] target/mips: Boring code reordering Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2020-12-06 23:39 ` [PATCH 08/19] target/mips: Extract cpu_supports*/cpu_set* translate.c Philippe Mathieu-Daudé
@ 2020-12-06 23:39 ` Philippe Mathieu-Daudé
2020-12-08 21:55 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 10/19] target/mips: Add !CONFIG_USER_ONLY comment after #endif Philippe Mathieu-Daudé
` (10 subsequent siblings)
19 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-06 23:39 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Philippe Mathieu-Daudé,
Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/cpu.c | 33 +++++++++++++++++++++++++++++++++
target/mips/helper.c | 33 ---------------------------------
2 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 8d9ef139f07..e612a7ac41a 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -30,6 +30,7 @@
#include "exec/exec-all.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-clock.h"
+#include "qapi/qapi-commands-machine-target.h"
static void mips_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -299,6 +300,38 @@ static void mips_cpu_register_types(void)
type_init(mips_cpu_register_types)
+static void mips_cpu_add_definition(gpointer data, gpointer user_data)
+{
+ ObjectClass *oc = data;
+ CpuDefinitionInfoList **cpu_list = user_data;
+ CpuDefinitionInfoList *entry;
+ CpuDefinitionInfo *info;
+ const char *typename;
+
+ typename = object_class_get_name(oc);
+ info = g_malloc0(sizeof(*info));
+ info->name = g_strndup(typename,
+ strlen(typename) - strlen("-" TYPE_MIPS_CPU));
+ info->q_typename = g_strdup(typename);
+
+ entry = g_malloc0(sizeof(*entry));
+ entry->value = info;
+ entry->next = *cpu_list;
+ *cpu_list = entry;
+}
+
+CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
+{
+ CpuDefinitionInfoList *cpu_list = NULL;
+ GSList *list;
+
+ list = object_class_get_list(TYPE_MIPS_CPU, false);
+ g_slist_foreach(list, mips_cpu_add_definition, &cpu_list);
+ g_slist_free(list);
+
+ return cpu_list;
+}
+
/* Could be used by generic CPU object */
MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
{
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 063b65c0528..bb962a3e8cc 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -24,7 +24,6 @@
#include "exec/cpu_ldst.h"
#include "exec/log.h"
#include "hw/mips/cpudevs.h"
-#include "qapi/qapi-commands-machine-target.h"
enum {
TLBRET_XI = -6,
@@ -1497,35 +1496,3 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
cpu_loop_exit_restore(cs, pc);
}
-
-static void mips_cpu_add_definition(gpointer data, gpointer user_data)
-{
- ObjectClass *oc = data;
- CpuDefinitionInfoList **cpu_list = user_data;
- CpuDefinitionInfoList *entry;
- CpuDefinitionInfo *info;
- const char *typename;
-
- typename = object_class_get_name(oc);
- info = g_malloc0(sizeof(*info));
- info->name = g_strndup(typename,
- strlen(typename) - strlen("-" TYPE_MIPS_CPU));
- info->q_typename = g_strdup(typename);
-
- entry = g_malloc0(sizeof(*entry));
- entry->value = info;
- entry->next = *cpu_list;
- *cpu_list = entry;
-}
-
-CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
-{
- CpuDefinitionInfoList *cpu_list = NULL;
- GSList *list;
-
- list = object_class_get_list(TYPE_MIPS_CPU, false);
- g_slist_foreach(list, mips_cpu_add_definition, &cpu_list);
- g_slist_free(list);
-
- return cpu_list;
-}
--
2.26.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 10/19] target/mips: Add !CONFIG_USER_ONLY comment after #endif
2020-12-06 23:39 [PATCH 00/19] target/mips: Boring code reordering Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2020-12-06 23:39 ` [PATCH 09/19] target/mips: Move mips_cpu_add_definition() from helper.c to cpu.c Philippe Mathieu-Daudé
@ 2020-12-06 23:39 ` Philippe Mathieu-Daudé
2020-12-08 21:59 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 11/19] target/mips: Extract common helpers from helper.c to common_helper.c Philippe Mathieu-Daudé
` (9 subsequent siblings)
19 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-06 23:39 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Philippe Mathieu-Daudé,
Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
To help understand ifdef'ry, add comment after #endif.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/helper.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index bb962a3e8cc..6d33809fb8b 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -455,7 +455,8 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
}
}
}
-#endif
+
+#endif /* !CONFIG_USER_ONLY */
static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
int rw, int tlb_error)
@@ -537,6 +538,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
}
#if !defined(CONFIG_USER_ONLY)
+
hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
MIPSCPU *cpu = MIPS_CPU(cs);
@@ -550,9 +552,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
}
return phys_addr;
}
-#endif
-#if !defined(CONFIG_USER_ONLY)
#if !defined(TARGET_MIPS64)
/*
@@ -886,7 +886,7 @@ refill:
return true;
}
#endif
-#endif
+#endif /* !CONFIG_USER_ONLY */
bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
@@ -1017,7 +1017,7 @@ static const char * const excp_names[EXCP_LAST + 1] = {
[EXCP_MSADIS] = "MSA disabled",
[EXCP_MSAFPE] = "MSA floating point",
};
-#endif
+#endif /* !CONFIG_USER_ONLY */
target_ulong exception_resume_pc(CPUMIPSState *env)
{
@@ -1080,7 +1080,8 @@ static inline void set_badinstr_registers(CPUMIPSState *env)
env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
}
}
-#endif
+
+#endif /* !CONFIG_USER_ONLY */
void mips_cpu_do_interrupt(CPUState *cs)
{
@@ -1480,7 +1481,7 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
}
}
}
-#endif
+#endif /* !CONFIG_USER_ONLY */
void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
uint32_t exception,
--
2.26.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 11/19] target/mips: Extract common helpers from helper.c to common_helper.c
2020-12-06 23:39 [PATCH 00/19] target/mips: Boring code reordering Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2020-12-06 23:39 ` [PATCH 10/19] target/mips: Add !CONFIG_USER_ONLY comment after #endif Philippe Mathieu-Daudé
@ 2020-12-06 23:39 ` Philippe Mathieu-Daudé
2020-12-08 22:06 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 12/19] target/mips: Rename helper.c as tlb_helper.c Philippe Mathieu-Daudé
` (8 subsequent siblings)
19 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-06 23:39 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Philippe Mathieu-Daudé,
Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
The rest of helper.c is TLB related. Extract the non TLB
specific functions to a new file, so we can rename helper.c
as tlb_helper.c in the next commit.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
Any better name? xxx_helper.c are usually TCG helpers.
---
target/mips/common_helper.c | 178 ++++++++++++++++++++++++++++++++++++
target/mips/helper.c | 152 ------------------------------
target/mips/meson.build | 1 +
3 files changed, 179 insertions(+), 152 deletions(-)
create mode 100644 target/mips/common_helper.c
diff --git a/target/mips/common_helper.c b/target/mips/common_helper.c
new file mode 100644
index 00000000000..07c947ecc55
--- /dev/null
+++ b/target/mips/common_helper.c
@@ -0,0 +1,178 @@
+/*
+ * MIPS emulation helpers for qemu.
+ *
+ * Copyright (c) 2004-2005 Jocelyn Mayer
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "qemu/osdep.h"
+
+#include "cpu.h"
+#include "internal.h"
+#include "exec/exec-all.h"
+#include "exec/log.h"
+
+#if !defined(CONFIG_USER_ONLY)
+
+/* Called for updates to CP0_Status. */
+void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
+{
+ int32_t tcstatus, *tcst;
+ uint32_t v = cpu->CP0_Status;
+ uint32_t cu, mx, asid, ksu;
+ uint32_t mask = ((1 << CP0TCSt_TCU3)
+ | (1 << CP0TCSt_TCU2)
+ | (1 << CP0TCSt_TCU1)
+ | (1 << CP0TCSt_TCU0)
+ | (1 << CP0TCSt_TMX)
+ | (3 << CP0TCSt_TKSU)
+ | (0xff << CP0TCSt_TASID));
+
+ cu = (v >> CP0St_CU0) & 0xf;
+ mx = (v >> CP0St_MX) & 0x1;
+ ksu = (v >> CP0St_KSU) & 0x3;
+ asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
+
+ tcstatus = cu << CP0TCSt_TCU0;
+ tcstatus |= mx << CP0TCSt_TMX;
+ tcstatus |= ksu << CP0TCSt_TKSU;
+ tcstatus |= asid;
+
+ if (tc == cpu->current_tc) {
+ tcst = &cpu->active_tc.CP0_TCStatus;
+ } else {
+ tcst = &cpu->tcs[tc].CP0_TCStatus;
+ }
+
+ *tcst &= ~mask;
+ *tcst |= tcstatus;
+ compute_hflags(cpu);
+}
+
+void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
+{
+ uint32_t mask = env->CP0_Status_rw_bitmask;
+ target_ulong old = env->CP0_Status;
+
+ if (env->insn_flags & ISA_MIPS32R6) {
+ bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
+#if defined(TARGET_MIPS64)
+ uint32_t ksux = (1 << CP0St_KX) & val;
+ ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
+ ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
+ val = (val & ~(7 << CP0St_UX)) | ksux;
+#endif
+ if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
+ mask &= ~(3 << CP0St_KSU);
+ }
+ mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
+ }
+
+ env->CP0_Status = (old & ~mask) | (val & mask);
+#if defined(TARGET_MIPS64)
+ if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
+ /* Access to at least one of the 64-bit segments has been disabled */
+ tlb_flush(env_cpu(env));
+ }
+#endif
+ if (env->CP0_Config3 & (1 << CP0C3_MT)) {
+ sync_c0_status(env, env, env->current_tc);
+ } else {
+ compute_hflags(env);
+ }
+}
+
+void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
+{
+ uint32_t mask = 0x00C00300;
+ uint32_t old = env->CP0_Cause;
+ int i;
+
+ if (env->insn_flags & ISA_MIPS32R2) {
+ mask |= 1 << CP0Ca_DC;
+ }
+ if (env->insn_flags & ISA_MIPS32R6) {
+ mask &= ~((1 << CP0Ca_WP) & val);
+ }
+
+ env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
+
+ if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
+ if (env->CP0_Cause & (1 << CP0Ca_DC)) {
+ cpu_mips_stop_count(env);
+ } else {
+ cpu_mips_start_count(env);
+ }
+ }
+
+ /* Set/reset software interrupts */
+ for (i = 0 ; i < 2 ; i++) {
+ if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
+ cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
+ }
+ }
+}
+
+#endif /* !CONFIG_USER_ONLY */
+
+target_ulong exception_resume_pc(CPUMIPSState *env)
+{
+ target_ulong bad_pc;
+ target_ulong isa_mode;
+
+ isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
+ bad_pc = env->active_tc.PC | isa_mode;
+ if (env->hflags & MIPS_HFLAG_BMASK) {
+ /*
+ * If the exception was raised from a delay slot, come back to
+ * the jump.
+ */
+ bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
+ }
+
+ return bad_pc;
+}
+
+bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+ if (interrupt_request & CPU_INTERRUPT_HARD) {
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
+
+ if (cpu_mips_hw_interrupts_enabled(env) &&
+ cpu_mips_hw_interrupts_pending(env)) {
+ /* Raise it */
+ cs->exception_index = EXCP_EXT_INTERRUPT;
+ env->error_code = 0;
+ mips_cpu_do_interrupt(cs);
+ return true;
+ }
+ }
+ return false;
+}
+
+void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
+ uint32_t exception,
+ int error_code,
+ uintptr_t pc)
+{
+ CPUState *cs = env_cpu(env);
+
+ qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n",
+ __func__, exception, error_code);
+ cs->exception_index = exception;
+ env->error_code = error_code;
+
+ cpu_loop_exit_restore(cs, pc);
+}
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 6d33809fb8b..5db7e80e22b 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -357,105 +357,6 @@ void cpu_mips_tlb_flush(CPUMIPSState *env)
env->tlb->tlb_in_use = env->tlb->nb_tlb;
}
-/* Called for updates to CP0_Status. */
-void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
-{
- int32_t tcstatus, *tcst;
- uint32_t v = cpu->CP0_Status;
- uint32_t cu, mx, asid, ksu;
- uint32_t mask = ((1 << CP0TCSt_TCU3)
- | (1 << CP0TCSt_TCU2)
- | (1 << CP0TCSt_TCU1)
- | (1 << CP0TCSt_TCU0)
- | (1 << CP0TCSt_TMX)
- | (3 << CP0TCSt_TKSU)
- | (0xff << CP0TCSt_TASID));
-
- cu = (v >> CP0St_CU0) & 0xf;
- mx = (v >> CP0St_MX) & 0x1;
- ksu = (v >> CP0St_KSU) & 0x3;
- asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
-
- tcstatus = cu << CP0TCSt_TCU0;
- tcstatus |= mx << CP0TCSt_TMX;
- tcstatus |= ksu << CP0TCSt_TKSU;
- tcstatus |= asid;
-
- if (tc == cpu->current_tc) {
- tcst = &cpu->active_tc.CP0_TCStatus;
- } else {
- tcst = &cpu->tcs[tc].CP0_TCStatus;
- }
-
- *tcst &= ~mask;
- *tcst |= tcstatus;
- compute_hflags(cpu);
-}
-
-void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
-{
- uint32_t mask = env->CP0_Status_rw_bitmask;
- target_ulong old = env->CP0_Status;
-
- if (env->insn_flags & ISA_MIPS32R6) {
- bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
-#if defined(TARGET_MIPS64)
- uint32_t ksux = (1 << CP0St_KX) & val;
- ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
- ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
- val = (val & ~(7 << CP0St_UX)) | ksux;
-#endif
- if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
- mask &= ~(3 << CP0St_KSU);
- }
- mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
- }
-
- env->CP0_Status = (old & ~mask) | (val & mask);
-#if defined(TARGET_MIPS64)
- if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
- /* Access to at least one of the 64-bit segments has been disabled */
- tlb_flush(env_cpu(env));
- }
-#endif
- if (env->CP0_Config3 & (1 << CP0C3_MT)) {
- sync_c0_status(env, env, env->current_tc);
- } else {
- compute_hflags(env);
- }
-}
-
-void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
-{
- uint32_t mask = 0x00C00300;
- uint32_t old = env->CP0_Cause;
- int i;
-
- if (env->insn_flags & ISA_MIPS32R2) {
- mask |= 1 << CP0Ca_DC;
- }
- if (env->insn_flags & ISA_MIPS32R6) {
- mask &= ~((1 << CP0Ca_WP) & val);
- }
-
- env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
-
- if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
- if (env->CP0_Cause & (1 << CP0Ca_DC)) {
- cpu_mips_stop_count(env);
- } else {
- cpu_mips_start_count(env);
- }
- }
-
- /* Set/reset software interrupts */
- for (i = 0 ; i < 2 ; i++) {
- if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
- cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
- }
- }
-}
-
#endif /* !CONFIG_USER_ONLY */
static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
@@ -1017,27 +918,7 @@ static const char * const excp_names[EXCP_LAST + 1] = {
[EXCP_MSADIS] = "MSA disabled",
[EXCP_MSAFPE] = "MSA floating point",
};
-#endif /* !CONFIG_USER_ONLY */
-target_ulong exception_resume_pc(CPUMIPSState *env)
-{
- target_ulong bad_pc;
- target_ulong isa_mode;
-
- isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
- bad_pc = env->active_tc.PC | isa_mode;
- if (env->hflags & MIPS_HFLAG_BMASK) {
- /*
- * If the exception was raised from a delay slot, come back to
- * the jump.
- */
- bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
- }
-
- return bad_pc;
-}
-
-#if !defined(CONFIG_USER_ONLY)
static void set_hflags_for_handler(CPUMIPSState *env)
{
/* Exception handlers are entered in 32-bit mode. */
@@ -1398,24 +1279,6 @@ void mips_cpu_do_interrupt(CPUState *cs)
cs->exception_index = EXCP_NONE;
}
-bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
-{
- if (interrupt_request & CPU_INTERRUPT_HARD) {
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
-
- if (cpu_mips_hw_interrupts_enabled(env) &&
- cpu_mips_hw_interrupts_pending(env)) {
- /* Raise it */
- cs->exception_index = EXCP_EXT_INTERRUPT;
- env->error_code = 0;
- mips_cpu_do_interrupt(cs);
- return true;
- }
- }
- return false;
-}
-
#if !defined(CONFIG_USER_ONLY)
void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
{
@@ -1482,18 +1345,3 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
}
}
#endif /* !CONFIG_USER_ONLY */
-
-void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
- uint32_t exception,
- int error_code,
- uintptr_t pc)
-{
- CPUState *cs = env_cpu(env);
-
- qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n",
- __func__, exception, error_code);
- cs->exception_index = exception;
- env->error_code = error_code;
-
- cpu_loop_exit_restore(cs, pc);
-}
diff --git a/target/mips/meson.build b/target/mips/meson.build
index d980240f9e3..4858bf86ad6 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -1,5 +1,6 @@
mips_ss = ss.source_set()
mips_ss.add(files(
+ 'common_helper.c',
'cp0_helper.c',
'cpu.c',
'dsp_helper.c',
--
2.26.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 12/19] target/mips: Rename helper.c as tlb_helper.c
2020-12-06 23:39 [PATCH 00/19] target/mips: Boring code reordering Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2020-12-06 23:39 ` [PATCH 11/19] target/mips: Extract common helpers from helper.c to common_helper.c Philippe Mathieu-Daudé
@ 2020-12-06 23:39 ` Philippe Mathieu-Daudé
2020-12-08 22:09 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 13/19] target/mips: Fix code style for checkpatch.pl Philippe Mathieu-Daudé
` (7 subsequent siblings)
19 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-06 23:39 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Philippe Mathieu-Daudé,
Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
This file contains functions related to TLB management,
rename it as 'tlb_helper.c'.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
Maybe I missed some functions not TLB specific...
---
target/mips/{helper.c => tlb_helper.c} | 2 +-
target/mips/meson.build | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
rename target/mips/{helper.c => tlb_helper.c} (99%)
diff --git a/target/mips/helper.c b/target/mips/tlb_helper.c
similarity index 99%
rename from target/mips/helper.c
rename to target/mips/tlb_helper.c
index 5db7e80e22b..7022be13ae4 100644
--- a/target/mips/helper.c
+++ b/target/mips/tlb_helper.c
@@ -1,5 +1,5 @@
/*
- * MIPS emulation helpers for qemu.
+ * MIPS TLB (Translation lookaside buffer) helpers.
*
* Copyright (c) 2004-2005 Jocelyn Mayer
*
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 4858bf86ad6..c685f03fb28 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -6,10 +6,10 @@
'dsp_helper.c',
'fpu_helper.c',
'gdbstub.c',
- 'helper.c',
'lmmi_helper.c',
'msa_helper.c',
'op_helper.c',
+ 'tlb_helper.c',
'translate.c',
))
mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
--
2.26.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 13/19] target/mips: Fix code style for checkpatch.pl
2020-12-06 23:39 [PATCH 00/19] target/mips: Boring code reordering Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2020-12-06 23:39 ` [PATCH 12/19] target/mips: Rename helper.c as tlb_helper.c Philippe Mathieu-Daudé
@ 2020-12-06 23:39 ` Philippe Mathieu-Daudé
2020-12-08 22:11 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 14/19] target/mips: Move mmu_init() functions to tlb_helper.c Philippe Mathieu-Daudé
` (6 subsequent siblings)
19 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-06 23:39 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Philippe Mathieu-Daudé,
Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
We are going to move this code, fix its style first.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate_init.c.inc | 36 ++++++++++++++++----------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index ea85d5c6a79..535b52b5444 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -932,19 +932,19 @@ void mips_cpu_list(void)
}
#ifndef CONFIG_USER_ONLY
-static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def)
{
env->tlb->nb_tlb = 1;
env->tlb->map_address = &no_mmu_map_address;
}
-static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def)
{
env->tlb->nb_tlb = 1;
env->tlb->map_address = &fixed_mmu_map_address;
}
-static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def)
{
env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
env->tlb->map_address = &r4k_map_address;
@@ -956,25 +956,25 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
}
-static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void mmu_init(CPUMIPSState *env, const mips_def_t *def)
{
env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
switch (def->mmu_type) {
- case MMU_TYPE_NONE:
- no_mmu_init(env, def);
- break;
- case MMU_TYPE_R4000:
- r4k_mmu_init(env, def);
- break;
- case MMU_TYPE_FMT:
- fixed_mmu_init(env, def);
- break;
- case MMU_TYPE_R3000:
- case MMU_TYPE_R6000:
- case MMU_TYPE_R8000:
- default:
- cpu_abort(env_cpu(env), "MMU type not supported\n");
+ case MMU_TYPE_NONE:
+ no_mmu_init(env, def);
+ break;
+ case MMU_TYPE_R4000:
+ r4k_mmu_init(env, def);
+ break;
+ case MMU_TYPE_FMT:
+ fixed_mmu_init(env, def);
+ break;
+ case MMU_TYPE_R3000:
+ case MMU_TYPE_R6000:
+ case MMU_TYPE_R8000:
+ default:
+ cpu_abort(env_cpu(env), "MMU type not supported\n");
}
}
#endif /* CONFIG_USER_ONLY */
--
2.26.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 14/19] target/mips: Move mmu_init() functions to tlb_helper.c
2020-12-06 23:39 [PATCH 00/19] target/mips: Boring code reordering Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2020-12-06 23:39 ` [PATCH 13/19] target/mips: Fix code style for checkpatch.pl Philippe Mathieu-Daudé
@ 2020-12-06 23:39 ` Philippe Mathieu-Daudé
2020-12-08 22:19 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 15/19] target/mips: Move cpu definitions, reset() and realize() to cpu.c Philippe Mathieu-Daudé
` (5 subsequent siblings)
19 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-06 23:39 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Philippe Mathieu-Daudé,
Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/internal.h | 1 +
target/mips/tlb_helper.c | 46 ++++++++++++++++++++++++++++++
target/mips/translate_init.c.inc | 48 --------------------------------
3 files changed, 47 insertions(+), 48 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 76b7a85cbb3..142fa3e5007 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -218,6 +218,7 @@ void cpu_mips_start_count(CPUMIPSState *env);
void cpu_mips_stop_count(CPUMIPSState *env);
/* helper.c */
+void mmu_init(CPUMIPSState *env, const mips_def_t *def);
bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c
index 7022be13ae4..366cc526a14 100644
--- a/target/mips/tlb_helper.c
+++ b/target/mips/tlb_helper.c
@@ -120,6 +120,52 @@ int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
return TLBRET_NOMATCH;
}
+static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def)
+{
+ env->tlb->nb_tlb = 1;
+ env->tlb->map_address = &no_mmu_map_address;
+}
+
+static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def)
+{
+ env->tlb->nb_tlb = 1;
+ env->tlb->map_address = &fixed_mmu_map_address;
+}
+
+static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def)
+{
+ env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
+ env->tlb->map_address = &r4k_map_address;
+ env->tlb->helper_tlbwi = r4k_helper_tlbwi;
+ env->tlb->helper_tlbwr = r4k_helper_tlbwr;
+ env->tlb->helper_tlbp = r4k_helper_tlbp;
+ env->tlb->helper_tlbr = r4k_helper_tlbr;
+ env->tlb->helper_tlbinv = r4k_helper_tlbinv;
+ env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
+}
+
+void mmu_init(CPUMIPSState *env, const mips_def_t *def)
+{
+ env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
+
+ switch (def->mmu_type) {
+ case MMU_TYPE_NONE:
+ no_mmu_init(env, def);
+ break;
+ case MMU_TYPE_R4000:
+ r4k_mmu_init(env, def);
+ break;
+ case MMU_TYPE_FMT:
+ fixed_mmu_init(env, def);
+ break;
+ case MMU_TYPE_R3000:
+ case MMU_TYPE_R6000:
+ case MMU_TYPE_R8000:
+ default:
+ cpu_abort(env_cpu(env), "MMU type not supported\n");
+ }
+}
+
static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
{
/*
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index 535b52b5444..f3daf451a63 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -931,54 +931,6 @@ void mips_cpu_list(void)
}
}
-#ifndef CONFIG_USER_ONLY
-static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def)
-{
- env->tlb->nb_tlb = 1;
- env->tlb->map_address = &no_mmu_map_address;
-}
-
-static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def)
-{
- env->tlb->nb_tlb = 1;
- env->tlb->map_address = &fixed_mmu_map_address;
-}
-
-static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def)
-{
- env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
- env->tlb->map_address = &r4k_map_address;
- env->tlb->helper_tlbwi = r4k_helper_tlbwi;
- env->tlb->helper_tlbwr = r4k_helper_tlbwr;
- env->tlb->helper_tlbp = r4k_helper_tlbp;
- env->tlb->helper_tlbr = r4k_helper_tlbr;
- env->tlb->helper_tlbinv = r4k_helper_tlbinv;
- env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
-}
-
-static void mmu_init(CPUMIPSState *env, const mips_def_t *def)
-{
- env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
-
- switch (def->mmu_type) {
- case MMU_TYPE_NONE:
- no_mmu_init(env, def);
- break;
- case MMU_TYPE_R4000:
- r4k_mmu_init(env, def);
- break;
- case MMU_TYPE_FMT:
- fixed_mmu_init(env, def);
- break;
- case MMU_TYPE_R3000:
- case MMU_TYPE_R6000:
- case MMU_TYPE_R8000:
- default:
- cpu_abort(env_cpu(env), "MMU type not supported\n");
- }
-}
-#endif /* CONFIG_USER_ONLY */
-
static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
{
int i;
--
2.26.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 15/19] target/mips: Move cpu definitions, reset() and realize() to cpu.c
2020-12-06 23:39 [PATCH 00/19] target/mips: Boring code reordering Philippe Mathieu-Daudé
` (13 preceding siblings ...)
2020-12-06 23:39 ` [PATCH 14/19] target/mips: Move mmu_init() functions to tlb_helper.c Philippe Mathieu-Daudé
@ 2020-12-06 23:39 ` Philippe Mathieu-Daudé
2020-12-08 22:27 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 16/19] target/mips: Inline cpu_mips_realize_env() in mips_cpu_realizefn() Philippe Mathieu-Daudé
` (4 subsequent siblings)
19 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-06 23:39 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Philippe Mathieu-Daudé,
Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
Nothing TCG specific there, move to common cpu code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/internal.h | 4 -
target/mips/cpu.c | 243 ++++++++++++++++++++++++++++++++++++++++
target/mips/translate.c | 240 ---------------------------------------
3 files changed, 243 insertions(+), 244 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 142fa3e5007..fcd5e8335ec 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -206,10 +206,6 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
void mips_tcg_init(void);
-/* TODO QOM'ify CPU reset and remove */
-void cpu_state_reset(CPUMIPSState *s);
-void cpu_mips_realize_env(CPUMIPSState *env);
-
/* cp0_timer.c */
uint32_t cpu_mips_get_count(CPUMIPSState *env);
void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index e612a7ac41a..1073db7f257 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "qemu/cutils.h"
+#include "qemu/qemu-print.h"
#include "qapi/error.h"
#include "cpu.h"
#include "internal.h"
@@ -30,6 +31,7 @@
#include "exec/exec-all.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-clock.h"
+#include "hw/semihosting/semihost.h"
#include "qapi/qapi-commands-machine-target.h"
static void mips_cpu_set_pc(CPUState *cs, vaddr value)
@@ -100,6 +102,247 @@ static bool mips_cpu_has_work(CPUState *cs)
return has_work;
}
+#include "translate_init.c.inc"
+
+static void cpu_mips_realize_env(CPUMIPSState *env)
+{
+ env->exception_base = (int32_t)0xBFC00000;
+
+#ifndef CONFIG_USER_ONLY
+ mmu_init(env, env->cpu_model);
+#endif
+ fpu_init(env, env->cpu_model);
+ mvp_init(env, env->cpu_model);
+}
+
+/* TODO QOM'ify CPU reset and remove */
+static void cpu_state_reset(CPUMIPSState *env)
+{
+ CPUState *cs = env_cpu(env);
+
+ /* Reset registers to their default values */
+ env->CP0_PRid = env->cpu_model->CP0_PRid;
+ env->CP0_Config0 = env->cpu_model->CP0_Config0;
+#ifdef TARGET_WORDS_BIGENDIAN
+ env->CP0_Config0 |= (1 << CP0C0_BE);
+#endif
+ env->CP0_Config1 = env->cpu_model->CP0_Config1;
+ env->CP0_Config2 = env->cpu_model->CP0_Config2;
+ env->CP0_Config3 = env->cpu_model->CP0_Config3;
+ env->CP0_Config4 = env->cpu_model->CP0_Config4;
+ env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask;
+ env->CP0_Config5 = env->cpu_model->CP0_Config5;
+ env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
+ env->CP0_Config6 = env->cpu_model->CP0_Config6;
+ env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask;
+ env->CP0_Config7 = env->cpu_model->CP0_Config7;
+ env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask;
+ env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
+ << env->cpu_model->CP0_LLAddr_shift;
+ env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift;
+ env->SYNCI_Step = env->cpu_model->SYNCI_Step;
+ env->CCRes = env->cpu_model->CCRes;
+ env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask;
+ env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask;
+ env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl;
+ env->current_tc = 0;
+ env->SEGBITS = env->cpu_model->SEGBITS;
+ env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1);
+#if defined(TARGET_MIPS64)
+ if (env->cpu_model->insn_flags & ISA_MIPS3) {
+ env->SEGMask |= 3ULL << 62;
+ }
+#endif
+ env->PABITS = env->cpu_model->PABITS;
+ env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask;
+ env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0;
+ env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask;
+ env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1;
+ env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask;
+ env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2;
+ env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask;
+ env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3;
+ env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask;
+ env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4;
+ env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask;
+ env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
+ env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask;
+ env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
+ env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask;
+ env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
+ env->msair = env->cpu_model->MSAIR;
+ env->insn_flags = env->cpu_model->insn_flags;
+
+#if defined(CONFIG_USER_ONLY)
+ env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);
+# ifdef TARGET_MIPS64
+ /* Enable 64-bit register mode. */
+ env->CP0_Status |= (1 << CP0St_PX);
+# endif
+# ifdef TARGET_ABI_MIPSN64
+ /* Enable 64-bit address mode. */
+ env->CP0_Status |= (1 << CP0St_UX);
+# endif
+ /*
+ * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
+ * hardware registers.
+ */
+ env->CP0_HWREna |= 0x0000000F;
+ if (env->CP0_Config1 & (1 << CP0C1_FP)) {
+ env->CP0_Status |= (1 << CP0St_CU1);
+ }
+ if (env->CP0_Config3 & (1 << CP0C3_DSPP)) {
+ env->CP0_Status |= (1 << CP0St_MX);
+ }
+# if defined(TARGET_MIPS64)
+ /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */
+ if ((env->CP0_Config1 & (1 << CP0C1_FP)) &&
+ (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
+ env->CP0_Status |= (1 << CP0St_FR);
+ }
+# endif
+#else
+ if (env->hflags & MIPS_HFLAG_BMASK) {
+ /*
+ * If the exception was raised from a delay slot,
+ * come back to the jump.
+ */
+ env->CP0_ErrorEPC = (env->active_tc.PC
+ - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4));
+ } else {
+ env->CP0_ErrorEPC = env->active_tc.PC;
+ }
+ env->active_tc.PC = env->exception_base;
+ env->CP0_Random = env->tlb->nb_tlb - 1;
+ env->tlb->tlb_in_use = env->tlb->nb_tlb;
+ env->CP0_Wired = 0;
+ env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId;
+ env->CP0_EBase = (cs->cpu_index & 0x3FF);
+ if (mips_um_ksegs_enabled()) {
+ env->CP0_EBase |= 0x40000000;
+ } else {
+ env->CP0_EBase |= (int32_t)0x80000000;
+ }
+ if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {
+ env->CP0_CMGCRBase = 0x1fbf8000 >> 4;
+ }
+ env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ?
+ 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff;
+ env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
+ /*
+ * Vectored interrupts not implemented, timer on int 7,
+ * no performance counters.
+ */
+ env->CP0_IntCtl = 0xe0000000;
+ {
+ int i;
+
+ for (i = 0; i < 7; i++) {
+ env->CP0_WatchLo[i] = 0;
+ env->CP0_WatchHi[i] = 0x80000000;
+ }
+ env->CP0_WatchLo[7] = 0;
+ env->CP0_WatchHi[7] = 0;
+ }
+ /* Count register increments in debug mode, EJTAG version 1 */
+ env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
+
+ cpu_mips_store_count(env, 1);
+
+ if (env->CP0_Config3 & (1 << CP0C3_MT)) {
+ int i;
+
+ /* Only TC0 on VPE 0 starts as active. */
+ for (i = 0; i < ARRAY_SIZE(env->tcs); i++) {
+ env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE;
+ env->tcs[i].CP0_TCHalt = 1;
+ }
+ env->active_tc.CP0_TCHalt = 1;
+ cs->halted = 1;
+
+ if (cs->cpu_index == 0) {
+ /* VPE0 starts up enabled. */
+ env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
+ env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
+
+ /* TC0 starts up unhalted. */
+ cs->halted = 0;
+ env->active_tc.CP0_TCHalt = 0;
+ env->tcs[0].CP0_TCHalt = 0;
+ /* With thread 0 active. */
+ env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A);
+ env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A);
+ }
+ }
+
+ /*
+ * Configure default legacy segmentation control. We use this regardless of
+ * whether segmentation control is presented to the guest.
+ */
+ /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */
+ env->CP0_SegCtl0 = (CP0SC_AM_MK << CP0SC_AM);
+ /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */
+ env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16;
+ /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */
+ env->CP0_SegCtl1 = (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) |
+ (2 << CP0SC_C);
+ /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */
+ env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) |
+ (3 << CP0SC_C)) << 16;
+ /* USeg (seg4 0x40000000..0x7FFFFFFF) */
+ env->CP0_SegCtl2 = (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) |
+ (1 << CP0SC_EU) | (2 << CP0SC_C);
+ /* USeg (seg5 0x00000000..0x3FFFFFFF) */
+ env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) |
+ (1 << CP0SC_EU) | (2 << CP0SC_C)) << 16;
+ /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */
+ env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM);
+#endif
+ if ((env->insn_flags & ISA_MIPS32R6) &&
+ (env->active_fpu.fcr0 & (1 << FCR0_F64))) {
+ /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
+ env->CP0_Status |= (1 << CP0St_FR);
+ }
+
+ if (env->insn_flags & ISA_MIPS32R6) {
+ /* PTW = 1 */
+ env->CP0_PWSize = 0x40;
+ /* GDI = 12 */
+ /* UDI = 12 */
+ /* MDI = 12 */
+ /* PRI = 12 */
+ /* PTEI = 2 */
+ env->CP0_PWField = 0x0C30C302;
+ } else {
+ /* GDI = 0 */
+ /* UDI = 0 */
+ /* MDI = 0 */
+ /* PRI = 0 */
+ /* PTEI = 2 */
+ env->CP0_PWField = 0x02;
+ }
+
+ if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) {
+ /* microMIPS on reset when Config3.ISA is 3 */
+ env->hflags |= MIPS_HFLAG_M16;
+ }
+
+ /* MSA */
+ if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
+ msa_reset(env);
+ }
+
+ compute_hflags(env);
+ restore_fp_status(env);
+ restore_pamask(env);
+ cs->exception_index = EXCP_NONE;
+
+ if (semihosting_get_argc()) {
+ /* UHI interface can be used to obtain argc and argv */
+ env->active_tc.gpr[4] = -1;
+ }
+}
+
static void mips_cpu_reset(DeviceState *dev)
{
CPUState *s = CPU(dev);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index dbb71fdaa5d..19933b7868c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31753,246 +31753,6 @@ void mips_tcg_init(void)
#endif
}
-#include "translate_init.c.inc"
-
-void cpu_mips_realize_env(CPUMIPSState *env)
-{
- env->exception_base = (int32_t)0xBFC00000;
-
-#ifndef CONFIG_USER_ONLY
- mmu_init(env, env->cpu_model);
-#endif
- fpu_init(env, env->cpu_model);
- mvp_init(env, env->cpu_model);
-}
-
-void cpu_state_reset(CPUMIPSState *env)
-{
- CPUState *cs = env_cpu(env);
-
- /* Reset registers to their default values */
- env->CP0_PRid = env->cpu_model->CP0_PRid;
- env->CP0_Config0 = env->cpu_model->CP0_Config0;
-#ifdef TARGET_WORDS_BIGENDIAN
- env->CP0_Config0 |= (1 << CP0C0_BE);
-#endif
- env->CP0_Config1 = env->cpu_model->CP0_Config1;
- env->CP0_Config2 = env->cpu_model->CP0_Config2;
- env->CP0_Config3 = env->cpu_model->CP0_Config3;
- env->CP0_Config4 = env->cpu_model->CP0_Config4;
- env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask;
- env->CP0_Config5 = env->cpu_model->CP0_Config5;
- env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
- env->CP0_Config6 = env->cpu_model->CP0_Config6;
- env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask;
- env->CP0_Config7 = env->cpu_model->CP0_Config7;
- env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask;
- env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
- << env->cpu_model->CP0_LLAddr_shift;
- env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift;
- env->SYNCI_Step = env->cpu_model->SYNCI_Step;
- env->CCRes = env->cpu_model->CCRes;
- env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask;
- env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask;
- env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl;
- env->current_tc = 0;
- env->SEGBITS = env->cpu_model->SEGBITS;
- env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1);
-#if defined(TARGET_MIPS64)
- if (env->cpu_model->insn_flags & ISA_MIPS3) {
- env->SEGMask |= 3ULL << 62;
- }
-#endif
- env->PABITS = env->cpu_model->PABITS;
- env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask;
- env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0;
- env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask;
- env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1;
- env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask;
- env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2;
- env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask;
- env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3;
- env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask;
- env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4;
- env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask;
- env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
- env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask;
- env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
- env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask;
- env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
- env->msair = env->cpu_model->MSAIR;
- env->insn_flags = env->cpu_model->insn_flags;
-
-#if defined(CONFIG_USER_ONLY)
- env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);
-# ifdef TARGET_MIPS64
- /* Enable 64-bit register mode. */
- env->CP0_Status |= (1 << CP0St_PX);
-# endif
-# ifdef TARGET_ABI_MIPSN64
- /* Enable 64-bit address mode. */
- env->CP0_Status |= (1 << CP0St_UX);
-# endif
- /*
- * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
- * hardware registers.
- */
- env->CP0_HWREna |= 0x0000000F;
- if (env->CP0_Config1 & (1 << CP0C1_FP)) {
- env->CP0_Status |= (1 << CP0St_CU1);
- }
- if (env->CP0_Config3 & (1 << CP0C3_DSPP)) {
- env->CP0_Status |= (1 << CP0St_MX);
- }
-# if defined(TARGET_MIPS64)
- /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */
- if ((env->CP0_Config1 & (1 << CP0C1_FP)) &&
- (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
- env->CP0_Status |= (1 << CP0St_FR);
- }
-# endif
-#else
- if (env->hflags & MIPS_HFLAG_BMASK) {
- /*
- * If the exception was raised from a delay slot,
- * come back to the jump.
- */
- env->CP0_ErrorEPC = (env->active_tc.PC
- - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4));
- } else {
- env->CP0_ErrorEPC = env->active_tc.PC;
- }
- env->active_tc.PC = env->exception_base;
- env->CP0_Random = env->tlb->nb_tlb - 1;
- env->tlb->tlb_in_use = env->tlb->nb_tlb;
- env->CP0_Wired = 0;
- env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId;
- env->CP0_EBase = (cs->cpu_index & 0x3FF);
- if (mips_um_ksegs_enabled()) {
- env->CP0_EBase |= 0x40000000;
- } else {
- env->CP0_EBase |= (int32_t)0x80000000;
- }
- if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {
- env->CP0_CMGCRBase = 0x1fbf8000 >> 4;
- }
- env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ?
- 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff;
- env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
- /*
- * Vectored interrupts not implemented, timer on int 7,
- * no performance counters.
- */
- env->CP0_IntCtl = 0xe0000000;
- {
- int i;
-
- for (i = 0; i < 7; i++) {
- env->CP0_WatchLo[i] = 0;
- env->CP0_WatchHi[i] = 0x80000000;
- }
- env->CP0_WatchLo[7] = 0;
- env->CP0_WatchHi[7] = 0;
- }
- /* Count register increments in debug mode, EJTAG version 1 */
- env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
-
- cpu_mips_store_count(env, 1);
-
- if (env->CP0_Config3 & (1 << CP0C3_MT)) {
- int i;
-
- /* Only TC0 on VPE 0 starts as active. */
- for (i = 0; i < ARRAY_SIZE(env->tcs); i++) {
- env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE;
- env->tcs[i].CP0_TCHalt = 1;
- }
- env->active_tc.CP0_TCHalt = 1;
- cs->halted = 1;
-
- if (cs->cpu_index == 0) {
- /* VPE0 starts up enabled. */
- env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
- env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
-
- /* TC0 starts up unhalted. */
- cs->halted = 0;
- env->active_tc.CP0_TCHalt = 0;
- env->tcs[0].CP0_TCHalt = 0;
- /* With thread 0 active. */
- env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A);
- env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A);
- }
- }
-
- /*
- * Configure default legacy segmentation control. We use this regardless of
- * whether segmentation control is presented to the guest.
- */
- /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */
- env->CP0_SegCtl0 = (CP0SC_AM_MK << CP0SC_AM);
- /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */
- env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16;
- /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */
- env->CP0_SegCtl1 = (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) |
- (2 << CP0SC_C);
- /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */
- env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) |
- (3 << CP0SC_C)) << 16;
- /* USeg (seg4 0x40000000..0x7FFFFFFF) */
- env->CP0_SegCtl2 = (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) |
- (1 << CP0SC_EU) | (2 << CP0SC_C);
- /* USeg (seg5 0x00000000..0x3FFFFFFF) */
- env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) |
- (1 << CP0SC_EU) | (2 << CP0SC_C)) << 16;
- /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */
- env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM);
-#endif
- if ((env->insn_flags & ISA_MIPS32R6) &&
- (env->active_fpu.fcr0 & (1 << FCR0_F64))) {
- /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
- env->CP0_Status |= (1 << CP0St_FR);
- }
-
- if (env->insn_flags & ISA_MIPS32R6) {
- /* PTW = 1 */
- env->CP0_PWSize = 0x40;
- /* GDI = 12 */
- /* UDI = 12 */
- /* MDI = 12 */
- /* PRI = 12 */
- /* PTEI = 2 */
- env->CP0_PWField = 0x0C30C302;
- } else {
- /* GDI = 0 */
- /* UDI = 0 */
- /* MDI = 0 */
- /* PRI = 0 */
- /* PTEI = 2 */
- env->CP0_PWField = 0x02;
- }
-
- if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) {
- /* microMIPS on reset when Config3.ISA is 3 */
- env->hflags |= MIPS_HFLAG_M16;
- }
-
- /* MSA */
- if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
- msa_reset(env);
- }
-
- compute_hflags(env);
- restore_fp_status(env);
- restore_pamask(env);
- cs->exception_index = EXCP_NONE;
-
- if (semihosting_get_argc()) {
- /* UHI interface can be used to obtain argc and argv */
- env->active_tc.gpr[4] = -1;
- }
-}
-
void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb,
target_ulong *data)
{
--
2.26.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 16/19] target/mips: Inline cpu_mips_realize_env() in mips_cpu_realizefn()
2020-12-06 23:39 [PATCH 00/19] target/mips: Boring code reordering Philippe Mathieu-Daudé
` (14 preceding siblings ...)
2020-12-06 23:39 ` [PATCH 15/19] target/mips: Move cpu definitions, reset() and realize() to cpu.c Philippe Mathieu-Daudé
@ 2020-12-06 23:39 ` Philippe Mathieu-Daudé
2020-12-08 22:27 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 17/19] target/mips: Rename translate_init.c as cpu-defs.c Philippe Mathieu-Daudé
` (3 subsequent siblings)
19 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-06 23:39 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Philippe Mathieu-Daudé,
Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/cpu.c | 20 ++++++++------------
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 1073db7f257..899a746c3e5 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -104,17 +104,6 @@ static bool mips_cpu_has_work(CPUState *cs)
#include "translate_init.c.inc"
-static void cpu_mips_realize_env(CPUMIPSState *env)
-{
- env->exception_base = (int32_t)0xBFC00000;
-
-#ifndef CONFIG_USER_ONLY
- mmu_init(env, env->cpu_model);
-#endif
- fpu_init(env, env->cpu_model);
- mvp_init(env, env->cpu_model);
-}
-
/* TODO QOM'ify CPU reset and remove */
static void cpu_state_reset(CPUMIPSState *env)
{
@@ -400,6 +389,7 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
MIPSCPU *cpu = MIPS_CPU(dev);
+ CPUMIPSState *env = &cpu->env;
MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
Error *local_err = NULL;
@@ -423,7 +413,13 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
- cpu_mips_realize_env(&cpu->env);
+ env->exception_base = (int32_t)0xBFC00000;
+
+#ifndef CONFIG_USER_ONLY
+ mmu_init(env, env->cpu_model);
+#endif
+ fpu_init(env, env->cpu_model);
+ mvp_init(env, env->cpu_model);
cpu_reset(cs);
qemu_init_vcpu(cs);
--
2.26.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 17/19] target/mips: Rename translate_init.c as cpu-defs.c
2020-12-06 23:39 [PATCH 00/19] target/mips: Boring code reordering Philippe Mathieu-Daudé
` (15 preceding siblings ...)
2020-12-06 23:39 ` [PATCH 16/19] target/mips: Inline cpu_mips_realize_env() in mips_cpu_realizefn() Philippe Mathieu-Daudé
@ 2020-12-06 23:39 ` Philippe Mathieu-Daudé
2020-12-08 22:30 ` Richard Henderson
2020-12-06 23:39 ` [RFC PATCH 18/19] target/mips: Restrict some TCG specific CPUClass handlers Philippe Mathieu-Daudé
` (2 subsequent siblings)
19 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-06 23:39 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Philippe Mathieu-Daudé,
Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
This file is not TCG specific, contains CPU definitions
and is consumed by cpu.c. Rename it as such.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
cpu-defs.c still contains fpu_init()/mvp_init()/msa_reset().
They are moved out in different series (already posted).
---
target/mips/cpu.c | 11 ++++++++++-
target/mips/{translate_init.c.inc => cpu-defs.c.inc} | 9 ---------
2 files changed, 10 insertions(+), 10 deletions(-)
rename target/mips/{translate_init.c.inc => cpu-defs.c.inc} (99%)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 899a746c3e5..8a4486e3ea1 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -102,7 +102,16 @@ static bool mips_cpu_has_work(CPUState *cs)
return has_work;
}
-#include "translate_init.c.inc"
+#include "cpu-defs.c.inc"
+
+void mips_cpu_list(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
+ qemu_printf("MIPS '%s'\n", mips_defs[i].name);
+ }
+}
/* TODO QOM'ify CPU reset and remove */
static void cpu_state_reset(CPUMIPSState *env)
diff --git a/target/mips/translate_init.c.inc b/target/mips/cpu-defs.c.inc
similarity index 99%
rename from target/mips/translate_init.c.inc
rename to target/mips/cpu-defs.c.inc
index f3daf451a63..ad578cb8601 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -922,15 +922,6 @@ const mips_def_t mips_defs[] =
};
const int mips_defs_number = ARRAY_SIZE(mips_defs);
-void mips_cpu_list(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
- qemu_printf("MIPS '%s'\n", mips_defs[i].name);
- }
-}
-
static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
{
int i;
--
2.26.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCH 18/19] target/mips: Restrict some TCG specific CPUClass handlers
2020-12-06 23:39 [PATCH 00/19] target/mips: Boring code reordering Philippe Mathieu-Daudé
` (16 preceding siblings ...)
2020-12-06 23:39 ` [PATCH 17/19] target/mips: Rename translate_init.c as cpu-defs.c Philippe Mathieu-Daudé
@ 2020-12-06 23:39 ` Philippe Mathieu-Daudé
2020-12-07 7:59 ` Claudio Fontana
2020-12-06 23:39 ` [RFC PATCH 19/19] target/mips: Only build TCG code when CONFIG_TCG is set Philippe Mathieu-Daudé
2020-12-06 23:45 ` [PATCH 00/19] target/mips: Boring code reordering no-reply
19 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-06 23:39 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Philippe Mathieu-Daudé,
Richard Henderson, Aleksandar Rikalo, Paolo Bonzini,
Claudio Fontana
Restrict the following CPUClass handlers to TCG:
- do_interrupt
- do_transaction_failed
- do_unaligned_access
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
Cc: Claudio Fontana <cfontana@suse.de>
target/mips/cpu.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 8a4486e3ea1..03bd35b7903 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -483,7 +483,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = mips_cpu_class_by_name;
cc->has_work = mips_cpu_has_work;
- cc->do_interrupt = mips_cpu_do_interrupt;
cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->dump_state = mips_cpu_dump_state;
cc->set_pc = mips_cpu_set_pc;
@@ -491,8 +490,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = mips_cpu_do_transaction_failed;
- cc->do_unaligned_access = mips_cpu_do_unaligned_access;
+ cc->do_interrupt = mips_cpu_do_interrupt;
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_mips_cpu;
#endif
@@ -500,6 +498,10 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
#ifdef CONFIG_TCG
cc->tcg_initialize = mips_tcg_init;
cc->tlb_fill = mips_cpu_tlb_fill;
+#if !defined(CONFIG_USER_ONLY)
+ cc->do_unaligned_access = mips_cpu_do_unaligned_access;
+ cc->do_transaction_failed = mips_cpu_do_transaction_failed;
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
#endif
cc->gdb_num_core_regs = 73;
--
2.26.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCH 19/19] target/mips: Only build TCG code when CONFIG_TCG is set
2020-12-06 23:39 [PATCH 00/19] target/mips: Boring code reordering Philippe Mathieu-Daudé
` (17 preceding siblings ...)
2020-12-06 23:39 ` [RFC PATCH 18/19] target/mips: Restrict some TCG specific CPUClass handlers Philippe Mathieu-Daudé
@ 2020-12-06 23:39 ` Philippe Mathieu-Daudé
2020-12-08 22:30 ` Richard Henderson
2020-12-06 23:45 ` [PATCH 00/19] target/mips: Boring code reordering no-reply
19 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-06 23:39 UTC (permalink / raw)
To: qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Philippe Mathieu-Daudé,
Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
We are very close to build with '--enable-kvm --disable-tcg' :)
---
target/mips/meson.build | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/mips/meson.build b/target/mips/meson.build
index c685f03fb28..ef70d9040e2 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -1,11 +1,13 @@
mips_ss = ss.source_set()
mips_ss.add(files(
- 'common_helper.c',
- 'cp0_helper.c',
'cpu.c',
+ 'gdbstub.c',
+ 'common_helper.c',
+))
+mips_ss.add(when: 'CONFIG_TCG', if_true: files(
+ 'cp0_helper.c',
'dsp_helper.c',
'fpu_helper.c',
- 'gdbstub.c',
'lmmi_helper.c',
'msa_helper.c',
'op_helper.c',
--
2.26.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH 00/19] target/mips: Boring code reordering
2020-12-06 23:39 [PATCH 00/19] target/mips: Boring code reordering Philippe Mathieu-Daudé
` (18 preceding siblings ...)
2020-12-06 23:39 ` [RFC PATCH 19/19] target/mips: Only build TCG code when CONFIG_TCG is set Philippe Mathieu-Daudé
@ 2020-12-06 23:45 ` no-reply
19 siblings, 0 replies; 47+ messages in thread
From: no-reply @ 2020-12-06 23:45 UTC (permalink / raw)
To: f4bug
Cc: qemu-devel, aurelien, jiaxun.yang, paulburton, kvm, chenhuacai,
f4bug, richard.henderson, aleksandar.rikalo, pbonzini
Patchew URL: https://patchew.org/QEMU/20201206233949.3783184-1-f4bug@amsat.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20201206233949.3783184-1-f4bug@amsat.org
Subject: [PATCH 00/19] target/mips: Boring code reordering
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20201206233949.3783184-1-f4bug@amsat.org -> patchew/20201206233949.3783184-1-f4bug@amsat.org
Switched to a new branch 'test'
5955800 target/mips: Only build TCG code when CONFIG_TCG is set
74fb03f target/mips: Restrict some TCG specific CPUClass handlers
1da507c target/mips: Rename translate_init.c as cpu-defs.c
f8b846e target/mips: Inline cpu_mips_realize_env() in mips_cpu_realizefn()
68eb53c target/mips: Move cpu definitions, reset() and realize() to cpu.c
9416a38 target/mips: Move mmu_init() functions to tlb_helper.c
730ab18 target/mips: Fix code style for checkpatch.pl
1c460f4 target/mips: Rename helper.c as tlb_helper.c
9325849 target/mips: Extract common helpers from helper.c to common_helper.c
aacb03c target/mips: Add !CONFIG_USER_ONLY comment after #endif
301d3f7 target/mips: Move mips_cpu_add_definition() from helper.c to cpu.c
518b46c target/mips: Extract cpu_supports*/cpu_set* translate.c
3a9ee45 target/mips: Include "exec/memattrs.h" in 'internal.h'
06e88ca target/mips: Remove unused headers from kvm.c
97f7fd0 target/mips: Remove unused headers from op_helper.c
6a9df4d target/mips: Remove unused headers from cp0_helper.c
b97a6c1b target/mips: Remove unused headers from fpu_helper.c
a6de350 target/mips: Remove unused headers from translate.c
eeb48e2 hw/mips: Move address translation helpers to target/mips/
=== OUTPUT BEGIN ===
1/19 Checking commit eeb48e24ca66 (hw/mips: Move address translation helpers to target/mips/)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#60:
rename from hw/mips/addr.c
total: 0 errors, 1 warnings, 63 lines checked
Patch 1/19 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/19 Checking commit a6de350699a4 (target/mips: Remove unused headers from translate.c)
3/19 Checking commit b97a6c1bc3ca (target/mips: Remove unused headers from fpu_helper.c)
4/19 Checking commit 6a9df4de3a97 (target/mips: Remove unused headers from cp0_helper.c)
5/19 Checking commit 97f7fd0c4202 (target/mips: Remove unused headers from op_helper.c)
6/19 Checking commit 06e88ca591f6 (target/mips: Remove unused headers from kvm.c)
7/19 Checking commit 3a9ee45ad452 (target/mips: Include "exec/memattrs.h" in 'internal.h')
8/19 Checking commit 518b46c99f1a (target/mips: Extract cpu_supports*/cpu_set* translate.c)
9/19 Checking commit 301d3f7162f6 (target/mips: Move mips_cpu_add_definition() from helper.c to cpu.c)
10/19 Checking commit aacb03c8af58 (target/mips: Add !CONFIG_USER_ONLY comment after #endif)
11/19 Checking commit 93258497b42f (target/mips: Extract common helpers from helper.c to common_helper.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#15:
new file mode 100644
ERROR: space prohibited after that '&' (ctx:WxW)
#61: FILE: target/mips/common_helper.c:42:
+ cu = (v >> CP0St_CU0) & 0xf;
^
ERROR: space prohibited after that '&' (ctx:WxW)
#62: FILE: target/mips/common_helper.c:43:
+ mx = (v >> CP0St_MX) & 0x1;
^
ERROR: space prohibited after that '&' (ctx:WxW)
#63: FILE: target/mips/common_helper.c:44:
+ ksu = (v >> CP0St_KSU) & 0x3;
^
ERROR: space prohibited after that '&' (ctx:WxW)
#90: FILE: target/mips/common_helper.c:71:
+ uint32_t ksux = (1 << CP0St_KX) & val;
^
ERROR: space prohibited after that '&' (ctx:WxW)
#98: FILE: target/mips/common_helper.c:79:
+ mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
^
ERROR: space prohibited after that '&' (ctx:WxW)
#125: FILE: target/mips/common_helper.c:106:
+ mask &= ~((1 << CP0Ca_WP) & val);
^
ERROR: space prohibited after that '&' (ctx:WxW)
#130: FILE: target/mips/common_helper.c:111:
+ if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
^
ERROR: space prohibited after that '&' (ctx:WxW)
#140: FILE: target/mips/common_helper.c:121:
+ if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
^
total: 8 errors, 1 warnings, 343 lines checked
Patch 11/19 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
12/19 Checking commit 1c460f4d205c (target/mips: Rename helper.c as tlb_helper.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
rename from target/mips/helper.c
total: 0 errors, 1 warnings, 17 lines checked
Patch 12/19 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/19 Checking commit 730ab184536c (target/mips: Fix code style for checkpatch.pl)
14/19 Checking commit 9416a385f0e7 (target/mips: Move mmu_init() functions to tlb_helper.c)
15/19 Checking commit 68eb53c2ca47 (target/mips: Move cpu definitions, reset() and realize() to cpu.c)
16/19 Checking commit f8b846e71622 (target/mips: Inline cpu_mips_realize_env() in mips_cpu_realizefn())
17/19 Checking commit 1da507c9dd58 (target/mips: Rename translate_init.c as cpu-defs.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#15:
rename from target/mips/translate_init.c.inc
total: 0 errors, 1 warnings, 32 lines checked
Patch 17/19 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/19 Checking commit 74fb03fbc278 (target/mips: Restrict some TCG specific CPUClass handlers)
19/19 Checking commit 59558002f58b (target/mips: Only build TCG code when CONFIG_TCG is set)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20201206233949.3783184-1-f4bug@amsat.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH 18/19] target/mips: Restrict some TCG specific CPUClass handlers
2020-12-06 23:39 ` [RFC PATCH 18/19] target/mips: Restrict some TCG specific CPUClass handlers Philippe Mathieu-Daudé
@ 2020-12-07 7:59 ` Claudio Fontana
2020-12-07 8:53 ` Claudio Fontana
0 siblings, 1 reply; 47+ messages in thread
From: Claudio Fontana @ 2020-12-07 7:59 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
On 12/7/20 12:39 AM, Philippe Mathieu-Daudé wrote:
> Restrict the following CPUClass handlers to TCG:
> - do_interrupt
In this patch it seems do_interrupt is changed to be CONFIG_USER_ONLY, it is not restricted to TCG.
Was this desired, should be commented as such?
Also, should the whole function then be #ifdefed out in helpers.c?
I guess I am vouching for moving the ifndef CONFIG_USER_ONLY one line up in helpers.c.
But you wanted this CONFIG_TCG-only?
> - do_transaction_failed
> - do_unaligned_access
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> Cc: Claudio Fontana <cfontana@suse.de>
>
> target/mips/cpu.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/target/mips/cpu.c b/target/mips/cpu.c
> index 8a4486e3ea1..03bd35b7903 100644
> --- a/target/mips/cpu.c
> +++ b/target/mips/cpu.c
> @@ -483,7 +483,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
>
> cc->class_by_name = mips_cpu_class_by_name;
> cc->has_work = mips_cpu_has_work;
> - cc->do_interrupt = mips_cpu_do_interrupt;
> cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
> cc->dump_state = mips_cpu_dump_state;
> cc->set_pc = mips_cpu_set_pc;
> @@ -491,8 +490,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
> cc->gdb_read_register = mips_cpu_gdb_read_register;
> cc->gdb_write_register = mips_cpu_gdb_write_register;
> #ifndef CONFIG_USER_ONLY
> - cc->do_transaction_failed = mips_cpu_do_transaction_failed;
> - cc->do_unaligned_access = mips_cpu_do_unaligned_access;
> + cc->do_interrupt = mips_cpu_do_interrupt;
> cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
> cc->vmsd = &vmstate_mips_cpu;
> #endif
> @@ -500,6 +498,10 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
> #ifdef CONFIG_TCG
> cc->tcg_initialize = mips_tcg_init;
> cc->tlb_fill = mips_cpu_tlb_fill;
> +#if !defined(CONFIG_USER_ONLY)
> + cc->do_unaligned_access = mips_cpu_do_unaligned_access;
> + cc->do_transaction_failed = mips_cpu_do_transaction_failed;
> +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
> #endif
>
> cc->gdb_num_core_regs = 73;
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH 18/19] target/mips: Restrict some TCG specific CPUClass handlers
2020-12-07 7:59 ` Claudio Fontana
@ 2020-12-07 8:53 ` Claudio Fontana
2020-12-07 9:07 ` Claudio Fontana
0 siblings, 1 reply; 47+ messages in thread
From: Claudio Fontana @ 2020-12-07 8:53 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
On 12/7/20 8:59 AM, Claudio Fontana wrote:
> On 12/7/20 12:39 AM, Philippe Mathieu-Daudé wrote:
>> Restrict the following CPUClass handlers to TCG:
>> - do_interrupt
>
> In this patch it seems do_interrupt is changed to be CONFIG_USER_ONLY, it is not restricted to TCG.
Of course it _is_ as only TCG can do -user- , but would it be better to wrap everything around CONFIG_TCG for what is tcg-only, and then add a subsection in there for CONFIG_USER_ONLY?
> Was this desired, should be commented as such?
>
> Also, should the whole function then be #ifdefed out in helpers.c?
> I guess I am vouching for moving the ifndef CONFIG_USER_ONLY one line up in helpers.c.
>
> But you wanted this CONFIG_TCG-only?
>
>
>> - do_transaction_failed
>> - do_unaligned_access
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>> Cc: Claudio Fontana <cfontana@suse.de>
>>
>> target/mips/cpu.c | 8 +++++---
>> 1 file changed, 5 insertions(+), 3 deletions(-)
>>
>> diff --git a/target/mips/cpu.c b/target/mips/cpu.c
>> index 8a4486e3ea1..03bd35b7903 100644
>> --- a/target/mips/cpu.c
>> +++ b/target/mips/cpu.c
>> @@ -483,7 +483,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
>>
>> cc->class_by_name = mips_cpu_class_by_name;
>> cc->has_work = mips_cpu_has_work;
>> - cc->do_interrupt = mips_cpu_do_interrupt;
>> cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
>> cc->dump_state = mips_cpu_dump_state;
>> cc->set_pc = mips_cpu_set_pc;
>> @@ -491,8 +490,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
>> cc->gdb_read_register = mips_cpu_gdb_read_register;
>> cc->gdb_write_register = mips_cpu_gdb_write_register;
>> #ifndef CONFIG_USER_ONLY
>> - cc->do_transaction_failed = mips_cpu_do_transaction_failed;
>> - cc->do_unaligned_access = mips_cpu_do_unaligned_access;
>> + cc->do_interrupt = mips_cpu_do_interrupt;
>> cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
>> cc->vmsd = &vmstate_mips_cpu;
>> #endif
>> @@ -500,6 +498,10 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
>> #ifdef CONFIG_TCG
>> cc->tcg_initialize = mips_tcg_init;
>> cc->tlb_fill = mips_cpu_tlb_fill;
>> +#if !defined(CONFIG_USER_ONLY)
>> + cc->do_unaligned_access = mips_cpu_do_unaligned_access;
>> + cc->do_transaction_failed = mips_cpu_do_transaction_failed;
>> +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
>> #endif
>>
>> cc->gdb_num_core_regs = 73;
>>
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH 18/19] target/mips: Restrict some TCG specific CPUClass handlers
2020-12-07 8:53 ` Claudio Fontana
@ 2020-12-07 9:07 ` Claudio Fontana
2020-12-07 11:43 ` Claudio Fontana
0 siblings, 1 reply; 47+ messages in thread
From: Claudio Fontana @ 2020-12-07 9:07 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm,
Huacai Chen, Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
On 12/7/20 9:53 AM, Claudio Fontana wrote:
> On 12/7/20 8:59 AM, Claudio Fontana wrote:
>> On 12/7/20 12:39 AM, Philippe Mathieu-Daudé wrote:
>>> Restrict the following CPUClass handlers to TCG:
>>> - do_interrupt
>>
>> In this patch it seems do_interrupt is changed to be CONFIG_USER_ONLY, it is not restricted to TCG.
>
> Of course it _is_ as only TCG can do -user- , but would it be better to wrap everything around CONFIG_TCG for what is tcg-only, and then add a subsection in there for CONFIG_USER_ONLY?
Need coffee, sorry. I think you can see the issue there, sorry for the confusion.
Thanks,
Claudio
>
>> Was this desired, should be commented as such?
>>
>> Also, should the whole function then be #ifdefed out in helpers.c?
>> I guess I am vouching for moving the ifndef CONFIG_USER_ONLY one line up in helpers.c.
>>
>> But you wanted this CONFIG_TCG-only?
>>
>>
>>> - do_transaction_failed
>>> - do_unaligned_access
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>> ---
>>> Cc: Claudio Fontana <cfontana@suse.de>
>>>
>>> target/mips/cpu.c | 8 +++++---
>>> 1 file changed, 5 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/target/mips/cpu.c b/target/mips/cpu.c
>>> index 8a4486e3ea1..03bd35b7903 100644
>>> --- a/target/mips/cpu.c
>>> +++ b/target/mips/cpu.c
>>> @@ -483,7 +483,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
>>>
>>> cc->class_by_name = mips_cpu_class_by_name;
>>> cc->has_work = mips_cpu_has_work;
>>> - cc->do_interrupt = mips_cpu_do_interrupt;
>>> cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
>>> cc->dump_state = mips_cpu_dump_state;
>>> cc->set_pc = mips_cpu_set_pc;
>>> @@ -491,8 +490,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
>>> cc->gdb_read_register = mips_cpu_gdb_read_register;
>>> cc->gdb_write_register = mips_cpu_gdb_write_register;
>>> #ifndef CONFIG_USER_ONLY
>>> - cc->do_transaction_failed = mips_cpu_do_transaction_failed;
>>> - cc->do_unaligned_access = mips_cpu_do_unaligned_access;
>>> + cc->do_interrupt = mips_cpu_do_interrupt;
>>> cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
>>> cc->vmsd = &vmstate_mips_cpu;
>>> #endif
>>> @@ -500,6 +498,10 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
>>> #ifdef CONFIG_TCG
>>> cc->tcg_initialize = mips_tcg_init;
>>> cc->tlb_fill = mips_cpu_tlb_fill;
>>> +#if !defined(CONFIG_USER_ONLY)
>>> + cc->do_unaligned_access = mips_cpu_do_unaligned_access;
>>> + cc->do_transaction_failed = mips_cpu_do_transaction_failed;
>>> +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
>>> #endif
>>>
>>> cc->gdb_num_core_regs = 73;
>>>
>>
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH 18/19] target/mips: Restrict some TCG specific CPUClass handlers
2020-12-07 9:07 ` Claudio Fontana
@ 2020-12-07 11:43 ` Claudio Fontana
2020-12-07 12:49 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 47+ messages in thread
From: Claudio Fontana @ 2020-12-07 11:43 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm,
Huacai Chen, Richard Henderson, Aleksandar Rikalo, Paolo Bonzini
I am adding to my cleanup series the following, so this is done for all targets:
Author: Claudio Fontana <cfontana@suse.de>
Date: Mon Dec 7 11:02:34 2020 +0100
cpu: move do_unaligned_access to tcg_ops
make it consistently SOFTMMU-only.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
commit 1ee8254b568a47453ab481aa206fb9fecc7c16f7
Author: Claudio Fontana <cfontana@suse.de>
Date: Mon Dec 7 10:29:22 2020 +0100
cpu: move cc->transaction_failed to tcg_ops
Signed-off-by: Claudio Fontana <cfontana@suse.de>
commit 1a03124581841b5c473f879f5fd396dccde48667
Author: Claudio Fontana <cfontana@suse.de>
Date: Mon Dec 7 10:02:07 2020 +0100
cpu: move cc->do_interrupt to tcg_ops
Signed-off-by: Claudio Fontana <cfontana@suse.de>
commit 6a35e8f4ee68923006bba404f1f2471038b1039c
Author: Claudio Fontana <cfontana@suse.de>
Date: Mon Dec 7 09:31:14 2020 +0100
target/arm: do not use cc->do_interrupt for KVM directly
cc->do_interrupt is a TCG callback used in accel/tcg only,
call instead directly the arm_cpu_do_interrupt for the
injection of exeptions from KVM, so that
do_interrupt can be exported to TCG-only operations in
the CPUClass.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
On 12/7/20 10:07 AM, Claudio Fontana wrote:
> On 12/7/20 9:53 AM, Claudio Fontana wrote:
>> On 12/7/20 8:59 AM, Claudio Fontana wrote:
>>> On 12/7/20 12:39 AM, Philippe Mathieu-Daudé wrote:
>>>> Restrict the following CPUClass handlers to TCG:
>>>> - do_interrupt
>>>
>>> In this patch it seems do_interrupt is changed to be CONFIG_USER_ONLY, it is not restricted to TCG.
>>
>> Of course it _is_ as only TCG can do -user- , but would it be better to wrap everything around CONFIG_TCG for what is tcg-only, and then add a subsection in there for CONFIG_USER_ONLY?
>
>
> Need coffee, sorry. I think you can see the issue there, sorry for the confusion.
>
> Thanks,
>
> Claudio
>
>
>>
>>> Was this desired, should be commented as such?
>>>
>>> Also, should the whole function then be #ifdefed out in helpers.c?
>>> I guess I am vouching for moving the ifndef CONFIG_USER_ONLY one line up in helpers.c.
>>>
>>> But you wanted this CONFIG_TCG-only?
>>>
>>>
>>>> - do_transaction_failed
>>>> - do_unaligned_access
>>>>
>>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>>> ---
>>>> Cc: Claudio Fontana <cfontana@suse.de>
>>>>
>>>> target/mips/cpu.c | 8 +++++---
>>>> 1 file changed, 5 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/target/mips/cpu.c b/target/mips/cpu.c
>>>> index 8a4486e3ea1..03bd35b7903 100644
>>>> --- a/target/mips/cpu.c
>>>> +++ b/target/mips/cpu.c
>>>> @@ -483,7 +483,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
>>>>
>>>> cc->class_by_name = mips_cpu_class_by_name;
>>>> cc->has_work = mips_cpu_has_work;
>>>> - cc->do_interrupt = mips_cpu_do_interrupt;
>>>> cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
>>>> cc->dump_state = mips_cpu_dump_state;
>>>> cc->set_pc = mips_cpu_set_pc;
>>>> @@ -491,8 +490,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
>>>> cc->gdb_read_register = mips_cpu_gdb_read_register;
>>>> cc->gdb_write_register = mips_cpu_gdb_write_register;
>>>> #ifndef CONFIG_USER_ONLY
>>>> - cc->do_transaction_failed = mips_cpu_do_transaction_failed;
>>>> - cc->do_unaligned_access = mips_cpu_do_unaligned_access;
>>>> + cc->do_interrupt = mips_cpu_do_interrupt;
>>>> cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
>>>> cc->vmsd = &vmstate_mips_cpu;
>>>> #endif
>>>> @@ -500,6 +498,10 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
>>>> #ifdef CONFIG_TCG
>>>> cc->tcg_initialize = mips_tcg_init;
>>>> cc->tlb_fill = mips_cpu_tlb_fill;
>>>> +#if !defined(CONFIG_USER_ONLY)
>>>> + cc->do_unaligned_access = mips_cpu_do_unaligned_access;
>>>> + cc->do_transaction_failed = mips_cpu_do_transaction_failed;
>>>> +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
>>>> #endif
>>>>
>>>> cc->gdb_num_core_regs = 73;
>>>>
>>>
>>
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH 18/19] target/mips: Restrict some TCG specific CPUClass handlers
2020-12-07 11:43 ` Claudio Fontana
@ 2020-12-07 12:49 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-07 12:49 UTC (permalink / raw)
To: Claudio Fontana
Cc: Aleksandar Rikalo, kvm, Paul Burton, Huacai Chen,
Richard Henderson, qemu-devel, Paolo Bonzini, Aurelien Jarno
On 12/7/20 12:43 PM, Claudio Fontana wrote:
> I am adding to my cleanup series the following, so this is done for all targets:
Great! thank you Claudio :)
>
>
> Author: Claudio Fontana <cfontana@suse.de>
> Date: Mon Dec 7 11:02:34 2020 +0100
>
> cpu: move do_unaligned_access to tcg_ops
>
> make it consistently SOFTMMU-only.
>
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
>
> commit 1ee8254b568a47453ab481aa206fb9fecc7c16f7
> Author: Claudio Fontana <cfontana@suse.de>
> Date: Mon Dec 7 10:29:22 2020 +0100
>
> cpu: move cc->transaction_failed to tcg_ops
>
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
>
> commit 1a03124581841b5c473f879f5fd396dccde48667
> Author: Claudio Fontana <cfontana@suse.de>
> Date: Mon Dec 7 10:02:07 2020 +0100
>
> cpu: move cc->do_interrupt to tcg_ops
>
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
>
> commit 6a35e8f4ee68923006bba404f1f2471038b1039c
> Author: Claudio Fontana <cfontana@suse.de>
> Date: Mon Dec 7 09:31:14 2020 +0100
>
> target/arm: do not use cc->do_interrupt for KVM directly
>
> cc->do_interrupt is a TCG callback used in accel/tcg only,
> call instead directly the arm_cpu_do_interrupt for the
> injection of exeptions from KVM, so that
>
> do_interrupt can be exported to TCG-only operations in
> the CPUClass.
>
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 01/19] hw/mips: Move address translation helpers to target/mips/
2020-12-06 23:39 ` [PATCH 01/19] hw/mips: Move address translation helpers to target/mips/ Philippe Mathieu-Daudé
@ 2020-12-08 21:46 ` Richard Henderson
0 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-08 21:46 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Aleksandar Rikalo, Paolo Bonzini
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Address translation is an architectural thing (not hardware
> related). Move the helpers from hw/ to target/.
>
> As physical address and KVM are specific to system mode
> emulation, restrict this file to softmmu, so it doesn't
> get compiled for user-mode emulation.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> include/hw/mips/cpudevs.h | 7 -------
> target/mips/cpu.h | 8 ++++++++
> hw/mips/boston.c | 1 -
> {hw => target}/mips/addr.c | 2 +-
> target/mips/translate.c | 2 --
> hw/mips/meson.build | 2 +-
> target/mips/meson.build | 1 +
> 7 files changed, 11 insertions(+), 12 deletions(-)
> rename {hw => target}/mips/addr.c (98%)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 02/19] target/mips: Remove unused headers from translate.c
2020-12-06 23:39 ` [PATCH 02/19] target/mips: Remove unused headers from translate.c Philippe Mathieu-Daudé
@ 2020-12-08 21:47 ` Richard Henderson
0 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-08 21:47 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Aleksandar Rikalo, Paolo Bonzini
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/translate.c | 2 --
> 1 file changed, 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 03/19] target/mips: Remove unused headers from fpu_helper.c
2020-12-06 23:39 ` [PATCH 03/19] target/mips: Remove unused headers from fpu_helper.c Philippe Mathieu-Daudé
@ 2020-12-08 21:49 ` Richard Henderson
0 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-08 21:49 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Aleksandar Rikalo, Paolo Bonzini
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/fpu_helper.c | 4 ----
> 1 file changed, 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 04/19] target/mips: Remove unused headers from cp0_helper.c
2020-12-06 23:39 ` [PATCH 04/19] target/mips: Remove unused headers from cp0_helper.c Philippe Mathieu-Daudé
@ 2020-12-08 21:50 ` Richard Henderson
0 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-08 21:50 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Aleksandar Rikalo, Paolo Bonzini
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Remove unused headers and add missing "qemu/log.h" since
> qemu_log() is called.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/cp0_helper.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 05/19] target/mips: Remove unused headers from op_helper.c
2020-12-06 23:39 ` [PATCH 05/19] target/mips: Remove unused headers from op_helper.c Philippe Mathieu-Daudé
@ 2020-12-08 21:50 ` Richard Henderson
0 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-08 21:50 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Aleksandar Rikalo, Paolo Bonzini
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/op_helper.c | 4 ----
> 1 file changed, 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 06/19] target/mips: Remove unused headers from kvm.c
2020-12-06 23:39 ` [PATCH 06/19] target/mips: Remove unused headers from kvm.c Philippe Mathieu-Daudé
@ 2020-12-08 21:50 ` Richard Henderson
0 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-08 21:50 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Aleksandar Rikalo, Paolo Bonzini
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/kvm.c | 2 --
> 1 file changed, 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 07/19] target/mips: Include "exec/memattrs.h" in 'internal.h'
2020-12-06 23:39 ` [PATCH 07/19] target/mips: Include "exec/memattrs.h" in 'internal.h' Philippe Mathieu-Daudé
@ 2020-12-08 21:51 ` Richard Henderson
0 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-08 21:51 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Aleksandar Rikalo, Paolo Bonzini
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> mips_cpu_do_transaction_failed() requires MemTxAttrs
> and MemTxResult declarations.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/internal.h | 1 +
> target/mips/kvm.c | 1 -
> 2 files changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 08/19] target/mips: Extract cpu_supports*/cpu_set* translate.c
2020-12-06 23:39 ` [PATCH 08/19] target/mips: Extract cpu_supports*/cpu_set* translate.c Philippe Mathieu-Daudé
@ 2020-12-08 21:53 ` Richard Henderson
0 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-08 21:53 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Aleksandar Rikalo, Paolo Bonzini
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Move cpu_supports*() and cpu_set_exception_base() from
> translate.c to cpu.c.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/cpu.c | 18 ++++++++++++++++++
> target/mips/translate.c | 18 ------------------
> 2 files changed, 18 insertions(+), 18 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 09/19] target/mips: Move mips_cpu_add_definition() from helper.c to cpu.c
2020-12-06 23:39 ` [PATCH 09/19] target/mips: Move mips_cpu_add_definition() from helper.c to cpu.c Philippe Mathieu-Daudé
@ 2020-12-08 21:55 ` Richard Henderson
0 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-08 21:55 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Aleksandar Rikalo, Paolo Bonzini
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/cpu.c | 33 +++++++++++++++++++++++++++++++++
> target/mips/helper.c | 33 ---------------------------------
> 2 files changed, 33 insertions(+), 33 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 10/19] target/mips: Add !CONFIG_USER_ONLY comment after #endif
2020-12-06 23:39 ` [PATCH 10/19] target/mips: Add !CONFIG_USER_ONLY comment after #endif Philippe Mathieu-Daudé
@ 2020-12-08 21:59 ` Richard Henderson
0 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-08 21:59 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Aleksandar Rikalo, Paolo Bonzini
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> To help understand ifdef'ry, add comment after #endif.
This does more than that.
> @@ -550,9 +552,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
> }
> return phys_addr;
> }
> -#endif
>
> -#if !defined(CONFIG_USER_ONLY)
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 11/19] target/mips: Extract common helpers from helper.c to common_helper.c
2020-12-06 23:39 ` [PATCH 11/19] target/mips: Extract common helpers from helper.c to common_helper.c Philippe Mathieu-Daudé
@ 2020-12-08 22:06 ` Richard Henderson
2020-12-14 14:23 ` Philippe Mathieu-Daudé
[not found] ` <CAE2XoE_WzMzCbvxtPdQfbU2rs-wd26GXpds9VypW7B-ik7qWJA@mail.gmail.com>
0 siblings, 2 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-08 22:06 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Aleksandar Rikalo, Paolo Bonzini
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> The rest of helper.c is TLB related. Extract the non TLB
> specific functions to a new file, so we can rename helper.c
> as tlb_helper.c in the next commit.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> Any better name? xxx_helper.c are usually TCG helpers.
*shrug* perhaps cpu_common.c, no "helper" at all?
Perhaps just move these bits to cpu.c?
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 12/19] target/mips: Rename helper.c as tlb_helper.c
2020-12-06 23:39 ` [PATCH 12/19] target/mips: Rename helper.c as tlb_helper.c Philippe Mathieu-Daudé
@ 2020-12-08 22:09 ` Richard Henderson
0 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-08 22:09 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Aleksandar Rikalo, Paolo Bonzini
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> This file contains functions related to TLB management,
> rename it as 'tlb_helper.c'.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> Maybe I missed some functions not TLB specific...
> ---
> target/mips/{helper.c => tlb_helper.c} | 2 +-
> target/mips/meson.build | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
> rename target/mips/{helper.c => tlb_helper.c} (99%)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 13/19] target/mips: Fix code style for checkpatch.pl
2020-12-06 23:39 ` [PATCH 13/19] target/mips: Fix code style for checkpatch.pl Philippe Mathieu-Daudé
@ 2020-12-08 22:11 ` Richard Henderson
0 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-08 22:11 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Aleksandar Rikalo, Paolo Bonzini
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> We are going to move this code, fix its style first.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/translate_init.c.inc | 36 ++++++++++++++++----------------
> 1 file changed, 18 insertions(+), 18 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 14/19] target/mips: Move mmu_init() functions to tlb_helper.c
2020-12-06 23:39 ` [PATCH 14/19] target/mips: Move mmu_init() functions to tlb_helper.c Philippe Mathieu-Daudé
@ 2020-12-08 22:19 ` Richard Henderson
0 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-08 22:19 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Aleksandar Rikalo, Paolo Bonzini
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/internal.h | 1 +
> target/mips/tlb_helper.c | 46 ++++++++++++++++++++++++++++++
> target/mips/translate_init.c.inc | 48 --------------------------------
> 3 files changed, 47 insertions(+), 48 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 15/19] target/mips: Move cpu definitions, reset() and realize() to cpu.c
2020-12-06 23:39 ` [PATCH 15/19] target/mips: Move cpu definitions, reset() and realize() to cpu.c Philippe Mathieu-Daudé
@ 2020-12-08 22:27 ` Richard Henderson
0 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-08 22:27 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Aleksandar Rikalo, Paolo Bonzini
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Nothing TCG specific there, move to common cpu code.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/internal.h | 4 -
> target/mips/cpu.c | 243 ++++++++++++++++++++++++++++++++++++++++
> target/mips/translate.c | 240 ---------------------------------------
> 3 files changed, 243 insertions(+), 244 deletions(-)
I see translate_init.c.inc is handled later.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 16/19] target/mips: Inline cpu_mips_realize_env() in mips_cpu_realizefn()
2020-12-06 23:39 ` [PATCH 16/19] target/mips: Inline cpu_mips_realize_env() in mips_cpu_realizefn() Philippe Mathieu-Daudé
@ 2020-12-08 22:27 ` Richard Henderson
0 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-08 22:27 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Aleksandar Rikalo, Paolo Bonzini
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/cpu.c | 20 ++++++++------------
> 1 file changed, 8 insertions(+), 12 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 17/19] target/mips: Rename translate_init.c as cpu-defs.c
2020-12-06 23:39 ` [PATCH 17/19] target/mips: Rename translate_init.c as cpu-defs.c Philippe Mathieu-Daudé
@ 2020-12-08 22:30 ` Richard Henderson
2020-12-14 14:40 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 47+ messages in thread
From: Richard Henderson @ 2020-12-08 22:30 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Aleksandar Rikalo, Paolo Bonzini
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> This file is not TCG specific, contains CPU definitions
> and is consumed by cpu.c. Rename it as such.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> cpu-defs.c still contains fpu_init()/mvp_init()/msa_reset().
> They are moved out in different series (already posted).
After the other functions are moved, then this file may be compiled separately?
Or... why is mips_cpu_list moved? I guess it wouldn't be able to be separately
compiled, because of the ARRAY_SIZE.
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH 19/19] target/mips: Only build TCG code when CONFIG_TCG is set
2020-12-06 23:39 ` [RFC PATCH 19/19] target/mips: Only build TCG code when CONFIG_TCG is set Philippe Mathieu-Daudé
@ 2020-12-08 22:30 ` Richard Henderson
0 siblings, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2020-12-08 22:30 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aurelien Jarno, Jiaxun Yang, Paul Burton, kvm, Huacai Chen,
Aleksandar Rikalo, Paolo Bonzini
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> We are very close to build with '--enable-kvm --disable-tcg' :)
> ---
> target/mips/meson.build | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 11/19] target/mips: Extract common helpers from helper.c to common_helper.c
2020-12-08 22:06 ` Richard Henderson
@ 2020-12-14 14:23 ` Philippe Mathieu-Daudé
[not found] ` <CAE2XoE_WzMzCbvxtPdQfbU2rs-wd26GXpds9VypW7B-ik7qWJA@mail.gmail.com>
1 sibling, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 14:23 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Aleksandar Rikalo, kvm, Paul Burton, Huacai Chen, Paolo Bonzini,
Aurelien Jarno
On 12/8/20 11:06 PM, Richard Henderson wrote:
> On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
>> The rest of helper.c is TLB related. Extract the non TLB
>> specific functions to a new file, so we can rename helper.c
>> as tlb_helper.c in the next commit.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>> Any better name? xxx_helper.c are usually TCG helpers.
>
> *shrug* perhaps cpu_common.c, no "helper" at all?
> Perhaps just move these bits to cpu.c?
Sounds good, thanks :)
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 17/19] target/mips: Rename translate_init.c as cpu-defs.c
2020-12-08 22:30 ` Richard Henderson
@ 2020-12-14 14:40 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 14:40 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Aleksandar Rikalo, kvm, Paul Burton, Huacai Chen, Paolo Bonzini,
Aurelien Jarno
On 12/8/20 11:30 PM, Richard Henderson wrote:
> On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
>> This file is not TCG specific, contains CPU definitions
>> and is consumed by cpu.c. Rename it as such.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>> cpu-defs.c still contains fpu_init()/mvp_init()/msa_reset().
>> They are moved out in different series (already posted).
>
> After the other functions are moved, then this file may be compiled separately?
>
> Or... why is mips_cpu_list moved? I guess it wouldn't be able to be separately
> compiled, because of the ARRAY_SIZE.
Indeed, I missed that.
Thanks,
Phil.
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 11/19] target/mips: Extract common helpers from helper.c to common_helper.c
[not found] ` <CAE2XoE_WzMzCbvxtPdQfbU2rs-wd26GXpds9VypW7B-ik7qWJA@mail.gmail.com>
@ 2020-12-14 14:54 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 14:54 UTC (permalink / raw)
To: luoyonggang, Richard Henderson
Cc: Aleksandar Rikalo, kvm, Paul Burton, Huacai Chen, qemu-level,
Paolo Bonzini, Aurelien Jarno
On 12/14/20 3:51 PM, 罗勇刚(Yonggang Luo) wrote:
> On Wed, Dec 9, 2020 at 6:09 AM Richard Henderson
> <richard.henderson@linaro.org <mailto:richard.henderson@linaro.org>> wrote:
>>
>> On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
>> > The rest of helper.c is TLB related. Extract the non TLB
>> > specific functions to a new file, so we can rename helper.c
>> > as tlb_helper.c in the next commit.
>> >
>> > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org
> <mailto:f4bug@amsat.org>>
>> > ---
>> > Any better name? xxx_helper.c are usually TCG helpers.
>>
>> *shrug* perhaps cpu_common.c, no "helper" at all?
>> Perhaps just move these bits to cpu.c?
>>
>>
>> r~
>>
> Does these are general cpu bits or misp_cpu bits?
> if only misp cpu related, prefer misp_cpu.c
> or cpu.c under misp folder.
Yes, as the patch subject prefix implies, this is a change
local to the target/mips/ directory.
Regards,
Phil.
^ permalink raw reply [flat|nested] 47+ messages in thread
end of thread, other threads:[~2020-12-14 14:58 UTC | newest]
Thread overview: 47+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-06 23:39 [PATCH 00/19] target/mips: Boring code reordering Philippe Mathieu-Daudé
2020-12-06 23:39 ` [PATCH 01/19] hw/mips: Move address translation helpers to target/mips/ Philippe Mathieu-Daudé
2020-12-08 21:46 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 02/19] target/mips: Remove unused headers from translate.c Philippe Mathieu-Daudé
2020-12-08 21:47 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 03/19] target/mips: Remove unused headers from fpu_helper.c Philippe Mathieu-Daudé
2020-12-08 21:49 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 04/19] target/mips: Remove unused headers from cp0_helper.c Philippe Mathieu-Daudé
2020-12-08 21:50 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 05/19] target/mips: Remove unused headers from op_helper.c Philippe Mathieu-Daudé
2020-12-08 21:50 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 06/19] target/mips: Remove unused headers from kvm.c Philippe Mathieu-Daudé
2020-12-08 21:50 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 07/19] target/mips: Include "exec/memattrs.h" in 'internal.h' Philippe Mathieu-Daudé
2020-12-08 21:51 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 08/19] target/mips: Extract cpu_supports*/cpu_set* translate.c Philippe Mathieu-Daudé
2020-12-08 21:53 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 09/19] target/mips: Move mips_cpu_add_definition() from helper.c to cpu.c Philippe Mathieu-Daudé
2020-12-08 21:55 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 10/19] target/mips: Add !CONFIG_USER_ONLY comment after #endif Philippe Mathieu-Daudé
2020-12-08 21:59 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 11/19] target/mips: Extract common helpers from helper.c to common_helper.c Philippe Mathieu-Daudé
2020-12-08 22:06 ` Richard Henderson
2020-12-14 14:23 ` Philippe Mathieu-Daudé
[not found] ` <CAE2XoE_WzMzCbvxtPdQfbU2rs-wd26GXpds9VypW7B-ik7qWJA@mail.gmail.com>
2020-12-14 14:54 ` Philippe Mathieu-Daudé
2020-12-06 23:39 ` [PATCH 12/19] target/mips: Rename helper.c as tlb_helper.c Philippe Mathieu-Daudé
2020-12-08 22:09 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 13/19] target/mips: Fix code style for checkpatch.pl Philippe Mathieu-Daudé
2020-12-08 22:11 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 14/19] target/mips: Move mmu_init() functions to tlb_helper.c Philippe Mathieu-Daudé
2020-12-08 22:19 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 15/19] target/mips: Move cpu definitions, reset() and realize() to cpu.c Philippe Mathieu-Daudé
2020-12-08 22:27 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 16/19] target/mips: Inline cpu_mips_realize_env() in mips_cpu_realizefn() Philippe Mathieu-Daudé
2020-12-08 22:27 ` Richard Henderson
2020-12-06 23:39 ` [PATCH 17/19] target/mips: Rename translate_init.c as cpu-defs.c Philippe Mathieu-Daudé
2020-12-08 22:30 ` Richard Henderson
2020-12-14 14:40 ` Philippe Mathieu-Daudé
2020-12-06 23:39 ` [RFC PATCH 18/19] target/mips: Restrict some TCG specific CPUClass handlers Philippe Mathieu-Daudé
2020-12-07 7:59 ` Claudio Fontana
2020-12-07 8:53 ` Claudio Fontana
2020-12-07 9:07 ` Claudio Fontana
2020-12-07 11:43 ` Claudio Fontana
2020-12-07 12:49 ` Philippe Mathieu-Daudé
2020-12-06 23:39 ` [RFC PATCH 19/19] target/mips: Only build TCG code when CONFIG_TCG is set Philippe Mathieu-Daudé
2020-12-08 22:30 ` Richard Henderson
2020-12-06 23:45 ` [PATCH 00/19] target/mips: Boring code reordering no-reply
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