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From: Zenghui Yu <yuzenghui@huawei.com>
To: <linux-kernel@vger.kernel.org>, <maz@kernel.org>
Cc: jason@lakedaemon.net, tglx@linutronix.de,
	kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 2/6] irqchip/gic-v4.1: Set vpe_l1_base for all redistributors
Date: Thu, 6 Feb 2020 15:57:07 +0800	[thread overview]
Message-ID: <20200206075711.1275-3-yuzenghui@huawei.com> (raw)
In-Reply-To: <20200206075711.1275-1-yuzenghui@huawei.com>

Currently, we will not set vpe_l1_page for the current RD if we can
inherit the vPE configuration table from another RD (or ITS), which
results in an inconsistency between RDs within the same CommonLPIAff
group.

Let's rename it to vpe_l1_base to indicate the base address of the
vPE configuration table of this RD, and set it properly for *all*
v4.1 redistributors.

Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
---
 drivers/irqchip/irq-gic-v3-its.c   | 5 ++++-
 include/linux/irqchip/arm-gic-v3.h | 2 +-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 992bc72cab6f..0f1fe56ce0af 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -2376,6 +2376,8 @@ static u64 inherit_vpe_l1_table_from_its(void)
 			continue;
 
 		/* We have a winner! */
+		gic_data_rdist()->vpe_l1_base = its->tables[2].base;
+
 		val  = GICR_VPROPBASER_4_1_VALID;
 		if (baser & GITS_BASER_INDIRECT)
 			val |= GICR_VPROPBASER_4_1_INDIRECT;
@@ -2432,6 +2434,7 @@ static u64 inherit_vpe_l1_table_from_rd(cpumask_t **mask)
 		val = gits_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
 		val &= ~GICR_VPROPBASER_4_1_Z;
 
+		gic_data_rdist()->vpe_l1_base = gic_data_rdist_cpu(cpu)->vpe_l1_base;
 		*mask = gic_data_rdist_cpu(cpu)->vpe_table_mask;
 
 		return val;
@@ -2542,7 +2545,7 @@ static int allocate_vpe_l1_table(void)
 	if (!page)
 		return -ENOMEM;
 
-	gic_data_rdist()->vpe_l1_page = page;
+	gic_data_rdist()->vpe_l1_base = page_address(page);
 	pa = virt_to_phys(page_address(page));
 	WARN_ON(!IS_ALIGNED(pa, psz));
 
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index f0b8ca766e7d..83439bfb6c5b 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -652,10 +652,10 @@ struct rdists {
 	struct {
 		void __iomem	*rd_base;
 		struct page	*pend_page;
-		struct page	*vpe_l1_page;
 		phys_addr_t	phys_base;
 		bool		lpi_enabled;
 		cpumask_t	*vpe_table_mask;
+		void		*vpe_l1_base;
 	} __percpu		*rdist;
 	phys_addr_t		prop_table_pa;
 	void			*prop_table_va;
-- 
2.19.1


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  parent reply	other threads:[~2020-02-06  7:58 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-06  7:57 [PATCH v2 0/6] irqchip/gic-v4.1: Cleanup and fixes for GICv4.1 Zenghui Yu
2020-02-06  7:57 ` [PATCH v2 1/6] irqchip/gic-v4.1: Fix programming of GICR_VPROPBASER_4_1_SIZE Zenghui Yu
2020-02-06  7:57 ` Zenghui Yu [this message]
2020-02-06  7:57 ` [PATCH v2 3/6] irqchip/gic-v4.1: Ensure L2 vPE table is allocated at RD level Zenghui Yu
2020-02-13 14:22   ` Marc Zyngier
2020-02-13 15:11     ` Zenghui Yu
2020-02-06  7:57 ` [PATCH v2 4/6] irqchip/gic-v4.1: Drop 'tmp' in inherit_vpe_l1_table_from_rd() Zenghui Yu
2020-02-06  7:57 ` [PATCH v2 5/6] irqchip/gic-v3-its: Remove superfluous WARN_ON Zenghui Yu
2020-02-06  7:57 ` [PATCH v2 6/6] irqchip/gic-v3-its: Rename VPENDBASER/VPROPBASER accessors Zenghui Yu

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