* [PATCH v1 0/3] Enable writable for ID_AA64DFR0_EL1 and ID_DFR0_EL1
@ 2023-03-26 1:19 Jing Zhang
2023-03-26 1:19 ` [PATCH v1 1/3] KVM: arm64: Enable writable for BRPs and CTX_CMPs for ID_AA64DFR0_EL1 Jing Zhang
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Jing Zhang @ 2023-03-26 1:19 UTC (permalink / raw)
To: KVM, KVMARM, ARMLinux, Marc Zyngier, Oliver Upton
Cc: Will Deacon, Paolo Bonzini, James Morse, Alexandru Elisei,
Suzuki K Poulose, Fuad Tabba, Reiji Watanabe, Ricardo Koller,
Raghavendra Rao Ananta, Jing Zhang
This patch series is based on a previous patch series which adds the framework
to allow enabling writable from userspace for CPU ID register easily. That patch
series is at https://lore.kernel.org/all/20230317050637.766317-1-jingzhangos@google.com.
This patch series shows how easy to enable writable for feature fields with
dependencies and enable writable for a bunch of feature fields in an ID register.
---
Jing Zhang (3):
KVM: arm64: Enable writable for BRPs and CTX_CMPs for ID_AA64DFR0_EL1
KVM: arm64: Enable writable for remaining fields for ID_AA64DFR0_EL1
KVM: arm64: Enable writable for all fields in ID_DFR0_EL1
arch/arm64/kvm/id_regs.c | 45 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 44 insertions(+), 1 deletion(-)
base-commit: 020e96f196a31bf5c5aa2549cdfc4a401a8cf478
--
2.40.0.348.gf938b09366-goog
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v1 1/3] KVM: arm64: Enable writable for BRPs and CTX_CMPs for ID_AA64DFR0_EL1
2023-03-26 1:19 [PATCH v1 0/3] Enable writable for ID_AA64DFR0_EL1 and ID_DFR0_EL1 Jing Zhang
@ 2023-03-26 1:19 ` Jing Zhang
2023-03-26 1:19 ` [PATCH v1 2/3] KVM: arm64: Enable writable for remaining fields " Jing Zhang
2023-03-26 1:19 ` [PATCH v1 3/3] KVM: arm64: Enable writable for all fields in ID_DFR0_EL1 Jing Zhang
2 siblings, 0 replies; 4+ messages in thread
From: Jing Zhang @ 2023-03-26 1:19 UTC (permalink / raw)
To: KVM, KVMARM, ARMLinux, Marc Zyngier, Oliver Upton
Cc: Will Deacon, Paolo Bonzini, James Morse, Alexandru Elisei,
Suzuki K Poulose, Fuad Tabba, Reiji Watanabe, Ricardo Koller,
Raghavendra Rao Ananta, Jing Zhang
Since number of context-aware breakpoints must be no more than number
of supported breakpoints according to Arm ARM, return an error if
userspace tries to set CTX_CMPS field to such value.
Signed-off-by: Jing Zhang <jingzhangos@google.com>
---
arch/arm64/kvm/id_regs.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c
index 726b810b6e06..64691273980b 100644
--- a/arch/arm64/kvm/id_regs.c
+++ b/arch/arm64/kvm/id_regs.c
@@ -362,10 +362,15 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
const struct sys_reg_desc *rd,
u64 val)
{
- u8 pmuver, host_pmuver;
+ u8 pmuver, host_pmuver, brps, ctx_cmps;
bool valid_pmu;
int ret;
+ brps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_BRPs), val);
+ ctx_cmps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_CTX_CMPs), val);
+ if (ctx_cmps > brps)
+ return -EINVAL;
+
host_pmuver = kvm_arm_pmu_get_pmuver_limit();
/*
@@ -623,6 +628,10 @@ static struct id_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
.ftr_bits = {
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
ID_AA64DFR0_EL1_PMUVer_SHIFT, ID_AA64DFR0_EL1_PMUVer_WIDTH, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+ ID_AA64DFR0_EL1_BRPs_SHIFT, ID_AA64DFR0_EL1_BRPs_WIDTH, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+ ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, ID_AA64DFR0_EL1_CTX_CMPs_WIDTH, 0),
ARM64_FTR_END, },
.init = init_id_aa64dfr0_el1,
},
--
2.40.0.348.gf938b09366-goog
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v1 2/3] KVM: arm64: Enable writable for remaining fields for ID_AA64DFR0_EL1
2023-03-26 1:19 [PATCH v1 0/3] Enable writable for ID_AA64DFR0_EL1 and ID_DFR0_EL1 Jing Zhang
2023-03-26 1:19 ` [PATCH v1 1/3] KVM: arm64: Enable writable for BRPs and CTX_CMPs for ID_AA64DFR0_EL1 Jing Zhang
@ 2023-03-26 1:19 ` Jing Zhang
2023-03-26 1:19 ` [PATCH v1 3/3] KVM: arm64: Enable writable for all fields in ID_DFR0_EL1 Jing Zhang
2 siblings, 0 replies; 4+ messages in thread
From: Jing Zhang @ 2023-03-26 1:19 UTC (permalink / raw)
To: KVM, KVMARM, ARMLinux, Marc Zyngier, Oliver Upton
Cc: Will Deacon, Paolo Bonzini, James Morse, Alexandru Elisei,
Suzuki K Poulose, Fuad Tabba, Reiji Watanabe, Ricardo Koller,
Raghavendra Rao Ananta, Jing Zhang
Enable writable from userspace for all remaining fields in
ID_AA64DFR0_EL1, which don't need special handlings for dependency.
Signed-off-by: Jing Zhang <jingzhangos@google.com>
---
arch/arm64/kvm/id_regs.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c
index 64691273980b..e64152aa448b 100644
--- a/arch/arm64/kvm/id_regs.c
+++ b/arch/arm64/kvm/id_regs.c
@@ -626,12 +626,32 @@ static struct id_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
.get_user = get_id_reg,
.set_user = set_id_aa64dfr0_el1, },
.ftr_bits = {
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+ ID_AA64DFR0_EL1_DebugVer_SHIFT, ID_AA64DFR0_EL1_DebugVer_WIDTH, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+ ID_AA64DFR0_EL1_TraceVer_SHIFT, ID_AA64DFR0_EL1_TraceVer_WIDTH, 0),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
ID_AA64DFR0_EL1_PMUVer_SHIFT, ID_AA64DFR0_EL1_PMUVer_WIDTH, 0),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
ID_AA64DFR0_EL1_BRPs_SHIFT, ID_AA64DFR0_EL1_BRPs_WIDTH, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+ ID_AA64DFR0_EL1_WRPs_SHIFT, ID_AA64DFR0_EL1_WRPs_WIDTH, 0),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, ID_AA64DFR0_EL1_CTX_CMPs_WIDTH, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+ ID_AA64DFR0_EL1_PMSVer_SHIFT, ID_AA64DFR0_EL1_PMSVer_WIDTH, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+ ID_AA64DFR0_EL1_DoubleLock_SHIFT, ID_AA64DFR0_EL1_DoubleLock_WIDTH, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+ ID_AA64DFR0_EL1_TraceFilt_SHIFT, ID_AA64DFR0_EL1_TraceFilt_WIDTH, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+ ID_AA64DFR0_EL1_TraceBuffer_SHIFT, ID_AA64DFR0_EL1_TraceBuffer_WIDTH, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+ ID_AA64DFR0_EL1_MTPMU_SHIFT, ID_AA64DFR0_EL1_MTPMU_WIDTH, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+ ID_AA64DFR0_EL1_BRBE_SHIFT, ID_AA64DFR0_EL1_BRBE_WIDTH, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+ ID_AA64DFR0_EL1_HPMN0_SHIFT, ID_AA64DFR0_EL1_HPMN0_WIDTH, 0),
ARM64_FTR_END, },
.init = init_id_aa64dfr0_el1,
},
--
2.40.0.348.gf938b09366-goog
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v1 3/3] KVM: arm64: Enable writable for all fields in ID_DFR0_EL1
2023-03-26 1:19 [PATCH v1 0/3] Enable writable for ID_AA64DFR0_EL1 and ID_DFR0_EL1 Jing Zhang
2023-03-26 1:19 ` [PATCH v1 1/3] KVM: arm64: Enable writable for BRPs and CTX_CMPs for ID_AA64DFR0_EL1 Jing Zhang
2023-03-26 1:19 ` [PATCH v1 2/3] KVM: arm64: Enable writable for remaining fields " Jing Zhang
@ 2023-03-26 1:19 ` Jing Zhang
2 siblings, 0 replies; 4+ messages in thread
From: Jing Zhang @ 2023-03-26 1:19 UTC (permalink / raw)
To: KVM, KVMARM, ARMLinux, Marc Zyngier, Oliver Upton
Cc: Will Deacon, Paolo Bonzini, James Morse, Alexandru Elisei,
Suzuki K Poulose, Fuad Tabba, Reiji Watanabe, Ricardo Koller,
Raghavendra Rao Ananta, Jing Zhang
All valid fields in ID_DFR0_EL1 are writable from usrespace with this
change.
Signed-off-by: Jing Zhang <jingzhangos@google.com>
---
arch/arm64/kvm/id_regs.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c
index e64152aa448b..7dc2fb8121f3 100644
--- a/arch/arm64/kvm/id_regs.c
+++ b/arch/arm64/kvm/id_regs.c
@@ -565,8 +565,22 @@ static struct id_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
.set_user = set_id_dfr0_el1,
.visibility = aa32_id_visibility, },
.ftr_bits = {
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+ ID_DFR0_EL1_CopDbg_SHIFT, ID_DFR0_EL1_CopDbg_WIDTH, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+ ID_DFR0_EL1_CopSDbg_SHIFT, ID_DFR0_EL1_CopSDbg_WIDTH, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+ ID_DFR0_EL1_MMapDbg_SHIFT, ID_DFR0_EL1_MMapDbg_WIDTH, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+ ID_DFR0_EL1_CopTrc_SHIFT, ID_DFR0_EL1_CopTrc_WIDTH, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+ ID_DFR0_EL1_MMapTrc_SHIFT, ID_DFR0_EL1_MMapTrc_WIDTH, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+ ID_DFR0_EL1_MProfDbg_SHIFT, ID_DFR0_EL1_MProfDbg_WIDTH, 0),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
ID_DFR0_EL1_PerfMon_SHIFT, ID_DFR0_EL1_PerfMon_WIDTH, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+ ID_DFR0_EL1_TraceFilt_SHIFT, ID_DFR0_EL1_TraceFilt_WIDTH, 0),
ARM64_FTR_END, },
.init = init_id_dfr0_el1,
},
--
2.40.0.348.gf938b09366-goog
^ permalink raw reply related [flat|nested] 4+ messages in thread
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2023-03-26 1:19 [PATCH v1 0/3] Enable writable for ID_AA64DFR0_EL1 and ID_DFR0_EL1 Jing Zhang
2023-03-26 1:19 ` [PATCH v1 1/3] KVM: arm64: Enable writable for BRPs and CTX_CMPs for ID_AA64DFR0_EL1 Jing Zhang
2023-03-26 1:19 ` [PATCH v1 2/3] KVM: arm64: Enable writable for remaining fields " Jing Zhang
2023-03-26 1:19 ` [PATCH v1 3/3] KVM: arm64: Enable writable for all fields in ID_DFR0_EL1 Jing Zhang
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