* [PATCH 1/3] arm64: Add missing _EL12 encodings
2023-09-13 18:52 [PATCH 0/3] Fine grain sysregs allowed to trap for nested virtualization Miguel Luis
@ 2023-09-13 18:52 ` Miguel Luis
2023-09-13 18:52 ` [PATCH 2/3] arm64/kvm: Fine grain _EL2 system registers list that affect nested virtualization Miguel Luis
2023-09-13 18:52 ` [PATCH 3/3] KVM: arm64: nv: Handle all _EL02 and _EL12 registers Miguel Luis
2 siblings, 0 replies; 11+ messages in thread
From: Miguel Luis @ 2023-09-13 18:52 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Marc Zyngier, Oliver Upton,
James Morse, Suzuki K Poulose, Zenghui Yu, linux-arm-kernel,
linux-kernel, kvmarm
Cc: miguel.luis
Some _EL12 encodings are missing. Add them.
Signed-off-by: Miguel Luis <miguel.luis@oracle.com>
---
arch/arm64/include/asm/sysreg.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 38296579a4fd..c8b39f65660b 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -568,18 +568,29 @@
/* VHE encodings for architectural EL0/1 system registers */
#define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
+#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
+#define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3)
+#define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
+#define SYS_TRFCR_EL12 sys_reg(3, 5, 1, 2, 1)
+#define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2, 6)
#define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
#define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
#define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
+#define SYS_TCR2_EL12 sys_reg(3, 5, 2, 0, 3)
#define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
#define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
#define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
#define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
#define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
#define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
+#define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
+#define SYS_BRBCR_EL12 sys_reg(3, 5, 9, 0, 0)
+#define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0)
#define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
#define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
#define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
+#define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
+#define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
#define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
#define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
#define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
--
2.39.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/3] arm64/kvm: Fine grain _EL2 system registers list that affect nested virtualization
2023-09-13 18:52 [PATCH 0/3] Fine grain sysregs allowed to trap for nested virtualization Miguel Luis
2023-09-13 18:52 ` [PATCH 1/3] arm64: Add missing _EL12 encodings Miguel Luis
@ 2023-09-13 18:52 ` Miguel Luis
2023-09-18 9:40 ` Marc Zyngier
2023-09-13 18:52 ` [PATCH 3/3] KVM: arm64: nv: Handle all _EL02 and _EL12 registers Miguel Luis
2 siblings, 1 reply; 11+ messages in thread
From: Miguel Luis @ 2023-09-13 18:52 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Marc Zyngier, Oliver Upton,
James Morse, Suzuki K Poulose, Zenghui Yu, linux-arm-kernel,
linux-kernel, kvmarm
Cc: miguel.luis
Some _EL1 registers got included in the _EL2 ranges, which are not
affected by NV. Remove them and fine grain the ranges to exclusively
include the _EL2 ones.
Signed-off-by: Miguel Luis <miguel.luis@oracle.com>
---
arch/arm64/kvm/emulate-nested.c | 44 ++++++++++++++++++++++++++++-----
1 file changed, 38 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
index 9ced1bf0c2b7..9aa1c06abdb7 100644
--- a/arch/arm64/kvm/emulate-nested.c
+++ b/arch/arm64/kvm/emulate-nested.c
@@ -649,14 +649,46 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = {
SR_TRAP(SYS_APGAKEYHI_EL1, CGT_HCR_APK),
/* All _EL2 registers */
SR_RANGE_TRAP(sys_reg(3, 4, 0, 0, 0),
- sys_reg(3, 4, 3, 15, 7), CGT_HCR_NV),
+ sys_reg(3, 4, 4, 0, 1), CGT_HCR_NV),
/* Skip the SP_EL1 encoding... */
- SR_TRAP(SYS_SPSR_EL2, CGT_HCR_NV),
- SR_TRAP(SYS_ELR_EL2, CGT_HCR_NV),
- SR_RANGE_TRAP(sys_reg(3, 4, 4, 1, 1),
- sys_reg(3, 4, 10, 15, 7), CGT_HCR_NV),
+ SR_RANGE_TRAP(sys_reg(3, 4, 4, 3, 0),
+ sys_reg(3, 4, 10, 6, 7), CGT_HCR_NV),
+ /* skip MECID_A0_EL2, MECID_A1_EL2, MECID_P0_EL2,
+ * MECID_P1_EL2, MECIDR_EL2, VMECID_A_EL2,
+ * VMECID_P_EL2.
+ */
SR_RANGE_TRAP(sys_reg(3, 4, 12, 0, 0),
- sys_reg(3, 4, 14, 15, 7), CGT_HCR_NV),
+ sys_reg(3, 4, 12, 1, 1), CGT_HCR_NV),
+ /* ICH_AP0R<m>_EL2 */
+ SR_RANGE_TRAP(SYS_ICH_AP0R0_EL2,
+ SYS_ICH_AP0R3_EL2, CGT_HCR_NV),
+ /* ICH_AP1R<m>_EL2 */
+ SR_RANGE_TRAP(SYS_ICH_AP1R0_EL2,
+ SYS_ICH_AP1R3_EL2, CGT_HCR_NV),
+ SR_RANGE_TRAP(sys_reg(3, 4, 12, 9, 5),
+ sys_reg(3, 4, 12, 11, 7), CGT_HCR_NV),
+ /* ICH_LR<m>_EL2 */
+ SR_TRAP(SYS_ICH_LR0_EL2, CGT_HCR_NV),
+ SR_TRAP(SYS_ICH_LR1_EL2, CGT_HCR_NV),
+ SR_TRAP(SYS_ICH_LR2_EL2, CGT_HCR_NV),
+ SR_TRAP(SYS_ICH_LR3_EL2, CGT_HCR_NV),
+ SR_TRAP(SYS_ICH_LR4_EL2, CGT_HCR_NV),
+ SR_TRAP(SYS_ICH_LR5_EL2, CGT_HCR_NV),
+ SR_TRAP(SYS_ICH_LR6_EL2, CGT_HCR_NV),
+ SR_TRAP(SYS_ICH_LR7_EL2, CGT_HCR_NV),
+ SR_TRAP(SYS_ICH_LR8_EL2, CGT_HCR_NV),
+ SR_TRAP(SYS_ICH_LR9_EL2, CGT_HCR_NV),
+ SR_TRAP(SYS_ICH_LR10_EL2, CGT_HCR_NV),
+ SR_TRAP(SYS_ICH_LR11_EL2, CGT_HCR_NV),
+ SR_TRAP(SYS_ICH_LR12_EL2, CGT_HCR_NV),
+ SR_TRAP(SYS_ICH_LR13_EL2, CGT_HCR_NV),
+ SR_TRAP(SYS_ICH_LR14_EL2, CGT_HCR_NV),
+ SR_TRAP(SYS_ICH_LR15_EL2, CGT_HCR_NV),
+ SR_RANGE_TRAP(sys_reg(3, 4, 13, 0, 1),
+ sys_reg(3, 4, 13, 0, 7), CGT_HCR_NV),
+ /* skip AMEVCNTVOFF0<n>_EL2 and AMEVCNTVOFF1<n>_EL2 */
+ SR_RANGE_TRAP(sys_reg(3, 4, 14, 0, 3),
+ sys_reg(3, 4, 14, 5, 2), CGT_HCR_NV),
/* All _EL02, _EL12 registers */
SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0),
sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV),
--
2.39.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 2/3] arm64/kvm: Fine grain _EL2 system registers list that affect nested virtualization
2023-09-13 18:52 ` [PATCH 2/3] arm64/kvm: Fine grain _EL2 system registers list that affect nested virtualization Miguel Luis
@ 2023-09-18 9:40 ` Marc Zyngier
2023-09-19 14:54 ` Miguel Luis
0 siblings, 1 reply; 11+ messages in thread
From: Marc Zyngier @ 2023-09-18 9:40 UTC (permalink / raw)
To: Miguel Luis
Cc: Catalin Marinas, Will Deacon, Oliver Upton, James Morse,
Suzuki K Poulose, Zenghui Yu, linux-arm-kernel, linux-kernel,
kvmarm
Hi Miguel,
On Wed, 13 Sep 2023 19:52:07 +0100,
Miguel Luis <miguel.luis@oracle.com> wrote:
>
> Some _EL1 registers got included in the _EL2 ranges, which are not
> affected by NV. Remove them and fine grain the ranges to exclusively
> include the _EL2 ones.
>
> Signed-off-by: Miguel Luis <miguel.luis@oracle.com>
> ---
> arch/arm64/kvm/emulate-nested.c | 44 ++++++++++++++++++++++++++++-----
> 1 file changed, 38 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
> index 9ced1bf0c2b7..9aa1c06abdb7 100644
> --- a/arch/arm64/kvm/emulate-nested.c
> +++ b/arch/arm64/kvm/emulate-nested.c
> @@ -649,14 +649,46 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = {
> SR_TRAP(SYS_APGAKEYHI_EL1, CGT_HCR_APK),
> /* All _EL2 registers */
> SR_RANGE_TRAP(sys_reg(3, 4, 0, 0, 0),
> - sys_reg(3, 4, 3, 15, 7), CGT_HCR_NV),
> + sys_reg(3, 4, 4, 0, 1), CGT_HCR_NV),
It would be good if the commit message explained that you are folding
SPSR/ELR into the existing range. Also, please keep the two ends of
the ranges vertically aligned.
> /* Skip the SP_EL1 encoding... */
> - SR_TRAP(SYS_SPSR_EL2, CGT_HCR_NV),
> - SR_TRAP(SYS_ELR_EL2, CGT_HCR_NV),
> - SR_RANGE_TRAP(sys_reg(3, 4, 4, 1, 1),
> - sys_reg(3, 4, 10, 15, 7), CGT_HCR_NV),
> + SR_RANGE_TRAP(sys_reg(3, 4, 4, 3, 0),
> + sys_reg(3, 4, 10, 6, 7), CGT_HCR_NV),
> + /* skip MECID_A0_EL2, MECID_A1_EL2, MECID_P0_EL2,
> + * MECID_P1_EL2, MECIDR_EL2, VMECID_A_EL2,
> + * VMECID_P_EL2.
> + */
Please follow the kernel comment format. Also, why are you skipping
the MEC registers, but not the MPAM ones? At least indicate a
rationale for this.
> SR_RANGE_TRAP(sys_reg(3, 4, 12, 0, 0),
> - sys_reg(3, 4, 14, 15, 7), CGT_HCR_NV),
> + sys_reg(3, 4, 12, 1, 1), CGT_HCR_NV),
> + /* ICH_AP0R<m>_EL2 */
> + SR_RANGE_TRAP(SYS_ICH_AP0R0_EL2,
> + SYS_ICH_AP0R3_EL2, CGT_HCR_NV),
> + /* ICH_AP1R<m>_EL2 */
> + SR_RANGE_TRAP(SYS_ICH_AP1R0_EL2,
> + SYS_ICH_AP1R3_EL2, CGT_HCR_NV),
> + SR_RANGE_TRAP(sys_reg(3, 4, 12, 9, 5),
> + sys_reg(3, 4, 12, 11, 7), CGT_HCR_NV),
> + /* ICH_LR<m>_EL2 */
> + SR_TRAP(SYS_ICH_LR0_EL2, CGT_HCR_NV),
> + SR_TRAP(SYS_ICH_LR1_EL2, CGT_HCR_NV),
> + SR_TRAP(SYS_ICH_LR2_EL2, CGT_HCR_NV),
> + SR_TRAP(SYS_ICH_LR3_EL2, CGT_HCR_NV),
> + SR_TRAP(SYS_ICH_LR4_EL2, CGT_HCR_NV),
> + SR_TRAP(SYS_ICH_LR5_EL2, CGT_HCR_NV),
> + SR_TRAP(SYS_ICH_LR6_EL2, CGT_HCR_NV),
> + SR_TRAP(SYS_ICH_LR7_EL2, CGT_HCR_NV),
> + SR_TRAP(SYS_ICH_LR8_EL2, CGT_HCR_NV),
> + SR_TRAP(SYS_ICH_LR9_EL2, CGT_HCR_NV),
> + SR_TRAP(SYS_ICH_LR10_EL2, CGT_HCR_NV),
> + SR_TRAP(SYS_ICH_LR11_EL2, CGT_HCR_NV),
> + SR_TRAP(SYS_ICH_LR12_EL2, CGT_HCR_NV),
> + SR_TRAP(SYS_ICH_LR13_EL2, CGT_HCR_NV),
> + SR_TRAP(SYS_ICH_LR14_EL2, CGT_HCR_NV),
> + SR_TRAP(SYS_ICH_LR15_EL2, CGT_HCR_NV),
You could describe all the LRs a single range.
> + SR_RANGE_TRAP(sys_reg(3, 4, 13, 0, 1),
> + sys_reg(3, 4, 13, 0, 7), CGT_HCR_NV),
> + /* skip AMEVCNTVOFF0<n>_EL2 and AMEVCNTVOFF1<n>_EL2 */
Why?
> + SR_RANGE_TRAP(sys_reg(3, 4, 14, 0, 3),
> + sys_reg(3, 4, 14, 5, 2), CGT_HCR_NV),
> /* All _EL02, _EL12 registers */
> SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0),
> sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV),
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 2/3] arm64/kvm: Fine grain _EL2 system registers list that affect nested virtualization
2023-09-18 9:40 ` Marc Zyngier
@ 2023-09-19 14:54 ` Miguel Luis
2023-09-19 16:31 ` Marc Zyngier
0 siblings, 1 reply; 11+ messages in thread
From: Miguel Luis @ 2023-09-19 14:54 UTC (permalink / raw)
To: Marc Zyngier
Cc: Catalin Marinas, Will Deacon, Oliver Upton, James Morse,
Suzuki K Poulose, Zenghui Yu, linux-arm-kernel, linux-kernel,
kvmarm
Hi Marc,
> On 18 Sep 2023, at 09:40, Marc Zyngier <maz@kernel.org> wrote:
>
> Hi Miguel,
>
> On Wed, 13 Sep 2023 19:52:07 +0100,
> Miguel Luis <miguel.luis@oracle.com> wrote:
>>
>> Some _EL1 registers got included in the _EL2 ranges, which are not
>> affected by NV. Remove them and fine grain the ranges to exclusively
>> include the _EL2 ones.
>>
>> Signed-off-by: Miguel Luis <miguel.luis@oracle.com>
>> ---
>> arch/arm64/kvm/emulate-nested.c | 44 ++++++++++++++++++++++++++++-----
>> 1 file changed, 38 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
>> index 9ced1bf0c2b7..9aa1c06abdb7 100644
>> --- a/arch/arm64/kvm/emulate-nested.c
>> +++ b/arch/arm64/kvm/emulate-nested.c
>> @@ -649,14 +649,46 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = {
>> SR_TRAP(SYS_APGAKEYHI_EL1, CGT_HCR_APK),
>> /* All _EL2 registers */
>> SR_RANGE_TRAP(sys_reg(3, 4, 0, 0, 0),
>> - sys_reg(3, 4, 3, 15, 7), CGT_HCR_NV),
>> + sys_reg(3, 4, 4, 0, 1), CGT_HCR_NV),
>
> It would be good if the commit message explained that you are folding
> SPSR/ELR into the existing range. Also, please keep the two ends of
> the ranges vertically aligned.
>
OK.
>> /* Skip the SP_EL1 encoding... */
>> - SR_TRAP(SYS_SPSR_EL2, CGT_HCR_NV),
>> - SR_TRAP(SYS_ELR_EL2, CGT_HCR_NV),
>> - SR_RANGE_TRAP(sys_reg(3, 4, 4, 1, 1),
>> - sys_reg(3, 4, 10, 15, 7), CGT_HCR_NV),
>> + SR_RANGE_TRAP(sys_reg(3, 4, 4, 3, 0),
>> + sys_reg(3, 4, 10, 6, 7), CGT_HCR_NV),
>> + /* skip MECID_A0_EL2, MECID_A1_EL2, MECID_P0_EL2,
>> + * MECID_P1_EL2, MECIDR_EL2, VMECID_A_EL2,
>> + * VMECID_P_EL2.
>> + */
>
> Please follow the kernel comment format. Also, why are you skipping
> the MEC registers, but not the MPAM ones? At least indicate a
> rationale for this.
>
I’m not aware of any exceptions for MPAM registers, although there are for MEC
when HCR_EL2.NV2 is 0.
>> SR_RANGE_TRAP(sys_reg(3, 4, 12, 0, 0),
>> - sys_reg(3, 4, 14, 15, 7), CGT_HCR_NV),
>> + sys_reg(3, 4, 12, 1, 1), CGT_HCR_NV),
>> + /* ICH_AP0R<m>_EL2 */
>> + SR_RANGE_TRAP(SYS_ICH_AP0R0_EL2,
>> + SYS_ICH_AP0R3_EL2, CGT_HCR_NV),
>> + /* ICH_AP1R<m>_EL2 */
>> + SR_RANGE_TRAP(SYS_ICH_AP1R0_EL2,
>> + SYS_ICH_AP1R3_EL2, CGT_HCR_NV),
>> + SR_RANGE_TRAP(sys_reg(3, 4, 12, 9, 5),
>> + sys_reg(3, 4, 12, 11, 7), CGT_HCR_NV),
>> + /* ICH_LR<m>_EL2 */
>> + SR_TRAP(SYS_ICH_LR0_EL2, CGT_HCR_NV),
>> + SR_TRAP(SYS_ICH_LR1_EL2, CGT_HCR_NV),
>> + SR_TRAP(SYS_ICH_LR2_EL2, CGT_HCR_NV),
>> + SR_TRAP(SYS_ICH_LR3_EL2, CGT_HCR_NV),
>> + SR_TRAP(SYS_ICH_LR4_EL2, CGT_HCR_NV),
>> + SR_TRAP(SYS_ICH_LR5_EL2, CGT_HCR_NV),
>> + SR_TRAP(SYS_ICH_LR6_EL2, CGT_HCR_NV),
>> + SR_TRAP(SYS_ICH_LR7_EL2, CGT_HCR_NV),
>> + SR_TRAP(SYS_ICH_LR8_EL2, CGT_HCR_NV),
>> + SR_TRAP(SYS_ICH_LR9_EL2, CGT_HCR_NV),
>> + SR_TRAP(SYS_ICH_LR10_EL2, CGT_HCR_NV),
>> + SR_TRAP(SYS_ICH_LR11_EL2, CGT_HCR_NV),
>> + SR_TRAP(SYS_ICH_LR12_EL2, CGT_HCR_NV),
>> + SR_TRAP(SYS_ICH_LR13_EL2, CGT_HCR_NV),
>> + SR_TRAP(SYS_ICH_LR14_EL2, CGT_HCR_NV),
>> + SR_TRAP(SYS_ICH_LR15_EL2, CGT_HCR_NV),
>
> You could describe all the LRs a single range.
>
Should we skip the gap between LR7 - LR8 ?
>> + SR_RANGE_TRAP(sys_reg(3, 4, 13, 0, 1),
>> + sys_reg(3, 4, 13, 0, 7), CGT_HCR_NV),
>> + /* skip AMEVCNTVOFF0<n>_EL2 and AMEVCNTVOFF1<n>_EL2 */
>
> Why?
I didn’t find its definition TBH although these could use a single range.
Thanks,
Miguel
>
>> + SR_RANGE_TRAP(sys_reg(3, 4, 14, 0, 3),
>> + sys_reg(3, 4, 14, 5, 2), CGT_HCR_NV),
>> /* All _EL02, _EL12 registers */
>> SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0),
>> sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV),
>
> Thanks,
>
> M.
>
> --
> Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 2/3] arm64/kvm: Fine grain _EL2 system registers list that affect nested virtualization
2023-09-19 14:54 ` Miguel Luis
@ 2023-09-19 16:31 ` Marc Zyngier
0 siblings, 0 replies; 11+ messages in thread
From: Marc Zyngier @ 2023-09-19 16:31 UTC (permalink / raw)
To: Miguel Luis
Cc: Catalin Marinas, Will Deacon, Oliver Upton, James Morse,
Suzuki K Poulose, Zenghui Yu, linux-arm-kernel, linux-kernel,
kvmarm
On Tue, 19 Sep 2023 15:54:53 +0100,
Miguel Luis <miguel.luis@oracle.com> wrote:
>
> Hi Marc,
>
> > On 18 Sep 2023, at 09:40, Marc Zyngier <maz@kernel.org> wrote:
> >
> > Hi Miguel,
> >
> > On Wed, 13 Sep 2023 19:52:07 +0100,
> > Miguel Luis <miguel.luis@oracle.com> wrote:
> >>
> >> Some _EL1 registers got included in the _EL2 ranges, which are not
> >> affected by NV. Remove them and fine grain the ranges to exclusively
> >> include the _EL2 ones.
> >>
> >> Signed-off-by: Miguel Luis <miguel.luis@oracle.com>
> >> ---
> >> arch/arm64/kvm/emulate-nested.c | 44 ++++++++++++++++++++++++++++-----
> >> 1 file changed, 38 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
> >> index 9ced1bf0c2b7..9aa1c06abdb7 100644
> >> --- a/arch/arm64/kvm/emulate-nested.c
> >> +++ b/arch/arm64/kvm/emulate-nested.c
> >> @@ -649,14 +649,46 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = {
> >> SR_TRAP(SYS_APGAKEYHI_EL1, CGT_HCR_APK),
> >> /* All _EL2 registers */
> >> SR_RANGE_TRAP(sys_reg(3, 4, 0, 0, 0),
> >> - sys_reg(3, 4, 3, 15, 7), CGT_HCR_NV),
> >> + sys_reg(3, 4, 4, 0, 1), CGT_HCR_NV),
> >
> > It would be good if the commit message explained that you are folding
> > SPSR/ELR into the existing range. Also, please keep the two ends of
> > the ranges vertically aligned.
> >
>
> OK.
>
> >> /* Skip the SP_EL1 encoding... */
> >> - SR_TRAP(SYS_SPSR_EL2, CGT_HCR_NV),
> >> - SR_TRAP(SYS_ELR_EL2, CGT_HCR_NV),
> >> - SR_RANGE_TRAP(sys_reg(3, 4, 4, 1, 1),
> >> - sys_reg(3, 4, 10, 15, 7), CGT_HCR_NV),
> >> + SR_RANGE_TRAP(sys_reg(3, 4, 4, 3, 0),
> >> + sys_reg(3, 4, 10, 6, 7), CGT_HCR_NV),
> >> + /* skip MECID_A0_EL2, MECID_A1_EL2, MECID_P0_EL2,
> >> + * MECID_P1_EL2, MECIDR_EL2, VMECID_A_EL2,
> >> + * VMECID_P_EL2.
> >> + */
> >
> > Please follow the kernel comment format. Also, why are you skipping
> > the MEC registers, but not the MPAM ones? At least indicate a
> > rationale for this.
> >
>
> I’m not aware of any exceptions for MPAM registers, although there
> are for MEC when HCR_EL2.NV2 is 0.
Then this rationale should probably be captured here.
>
> >> SR_RANGE_TRAP(sys_reg(3, 4, 12, 0, 0),
> >> - sys_reg(3, 4, 14, 15, 7), CGT_HCR_NV),
> >> + sys_reg(3, 4, 12, 1, 1), CGT_HCR_NV),
> >> + /* ICH_AP0R<m>_EL2 */
> >> + SR_RANGE_TRAP(SYS_ICH_AP0R0_EL2,
> >> + SYS_ICH_AP0R3_EL2, CGT_HCR_NV),
> >> + /* ICH_AP1R<m>_EL2 */
> >> + SR_RANGE_TRAP(SYS_ICH_AP1R0_EL2,
> >> + SYS_ICH_AP1R3_EL2, CGT_HCR_NV),
> >> + SR_RANGE_TRAP(sys_reg(3, 4, 12, 9, 5),
> >> + sys_reg(3, 4, 12, 11, 7), CGT_HCR_NV),
> >> + /* ICH_LR<m>_EL2 */
> >> + SR_TRAP(SYS_ICH_LR0_EL2, CGT_HCR_NV),
> >> + SR_TRAP(SYS_ICH_LR1_EL2, CGT_HCR_NV),
> >> + SR_TRAP(SYS_ICH_LR2_EL2, CGT_HCR_NV),
> >> + SR_TRAP(SYS_ICH_LR3_EL2, CGT_HCR_NV),
> >> + SR_TRAP(SYS_ICH_LR4_EL2, CGT_HCR_NV),
> >> + SR_TRAP(SYS_ICH_LR5_EL2, CGT_HCR_NV),
> >> + SR_TRAP(SYS_ICH_LR6_EL2, CGT_HCR_NV),
> >> + SR_TRAP(SYS_ICH_LR7_EL2, CGT_HCR_NV),
> >> + SR_TRAP(SYS_ICH_LR8_EL2, CGT_HCR_NV),
> >> + SR_TRAP(SYS_ICH_LR9_EL2, CGT_HCR_NV),
> >> + SR_TRAP(SYS_ICH_LR10_EL2, CGT_HCR_NV),
> >> + SR_TRAP(SYS_ICH_LR11_EL2, CGT_HCR_NV),
> >> + SR_TRAP(SYS_ICH_LR12_EL2, CGT_HCR_NV),
> >> + SR_TRAP(SYS_ICH_LR13_EL2, CGT_HCR_NV),
> >> + SR_TRAP(SYS_ICH_LR14_EL2, CGT_HCR_NV),
> >> + SR_TRAP(SYS_ICH_LR15_EL2, CGT_HCR_NV),
> >
> > You could describe all the LRs a single range.
> >
>
> Should we skip the gap between LR7 - LR8 ?
Which gap? LRn n described by (3,4,12,12,n) when n is in [0-7], and
(3,4,12,13,n-8) when n is in [8-15]. These two ranges are contiguous.
>
> >> + SR_RANGE_TRAP(sys_reg(3, 4, 13, 0, 1),
> >> + sys_reg(3, 4, 13, 0, 7), CGT_HCR_NV),
> >> + /* skip AMEVCNTVOFF0<n>_EL2 and AMEVCNTVOFF1<n>_EL2 */
> >
> > Why?
>
> I didn’t find its definition TBH although these could use a single range.
D19.6.11 and following?
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 3/3] KVM: arm64: nv: Handle all _EL02 and _EL12 registers
2023-09-13 18:52 [PATCH 0/3] Fine grain sysregs allowed to trap for nested virtualization Miguel Luis
2023-09-13 18:52 ` [PATCH 1/3] arm64: Add missing _EL12 encodings Miguel Luis
2023-09-13 18:52 ` [PATCH 2/3] arm64/kvm: Fine grain _EL2 system registers list that affect nested virtualization Miguel Luis
@ 2023-09-13 18:52 ` Miguel Luis
2023-09-18 9:44 ` Marc Zyngier
2 siblings, 1 reply; 11+ messages in thread
From: Miguel Luis @ 2023-09-13 18:52 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Marc Zyngier, Oliver Upton,
James Morse, Suzuki K Poulose, Zenghui Yu, linux-arm-kernel,
linux-kernel, kvmarm
Cc: miguel.luis
Specify both _EL02 and _EL12 system registers.
Signed-off-by: Miguel Luis <miguel.luis@oracle.com>
---
arch/arm64/kvm/emulate-nested.c | 35 +++++++++++++++++++++++++++++----
1 file changed, 31 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
index 9aa1c06abdb7..957afd97e488 100644
--- a/arch/arm64/kvm/emulate-nested.c
+++ b/arch/arm64/kvm/emulate-nested.c
@@ -690,10 +690,37 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = {
SR_RANGE_TRAP(sys_reg(3, 4, 14, 0, 3),
sys_reg(3, 4, 14, 5, 2), CGT_HCR_NV),
/* All _EL02, _EL12 registers */
- SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0),
- sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV),
- SR_RANGE_TRAP(sys_reg(3, 5, 12, 0, 0),
- sys_reg(3, 5, 14, 15, 7), CGT_HCR_NV),
+ SR_TRAP(SYS_SCTLR_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_CPACR_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_SCTLR2_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_ZCR_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_TRFCR_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_SMCR_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_TTBR0_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_TTBR1_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_TCR_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_TCR2_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_SPSR_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_ELR_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_AFSR0_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_AFSR1_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_ESR_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_TFSR_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_FAR_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_BRBCR_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_PMSCR_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_MAIR_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_AMAIR_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_VBAR_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_CONTEXTIDR_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_SCXTNUM_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_CNTKCTL_EL12, CGT_HCR_NV),
+ SR_TRAP(SYS_CNTP_TVAL_EL02, CGT_HCR_NV),
+ SR_TRAP(SYS_CNTP_CTL_EL02, CGT_HCR_NV),
+ SR_TRAP(SYS_CNTP_CVAL_EL02, CGT_HCR_NV),
+ SR_TRAP(SYS_CNTV_TVAL_EL02, CGT_HCR_NV),
+ SR_TRAP(SYS_CNTV_CTL_EL02, CGT_HCR_NV),
+ SR_TRAP(SYS_CNTV_CVAL_EL02, CGT_HCR_NV),
SR_TRAP(OP_AT_S1E2R, CGT_HCR_NV),
SR_TRAP(OP_AT_S1E2W, CGT_HCR_NV),
SR_TRAP(OP_AT_S12E1R, CGT_HCR_NV),
--
2.39.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 3/3] KVM: arm64: nv: Handle all _EL02 and _EL12 registers
2023-09-13 18:52 ` [PATCH 3/3] KVM: arm64: nv: Handle all _EL02 and _EL12 registers Miguel Luis
@ 2023-09-18 9:44 ` Marc Zyngier
2023-09-18 12:41 ` Miguel Luis
0 siblings, 1 reply; 11+ messages in thread
From: Marc Zyngier @ 2023-09-18 9:44 UTC (permalink / raw)
To: Miguel Luis
Cc: Catalin Marinas, Will Deacon, Oliver Upton, James Morse,
Suzuki K Poulose, Zenghui Yu, linux-arm-kernel, linux-kernel,
kvmarm
On Wed, 13 Sep 2023 19:52:08 +0100,
Miguel Luis <miguel.luis@oracle.com> wrote:
>
> Specify both _EL02 and _EL12 system registers.
>
> Signed-off-by: Miguel Luis <miguel.luis@oracle.com>
> ---
> arch/arm64/kvm/emulate-nested.c | 35 +++++++++++++++++++++++++++++----
> 1 file changed, 31 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
> index 9aa1c06abdb7..957afd97e488 100644
> --- a/arch/arm64/kvm/emulate-nested.c
> +++ b/arch/arm64/kvm/emulate-nested.c
> @@ -690,10 +690,37 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = {
> SR_RANGE_TRAP(sys_reg(3, 4, 14, 0, 3),
> sys_reg(3, 4, 14, 5, 2), CGT_HCR_NV),
> /* All _EL02, _EL12 registers */
> - SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0),
> - sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV),
> - SR_RANGE_TRAP(sys_reg(3, 5, 12, 0, 0),
> - sys_reg(3, 5, 14, 15, 7), CGT_HCR_NV),
> + SR_TRAP(SYS_SCTLR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_CPACR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_SCTLR2_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_ZCR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_TRFCR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_SMCR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_TTBR0_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_TTBR1_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_TCR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_TCR2_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_SPSR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_ELR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_AFSR0_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_AFSR1_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_ESR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_TFSR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_FAR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_BRBCR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_PMSCR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_MAIR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_AMAIR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_VBAR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_CONTEXTIDR_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_SCXTNUM_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_CNTKCTL_EL12, CGT_HCR_NV),
> + SR_TRAP(SYS_CNTP_TVAL_EL02, CGT_HCR_NV),
> + SR_TRAP(SYS_CNTP_CTL_EL02, CGT_HCR_NV),
> + SR_TRAP(SYS_CNTP_CVAL_EL02, CGT_HCR_NV),
> + SR_TRAP(SYS_CNTV_TVAL_EL02, CGT_HCR_NV),
> + SR_TRAP(SYS_CNTV_CTL_EL02, CGT_HCR_NV),
> + SR_TRAP(SYS_CNTV_CVAL_EL02, CGT_HCR_NV),
> SR_TRAP(OP_AT_S1E2R, CGT_HCR_NV),
> SR_TRAP(OP_AT_S1E2W, CGT_HCR_NV),
> SR_TRAP(OP_AT_S12E1R, CGT_HCR_NV),
While I could see the problem with the EL2 registers, I'm not
convinced by this patch. Is there an actual case for non _EL02, non
_EL12 registers that are included in the two ranges above?
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 3/3] KVM: arm64: nv: Handle all _EL02 and _EL12 registers
2023-09-18 9:44 ` Marc Zyngier
@ 2023-09-18 12:41 ` Miguel Luis
2023-09-18 12:56 ` Marc Zyngier
0 siblings, 1 reply; 11+ messages in thread
From: Miguel Luis @ 2023-09-18 12:41 UTC (permalink / raw)
To: Marc Zyngier
Cc: Catalin Marinas, Will Deacon, Oliver Upton, James Morse,
Suzuki K Poulose, Zenghui Yu, linux-arm-kernel, linux-kernel,
kvmarm
Hi Marc,
> On 18 Sep 2023, at 09:44, Marc Zyngier <maz@kernel.org> wrote:
>
> On Wed, 13 Sep 2023 19:52:08 +0100,
> Miguel Luis <miguel.luis@oracle.com> wrote:
>>
>> Specify both _EL02 and _EL12 system registers.
>>
>> Signed-off-by: Miguel Luis <miguel.luis@oracle.com>
>> ---
>> arch/arm64/kvm/emulate-nested.c | 35 +++++++++++++++++++++++++++++----
>> 1 file changed, 31 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
>> index 9aa1c06abdb7..957afd97e488 100644
>> --- a/arch/arm64/kvm/emulate-nested.c
>> +++ b/arch/arm64/kvm/emulate-nested.c
>> @@ -690,10 +690,37 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = {
>> SR_RANGE_TRAP(sys_reg(3, 4, 14, 0, 3),
>> sys_reg(3, 4, 14, 5, 2), CGT_HCR_NV),
>> /* All _EL02, _EL12 registers */
>> - SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0),
>> - sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV),
>> - SR_RANGE_TRAP(sys_reg(3, 5, 12, 0, 0),
>> - sys_reg(3, 5, 14, 15, 7), CGT_HCR_NV),
>> + SR_TRAP(SYS_SCTLR_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_CPACR_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_SCTLR2_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_ZCR_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_TRFCR_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_SMCR_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_TTBR0_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_TTBR1_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_TCR_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_TCR2_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_SPSR_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_ELR_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_AFSR0_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_AFSR1_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_ESR_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_TFSR_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_FAR_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_BRBCR_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_PMSCR_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_MAIR_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_AMAIR_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_VBAR_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_CONTEXTIDR_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_SCXTNUM_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_CNTKCTL_EL12, CGT_HCR_NV),
>> + SR_TRAP(SYS_CNTP_TVAL_EL02, CGT_HCR_NV),
>> + SR_TRAP(SYS_CNTP_CTL_EL02, CGT_HCR_NV),
>> + SR_TRAP(SYS_CNTP_CVAL_EL02, CGT_HCR_NV),
>> + SR_TRAP(SYS_CNTV_TVAL_EL02, CGT_HCR_NV),
>> + SR_TRAP(SYS_CNTV_CTL_EL02, CGT_HCR_NV),
>> + SR_TRAP(SYS_CNTV_CVAL_EL02, CGT_HCR_NV),
>> SR_TRAP(OP_AT_S1E2R, CGT_HCR_NV),
>> SR_TRAP(OP_AT_S1E2W, CGT_HCR_NV),
>> SR_TRAP(OP_AT_S12E1R, CGT_HCR_NV),
>
> While I could see the problem with the EL2 registers, I'm not
> convinced by this patch. Is there an actual case for non _EL02, non
> _EL12 registers that are included in the two ranges above?
>
Having DDI0487Ja as reference, there is none. It is not clear to me having two
separate ranges. If it is to cover _EL02 and _EL12 ranges separately then the
second range is covering both aliases. I couldn't find the reason for these
aliases start and end other than SYS_SCTLR_EL12 and SYS_CNTV_CVAL_EL02,
respectively.
Thanks
Miguel
> Thanks,
>
> M.
>
> --
> Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 3/3] KVM: arm64: nv: Handle all _EL02 and _EL12 registers
2023-09-18 12:41 ` Miguel Luis
@ 2023-09-18 12:56 ` Marc Zyngier
2023-09-25 11:04 ` Miguel Luis
0 siblings, 1 reply; 11+ messages in thread
From: Marc Zyngier @ 2023-09-18 12:56 UTC (permalink / raw)
To: Miguel Luis
Cc: Catalin Marinas, Will Deacon, Oliver Upton, James Morse,
Suzuki K Poulose, Zenghui Yu, linux-arm-kernel, linux-kernel,
kvmarm
On Mon, 18 Sep 2023 13:41:45 +0100,
Miguel Luis <miguel.luis@oracle.com> wrote:
>
> Hi Marc,
>
> > On 18 Sep 2023, at 09:44, Marc Zyngier <maz@kernel.org> wrote:
> >
> > On Wed, 13 Sep 2023 19:52:08 +0100,
> > Miguel Luis <miguel.luis@oracle.com> wrote:
> >>
> >> Specify both _EL02 and _EL12 system registers.
> >>
> >> Signed-off-by: Miguel Luis <miguel.luis@oracle.com>
> >> ---
> >> arch/arm64/kvm/emulate-nested.c | 35 +++++++++++++++++++++++++++++----
> >> 1 file changed, 31 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
> >> index 9aa1c06abdb7..957afd97e488 100644
> >> --- a/arch/arm64/kvm/emulate-nested.c
> >> +++ b/arch/arm64/kvm/emulate-nested.c
> >> @@ -690,10 +690,37 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = {
> >> SR_RANGE_TRAP(sys_reg(3, 4, 14, 0, 3),
> >> sys_reg(3, 4, 14, 5, 2), CGT_HCR_NV),
> >> /* All _EL02, _EL12 registers */
> >> - SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0),
> >> - sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV),
> >> - SR_RANGE_TRAP(sys_reg(3, 5, 12, 0, 0),
> >> - sys_reg(3, 5, 14, 15, 7), CGT_HCR_NV),
> >> + SR_TRAP(SYS_SCTLR_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_CPACR_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_SCTLR2_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_ZCR_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_TRFCR_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_SMCR_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_TTBR0_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_TTBR1_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_TCR_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_TCR2_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_SPSR_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_ELR_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_AFSR0_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_AFSR1_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_ESR_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_TFSR_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_FAR_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_BRBCR_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_PMSCR_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_MAIR_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_AMAIR_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_VBAR_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_CONTEXTIDR_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_SCXTNUM_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_CNTKCTL_EL12, CGT_HCR_NV),
> >> + SR_TRAP(SYS_CNTP_TVAL_EL02, CGT_HCR_NV),
> >> + SR_TRAP(SYS_CNTP_CTL_EL02, CGT_HCR_NV),
> >> + SR_TRAP(SYS_CNTP_CVAL_EL02, CGT_HCR_NV),
> >> + SR_TRAP(SYS_CNTV_TVAL_EL02, CGT_HCR_NV),
> >> + SR_TRAP(SYS_CNTV_CTL_EL02, CGT_HCR_NV),
> >> + SR_TRAP(SYS_CNTV_CVAL_EL02, CGT_HCR_NV),
> >> SR_TRAP(OP_AT_S1E2R, CGT_HCR_NV),
> >> SR_TRAP(OP_AT_S1E2W, CGT_HCR_NV),
> >> SR_TRAP(OP_AT_S12E1R, CGT_HCR_NV),
> >
> > While I could see the problem with the EL2 registers, I'm not
> > convinced by this patch. Is there an actual case for non _EL02, non
> > _EL12 registers that are included in the two ranges above?
> >
>
> Having DDI0487Ja as reference, there is none. It is not clear to me having two
> separate ranges. If it is to cover _EL02 and _EL12 ranges separately then the
> second range is covering both aliases. I couldn't find the reason for these
> aliases start and end other than SYS_SCTLR_EL12 and SYS_CNTV_CVAL_EL02,
> respectively.
The reason we have two ranges is to explicitly exclude the IMPDEF
range, which is trapped by HCR_EL2.TIDCP:
SR_RANGE_TRAP(sys_reg(3, 5, 11, 0, 0),
sys_reg(3, 5, 11, 15, 7), CGT_HCR_TIDCP),
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 3/3] KVM: arm64: nv: Handle all _EL02 and _EL12 registers
2023-09-18 12:56 ` Marc Zyngier
@ 2023-09-25 11:04 ` Miguel Luis
0 siblings, 0 replies; 11+ messages in thread
From: Miguel Luis @ 2023-09-25 11:04 UTC (permalink / raw)
To: Marc Zyngier
Cc: Catalin Marinas, Will Deacon, Oliver Upton, James Morse,
Suzuki K Poulose, Zenghui Yu, linux-arm-kernel, linux-kernel,
kvmarm
Hi Marc,
> On 18 Sep 2023, at 12:56, Marc Zyngier <maz@kernel.org> wrote:
>
> On Mon, 18 Sep 2023 13:41:45 +0100,
> Miguel Luis <miguel.luis@oracle.com> wrote:
>>
>> Hi Marc,
>>
>>> On 18 Sep 2023, at 09:44, Marc Zyngier <maz@kernel.org> wrote:
>>>
>>> On Wed, 13 Sep 2023 19:52:08 +0100,
>>> Miguel Luis <miguel.luis@oracle.com> wrote:
>>>>
>>>> Specify both _EL02 and _EL12 system registers.
>>>>
>>>> Signed-off-by: Miguel Luis <miguel.luis@oracle.com>
>>>> ---
>>>> arch/arm64/kvm/emulate-nested.c | 35 +++++++++++++++++++++++++++++----
>>>> 1 file changed, 31 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
>>>> index 9aa1c06abdb7..957afd97e488 100644
>>>> --- a/arch/arm64/kvm/emulate-nested.c
>>>> +++ b/arch/arm64/kvm/emulate-nested.c
>>>> @@ -690,10 +690,37 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = {
>>>> SR_RANGE_TRAP(sys_reg(3, 4, 14, 0, 3),
>>>> sys_reg(3, 4, 14, 5, 2), CGT_HCR_NV),
>>>> /* All _EL02, _EL12 registers */
>>>> - SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0),
>>>> - sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV),
>>>> - SR_RANGE_TRAP(sys_reg(3, 5, 12, 0, 0),
>>>> - sys_reg(3, 5, 14, 15, 7), CGT_HCR_NV),
>>>> + SR_TRAP(SYS_SCTLR_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_CPACR_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_SCTLR2_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_ZCR_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_TRFCR_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_SMCR_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_TTBR0_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_TTBR1_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_TCR_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_TCR2_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_SPSR_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_ELR_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_AFSR0_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_AFSR1_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_ESR_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_TFSR_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_FAR_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_BRBCR_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_PMSCR_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_MAIR_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_AMAIR_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_VBAR_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_CONTEXTIDR_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_SCXTNUM_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_CNTKCTL_EL12, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_CNTP_TVAL_EL02, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_CNTP_CTL_EL02, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_CNTP_CVAL_EL02, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_CNTV_TVAL_EL02, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_CNTV_CTL_EL02, CGT_HCR_NV),
>>>> + SR_TRAP(SYS_CNTV_CVAL_EL02, CGT_HCR_NV),
>>>> SR_TRAP(OP_AT_S1E2R, CGT_HCR_NV),
>>>> SR_TRAP(OP_AT_S1E2W, CGT_HCR_NV),
>>>> SR_TRAP(OP_AT_S12E1R, CGT_HCR_NV),
>>>
>>> While I could see the problem with the EL2 registers, I'm not
>>> convinced by this patch. Is there an actual case for non _EL02, non
>>> _EL12 registers that are included in the two ranges above?
>>>
>>
>> Having DDI0487Ja as reference, there is none. It is not clear to me having two
>> separate ranges. If it is to cover _EL02 and _EL12 ranges separately then the
>> second range is covering both aliases. I couldn't find the reason for these
>> aliases start and end other than SYS_SCTLR_EL12 and SYS_CNTV_CVAL_EL02,
>> respectively.
>
> The reason we have two ranges is to explicitly exclude the IMPDEF
> range, which is trapped by HCR_EL2.TIDCP:
>
> SR_RANGE_TRAP(sys_reg(3, 5, 11, 0, 0),
> sys_reg(3, 5, 11, 15, 7), CGT_HCR_TIDCP),
>
OK. I’m dropping this patch from the series.
The current approach satisfies the purpose.
Thanks
Miguel
> Thanks,
>
> M.
>
> --
> Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 11+ messages in thread