* [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes @ 2020-01-28 12:39 Anshuman Khandual 2020-01-28 12:39 ` [PATCH 1/6] arm64/cpufeature: Introduce ID_PFR2 CPU register Anshuman Khandual ` (2 more replies) 0 siblings, 3 replies; 12+ messages in thread From: Anshuman Khandual @ 2020-01-28 12:39 UTC (permalink / raw) To: linux-arm-kernel Cc: Catalin Marinas, Anshuman Khandual, linux-kernel, Marc Zyngier, Will Deacon, kvmarm This series is primarily motivated from an adhoc list from Mark Rutland during our ID_ISAR6 discussion [1]. Besides, it also includes a patch which does macro replacement for various open bits shift encodings in various CPU ID registers. This series is based on linux-next 20200124. [1] https://patchwork.kernel.org/patch/11287805/ Is there anything else apart from these changes which can be accommodated in this series, please do let me know. Thank you. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Marc Zyngier <maz@kernel.org> Cc: James Morse <james.morse@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: kvmarm@lists.cs.columbia.edu Cc: linux-kernel@vger.kernel.org Anshuman Khandual (6): arm64/cpufeature: Introduce ID_PFR2 CPU register arm64/cpufeature: Add DIT and CSV2 feature bits in ID_PFR0 register arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register arm64/cpufeature: Define an explicit ftr_id_isar0[] for ID_ISAR0 register arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register arm64/cpufeature: Replace all open bits shift encodings with macros arch/arm64/include/asm/cpu.h | 1 + arch/arm64/include/asm/sysreg.h | 51 +++++++++++++++++++ arch/arm64/kernel/cpufeature.c | 87 ++++++++++++++++++++++----------- arch/arm64/kernel/cpuinfo.c | 1 + arch/arm64/kvm/sys_regs.c | 2 +- 5 files changed, 112 insertions(+), 30 deletions(-) -- 2.20.1 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/6] arm64/cpufeature: Introduce ID_PFR2 CPU register 2020-01-28 12:39 [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes Anshuman Khandual @ 2020-01-28 12:39 ` Anshuman Khandual 2020-03-20 18:03 ` Suzuki K Poulose 2020-04-09 12:54 ` Will Deacon 2020-02-14 4:23 ` [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes Anshuman Khandual 2020-04-06 17:09 ` Will Deacon 2 siblings, 2 replies; 12+ messages in thread From: Anshuman Khandual @ 2020-01-28 12:39 UTC (permalink / raw) To: linux-arm-kernel Cc: Catalin Marinas, Anshuman Khandual, linux-kernel, Marc Zyngier, Will Deacon, kvmarm This adds basic building blocks required for ID_PFR2 CPU register which provides information about the AArch32 programmers model which must be interpreted along with ID_PFR0 and ID_PFR1 CPU registers. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Marc Zyngier <maz@kernel.org> Cc: James Morse <james.morse@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: kvmarm@lists.cs.columbia.edu Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> --- arch/arm64/include/asm/cpu.h | 1 + arch/arm64/include/asm/sysreg.h | 4 ++++ arch/arm64/kernel/cpufeature.c | 11 +++++++++++ arch/arm64/kernel/cpuinfo.c | 1 + arch/arm64/kvm/sys_regs.c | 2 +- 5 files changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h index b4a40535a3d8..464e828a994d 100644 --- a/arch/arm64/include/asm/cpu.h +++ b/arch/arm64/include/asm/cpu.h @@ -46,6 +46,7 @@ struct cpuinfo_arm64 { u32 reg_id_mmfr3; u32 reg_id_pfr0; u32 reg_id_pfr1; + u32 reg_id_pfr2; u32 reg_mvfr0; u32 reg_mvfr1; diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index b91570ff9db1..054aab7ebf1b 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -151,6 +151,7 @@ #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) +#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) @@ -717,6 +718,9 @@ #define ID_ISAR6_DP_SHIFT 4 #define ID_ISAR6_JSCVT_SHIFT 0 +#define ID_PFR2_SSBS_SHIFT 4 +#define ID_PFR2_CSV3_SHIFT 0 + #define MVFR0_FPROUND_SHIFT 28 #define MVFR0_FPSHVEC_SHIFT 24 #define MVFR0_FPSQRT_SHIFT 20 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 0b6715625cf6..c1e837fc8f97 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -348,6 +348,12 @@ static const struct arm64_ftr_bits ftr_id_pfr0[] = { ARM64_FTR_END, }; +static const struct arm64_ftr_bits ftr_id_pfr2[] = { + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0), + ARM64_FTR_END, +}; + static const struct arm64_ftr_bits ftr_id_dfr0[] = { ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */ @@ -429,6 +435,7 @@ static const struct __ftr_reg_entry { ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), + ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), /* Op1 = 0, CRn = 0, CRm = 4 */ ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), @@ -635,6 +642,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); + init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); @@ -802,6 +810,8 @@ void update_cpu_features(int cpu, info->reg_id_pfr0, boot->reg_id_pfr0); taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, info->reg_id_pfr1, boot->reg_id_pfr1); + taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, + info->reg_id_pfr2, boot->reg_id_pfr2); taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, info->reg_mvfr0, boot->reg_mvfr0); taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, @@ -851,6 +861,7 @@ static u64 __read_sysreg_by_encoding(u32 sys_id) switch (sys_id) { read_sysreg_case(SYS_ID_PFR0_EL1); read_sysreg_case(SYS_ID_PFR1_EL1); + read_sysreg_case(SYS_ID_PFR2_EL1); read_sysreg_case(SYS_ID_DFR0_EL1); read_sysreg_case(SYS_ID_MMFR0_EL1); read_sysreg_case(SYS_ID_MMFR1_EL1); diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 86136075ae41..cb79b083f97f 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -375,6 +375,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1); info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1); info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1); + info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1); info->reg_mvfr0 = read_cpuid(MVFR0_EL1); info->reg_mvfr1 = read_cpuid(MVFR1_EL1); diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 3e909b117f0c..e266219a35ff 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1431,7 +1431,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_SANITISED(MVFR1_EL1), ID_SANITISED(MVFR2_EL1), ID_UNALLOCATED(3,3), - ID_UNALLOCATED(3,4), + ID_SANITISED(ID_PFR2_EL1), ID_UNALLOCATED(3,5), ID_UNALLOCATED(3,6), ID_UNALLOCATED(3,7), -- 2.20.1 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 1/6] arm64/cpufeature: Introduce ID_PFR2 CPU register 2020-01-28 12:39 ` [PATCH 1/6] arm64/cpufeature: Introduce ID_PFR2 CPU register Anshuman Khandual @ 2020-03-20 18:03 ` Suzuki K Poulose 2020-04-09 12:54 ` Will Deacon 1 sibling, 0 replies; 12+ messages in thread From: Suzuki K Poulose @ 2020-03-20 18:03 UTC (permalink / raw) To: anshuman.khandual, linux-arm-kernel Cc: catalin.marinas, linux-kernel, maz, will, kvmarm On 01/28/2020 12:39 PM, Anshuman Khandual wrote: > This adds basic building blocks required for ID_PFR2 CPU register which > provides information about the AArch32 programmers model which must be > interpreted along with ID_PFR0 and ID_PFR1 CPU registers. > > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Marc Zyngier <maz@kernel.org> > Cc: James Morse <james.morse@arm.com> > Cc: Suzuki K Poulose <suzuki.poulose@arm.com> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: kvmarm@lists.cs.columbia.edu > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Sorry for the delay ! Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/6] arm64/cpufeature: Introduce ID_PFR2 CPU register 2020-01-28 12:39 ` [PATCH 1/6] arm64/cpufeature: Introduce ID_PFR2 CPU register Anshuman Khandual 2020-03-20 18:03 ` Suzuki K Poulose @ 2020-04-09 12:54 ` Will Deacon 2020-04-13 3:32 ` Anshuman Khandual 1 sibling, 1 reply; 12+ messages in thread From: Will Deacon @ 2020-04-09 12:54 UTC (permalink / raw) To: Anshuman Khandual Cc: Catalin Marinas, linux-kernel, Marc Zyngier, kvmarm, linux-arm-kernel On Tue, Jan 28, 2020 at 06:09:04PM +0530, Anshuman Khandual wrote: > This adds basic building blocks required for ID_PFR2 CPU register which > provides information about the AArch32 programmers model which must be > interpreted along with ID_PFR0 and ID_PFR1 CPU registers. > > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Marc Zyngier <maz@kernel.org> > Cc: James Morse <james.morse@arm.com> > Cc: Suzuki K Poulose <suzuki.poulose@arm.com> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: kvmarm@lists.cs.columbia.edu > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> > --- > arch/arm64/include/asm/cpu.h | 1 + > arch/arm64/include/asm/sysreg.h | 4 ++++ > arch/arm64/kernel/cpufeature.c | 11 +++++++++++ > arch/arm64/kernel/cpuinfo.c | 1 + > arch/arm64/kvm/sys_regs.c | 2 +- > 5 files changed, 18 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h > index b4a40535a3d8..464e828a994d 100644 > --- a/arch/arm64/include/asm/cpu.h > +++ b/arch/arm64/include/asm/cpu.h > @@ -46,6 +46,7 @@ struct cpuinfo_arm64 { > u32 reg_id_mmfr3; > u32 reg_id_pfr0; > u32 reg_id_pfr1; > + u32 reg_id_pfr2; > > u32 reg_mvfr0; > u32 reg_mvfr1; > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index b91570ff9db1..054aab7ebf1b 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -151,6 +151,7 @@ > #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) > #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) > #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) > +#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) > > #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) > #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) > @@ -717,6 +718,9 @@ > #define ID_ISAR6_DP_SHIFT 4 > #define ID_ISAR6_JSCVT_SHIFT 0 > > +#define ID_PFR2_SSBS_SHIFT 4 > +#define ID_PFR2_CSV3_SHIFT 0 > + > #define MVFR0_FPROUND_SHIFT 28 > #define MVFR0_FPSHVEC_SHIFT 24 > #define MVFR0_FPSQRT_SHIFT 20 > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 0b6715625cf6..c1e837fc8f97 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -348,6 +348,12 @@ static const struct arm64_ftr_bits ftr_id_pfr0[] = { > ARM64_FTR_END, > }; > > +static const struct arm64_ftr_bits ftr_id_pfr2[] = { > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0), Why is CSV3 strict here, but not when we see if in aa64pfr0? I think it should be non-strict in both cases. Will _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/6] arm64/cpufeature: Introduce ID_PFR2 CPU register 2020-04-09 12:54 ` Will Deacon @ 2020-04-13 3:32 ` Anshuman Khandual 0 siblings, 0 replies; 12+ messages in thread From: Anshuman Khandual @ 2020-04-13 3:32 UTC (permalink / raw) To: Will Deacon Cc: Catalin Marinas, linux-kernel, Marc Zyngier, kvmarm, linux-arm-kernel On 04/09/2020 06:24 PM, Will Deacon wrote: > On Tue, Jan 28, 2020 at 06:09:04PM +0530, Anshuman Khandual wrote: >> This adds basic building blocks required for ID_PFR2 CPU register which >> provides information about the AArch32 programmers model which must be >> interpreted along with ID_PFR0 and ID_PFR1 CPU registers. >> >> Cc: Catalin Marinas <catalin.marinas@arm.com> >> Cc: Will Deacon <will@kernel.org> >> Cc: Marc Zyngier <maz@kernel.org> >> Cc: James Morse <james.morse@arm.com> >> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> >> Cc: Mark Rutland <mark.rutland@arm.com> >> Cc: kvmarm@lists.cs.columbia.edu >> Cc: linux-kernel@vger.kernel.org >> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> >> --- >> arch/arm64/include/asm/cpu.h | 1 + >> arch/arm64/include/asm/sysreg.h | 4 ++++ >> arch/arm64/kernel/cpufeature.c | 11 +++++++++++ >> arch/arm64/kernel/cpuinfo.c | 1 + >> arch/arm64/kvm/sys_regs.c | 2 +- >> 5 files changed, 18 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h >> index b4a40535a3d8..464e828a994d 100644 >> --- a/arch/arm64/include/asm/cpu.h >> +++ b/arch/arm64/include/asm/cpu.h >> @@ -46,6 +46,7 @@ struct cpuinfo_arm64 { >> u32 reg_id_mmfr3; >> u32 reg_id_pfr0; >> u32 reg_id_pfr1; >> + u32 reg_id_pfr2; >> >> u32 reg_mvfr0; >> u32 reg_mvfr1; >> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h >> index b91570ff9db1..054aab7ebf1b 100644 >> --- a/arch/arm64/include/asm/sysreg.h >> +++ b/arch/arm64/include/asm/sysreg.h >> @@ -151,6 +151,7 @@ >> #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) >> #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) >> #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) >> +#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) >> >> #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) >> #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) >> @@ -717,6 +718,9 @@ >> #define ID_ISAR6_DP_SHIFT 4 >> #define ID_ISAR6_JSCVT_SHIFT 0 >> >> +#define ID_PFR2_SSBS_SHIFT 4 >> +#define ID_PFR2_CSV3_SHIFT 0 >> + >> #define MVFR0_FPROUND_SHIFT 28 >> #define MVFR0_FPSHVEC_SHIFT 24 >> #define MVFR0_FPSQRT_SHIFT 20 >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c >> index 0b6715625cf6..c1e837fc8f97 100644 >> --- a/arch/arm64/kernel/cpufeature.c >> +++ b/arch/arm64/kernel/cpufeature.c >> @@ -348,6 +348,12 @@ static const struct arm64_ftr_bits ftr_id_pfr0[] = { >> ARM64_FTR_END, >> }; >> >> +static const struct arm64_ftr_bits ftr_id_pfr2[] = { >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0), > > Why is CSV3 strict here, but not when we see if in aa64pfr0? I think it > should be non-strict in both cases. Sure, will do. > > Will > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes 2020-01-28 12:39 [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes Anshuman Khandual 2020-01-28 12:39 ` [PATCH 1/6] arm64/cpufeature: Introduce ID_PFR2 CPU register Anshuman Khandual @ 2020-02-14 4:23 ` Anshuman Khandual 2020-02-14 15:58 ` Peter Maydell 2020-03-20 18:49 ` Suzuki K Poulose 2020-04-06 17:09 ` Will Deacon 2 siblings, 2 replies; 12+ messages in thread From: Anshuman Khandual @ 2020-02-14 4:23 UTC (permalink / raw) To: linux-arm-kernel Cc: Catalin Marinas, linux-kernel, Marc Zyngier, Will Deacon, kvmarm On 01/28/2020 06:09 PM, Anshuman Khandual wrote: > This series is primarily motivated from an adhoc list from Mark Rutland > during our ID_ISAR6 discussion [1]. Besides, it also includes a patch > which does macro replacement for various open bits shift encodings in > various CPU ID registers. This series is based on linux-next 20200124. > > [1] https://patchwork.kernel.org/patch/11287805/ > > Is there anything else apart from these changes which can be accommodated > in this series, please do let me know. Thank you. Just a gentle ping. Any updates, does this series looks okay ? Is there anything else related to CPU ID register feature bits, which can be added up here. FWIW, the series still applies on v5.6-rc1. > > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Marc Zyngier <maz@kernel.org> > Cc: James Morse <james.morse@arm.com> > Cc: Suzuki K Poulose <suzuki.poulose@arm.com> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: kvmarm@lists.cs.columbia.edu > Cc: linux-kernel@vger.kernel.org > > Anshuman Khandual (6): > arm64/cpufeature: Introduce ID_PFR2 CPU register > arm64/cpufeature: Add DIT and CSV2 feature bits in ID_PFR0 register > arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register > arm64/cpufeature: Define an explicit ftr_id_isar0[] for ID_ISAR0 register > arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register > arm64/cpufeature: Replace all open bits shift encodings with macros > > arch/arm64/include/asm/cpu.h | 1 + > arch/arm64/include/asm/sysreg.h | 51 +++++++++++++++++++ > arch/arm64/kernel/cpufeature.c | 87 ++++++++++++++++++++++----------- > arch/arm64/kernel/cpuinfo.c | 1 + > arch/arm64/kvm/sys_regs.c | 2 +- > 5 files changed, 112 insertions(+), 30 deletions(-) > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes 2020-02-14 4:23 ` [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes Anshuman Khandual @ 2020-02-14 15:58 ` Peter Maydell 2020-04-02 2:33 ` Anshuman Khandual 2020-03-20 18:49 ` Suzuki K Poulose 1 sibling, 1 reply; 12+ messages in thread From: Peter Maydell @ 2020-02-14 15:58 UTC (permalink / raw) To: Anshuman Khandual Cc: Catalin Marinas, lkml - Kernel Mailing List, Marc Zyngier, Will Deacon, kvmarm, arm-mail-list On Fri, 14 Feb 2020 at 04:23, Anshuman Khandual <anshuman.khandual@arm.com> wrote: > > > > On 01/28/2020 06:09 PM, Anshuman Khandual wrote: > > This series is primarily motivated from an adhoc list from Mark Rutland > > during our ID_ISAR6 discussion [1]. Besides, it also includes a patch > > which does macro replacement for various open bits shift encodings in > > various CPU ID registers. This series is based on linux-next 20200124. > > > > [1] https://patchwork.kernel.org/patch/11287805/ > > > > Is there anything else apart from these changes which can be accommodated > > in this series, please do let me know. Thank you. > > Just a gentle ping. Any updates, does this series looks okay ? Is there > anything else related to CPU ID register feature bits, which can be added > up here. FWIW, the series still applies on v5.6-rc1. I just ran into some "32-bit KVM doesn't expose all the ID registers to userspace via the ONE_REG API" issues today. I don't know if they'd be reasonable as something to include in this patchset or if they're unrelated. Anyway, missing stuff I have noticed specifically: * MVFR2 * ID_MMFR4 * ID_ISAR6 More generally I would have expected all these 32-bit registers to exist and read-as-zero for the purpose of the ONE_REG APIs, because that's what the architecture says is supposed to happen and it means we have compatibility and QEMU doesn't gradually build up lots of "kernel doesn't support this yet" conditionals... I think we get this right for 64-bit KVM, but can we do it for 32-bit as well? thanks -- PMM _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes 2020-02-14 15:58 ` Peter Maydell @ 2020-04-02 2:33 ` Anshuman Khandual 0 siblings, 0 replies; 12+ messages in thread From: Anshuman Khandual @ 2020-04-02 2:33 UTC (permalink / raw) To: Peter Maydell Cc: Catalin Marinas, lkml - Kernel Mailing List, Marc Zyngier, Will Deacon, kvmarm, arm-mail-list On 02/14/2020 09:28 PM, Peter Maydell wrote: > On Fri, 14 Feb 2020 at 04:23, Anshuman Khandual > <anshuman.khandual@arm.com> wrote: >> >> >> >> On 01/28/2020 06:09 PM, Anshuman Khandual wrote: >>> This series is primarily motivated from an adhoc list from Mark Rutland >>> during our ID_ISAR6 discussion [1]. Besides, it also includes a patch >>> which does macro replacement for various open bits shift encodings in >>> various CPU ID registers. This series is based on linux-next 20200124. >>> >>> [1] https://patchwork.kernel.org/patch/11287805/ >>> >>> Is there anything else apart from these changes which can be accommodated >>> in this series, please do let me know. Thank you. >> >> Just a gentle ping. Any updates, does this series looks okay ? Is there >> anything else related to CPU ID register feature bits, which can be added >> up here. FWIW, the series still applies on v5.6-rc1. Sorry for the delay in response, was distracted on some other patches. > > I just ran into some "32-bit KVM doesn't expose all the ID > registers to userspace via the ONE_REG API" issues today. > I don't know if they'd be reasonable as something to include > in this patchset or if they're unrelated. IMHO, they are bit unrelated. > > Anyway, missing stuff I have noticed specifically: > * MVFR2 > * ID_MMFR4 > * ID_ISAR6 > > More generally I would have expected all these 32-bit registers > to exist and read-as-zero for the purpose of the ONE_REG APIs, > because that's what the architecture says is supposed to happen > and it means we have compatibility and QEMU doesn't gradually > build up lots of "kernel doesn't support this yet" conditionals... > I think we get this right for 64-bit KVM, but can we do it for > 32-bit as well? I am not very familiar with 32-bit KVM but will definitely keep these suggestions noted for later, also try and accommodate if possible. > thanks > -- PMM > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes 2020-02-14 4:23 ` [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes Anshuman Khandual 2020-02-14 15:58 ` Peter Maydell @ 2020-03-20 18:49 ` Suzuki K Poulose 1 sibling, 0 replies; 12+ messages in thread From: Suzuki K Poulose @ 2020-03-20 18:49 UTC (permalink / raw) To: anshuman.khandual, linux-arm-kernel Cc: catalin.marinas, linux-kernel, maz, will, kvmarm Hi Anshuman On 02/14/2020 04:23 AM, Anshuman Khandual wrote: > > > On 01/28/2020 06:09 PM, Anshuman Khandual wrote: >> This series is primarily motivated from an adhoc list from Mark Rutland >> during our ID_ISAR6 discussion [1]. Besides, it also includes a patch >> which does macro replacement for various open bits shift encodings in >> various CPU ID registers. This series is based on linux-next 20200124. >> >> [1] https://patchwork.kernel.org/patch/11287805/ >> >> Is there anything else apart from these changes which can be accommodated >> in this series, please do let me know. Thank you. > > Just a gentle ping. Any updates, does this series looks okay ? Is there > anything else related to CPU ID register feature bits, which can be added > up here. FWIW, the series still applies on v5.6-rc1. Sorry for the delay ! The series looks good to me, except for some minor comments. Please see the individual patches. Cheers Suzuki _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes 2020-01-28 12:39 [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes Anshuman Khandual 2020-01-28 12:39 ` [PATCH 1/6] arm64/cpufeature: Introduce ID_PFR2 CPU register Anshuman Khandual 2020-02-14 4:23 ` [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes Anshuman Khandual @ 2020-04-06 17:09 ` Will Deacon 2020-04-07 8:50 ` Anshuman Khandual 2 siblings, 1 reply; 12+ messages in thread From: Will Deacon @ 2020-04-06 17:09 UTC (permalink / raw) To: Anshuman Khandual Cc: Catalin Marinas, linux-kernel, Marc Zyngier, kvmarm, linux-arm-kernel On Tue, Jan 28, 2020 at 06:09:03PM +0530, Anshuman Khandual wrote: > This series is primarily motivated from an adhoc list from Mark Rutland > during our ID_ISAR6 discussion [1]. Besides, it also includes a patch > which does macro replacement for various open bits shift encodings in > various CPU ID registers. This series is based on linux-next 20200124. > > [1] https://patchwork.kernel.org/patch/11287805/ > > Is there anything else apart from these changes which can be accommodated > in this series, please do let me know. Thank you. The latest Arm ARM also talks about DFR1 and MMFR5. Please can you include those too? Might also be worth checking to see if anything is missing on the 64-bit side as well (I didn't look). Will _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes 2020-04-06 17:09 ` Will Deacon @ 2020-04-07 8:50 ` Anshuman Khandual 2020-04-09 13:54 ` Will Deacon 0 siblings, 1 reply; 12+ messages in thread From: Anshuman Khandual @ 2020-04-07 8:50 UTC (permalink / raw) To: Will Deacon Cc: Catalin Marinas, linux-kernel, Marc Zyngier, kvmarm, linux-arm-kernel On 04/06/2020 10:39 PM, Will Deacon wrote: > On Tue, Jan 28, 2020 at 06:09:03PM +0530, Anshuman Khandual wrote: >> This series is primarily motivated from an adhoc list from Mark Rutland >> during our ID_ISAR6 discussion [1]. Besides, it also includes a patch >> which does macro replacement for various open bits shift encodings in >> various CPU ID registers. This series is based on linux-next 20200124. >> >> [1] https://patchwork.kernel.org/patch/11287805/ >> >> Is there anything else apart from these changes which can be accommodated >> in this series, please do let me know. Thank you. > > The latest Arm ARM also talks about DFR1 and MMFR5. Please can you include Sure, will do. > those too? Might also be worth checking to see if anything is missing on > the 64-bit side as well (I didn't look). Yeah. Now there some missing ones, will add those as well. > > Will > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes 2020-04-07 8:50 ` Anshuman Khandual @ 2020-04-09 13:54 ` Will Deacon 0 siblings, 0 replies; 12+ messages in thread From: Will Deacon @ 2020-04-09 13:54 UTC (permalink / raw) To: Anshuman Khandual Cc: Catalin Marinas, linux-kernel, Marc Zyngier, kvmarm, linux-arm-kernel On Tue, Apr 07, 2020 at 02:20:20PM +0530, Anshuman Khandual wrote: > > > On 04/06/2020 10:39 PM, Will Deacon wrote: > > On Tue, Jan 28, 2020 at 06:09:03PM +0530, Anshuman Khandual wrote: > >> This series is primarily motivated from an adhoc list from Mark Rutland > >> during our ID_ISAR6 discussion [1]. Besides, it also includes a patch > >> which does macro replacement for various open bits shift encodings in > >> various CPU ID registers. This series is based on linux-next 20200124. > >> > >> [1] https://patchwork.kernel.org/patch/11287805/ > >> > >> Is there anything else apart from these changes which can be accommodated > >> in this series, please do let me know. Thank you. > > > > The latest Arm ARM also talks about DFR1 and MMFR5. Please can you include > > Sure, will do. > > > those too? Might also be worth checking to see if anything is missing on > > the 64-bit side as well (I didn't look). > > Yeah. Now there some missing ones, will add those as well. Thanks. Just as a heads up that I've also got a handful of changes in this area, but we can resolve the conflicts at -rc1. https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=sanity-checks Will _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-04-13 3:33 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-01-28 12:39 [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes Anshuman Khandual 2020-01-28 12:39 ` [PATCH 1/6] arm64/cpufeature: Introduce ID_PFR2 CPU register Anshuman Khandual 2020-03-20 18:03 ` Suzuki K Poulose 2020-04-09 12:54 ` Will Deacon 2020-04-13 3:32 ` Anshuman Khandual 2020-02-14 4:23 ` [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes Anshuman Khandual 2020-02-14 15:58 ` Peter Maydell 2020-04-02 2:33 ` Anshuman Khandual 2020-03-20 18:49 ` Suzuki K Poulose 2020-04-06 17:09 ` Will Deacon 2020-04-07 8:50 ` Anshuman Khandual 2020-04-09 13:54 ` Will Deacon
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