From: James Morse <james.morse@arm.com>
To: Andrew Scull <ascull@google.com>
Cc: qwandor@google.com, Marc Zyngier <maz@kernel.org>,
Steven Price <steven.price@arm.com>,
Will Deacon <will@kernel.org>,
wedsonaf@google.com, linux-arm-kernel@lists.infradead.org,
dbrazdil@google.com, kernel-team@android.com,
kvmarm@lists.cs.columbia.edu, tabba@google.com
Subject: Re: [RFC PATCH] arm64: unify WORKAROUND_SPECULATIVE_AT_{NVHE,VHE}
Date: Fri, 27 Mar 2020 16:11:56 +0000 [thread overview]
Message-ID: <a8cc7a17-cb84-3e52-15f4-87b27a01876b@arm.com> (raw)
In-Reply-To: <20200327143941.195626-1-ascull@google.com>
Hi Andrew,
On 3/27/20 2:39 PM, Andrew Scull wrote:
> Errata 1165522, 1319367 and 1530923 each allow TLB entries to be
> allocated as a result of a speculative AT instruction. In order to
> avoid mandating VHE on certain affected CPUs, apply the workaround to
> both the nVHE and the VHE case for all affected CPUs.
You're booting a VHE capable system without VHE, and need KVM?
Do tell!
Would enabling the nVHE workaround on a VHE capable part solve your problem?
Merging the errata has some side effects...
> ---
> I'm not able to test the workarounds properly for the affected CPUs but
> have built and booted under qemu configs with and without VHE as well as
> the workaround being enabled and disabled.
>
> As there exist work arounds for nVHE and VHE, it doesn't appear to be a
> technical limitation that meant VHE was being mandated. Please correct
> me if this understanding is inaccurate. Thanks!
The affected VHE parts came first. Then came those that didn't have VHE at all.
> diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c b/arch/arm64/kvm/hyp/sysreg-sr.c
> index 7672a978926c..2c1436fc0830 100644
> --- a/arch/arm64/kvm/hyp/sysreg-sr.c
> +++ b/arch/arm64/kvm/hyp/sysreg-sr.c
> @@ -118,7 +118,7 @@ static void __hyp_text __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
> write_sysreg(ctxt->sys_regs[MPIDR_EL1], vmpidr_el2);
> write_sysreg(ctxt->sys_regs[CSSELR_EL1], csselr_el1);
>
> - if (!cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT_NVHE)) {
> + if (!cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
> write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], SYS_SCTLR);
> write_sysreg_el1(ctxt->sys_regs[TCR_EL1], SYS_TCR);
> } else if (!ctxt->__hyp_running_vcpu) {
The comment just below here:
| /*
| * Must only be done for guest registers, hence the context
| * test. We're coming from the host, so SCTLR.M is already
| * set. Pairs with __activate_traps_nvhe().
| */
The VHE parts aren't going to run __activate_traps_nvhe(), so you skip restoring
the guest's SCTLR_EL1 and TCR_EL1...
Thanks,
James
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next prev parent reply other threads:[~2020-03-27 16:12 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-27 14:39 [RFC PATCH] arm64: unify WORKAROUND_SPECULATIVE_AT_{NVHE,VHE} Andrew Scull
2020-03-27 14:59 ` Steven Price
2020-03-27 17:48 ` Andrew Scull
2020-03-27 17:52 ` Marc Zyngier
2020-03-27 18:09 ` Will Deacon
2020-03-28 11:23 ` Marc Zyngier
2020-03-30 10:06 ` Will Deacon
2020-04-03 12:57 ` Andrew Scull
2020-04-17 16:41 ` Will Deacon
2020-04-20 13:46 ` Steven Price
2020-03-27 16:11 ` James Morse [this message]
2020-03-27 16:59 ` Will Deacon
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