* [PATCH 0/6] KVM: arm64: More PMU/debug ID register fixes @ 2021-01-14 10:56 Marc Zyngier 2021-01-14 10:56 ` [PATCH 1/6] KVM: arm64: Fix missing RES1 in emulation of DBGBIDR Marc Zyngier ` (5 more replies) 0 siblings, 6 replies; 15+ messages in thread From: Marc Zyngier @ 2021-01-14 10:56 UTC (permalink / raw) To: linux-arm-kernel, kvmarm, kvm; +Cc: kernel-team This is a respin of a series I posted in the 5.7 time frame, and completely forgot about it until I noticed again that a few things where not what I remembered... Given how long it has been, I'm pretending this is v1 again. Anyway, this covers a few gaps in our ID register handling for PMU and Debug, plus the upgrade of the PMU support to 8.4 when possible. I don't plan to take this into 5.11, but this is a likely candidate for 5.12. Marc Zyngier (6): KVM: arm64: Fix missing RES1 in emulation of DBGBIDR KVM: arm64: Fix AArch32 PMUv3 capping KVM: arm64: Add handling of AArch32 PCMEID{2,3} PMUv3 registers KVM: arm64: Refactor filtering of ID registers KVM: arm64: Limit the debug architecture to ARMv8.0 KVM: arm64: Upgrade PMU support to ARMv8.4 arch/arm64/kvm/sys_regs.c | 75 +++++++++++++++++++++++---------------- 1 file changed, 45 insertions(+), 30 deletions(-) -- 2.29.2 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 1/6] KVM: arm64: Fix missing RES1 in emulation of DBGBIDR 2021-01-14 10:56 [PATCH 0/6] KVM: arm64: More PMU/debug ID register fixes Marc Zyngier @ 2021-01-14 10:56 ` Marc Zyngier 2021-01-15 13:05 ` Auger Eric 2021-01-14 10:56 ` [PATCH 2/6] KVM: arm64: Fix AArch32 PMUv3 capping Marc Zyngier ` (4 subsequent siblings) 5 siblings, 1 reply; 15+ messages in thread From: Marc Zyngier @ 2021-01-14 10:56 UTC (permalink / raw) To: linux-arm-kernel, kvmarm, kvm; +Cc: kernel-team The AArch32 CP14 DBGDIDR has bit 15 set to RES1, which our current emulation doesn't set. Just add the missing bit. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> --- arch/arm64/kvm/sys_regs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 3313dedfa505..0c0832472c4a 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1711,7 +1711,7 @@ static bool trap_dbgidr(struct kvm_vcpu *vcpu, p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) | (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) | (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20) - | (6 << 16) | (el3 << 14) | (el3 << 12)); + | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12)); return true; } } -- 2.29.2 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 1/6] KVM: arm64: Fix missing RES1 in emulation of DBGBIDR 2021-01-14 10:56 ` [PATCH 1/6] KVM: arm64: Fix missing RES1 in emulation of DBGBIDR Marc Zyngier @ 2021-01-15 13:05 ` Auger Eric 0 siblings, 0 replies; 15+ messages in thread From: Auger Eric @ 2021-01-15 13:05 UTC (permalink / raw) To: Marc Zyngier, linux-arm-kernel, kvmarm, kvm; +Cc: kernel-team Hi Marc, On 1/14/21 11:56 AM, Marc Zyngier wrote: > The AArch32 CP14 DBGDIDR has bit 15 set to RES1, which our current > emulation doesn't set. Just add the missing bit. > > Reported-by: Peter Maydell <peter.maydell@linaro.org> > Signed-off-by: Marc Zyngier <maz@kernel.org> > --- > arch/arm64/kvm/sys_regs.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 3313dedfa505..0c0832472c4a 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -1711,7 +1711,7 @@ static bool trap_dbgidr(struct kvm_vcpu *vcpu, > p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) | > (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) | > (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20) > - | (6 << 16) | (el3 << 14) | (el3 << 12)); > + | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12)); > return true; > } > } > Reviewed-by: Eric Auger <eric.auger@redhat.com> Thanks Eric _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/6] KVM: arm64: Fix AArch32 PMUv3 capping 2021-01-14 10:56 [PATCH 0/6] KVM: arm64: More PMU/debug ID register fixes Marc Zyngier 2021-01-14 10:56 ` [PATCH 1/6] KVM: arm64: Fix missing RES1 in emulation of DBGBIDR Marc Zyngier @ 2021-01-14 10:56 ` Marc Zyngier 2021-01-15 13:05 ` Auger Eric 2021-01-14 10:56 ` [PATCH 3/6] KVM: arm64: Add handling of AArch32 PCMEID{2, 3} PMUv3 registers Marc Zyngier ` (3 subsequent siblings) 5 siblings, 1 reply; 15+ messages in thread From: Marc Zyngier @ 2021-01-14 10:56 UTC (permalink / raw) To: linux-arm-kernel, kvmarm, kvm; +Cc: kernel-team We shouldn't expose *any* PMU capability when no PMU has been configured for this VM. Signed-off-by: Marc Zyngier <maz@kernel.org> --- arch/arm64/kvm/sys_regs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 0c0832472c4a..ce08d28ab15c 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1048,8 +1048,8 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, } else if (id == SYS_ID_DFR0_EL1) { /* Limit guests to PMUv3 for ARMv8.1 */ val = cpuid_feature_cap_perfmon_field(val, - ID_DFR0_PERFMON_SHIFT, - ID_DFR0_PERFMON_8_1); + ID_DFR0_PERFMON_SHIFT, + kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_1 : 0); } return val; -- 2.29.2 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 2/6] KVM: arm64: Fix AArch32 PMUv3 capping 2021-01-14 10:56 ` [PATCH 2/6] KVM: arm64: Fix AArch32 PMUv3 capping Marc Zyngier @ 2021-01-15 13:05 ` Auger Eric 0 siblings, 0 replies; 15+ messages in thread From: Auger Eric @ 2021-01-15 13:05 UTC (permalink / raw) To: Marc Zyngier, linux-arm-kernel, kvmarm, kvm; +Cc: kernel-team Hi Marc, On 1/14/21 11:56 AM, Marc Zyngier wrote: > We shouldn't expose *any* PMU capability when no PMU has been > configured for this VM. > > Signed-off-by: Marc Zyngier <maz@kernel.org> > --- > arch/arm64/kvm/sys_regs.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 0c0832472c4a..ce08d28ab15c 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -1048,8 +1048,8 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, > } else if (id == SYS_ID_DFR0_EL1) { > /* Limit guests to PMUv3 for ARMv8.1 */ > val = cpuid_feature_cap_perfmon_field(val, > - ID_DFR0_PERFMON_SHIFT, > - ID_DFR0_PERFMON_8_1); > + ID_DFR0_PERFMON_SHIFT, > + kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_1 : 0); nit: Maybe you could use the same layout for SYS_ID_AA64DFR0_EL1 andremove cap there. Reviewed-by: Eric Auger <eric.auger@redhat.com> Eric > } > > return val; > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 3/6] KVM: arm64: Add handling of AArch32 PCMEID{2, 3} PMUv3 registers 2021-01-14 10:56 [PATCH 0/6] KVM: arm64: More PMU/debug ID register fixes Marc Zyngier 2021-01-14 10:56 ` [PATCH 1/6] KVM: arm64: Fix missing RES1 in emulation of DBGBIDR Marc Zyngier 2021-01-14 10:56 ` [PATCH 2/6] KVM: arm64: Fix AArch32 PMUv3 capping Marc Zyngier @ 2021-01-14 10:56 ` Marc Zyngier 2021-01-15 13:04 ` Auger Eric 2021-01-14 10:56 ` [PATCH 4/6] KVM: arm64: Refactor filtering of ID registers Marc Zyngier ` (2 subsequent siblings) 5 siblings, 1 reply; 15+ messages in thread From: Marc Zyngier @ 2021-01-14 10:56 UTC (permalink / raw) To: linux-arm-kernel, kvmarm, kvm; +Cc: kernel-team Despite advertising support for AArch32 PMUv3p1, we fail to handle the PMCEID{2,3} registers, which conveniently alias with with the top bits of PMCEID{0,1}_EL1. Implement these registers with the usual AA32(HI/LO) aliasing mechanism. Signed-off-by: Marc Zyngier <maz@kernel.org> --- arch/arm64/kvm/sys_regs.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index ce08d28ab15c..2bea0494b81d 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -685,14 +685,18 @@ static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { - u64 pmceid; + u64 pmceid, mask, shift; BUG_ON(p->is_write); if (pmu_access_el0_disabled(vcpu)) return false; + get_access_mask(r, &mask, &shift); + pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); + pmceid &= mask; + pmceid >>= shift; p->regval = pmceid; @@ -1895,8 +1899,8 @@ static const struct sys_reg_desc cp15_regs[] = { { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs }, { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc }, { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr }, - { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid }, - { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid }, + { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid }, + { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid }, { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr }, { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper }, { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr }, @@ -1904,6 +1908,8 @@ static const struct sys_reg_desc cp15_regs[] = { { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten }, { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten }, { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs }, + { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 4), access_pmceid }, + { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 5), access_pmceid }, /* PRRR/MAIR0 */ { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, -- 2.29.2 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 3/6] KVM: arm64: Add handling of AArch32 PCMEID{2, 3} PMUv3 registers 2021-01-14 10:56 ` [PATCH 3/6] KVM: arm64: Add handling of AArch32 PCMEID{2, 3} PMUv3 registers Marc Zyngier @ 2021-01-15 13:04 ` Auger Eric 0 siblings, 0 replies; 15+ messages in thread From: Auger Eric @ 2021-01-15 13:04 UTC (permalink / raw) To: Marc Zyngier, linux-arm-kernel, kvmarm, kvm; +Cc: kernel-team Hi Marc, On 1/14/21 11:56 AM, Marc Zyngier wrote: > Despite advertising support for AArch32 PMUv3p1, we fail to handle > the PMCEID{2,3} registers, which conveniently alias with with the top s/with with/with > bits of PMCEID{0,1}_EL1. > > Implement these registers with the usual AA32(HI/LO) aliasing > mechanism. > > Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Thanks Eric > --- > arch/arm64/kvm/sys_regs.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index ce08d28ab15c..2bea0494b81d 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -685,14 +685,18 @@ static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, > static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, > const struct sys_reg_desc *r) > { > - u64 pmceid; > + u64 pmceid, mask, shift; > > BUG_ON(p->is_write); > > if (pmu_access_el0_disabled(vcpu)) > return false; > > + get_access_mask(r, &mask, &shift); > + > pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); > + pmceid &= mask; > + pmceid >>= shift; > > p->regval = pmceid; > > @@ -1895,8 +1899,8 @@ static const struct sys_reg_desc cp15_regs[] = { > { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs }, > { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc }, > { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr }, > - { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid }, > - { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid }, > + { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid }, > + { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid }, > { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr }, > { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper }, > { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr }, > @@ -1904,6 +1908,8 @@ static const struct sys_reg_desc cp15_regs[] = { > { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten }, > { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten }, > { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs }, > + { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 4), access_pmceid }, > + { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 5), access_pmceid }, > > /* PRRR/MAIR0 */ > { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 4/6] KVM: arm64: Refactor filtering of ID registers 2021-01-14 10:56 [PATCH 0/6] KVM: arm64: More PMU/debug ID register fixes Marc Zyngier ` (2 preceding siblings ...) 2021-01-14 10:56 ` [PATCH 3/6] KVM: arm64: Add handling of AArch32 PCMEID{2, 3} PMUv3 registers Marc Zyngier @ 2021-01-14 10:56 ` Marc Zyngier 2021-01-15 13:31 ` Auger Eric 2021-01-14 10:56 ` [PATCH 5/6] KVM: arm64: Limit the debug architecture to ARMv8.0 Marc Zyngier 2021-01-14 10:56 ` [PATCH 6/6] KVM: arm64: Upgrade PMU support to ARMv8.4 Marc Zyngier 5 siblings, 1 reply; 15+ messages in thread From: Marc Zyngier @ 2021-01-14 10:56 UTC (permalink / raw) To: linux-arm-kernel, kvmarm, kvm; +Cc: kernel-team Our current ID register filtering is starting to be a mess of if() statements, and isn't going to get any saner. Let's turn it into a switch(), which has a chance of being more readable, and introduce a FEATURE() macro that allows easy generation of feature masks. No functionnal change intended. Signed-off-by: Marc Zyngier <maz@kernel.org> --- arch/arm64/kvm/sys_regs.c | 51 +++++++++++++++++++++------------------ 1 file changed, 28 insertions(+), 23 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 2bea0494b81d..dda16d60197b 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -9,6 +9,7 @@ * Christoffer Dall <c.dall@virtualopensystems.com> */ +#include <linux/bitfield.h> #include <linux/bsearch.h> #include <linux/kvm_host.h> #include <linux/mm.h> @@ -1016,6 +1017,8 @@ static bool access_arch_timer(struct kvm_vcpu *vcpu, return true; } +#define FEATURE(x) (GENMASK_ULL(x##_SHIFT + 3, x##_SHIFT)) + /* Read a sanitised cpufeature ID register by sys_reg_desc */ static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r, bool raz) @@ -1024,36 +1027,38 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); u64 val = raz ? 0 : read_sanitised_ftr_reg(id); - if (id == SYS_ID_AA64PFR0_EL1) { + switch (id) { + case SYS_ID_AA64PFR0_EL1: if (!vcpu_has_sve(vcpu)) - val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT); - val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT); - val &= ~(0xfUL << ID_AA64PFR0_CSV2_SHIFT); - val |= ((u64)vcpu->kvm->arch.pfr0_csv2 << ID_AA64PFR0_CSV2_SHIFT); - val &= ~(0xfUL << ID_AA64PFR0_CSV3_SHIFT); - val |= ((u64)vcpu->kvm->arch.pfr0_csv3 << ID_AA64PFR0_CSV3_SHIFT); - } else if (id == SYS_ID_AA64PFR1_EL1) { - val &= ~(0xfUL << ID_AA64PFR1_MTE_SHIFT); - } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) { - val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) | - (0xfUL << ID_AA64ISAR1_API_SHIFT) | - (0xfUL << ID_AA64ISAR1_GPA_SHIFT) | - (0xfUL << ID_AA64ISAR1_GPI_SHIFT)); - } else if (id == SYS_ID_AA64DFR0_EL1) { - u64 cap = 0; - + val &= ~FEATURE(ID_AA64PFR0_SVE); + val &= ~FEATURE(ID_AA64PFR0_AMU); + val &= ~FEATURE(ID_AA64PFR0_CSV2); + val |= FIELD_PREP(FEATURE(ID_AA64PFR0_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2); + val &= ~FEATURE(ID_AA64PFR0_CSV3); + val |= FIELD_PREP(FEATURE(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3); + break; + case SYS_ID_AA64PFR1_EL1: + val &= ~FEATURE(ID_AA64PFR1_MTE); + break; + case SYS_ID_AA64ISAR1_EL1: + if (!vcpu_has_ptrauth(vcpu)) + val &= ~(FEATURE(ID_AA64ISAR1_APA) | + FEATURE(ID_AA64ISAR1_API) | + FEATURE(ID_AA64ISAR1_GPA) | + FEATURE(ID_AA64ISAR1_GPI)); + break; + case SYS_ID_AA64DFR0_EL1: /* Limit guests to PMUv3 for ARMv8.1 */ - if (kvm_vcpu_has_pmu(vcpu)) - cap = ID_AA64DFR0_PMUVER_8_1; - val = cpuid_feature_cap_perfmon_field(val, - ID_AA64DFR0_PMUVER_SHIFT, - cap); - } else if (id == SYS_ID_DFR0_EL1) { + ID_AA64DFR0_PMUVER_SHIFT, + kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_1 : 0); + break; + case SYS_ID_DFR0_EL1: /* Limit guests to PMUv3 for ARMv8.1 */ val = cpuid_feature_cap_perfmon_field(val, ID_DFR0_PERFMON_SHIFT, kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_1 : 0); + break; } return val; -- 2.29.2 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 4/6] KVM: arm64: Refactor filtering of ID registers 2021-01-14 10:56 ` [PATCH 4/6] KVM: arm64: Refactor filtering of ID registers Marc Zyngier @ 2021-01-15 13:31 ` Auger Eric 0 siblings, 0 replies; 15+ messages in thread From: Auger Eric @ 2021-01-15 13:31 UTC (permalink / raw) To: Marc Zyngier, linux-arm-kernel, kvmarm, kvm; +Cc: kernel-team Hi Marc, On 1/14/21 11:56 AM, Marc Zyngier wrote: > Our current ID register filtering is starting to be a mess of if() > statements, and isn't going to get any saner. > > Let's turn it into a switch(), which has a chance of being more > readable, and introduce a FEATURE() macro that allows easy generation > of feature masks. > > No functionnal change intended. > > Signed-off-by: Marc Zyngier <maz@kernel.org> > --- > arch/arm64/kvm/sys_regs.c | 51 +++++++++++++++++++++------------------ > 1 file changed, 28 insertions(+), 23 deletions(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 2bea0494b81d..dda16d60197b 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -9,6 +9,7 @@ > * Christoffer Dall <c.dall@virtualopensystems.com> > */ > > +#include <linux/bitfield.h> > #include <linux/bsearch.h> > #include <linux/kvm_host.h> > #include <linux/mm.h> > @@ -1016,6 +1017,8 @@ static bool access_arch_timer(struct kvm_vcpu *vcpu, > return true; > } > > +#define FEATURE(x) (GENMASK_ULL(x##_SHIFT + 3, x##_SHIFT)) > + > /* Read a sanitised cpufeature ID register by sys_reg_desc */ > static u64 read_id_reg(const struct kvm_vcpu *vcpu, > struct sys_reg_desc const *r, bool raz) > @@ -1024,36 +1027,38 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, > (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); > u64 val = raz ? 0 : read_sanitised_ftr_reg(id); > > - if (id == SYS_ID_AA64PFR0_EL1) { > + switch (id) { > + case SYS_ID_AA64PFR0_EL1: > if (!vcpu_has_sve(vcpu)) > - val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT); > - val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT); > - val &= ~(0xfUL << ID_AA64PFR0_CSV2_SHIFT); > - val |= ((u64)vcpu->kvm->arch.pfr0_csv2 << ID_AA64PFR0_CSV2_SHIFT); > - val &= ~(0xfUL << ID_AA64PFR0_CSV3_SHIFT); > - val |= ((u64)vcpu->kvm->arch.pfr0_csv3 << ID_AA64PFR0_CSV3_SHIFT); > - } else if (id == SYS_ID_AA64PFR1_EL1) { > - val &= ~(0xfUL << ID_AA64PFR1_MTE_SHIFT); > - } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) { > - val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) | > - (0xfUL << ID_AA64ISAR1_API_SHIFT) | > - (0xfUL << ID_AA64ISAR1_GPA_SHIFT) | > - (0xfUL << ID_AA64ISAR1_GPI_SHIFT)); > - } else if (id == SYS_ID_AA64DFR0_EL1) { > - u64 cap = 0; > - > + val &= ~FEATURE(ID_AA64PFR0_SVE); > + val &= ~FEATURE(ID_AA64PFR0_AMU); > + val &= ~FEATURE(ID_AA64PFR0_CSV2); > + val |= FIELD_PREP(FEATURE(ID_AA64PFR0_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2); > + val &= ~FEATURE(ID_AA64PFR0_CSV3); > + val |= FIELD_PREP(FEATURE(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3); > + break; > + case SYS_ID_AA64PFR1_EL1: > + val &= ~FEATURE(ID_AA64PFR1_MTE); > + break; > + case SYS_ID_AA64ISAR1_EL1: > + if (!vcpu_has_ptrauth(vcpu)) > + val &= ~(FEATURE(ID_AA64ISAR1_APA) | > + FEATURE(ID_AA64ISAR1_API) | > + FEATURE(ID_AA64ISAR1_GPA) | > + FEATURE(ID_AA64ISAR1_GPI)); > + break; > + case SYS_ID_AA64DFR0_EL1: > /* Limit guests to PMUv3 for ARMv8.1 */ > - if (kvm_vcpu_has_pmu(vcpu)) > - cap = ID_AA64DFR0_PMUVER_8_1; > - > val = cpuid_feature_cap_perfmon_field(val, > - ID_AA64DFR0_PMUVER_SHIFT, > - cap); so you did the change evoked in my previous comment here. > - } else if (id == SYS_ID_DFR0_EL1) { > + ID_AA64DFR0_PMUVER_SHIFT, > + kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_1 : 0); > + break; > + case SYS_ID_DFR0_EL1: > /* Limit guests to PMUv3 for ARMv8.1 */ > val = cpuid_feature_cap_perfmon_field(val, > ID_DFR0_PERFMON_SHIFT, > kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_1 : 0); > + break; > } > > return val; > Looks indeed more readable Reviewed-by: Eric Auger <eric.auger@redhat.com> Eric _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 5/6] KVM: arm64: Limit the debug architecture to ARMv8.0 2021-01-14 10:56 [PATCH 0/6] KVM: arm64: More PMU/debug ID register fixes Marc Zyngier ` (3 preceding siblings ...) 2021-01-14 10:56 ` [PATCH 4/6] KVM: arm64: Refactor filtering of ID registers Marc Zyngier @ 2021-01-14 10:56 ` Marc Zyngier 2021-01-15 14:01 ` Auger Eric 2021-01-14 10:56 ` [PATCH 6/6] KVM: arm64: Upgrade PMU support to ARMv8.4 Marc Zyngier 5 siblings, 1 reply; 15+ messages in thread From: Marc Zyngier @ 2021-01-14 10:56 UTC (permalink / raw) To: linux-arm-kernel, kvmarm, kvm; +Cc: kernel-team Let's not pretend we support anything but ARMv8.0 as far as the debug architecture is concerned. Signed-off-by: Marc Zyngier <maz@kernel.org> --- arch/arm64/kvm/sys_regs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index dda16d60197b..8f79ec1fffa7 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1048,6 +1048,9 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, FEATURE(ID_AA64ISAR1_GPI)); break; case SYS_ID_AA64DFR0_EL1: + /* Limit debug to ARMv8.0 */ + val &= ~FEATURE(ID_AA64DFR0_DEBUGVER); + val |= FIELD_PREP(FEATURE(ID_AA64DFR0_DEBUGVER), 6); /* Limit guests to PMUv3 for ARMv8.1 */ val = cpuid_feature_cap_perfmon_field(val, ID_AA64DFR0_PMUVER_SHIFT, -- 2.29.2 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 5/6] KVM: arm64: Limit the debug architecture to ARMv8.0 2021-01-14 10:56 ` [PATCH 5/6] KVM: arm64: Limit the debug architecture to ARMv8.0 Marc Zyngier @ 2021-01-15 14:01 ` Auger Eric 0 siblings, 0 replies; 15+ messages in thread From: Auger Eric @ 2021-01-15 14:01 UTC (permalink / raw) To: Marc Zyngier, linux-arm-kernel, kvmarm, kvm; +Cc: kernel-team Hi Marc, On 1/14/21 11:56 AM, Marc Zyngier wrote: > Let's not pretend we support anything but ARMv8.0 as far as the > debug architecture is concerned. > > Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Eric > --- > arch/arm64/kvm/sys_regs.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index dda16d60197b..8f79ec1fffa7 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -1048,6 +1048,9 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, > FEATURE(ID_AA64ISAR1_GPI)); > break; > case SYS_ID_AA64DFR0_EL1: > + /* Limit debug to ARMv8.0 */ > + val &= ~FEATURE(ID_AA64DFR0_DEBUGVER); > + val |= FIELD_PREP(FEATURE(ID_AA64DFR0_DEBUGVER), 6); > /* Limit guests to PMUv3 for ARMv8.1 */ > val = cpuid_feature_cap_perfmon_field(val, > ID_AA64DFR0_PMUVER_SHIFT, > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 6/6] KVM: arm64: Upgrade PMU support to ARMv8.4 2021-01-14 10:56 [PATCH 0/6] KVM: arm64: More PMU/debug ID register fixes Marc Zyngier ` (4 preceding siblings ...) 2021-01-14 10:56 ` [PATCH 5/6] KVM: arm64: Limit the debug architecture to ARMv8.0 Marc Zyngier @ 2021-01-14 10:56 ` Marc Zyngier 2021-01-15 14:01 ` Auger Eric 5 siblings, 1 reply; 15+ messages in thread From: Marc Zyngier @ 2021-01-14 10:56 UTC (permalink / raw) To: linux-arm-kernel, kvmarm, kvm; +Cc: kernel-team Upgrading the PMU code from ARMv8.1 to ARMv8.4 turns out to be pretty easy. All that is required is support for PMMIR_EL1, which is read-only, and for which returning 0 is a valid option. Let's just do that and adjust what we return to the guest. Signed-off-by: Marc Zyngier <maz@kernel.org> --- arch/arm64/kvm/sys_regs.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 8f79ec1fffa7..2f4ecbd2abfb 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1051,10 +1051,10 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, /* Limit debug to ARMv8.0 */ val &= ~FEATURE(ID_AA64DFR0_DEBUGVER); val |= FIELD_PREP(FEATURE(ID_AA64DFR0_DEBUGVER), 6); - /* Limit guests to PMUv3 for ARMv8.1 */ + /* Limit guests to PMUv3 for ARMv8.4 */ val = cpuid_feature_cap_perfmon_field(val, ID_AA64DFR0_PMUVER_SHIFT, - kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_1 : 0); + kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0); break; case SYS_ID_DFR0_EL1: /* Limit guests to PMUv3 for ARMv8.1 */ @@ -1496,6 +1496,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 }, { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 }, + { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, -- 2.29.2 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 6/6] KVM: arm64: Upgrade PMU support to ARMv8.4 2021-01-14 10:56 ` [PATCH 6/6] KVM: arm64: Upgrade PMU support to ARMv8.4 Marc Zyngier @ 2021-01-15 14:01 ` Auger Eric 2021-01-15 16:42 ` Marc Zyngier 0 siblings, 1 reply; 15+ messages in thread From: Auger Eric @ 2021-01-15 14:01 UTC (permalink / raw) To: Marc Zyngier, linux-arm-kernel, kvmarm, kvm; +Cc: kernel-team Hi Marc, On 1/14/21 11:56 AM, Marc Zyngier wrote: > Upgrading the PMU code from ARMv8.1 to ARMv8.4 turns out to be > pretty easy. All that is required is support for PMMIR_EL1, which > is read-only, and for which returning 0 is a valid option. > > Let's just do that and adjust what we return to the guest. > > Signed-off-by: Marc Zyngier <maz@kernel.org> > --- > arch/arm64/kvm/sys_regs.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 8f79ec1fffa7..2f4ecbd2abfb 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -1051,10 +1051,10 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, > /* Limit debug to ARMv8.0 */ > val &= ~FEATURE(ID_AA64DFR0_DEBUGVER); > val |= FIELD_PREP(FEATURE(ID_AA64DFR0_DEBUGVER), 6); > - /* Limit guests to PMUv3 for ARMv8.1 */ > + /* Limit guests to PMUv3 for ARMv8.4 */ > val = cpuid_feature_cap_perfmon_field(val, > ID_AA64DFR0_PMUVER_SHIFT, > - kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_1 : 0); > + kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0); > break; > case SYS_ID_DFR0_EL1: > /* Limit guests to PMUv3 for ARMv8.1 */ what about the debug version in aarch32 state. Is it on purpose that you leave it as 8_1? Thanks Eric > @@ -1496,6 +1496,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { > > { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 }, > { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 }, > + { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, > > { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, > { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 6/6] KVM: arm64: Upgrade PMU support to ARMv8.4 2021-01-15 14:01 ` Auger Eric @ 2021-01-15 16:42 ` Marc Zyngier 2021-01-15 17:26 ` Auger Eric 0 siblings, 1 reply; 15+ messages in thread From: Marc Zyngier @ 2021-01-15 16:42 UTC (permalink / raw) To: Auger Eric; +Cc: kvm, kernel-team, kvmarm, linux-arm-kernel Hi Eric, On 2021-01-15 14:01, Auger Eric wrote: > Hi Marc, > > On 1/14/21 11:56 AM, Marc Zyngier wrote: >> Upgrading the PMU code from ARMv8.1 to ARMv8.4 turns out to be >> pretty easy. All that is required is support for PMMIR_EL1, which >> is read-only, and for which returning 0 is a valid option. >> >> Let's just do that and adjust what we return to the guest. >> >> Signed-off-by: Marc Zyngier <maz@kernel.org> >> --- >> arch/arm64/kvm/sys_regs.c | 5 +++-- >> 1 file changed, 3 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c >> index 8f79ec1fffa7..2f4ecbd2abfb 100644 >> --- a/arch/arm64/kvm/sys_regs.c >> +++ b/arch/arm64/kvm/sys_regs.c >> @@ -1051,10 +1051,10 @@ static u64 read_id_reg(const struct kvm_vcpu >> *vcpu, >> /* Limit debug to ARMv8.0 */ >> val &= ~FEATURE(ID_AA64DFR0_DEBUGVER); >> val |= FIELD_PREP(FEATURE(ID_AA64DFR0_DEBUGVER), 6); >> - /* Limit guests to PMUv3 for ARMv8.1 */ >> + /* Limit guests to PMUv3 for ARMv8.4 */ >> val = cpuid_feature_cap_perfmon_field(val, >> ID_AA64DFR0_PMUVER_SHIFT, >> - kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_1 : 0); >> + kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0); >> break; >> case SYS_ID_DFR0_EL1: >> /* Limit guests to PMUv3 for ARMv8.1 */ > what about the debug version in aarch32 state. Is it on purpose that > you > leave it as 8_1? That's a good point. There is also the fact that we keep reporting STALL_SLOT as a valid event even in PMCEID0_EL1 despite PMMIR_EL1.SLOTS always reporting 0. I'll fix that and resend something next week. Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 6/6] KVM: arm64: Upgrade PMU support to ARMv8.4 2021-01-15 16:42 ` Marc Zyngier @ 2021-01-15 17:26 ` Auger Eric 0 siblings, 0 replies; 15+ messages in thread From: Auger Eric @ 2021-01-15 17:26 UTC (permalink / raw) To: Marc Zyngier; +Cc: kvm, kernel-team, kvmarm, linux-arm-kernel Hi Marc, On 1/15/21 5:42 PM, Marc Zyngier wrote: > Hi Eric, > > On 2021-01-15 14:01, Auger Eric wrote: >> Hi Marc, >> >> On 1/14/21 11:56 AM, Marc Zyngier wrote: >>> Upgrading the PMU code from ARMv8.1 to ARMv8.4 turns out to be >>> pretty easy. All that is required is support for PMMIR_EL1, which >>> is read-only, and for which returning 0 is a valid option. >>> >>> Let's just do that and adjust what we return to the guest. >>> >>> Signed-off-by: Marc Zyngier <maz@kernel.org> >>> --- >>> arch/arm64/kvm/sys_regs.c | 5 +++-- >>> 1 file changed, 3 insertions(+), 2 deletions(-) >>> >>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c >>> index 8f79ec1fffa7..2f4ecbd2abfb 100644 >>> --- a/arch/arm64/kvm/sys_regs.c >>> +++ b/arch/arm64/kvm/sys_regs.c >>> @@ -1051,10 +1051,10 @@ static u64 read_id_reg(const struct kvm_vcpu >>> *vcpu, >>> /* Limit debug to ARMv8.0 */ >>> val &= ~FEATURE(ID_AA64DFR0_DEBUGVER); >>> val |= FIELD_PREP(FEATURE(ID_AA64DFR0_DEBUGVER), 6); >>> - /* Limit guests to PMUv3 for ARMv8.1 */ >>> + /* Limit guests to PMUv3 for ARMv8.4 */ >>> val = cpuid_feature_cap_perfmon_field(val, >>> ID_AA64DFR0_PMUVER_SHIFT, >>> - kvm_vcpu_has_pmu(vcpu) ? >>> ID_AA64DFR0_PMUVER_8_1 : 0); >>> + kvm_vcpu_has_pmu(vcpu) ? >>> ID_AA64DFR0_PMUVER_8_4 : 0); >>> break; >>> case SYS_ID_DFR0_EL1: >>> /* Limit guests to PMUv3 for ARMv8.1 */ >> what about the debug version in aarch32 state. Is it on purpose that you >> leave it as 8_1? > > That's a good point. There is also the fact that we keep reporting > STALL_SLOT as a valid event even in PMCEID0_EL1 despite PMMIR_EL1.SLOTS > always reporting 0. Hum OK. I did not notice that ;-) Thanks Eric > > I'll fix that and resend something next week. > > Thanks, > > M. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2021-01-15 17:26 UTC | newest] Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-01-14 10:56 [PATCH 0/6] KVM: arm64: More PMU/debug ID register fixes Marc Zyngier 2021-01-14 10:56 ` [PATCH 1/6] KVM: arm64: Fix missing RES1 in emulation of DBGBIDR Marc Zyngier 2021-01-15 13:05 ` Auger Eric 2021-01-14 10:56 ` [PATCH 2/6] KVM: arm64: Fix AArch32 PMUv3 capping Marc Zyngier 2021-01-15 13:05 ` Auger Eric 2021-01-14 10:56 ` [PATCH 3/6] KVM: arm64: Add handling of AArch32 PCMEID{2, 3} PMUv3 registers Marc Zyngier 2021-01-15 13:04 ` Auger Eric 2021-01-14 10:56 ` [PATCH 4/6] KVM: arm64: Refactor filtering of ID registers Marc Zyngier 2021-01-15 13:31 ` Auger Eric 2021-01-14 10:56 ` [PATCH 5/6] KVM: arm64: Limit the debug architecture to ARMv8.0 Marc Zyngier 2021-01-15 14:01 ` Auger Eric 2021-01-14 10:56 ` [PATCH 6/6] KVM: arm64: Upgrade PMU support to ARMv8.4 Marc Zyngier 2021-01-15 14:01 ` Auger Eric 2021-01-15 16:42 ` Marc Zyngier 2021-01-15 17:26 ` Auger Eric
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