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From: Jean-Philippe Brucker <jean-philippe@linaro.org>
To: Jonathan Cameron <jonathan.cameron@huawei.com>
Cc: iommu@lists.linux-foundation.org, devicetree@vger.kernel.org,
	linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com,
	lorenzo.pieralisi@arm.com, guohanjun@huawei.com,
	sudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org,
	will@kernel.org, robin.murphy@arm.com, zhangfei.gao@linaro.org,
	eric.auger@redhat.com
Subject: Re: [PATCH v2 6/8] iommu/arm-smmu-v3: Add second level of context descriptor table
Date: Fri, 22 Nov 2019 16:32:03 +0100
Message-ID: <20191122153203.GB810215@lophozonia> (raw)
In-Reply-To: <20191111155007.00002021@huawei.com>

On Mon, Nov 11, 2019 at 03:50:07PM +0000, Jonathan Cameron wrote:
> > +		cfg->l1ptr = dmam_alloc_coherent(smmu->dev, size,
> > +						 &cfg->l1ptr_dma,
> > +						 GFP_KERNEL | __GFP_ZERO);
> 
> As before.  Fairly sure __GFP_ZERO doesn't give you anything extra.

Indeed

> > +		if (!cfg->l1ptr) {
> > +			dev_warn(smmu->dev, "failed to allocate L1 context table\n");
> > +			return -ENOMEM;
> > +		}
> > +	}
> > +
> > +	cfg->tables = devm_kzalloc(smmu->dev, sizeof(struct arm_smmu_cd_table) *
> > +				   cfg->num_tables, GFP_KERNEL);
> > +	if (!cfg->tables) {
> > +		ret = -ENOMEM;
> > +		goto err_free_l1;
> > +	}
> > +
> > +	/* With two levels, leaf tables are allocated lazily */
> This comment is a kind of odd one.  It is actually talking about what
> 'doesn't' happen here I think..
> 
> Perhaps /*
>          * Only allocate a leaf table for linear case.
>          * With two levels, the leaf tables are allocated lazily.
> 	 */

Yes, that's clearer

> > +	if (!cfg->l1ptr) {
> > +		ret = arm_smmu_alloc_cd_leaf_table(smmu, &cfg->tables[0],
> > +						   max_contexts);
> > +		if (ret)
> > +			goto err_free_tables;
> > +	}
> > +
> > +	return 0;
> > +
> > +err_free_tables:
> > +	devm_kfree(smmu->dev, cfg->tables);
> > +err_free_l1:
> > +	if (cfg->l1ptr)
> > +		dmam_free_coherent(smmu->dev, size, cfg->l1ptr, cfg->l1ptr_dma);
> 
> This cleanup only occurs if we have had an error.
> Is there potential for this to rerun at some point later?  If so we should
> be careful to also reset relevant pointers - e.g. cfg->l1ptr = NULL as
> they are used to control the flow above.

Yes we should definitely clear l1ptr. The domain may be managed by a
device driver, and if attach_dev() fails they will call domain_free(),
which checks this pointer. Plus nothing prevents them from calling
attach_dev() again with the same domain.

> If there is no chance of a rerun why bother cleaning them up at all?  Something
> has gone horribly wrong so let the eventual smmu cleanup deal with them.

The domain is much shorter-lived than the SMMU device, so we need this
cleanup.

> > +	return ret;
> >  }
> >  
> >  static void arm_smmu_free_cd_tables(struct arm_smmu_domain *smmu_domain)
> >  {
> > +	int i;
> >  	struct arm_smmu_device *smmu = smmu_domain->smmu;
> >  	struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg;
> > +	size_t num_leaf_entries = 1 << cfg->s1cdmax;
> > +	struct arm_smmu_cd_table *table = cfg->tables;
> >  
> > -	arm_smmu_free_cd_leaf_table(smmu, &cfg->table, 1 << cfg->s1cdmax);
> > +	if (cfg->l1ptr) {
> > +		size_t size = cfg->num_tables * (CTXDESC_L1_DESC_DWORDS << 3);
> > +
> > +		dmam_free_coherent(smmu->dev, size, cfg->l1ptr, cfg->l1ptr_dma);
> 
> 		As above, if we can call this in a fashion that makes sense
> 		other than in eventual smmu tear down, then we need to be
> 		careful to reset the pointers.   If not, then why are we clearing
> 		managed resourced by hand anyway?

Yes, we call this on the error cleanup path (not only domain_free()), so
it needs to leave the domain in a usable state.

Thanks,
Jean

  reply index

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-08 15:25 [PATCH v2 0/8] iommu: Add PASID support to Arm SMMUv3 Jean-Philippe Brucker
2019-11-08 15:25 ` [PATCH v2 1/8] dt-bindings: document PASID property for IOMMU masters Jean-Philippe Brucker
2019-11-08 15:25 ` [PATCH v2 2/8] iommu/arm-smmu-v3: Support platform SSID Jean-Philippe Brucker
2019-11-08 15:25 ` [PATCH v2 3/8] ACPI/IORT: Support PASID for platform devices Jean-Philippe Brucker
2019-11-14  6:42   ` Hanjun Guo
2019-11-08 15:25 ` [PATCH v2 4/8] iommu/arm-smmu-v3: Prepare for SSID support Jean-Philippe Brucker
2019-11-11 14:38   ` Jonathan Cameron
2019-11-22 15:28     ` Jean-Philippe Brucker
2019-11-08 15:25 ` [PATCH v2 5/8] iommu/arm-smmu-v3: Add support for Substream IDs Jean-Philippe Brucker
2019-11-11 15:12   ` Jonathan Cameron
2019-11-08 15:25 ` [PATCH v2 6/8] iommu/arm-smmu-v3: Add second level of context descriptor table Jean-Philippe Brucker
2019-11-11 15:50   ` Jonathan Cameron
2019-11-22 15:32     ` Jean-Philippe Brucker [this message]
2019-11-08 15:25 ` [PATCH v2 7/8] iommu/arm-smmu-v3: Improve add_device() error handling Jean-Philippe Brucker
2019-11-11 15:58   ` Jonathan Cameron
2019-11-08 15:25 ` [PATCH v2 8/8] iommu/arm-smmu-v3: Add support for PCI PASID Jean-Philippe Brucker
2019-11-11 16:05   ` Jonathan Cameron
2019-11-22 15:33     ` Jean-Philippe Brucker
2019-11-12 10:02 ` [PATCH v2 0/8] iommu: Add PASID support to Arm SMMUv3 zhangfei

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