From: Sudeep Holla <sudeep.holla@arm.com>
To: Rob Herring <robh@kernel.org>
Cc: Robin Murphy <robin.murphy@arm.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
James Morse <james.morse@arm.com>,
Sudeep Holla <sudeep.holla@arm.com>,
Jeremy Linton <jeremy.linton@arm.com>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>,
devicetree@vger.kernel.org,
"open list:ACPI FOR ARM64 (ACPI/arm64)"
<linux-acpi@vger.kernel.org>
Subject: Re: [PATCH 2/6] cacheinfo: Set cache 'id' based on DT data
Date: Fri, 17 Dec 2021 19:08:10 +0000 [thread overview]
Message-ID: <20211217190810.qz44e3ff2bq4wmf2@bogus> (raw)
In-Reply-To: <20211217190345.kskfhnelqg3yx4j7@bogus>
On Fri, Dec 17, 2021 at 07:03:45PM +0000, Sudeep Holla wrote:
> On Fri, Dec 17, 2021 at 12:14:22PM -0600, Rob Herring wrote:
> > On Fri, Dec 17, 2021 at 10:57 AM Robin Murphy <robin.murphy@arm.com> wrote:
> > >
> > > Hi Rob,
> > >
> > > On 2021-12-16 23:31, Rob Herring wrote:
> > > > Use the minimum CPU h/w id of the CPUs associated with the cache for the
> > > > cache 'id'. This will provide a stable id value for a given system. As
>
> I am trying to follow the code. IIUC, the level one(I$ and D$) are skipped
> in this logic and the private unified cache if any will get the cpu hwid as
> the cache id which is all fine. But what happens if there are 2 levels of
> unified private cache ? I am assuming we only care about shared caches for
> MPAM and ignore private caches which sounds OK but I just wanted to confirm.
>
> > > > we need to check all possible CPUs, we can't use the shared_cpu_map
> > > > which is just online CPUs. There's not a cache to CPUs mapping in DT, so
> > > > we have to walk all CPU nodes and then walk cache levels.
>
> I would have preferred to add the cache IDs in DT similar to ACPI but I see
> you have certain concerns with that which are valid as well.
One thing I forgot to add is for some weird reasons, some platform supports
both DT and ACPI, this will force the ID generated here to be used in ACPI as
well to ensure same userspace scripts can be used to manage both. That doesn't
sound so great to me.
--
Regards,
Sudeep
next prev parent reply other threads:[~2021-12-17 19:08 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-16 23:31 [PATCH 0/6] cacheinfo: CPU affinity and Devicetree 'id' support Rob Herring
2021-12-16 23:31 ` [PATCH 1/6] cacheinfo: Allow for >32-bit cache 'id' Rob Herring
2021-12-16 23:31 ` [PATCH 2/6] cacheinfo: Set cache 'id' based on DT data Rob Herring
2021-12-17 16:57 ` Robin Murphy
2021-12-17 18:14 ` Rob Herring
2021-12-17 19:03 ` Sudeep Holla
2021-12-17 19:08 ` Sudeep Holla [this message]
2021-12-17 19:26 ` Rob Herring
2021-12-17 20:28 ` Jeremy Linton
2021-12-17 19:08 ` Robin Murphy
2021-12-17 19:35 ` Rob Herring
2021-12-17 20:22 ` Jeremy Linton
2021-12-17 21:13 ` Robin Murphy
2021-12-16 23:31 ` [PATCH 3/6] cacheinfo: Add cpu_affinity_map to store affinity for all CPUs Rob Herring
2021-12-16 23:31 ` [PATCH 4/6] ACPI / PPTT: Populate the cacheinfo.cpu_affinity_map Rob Herring
2021-12-16 23:31 ` [PATCH 5/6] cacheinfo: Use cpu_affinity_map for populating shared_cpu_map Rob Herring
2021-12-16 23:31 ` [PATCH 6/6] cacheinfo: Add cacheinfo_get_cache_affinity() function Rob Herring
2021-12-21 9:31 ` [PATCH 0/6] cacheinfo: CPU affinity and Devicetree 'id' support Greg Kroah-Hartman
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