[PATCH V2 0/2] ACPI: Add LoongArch-related definitions

[PATCH V2 0/2] ACPI: Add LoongArch-related definitions

[Huacai Chen]

LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V.
LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit
version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its
boot protocol LoongArch-specific interrupt controllers (similar to APIC)
are already added in the next revision of ACPI Specification (current
revision is 6.4).

This patchset are preparing to add LoongArch support in mainline kernel,
we can see a snapshot here:
https://github.com/loongson/linux/tree/loongarch-next

Cross-compile tool chain to build kernel:
https://github.com/loongson/build-tools/releases

Loongson and LoongArch documentations:
https://github.com/loongson/LoongArch-Documentation

ECR for LoongArch-specific interrupt controllers:
https://mantis.uefi.org/mantis/view.php?id=2203
https://mantis.uefi.org/mantis/view.php?id=2313

ACPI changes of LoongArch have been approved in the last year, but the
new version of ACPI SPEC hasn't been made public yet.

V2: Remove merged patches and update commit messages.

Huacai Chen and Jianmin Lv(2):
 ACPICA: MADT: Add LoongArch APICs support.
 ACPICA: Events: Support fixed pcie wake event.

Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn> 
---
 drivers/acpi/acpica/evevent.c  |  17 ++++--
 drivers/acpi/acpica/hwsleep.c  |  12 ++++
 drivers/acpi/acpica/utglobal.c |   4 ++
 drivers/acpi/tables.c          |  10 ++++
 include/acpi/actbl2.h          | 125 ++++++++++++++++++++++++++++++++++++++++-
 include/acpi/actypes.h         |   3 +-
 6 files changed, 163 insertions(+), 8 deletions(-)
--
2.27.0

[PATCH V2 1/2] ACPICA: MADT: Add LoongArch APICs support

[Huacai Chen]

LoongArch-specific interrupt controllers (similar to APIC) are added
in the next revision of ACPI Specification (current revision is 6.4),
which including CORE_PIC (CPUINTC), LIO_PIC (LIOINTC), EIO_PIC (EIOINTC),
HT_PIC (HTVECINTC), BIO_PIC (PCHINTC), LPC_PIC (PCHLPC) and MSI_PIC
(PCHMSI). This patch add their definition and handlings.

ACPI changes of LoongArch-specific interrupt controllers have already
been approved in the ECRs, and will be public in the next revision of
ACPI Specification.

Reference: https://mantis.uefi.org/mantis/view.php?id=2203
Reference: https://mantis.uefi.org/mantis/view.php?id=2313
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 drivers/acpi/tables.c |  10 ++++
 include/acpi/actbl2.h | 125 +++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 134 insertions(+), 1 deletion(-)

diff --git a/drivers/acpi/tables.c b/drivers/acpi/tables.c
index 34600b5b9d8e..5c6599c35e35 100644
--- a/drivers/acpi/tables.c
+++ b/drivers/acpi/tables.c
@@ -210,6 +210,16 @@ void acpi_table_print_madt_entry(struct acpi_subtable_header *header)
 		}
 		break;
 
+	case ACPI_MADT_TYPE_CORE_PIC:
+		{
+			struct acpi_madt_core_pic *p =
+			    (struct acpi_madt_core_pic *)header;
+			pr_debug("CORE PIC (processor_id[0x%02x] core_id[0x%02x] %s)\n",
+				 p->processor_id, p->core_id,
+				 (p->flags & ACPI_MADT_ENABLED) ? "enabled" : "disabled");
+		}
+		break;
+
 	default:
 		pr_warn("Found unsupported MADT entry (type = 0x%x)\n",
 			header->type);
diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h
index 16847c8d9d5f..2419f9e397e2 100644
--- a/include/acpi/actbl2.h
+++ b/include/acpi/actbl2.h
@@ -762,7 +762,14 @@ enum acpi_madt_type {
 	ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR = 14,
 	ACPI_MADT_TYPE_GENERIC_TRANSLATOR = 15,
 	ACPI_MADT_TYPE_MULTIPROC_WAKEUP = 16,
-	ACPI_MADT_TYPE_RESERVED = 17	/* 17 and greater are reserved */
+	ACPI_MADT_TYPE_CORE_PIC = 17,
+	ACPI_MADT_TYPE_LIO_PIC = 18,
+	ACPI_MADT_TYPE_HT_PIC = 19,
+	ACPI_MADT_TYPE_EIO_PIC = 20,
+	ACPI_MADT_TYPE_MSI_PIC = 21,
+	ACPI_MADT_TYPE_BIO_PIC = 22,
+	ACPI_MADT_TYPE_LPC_PIC = 23,
+	ACPI_MADT_TYPE_RESERVED = 24	/* 24 and greater are reserved */
 };
 
 /*
@@ -992,6 +999,122 @@ struct acpi_madt_multiproc_wakeup_mailbox {
 
 #define ACPI_MP_WAKE_COMMAND_WAKEUP    1
 
+/* Values for Version field above */
+
+enum acpi_madt_core_pic_version {
+	ACPI_MADT_CORE_PIC_VERSION_NONE = 0,
+	ACPI_MADT_CORE_PIC_VERSION_V1 = 1,
+	ACPI_MADT_CORE_PIC_VERSION_RESERVED = 2	/* 2 and greater are reserved */
+};
+
+enum acpi_madt_lio_pic_version {
+	ACPI_MADT_LIO_PIC_VERSION_NONE = 0,
+	ACPI_MADT_LIO_PIC_VERSION_V1 = 1,
+	ACPI_MADT_LIO_PIC_VERSION_RESERVED = 2	/* 2 and greater are reserved */
+};
+
+enum acpi_madt_eio_pic_version {
+	ACPI_MADT_EIO_PIC_VERSION_NONE = 0,
+	ACPI_MADT_EIO_PIC_VERSION_V1 = 1,
+	ACPI_MADT_EIO_PIC_VERSION_RESERVED = 2	/* 2 and greater are reserved */
+};
+
+enum acpi_madt_ht_pic_version {
+	ACPI_MADT_HT_PIC_VERSION_NONE = 0,
+	ACPI_MADT_HT_PIC_VERSION_V1 = 1,
+	ACPI_MADT_HT_PIC_VERSION_RESERVED = 2	/* 2 and greater are reserved */
+};
+
+enum acpi_madt_bio_pic_version {
+	ACPI_MADT_BIO_PIC_VERSION_NONE = 0,
+	ACPI_MADT_BIO_PIC_VERSION_V1 = 1,
+	ACPI_MADT_BIO_PIC_VERSION_RESERVED = 2	/* 2 and greater are reserved */
+};
+
+enum acpi_madt_msi_pic_version {
+	ACPI_MADT_MSI_PIC_VERSION_NONE = 0,
+	ACPI_MADT_MSI_PIC_VERSION_V1 = 1,
+	ACPI_MADT_MSI_PIC_VERSION_RESERVED = 2	/* 2 and greater are reserved */
+};
+
+enum acpi_madt_lpc_pic_version {
+	ACPI_MADT_LPC_PIC_VERSION_NONE = 0,
+	ACPI_MADT_LPC_PIC_VERSION_V1 = 1,
+	ACPI_MADT_LPC_PIC_VERSION_RESERVED = 2	/* 2 and greater are reserved */
+};
+
+/* Core Interrupt Controller */
+
+struct acpi_madt_core_pic {
+	struct acpi_subtable_header header;
+	u8 version;
+	u32 processor_id;
+	u32 core_id;
+	u32 flags;
+};
+
+/* Legacy I/O Interrupt Controller */
+
+struct acpi_madt_lio_pic {
+	struct acpi_subtable_header header;
+	u8 version;
+	u64 address;
+	u16 size;
+	u8 cascade[2];
+	u32 cascade_map[2];
+};
+
+/* Extend I/O Interrupt Controller */
+
+struct acpi_madt_eio_pic {
+	struct acpi_subtable_header header;
+	u8 version;
+	u8 cascade;
+	u8 node;
+	u64 node_map;
+};
+
+/* HT Interrupt Controller */
+
+struct acpi_madt_ht_pic {
+	struct acpi_subtable_header header;
+	u8 version;
+	u64 address;
+	u16 size;
+	u8 cascade[8];
+};
+
+/* Bridge I/O Interrupt Controller */
+
+struct acpi_madt_bio_pic {
+	struct acpi_subtable_header header;
+	u8 version;
+	u64 address;
+	u16 size;
+	u16 id;
+	u16 gsi_base;
+};
+
+/* MSI Interrupt Controller */
+
+struct acpi_madt_msi_pic {
+	struct acpi_subtable_header header;
+	u8 version;
+	u64 msg_address;
+	u32 start;
+	u32 count;
+};
+
+/* LPC Interrupt Controller */
+
+struct acpi_madt_lpc_pic {
+	struct acpi_subtable_header header;
+	u8 version;
+	u64 address;
+	u16 size;
+	u8 cascade;
+};
+
 /*
  * Common flags fields for MADT subtables
  */
-- 
2.27.0

[PATCH V2 2/2] ACPICA: Events: Support fixed pcie wake event

[Huacai Chen]

Some chipsets (such as Loongson's LS7A) support fixed pcie wake event
which is defined in the PM1 block(related description can be found in
4.8.4.1.1 PM1 Status Registers, 4.8.4.2.1 PM1 Control Registers and
5.2.9 Fixed ACPI Description Table (FADT)), so we add code to handle it.

ACPI Spec 6.4 link:
https://uefi.org/specifications/ACPI/6.4/

Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 drivers/acpi/acpica/evevent.c  | 17 +++++++++++------
 drivers/acpi/acpica/hwsleep.c  | 12 ++++++++++++
 drivers/acpi/acpica/utglobal.c |  4 ++++
 include/acpi/actypes.h         |  3 ++-
 4 files changed, 29 insertions(+), 7 deletions(-)

diff --git a/drivers/acpi/acpica/evevent.c b/drivers/acpi/acpica/evevent.c
index 35385148fedb..2340986de37b 100644
--- a/drivers/acpi/acpica/evevent.c
+++ b/drivers/acpi/acpica/evevent.c
@@ -140,9 +140,9 @@ static acpi_status acpi_ev_fixed_event_initialize(void)
 
 		if (acpi_gbl_fixed_event_info[i].enable_register_id != 0xFF) {
 			status =
-			    acpi_write_bit_register(acpi_gbl_fixed_event_info
-						    [i].enable_register_id,
-						    ACPI_DISABLE_EVENT);
+			    acpi_write_bit_register(acpi_gbl_fixed_event_info[i].enable_register_id,
+						    (i == ACPI_EVENT_PCIE_WAKE) ?
+						    ACPI_ENABLE_EVENT : ACPI_DISABLE_EVENT);
 			if (ACPI_FAILURE(status)) {
 				return (status);
 			}
@@ -185,6 +185,11 @@ u32 acpi_ev_fixed_event_detect(void)
 		return (int_status);
 	}
 
+	if (fixed_enable & ACPI_BITMASK_PCIEXP_WAKE_DISABLE)
+		fixed_enable &= ~ACPI_BITMASK_PCIEXP_WAKE_DISABLE;
+	else
+		fixed_enable |= ACPI_BITMASK_PCIEXP_WAKE_DISABLE;
+
 	ACPI_DEBUG_PRINT((ACPI_DB_INTERRUPTS,
 			  "Fixed Event Block: Enable %08X Status %08X\n",
 			  fixed_enable, fixed_status));
@@ -248,9 +253,9 @@ static u32 acpi_ev_fixed_event_dispatch(u32 event)
 	 * and disable the event to prevent further interrupts.
 	 */
 	if (!acpi_gbl_fixed_event_handlers[event].handler) {
-		(void)acpi_write_bit_register(acpi_gbl_fixed_event_info[event].
-					      enable_register_id,
-					      ACPI_DISABLE_EVENT);
+		(void)acpi_write_bit_register(acpi_gbl_fixed_event_info[event].enable_register_id,
+					      event == ACPI_EVENT_PCIE_WAKE ?
+					      ACPI_ENABLE_EVENT : ACPI_DISABLE_EVENT);
 
 		ACPI_ERROR((AE_INFO,
 			    "No installed handler for fixed event - %s (%u), disabling",
diff --git a/drivers/acpi/acpica/hwsleep.c b/drivers/acpi/acpica/hwsleep.c
index 5efa3d8e483e..fe677b5b31fe 100644
--- a/drivers/acpi/acpica/hwsleep.c
+++ b/drivers/acpi/acpica/hwsleep.c
@@ -311,6 +311,18 @@ acpi_status acpi_hw_legacy_wake(u8 sleep_state)
 				    [ACPI_EVENT_SLEEP_BUTTON].
 				    status_register_id, ACPI_CLEAR_STATUS);
 
+	/* Enable pcie wake event if support */
+	if ((acpi_gbl_FADT.flags & ACPI_FADT_PCI_EXPRESS_WAKE)) {
+		(void)
+		acpi_write_bit_register(acpi_gbl_fixed_event_info
+				[ACPI_EVENT_PCIE_WAKE].
+				enable_register_id, ACPI_DISABLE_EVENT);
+		(void)
+		acpi_write_bit_register(acpi_gbl_fixed_event_info
+				[ACPI_EVENT_PCIE_WAKE].
+				status_register_id, ACPI_CLEAR_STATUS);
+	}
+
 	acpi_hw_execute_sleep_method(METHOD_PATHNAME__SST, ACPI_SST_WORKING);
 	return_ACPI_STATUS(status);
 }
diff --git a/drivers/acpi/acpica/utglobal.c b/drivers/acpi/acpica/utglobal.c
index 59a48371a7bc..16f7a206fc6d 100644
--- a/drivers/acpi/acpica/utglobal.c
+++ b/drivers/acpi/acpica/utglobal.c
@@ -186,6 +186,10 @@ struct acpi_fixed_event_info acpi_gbl_fixed_event_info[ACPI_NUM_FIXED_EVENTS] =
 					ACPI_BITREG_RT_CLOCK_ENABLE,
 					ACPI_BITMASK_RT_CLOCK_STATUS,
 					ACPI_BITMASK_RT_CLOCK_ENABLE},
+	/* ACPI_EVENT_PCIE_WAKE	    */ {ACPI_BITREG_PCIEXP_WAKE_STATUS,
+					ACPI_BITREG_PCIEXP_WAKE_DISABLE,
+					ACPI_BITMASK_PCIEXP_WAKE_STATUS,
+					ACPI_BITMASK_PCIEXP_WAKE_DISABLE},
 };
 #endif				/* !ACPI_REDUCED_HARDWARE */
 
diff --git a/include/acpi/actypes.h b/include/acpi/actypes.h
index 69e89d572b9e..5a5bdcfc38c3 100644
--- a/include/acpi/actypes.h
+++ b/include/acpi/actypes.h
@@ -719,7 +719,8 @@ typedef u32 acpi_event_type;
 #define ACPI_EVENT_POWER_BUTTON         2
 #define ACPI_EVENT_SLEEP_BUTTON         3
 #define ACPI_EVENT_RTC                  4
-#define ACPI_EVENT_MAX                  4
+#define ACPI_EVENT_PCIE_WAKE            5
+#define ACPI_EVENT_MAX                  5
 #define ACPI_NUM_FIXED_EVENTS           ACPI_EVENT_MAX + 1
 
 /*
-- 
2.27.0

Re: [PATCH V2 0/2] ACPI: Add LoongArch-related definitions

[Rafael J. Wysocki]

On Sun, Mar 6, 2022 at 12:17 PM Huacai Chen <chenhuacai@loongson.cn> wrote:
>
> LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V.
> LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit
> version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its
> boot protocol LoongArch-specific interrupt controllers (similar to APIC)
> are already added in the next revision of ACPI Specification (current
> revision is 6.4).
>
> This patchset are preparing to add LoongArch support in mainline kernel,
> we can see a snapshot here:
> https://github.com/loongson/linux/tree/loongarch-next
>
> Cross-compile tool chain to build kernel:
> https://github.com/loongson/build-tools/releases
>
> Loongson and LoongArch documentations:
> https://github.com/loongson/LoongArch-Documentation
>
> ECR for LoongArch-specific interrupt controllers:
> https://mantis.uefi.org/mantis/view.php?id=2203
> https://mantis.uefi.org/mantis/view.php?id=2313
>
> ACPI changes of LoongArch have been approved in the last year, but the
> new version of ACPI SPEC hasn't been made public yet.
>
> V2: Remove merged patches and update commit messages.
>
> Huacai Chen and Jianmin Lv(2):
>  ACPICA: MADT: Add LoongArch APICs support.
>  ACPICA: Events: Support fixed pcie wake event.

Both patches in this series are mostly ACPICA material which needs to
be submitted to the upstream ACPICA project via
https://github.com/acpica/acpica

It will be pulled by the Linux kernel from there.

>
> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> ---
>  drivers/acpi/acpica/evevent.c  |  17 ++++--
>  drivers/acpi/acpica/hwsleep.c  |  12 ++++
>  drivers/acpi/acpica/utglobal.c |   4 ++
>  drivers/acpi/tables.c          |  10 ++++

This tables.c change can be submitted as a separate patch when the
ACPICA changes get integrated.

>  include/acpi/actbl2.h          | 125 ++++++++++++++++++++++++++++++++++++++++-
>  include/acpi/actypes.h         |   3 +-
>  6 files changed, 163 insertions(+), 8 deletions(-)
> --
> 2.27.0
>

Re: [PATCH V2 0/2] ACPI: Add LoongArch-related definitions

[Huacai Chen]

Hi, Rafael,

On Wed, Mar 9, 2022 at 2:49 AM Rafael J. Wysocki <rafael@kernel.org> wrote:
>
> On Sun, Mar 6, 2022 at 12:17 PM Huacai Chen <chenhuacai@loongson.cn> wrote:
> >
> > LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V.
> > LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit
> > version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its
> > boot protocol LoongArch-specific interrupt controllers (similar to APIC)
> > are already added in the next revision of ACPI Specification (current
> > revision is 6.4).
> >
> > This patchset are preparing to add LoongArch support in mainline kernel,
> > we can see a snapshot here:
> > https://github.com/loongson/linux/tree/loongarch-next
> >
> > Cross-compile tool chain to build kernel:
> > https://github.com/loongson/build-tools/releases
> >
> > Loongson and LoongArch documentations:
> > https://github.com/loongson/LoongArch-Documentation
> >
> > ECR for LoongArch-specific interrupt controllers:
> > https://mantis.uefi.org/mantis/view.php?id=2203
> > https://mantis.uefi.org/mantis/view.php?id=2313
> >
> > ACPI changes of LoongArch have been approved in the last year, but the
> > new version of ACPI SPEC hasn't been made public yet.
> >
> > V2: Remove merged patches and update commit messages.
> >
> > Huacai Chen and Jianmin Lv(2):
> >  ACPICA: MADT: Add LoongArch APICs support.
> >  ACPICA: Events: Support fixed pcie wake event.
>
> Both patches in this series are mostly ACPICA material which needs to
> be submitted to the upstream ACPICA project via
> https://github.com/acpica/acpica
>
> It will be pulled by the Linux kernel from there.
I found that you are also a maintainer of the ACPICA project, do you
mean I should submit by github PR, not by maillist?

>
> >
> > Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
> > Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> > ---
> >  drivers/acpi/acpica/evevent.c  |  17 ++++--
> >  drivers/acpi/acpica/hwsleep.c  |  12 ++++
> >  drivers/acpi/acpica/utglobal.c |   4 ++
> >  drivers/acpi/tables.c          |  10 ++++
>
> This tables.c change can be submitted as a separate patch when the
> ACPICA changes get integrated.
Do you mean split the first patch into .h parts and .c parts, then
submit the .h parts and the second patch by github PR, then submit the
.c parts of the first patch by maillist?

Huacai
>
> >  include/acpi/actbl2.h          | 125 ++++++++++++++++++++++++++++++++++++++++-
> >  include/acpi/actypes.h         |   3 +-
> >  6 files changed, 163 insertions(+), 8 deletions(-)
> > --
> > 2.27.0
> >

Re: [PATCH V2 0/2] ACPI: Add LoongArch-related definitions

[Huacai Chen]

Hi, Rafael,

On Wed, Mar 9, 2022 at 1:29 PM Huacai Chen <chenhuacai@gmail.com> wrote:
>
> Hi, Rafael,
>
> On Wed, Mar 9, 2022 at 2:49 AM Rafael J. Wysocki <rafael@kernel.org> wrote:
> >
> > On Sun, Mar 6, 2022 at 12:17 PM Huacai Chen <chenhuacai@loongson.cn> wrote:
> > >
> > > LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V.
> > > LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit
> > > version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its
> > > boot protocol LoongArch-specific interrupt controllers (similar to APIC)
> > > are already added in the next revision of ACPI Specification (current
> > > revision is 6.4).
> > >
> > > This patchset are preparing to add LoongArch support in mainline kernel,
> > > we can see a snapshot here:
> > > https://github.com/loongson/linux/tree/loongarch-next
> > >
> > > Cross-compile tool chain to build kernel:
> > > https://github.com/loongson/build-tools/releases
> > >
> > > Loongson and LoongArch documentations:
> > > https://github.com/loongson/LoongArch-Documentation
> > >
> > > ECR for LoongArch-specific interrupt controllers:
> > > https://mantis.uefi.org/mantis/view.php?id=2203
> > > https://mantis.uefi.org/mantis/view.php?id=2313
> > >
> > > ACPI changes of LoongArch have been approved in the last year, but the
> > > new version of ACPI SPEC hasn't been made public yet.
> > >
> > > V2: Remove merged patches and update commit messages.
> > >
> > > Huacai Chen and Jianmin Lv(2):
> > >  ACPICA: MADT: Add LoongArch APICs support.
> > >  ACPICA: Events: Support fixed pcie wake event.
> >
> > Both patches in this series are mostly ACPICA material which needs to
> > be submitted to the upstream ACPICA project via
> > https://github.com/acpica/acpica
> >
> > It will be pulled by the Linux kernel from there.
> I found that you are also a maintainer of the ACPICA project, do you
> mean I should submit by github PR, not by maillist?
I submit ACPICA project, please review:
https://github.com/acpica/acpica/pull/757

Huacai
>
> >
> > >
> > > Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
> > > Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> > > ---
> > >  drivers/acpi/acpica/evevent.c  |  17 ++++--
> > >  drivers/acpi/acpica/hwsleep.c  |  12 ++++
> > >  drivers/acpi/acpica/utglobal.c |   4 ++
> > >  drivers/acpi/tables.c          |  10 ++++
> >
> > This tables.c change can be submitted as a separate patch when the
> > ACPICA changes get integrated.
> Do you mean split the first patch into .h parts and .c parts, then
> submit the .h parts and the second patch by github PR, then submit the
> .c parts of the first patch by maillist?
>
> Huacai
> >
> > >  include/acpi/actbl2.h          | 125 ++++++++++++++++++++++++++++++++++++++++-
> > >  include/acpi/actypes.h         |   3 +-
> > >  6 files changed, 163 insertions(+), 8 deletions(-)
> > > --
> > > 2.27.0
> > >

RE: [PATCH V2 0/2] ACPI: Add LoongArch-related definitions

[Moore, Robert]

-----Original Message-----
From: Huacai Chen <chenhuacai@gmail.com> 
Sent: Tuesday, March 08, 2022 9:30 PM
To: Rafael J. Wysocki <rafael@kernel.org>
Cc: Huacai Chen <chenhuacai@loongson.cn>; Rafael J . Wysocki <rjw@rjwysocki.net>; Len Brown <lenb@kernel.org>; Moore, Robert <robert.moore@intel.com>; Erik Kaneda <erik.kaneda@intel.com>; ACPI Devel Maling List <linux-acpi@vger.kernel.org>; open list:ACPI COMPONENT ARCHITECTURE (ACPICA) <devel@acpica.org>; Xuefeng Li <lixuefeng@loongson.cn>; Jiaxun Yang <jiaxun.yang@flygoat.com>; Jianmin Lv <lvjianmin@loongson.cn>
Subject: Re: [PATCH V2 0/2] ACPI: Add LoongArch-related definitions

Hi, Rafael,

On Wed, Mar 9, 2022 at 2:49 AM Rafael J. Wysocki <rafael@kernel.org> wrote:
>
> On Sun, Mar 6, 2022 at 12:17 PM Huacai Chen <chenhuacai@loongson.cn> wrote:
> >
> > LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V.
> > LoongArch includes a reduced 32-bit version (LA32R), a standard 
> > 32-bit version (LA32S) and a 64-bit version (LA64). LoongArch use 
> > ACPI as its boot protocol LoongArch-specific interrupt controllers 
> > (similar to APIC) are already added in the next revision of ACPI 
> > Specification (current revision is 6.4).
> >
> > This patchset are preparing to add LoongArch support in mainline 
> > kernel, we can see a snapshot here:
> > https://github.com/loongson/linux/tree/loongarch-next
> >
> > Cross-compile tool chain to build kernel:
> > https://github.com/loongson/build-tools/releases
> >
> > Loongson and LoongArch documentations:
> > https://github.com/loongson/LoongArch-Documentation
> >
> > ECR for LoongArch-specific interrupt controllers:
> > https://mantis.uefi.org/mantis/view.php?id=2203
> > https://mantis.uefi.org/mantis/view.php?id=2313
> >
> > ACPI changes of LoongArch have been approved in the last year, but 
> > the new version of ACPI SPEC hasn't been made public yet.
> >
> > V2: Remove merged patches and update commit messages.
> >
> > Huacai Chen and Jianmin Lv(2):
> >  ACPICA: MADT: Add LoongArch APICs support.
> >  ACPICA: Events: Support fixed pcie wake event.
>
> Both patches in this series are mostly ACPICA material which needs to 
> be submitted to the upstream ACPICA project via 
> https://github.com/acpica/acpica
>
> It will be pulled by the Linux kernel from there.
I found that you are also a maintainer of the ACPICA project, do you mean I should submit by github PR, not by maillist?

Yes.
>
> >
> > Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
> > Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> > ---
> >  drivers/acpi/acpica/evevent.c  |  17 ++++--  
> > drivers/acpi/acpica/hwsleep.c  |  12 ++++
> >  drivers/acpi/acpica/utglobal.c |   4 ++
> >  drivers/acpi/tables.c          |  10 ++++
>
> This tables.c change can be submitted as a separate patch when the 
> ACPICA changes get integrated.
Do you mean split the first patch into .h parts and .c parts, then submit the .h parts and the second patch by github PR, then submit the .c parts of the first patch by maillist?

No, that is not necessary.

Huacai
>
> >  include/acpi/actbl2.h          | 125 ++++++++++++++++++++++++++++++++++++++++-
> >  include/acpi/actypes.h         |   3 +-
> >  6 files changed, 163 insertions(+), 8 deletions(-)
> > --
> > 2.27.0
> >

Re: [PATCH V2 0/2] ACPI: Add LoongArch-related definitions

[Huacai Chen]

Hi, Moore,

On Fri, Mar 11, 2022 at 11:16 PM Moore, Robert <robert.moore@intel.com> wrote:
>
>
>
> -----Original Message-----
> From: Huacai Chen <chenhuacai@gmail.com>
> Sent: Tuesday, March 08, 2022 9:30 PM
> To: Rafael J. Wysocki <rafael@kernel.org>
> Cc: Huacai Chen <chenhuacai@loongson.cn>; Rafael J . Wysocki <rjw@rjwysocki.net>; Len Brown <lenb@kernel.org>; Moore, Robert <robert.moore@intel.com>; Erik Kaneda <erik.kaneda@intel.com>; ACPI Devel Maling List <linux-acpi@vger.kernel.org>; open list:ACPI COMPONENT ARCHITECTURE (ACPICA) <devel@acpica.org>; Xuefeng Li <lixuefeng@loongson.cn>; Jiaxun Yang <jiaxun.yang@flygoat.com>; Jianmin Lv <lvjianmin@loongson.cn>
> Subject: Re: [PATCH V2 0/2] ACPI: Add LoongArch-related definitions
>
> Hi, Rafael,
>
> On Wed, Mar 9, 2022 at 2:49 AM Rafael J. Wysocki <rafael@kernel.org> wrote:
> >
> > On Sun, Mar 6, 2022 at 12:17 PM Huacai Chen <chenhuacai@loongson.cn> wrote:
> > >
> > > LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V.
> > > LoongArch includes a reduced 32-bit version (LA32R), a standard
> > > 32-bit version (LA32S) and a 64-bit version (LA64). LoongArch use
> > > ACPI as its boot protocol LoongArch-specific interrupt controllers
> > > (similar to APIC) are already added in the next revision of ACPI
> > > Specification (current revision is 6.4).
> > >
> > > This patchset are preparing to add LoongArch support in mainline
> > > kernel, we can see a snapshot here:
> > > https://github.com/loongson/linux/tree/loongarch-next
> > >
> > > Cross-compile tool chain to build kernel:
> > > https://github.com/loongson/build-tools/releases
> > >
> > > Loongson and LoongArch documentations:
> > > https://github.com/loongson/LoongArch-Documentation
> > >
> > > ECR for LoongArch-specific interrupt controllers:
> > > https://mantis.uefi.org/mantis/view.php?id=2203
> > > https://mantis.uefi.org/mantis/view.php?id=2313
> > >
> > > ACPI changes of LoongArch have been approved in the last year, but
> > > the new version of ACPI SPEC hasn't been made public yet.
> > >
> > > V2: Remove merged patches and update commit messages.
> > >
> > > Huacai Chen and Jianmin Lv(2):
> > >  ACPICA: MADT: Add LoongArch APICs support.
> > >  ACPICA: Events: Support fixed pcie wake event.
> >
> > Both patches in this series are mostly ACPICA material which needs to
> > be submitted to the upstream ACPICA project via
> > https://github.com/acpica/acpica
> >
> > It will be pulled by the Linux kernel from there.
> I found that you are also a maintainer of the ACPICA project, do you mean I should submit by github PR, not by maillist?
>
> Yes.
I have already submit by github PR.

Huacai
> >
> > >
> > > Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
> > > Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> > > ---
> > >  drivers/acpi/acpica/evevent.c  |  17 ++++--
> > > drivers/acpi/acpica/hwsleep.c  |  12 ++++
> > >  drivers/acpi/acpica/utglobal.c |   4 ++
> > >  drivers/acpi/tables.c          |  10 ++++
> >
> > This tables.c change can be submitted as a separate patch when the
> > ACPICA changes get integrated.
> Do you mean split the first patch into .h parts and .c parts, then submit the .h parts and the second patch by github PR, then submit the .c parts of the first patch by maillist?
>
> No, that is not necessary.
>
> Huacai
> >
> > >  include/acpi/actbl2.h          | 125 ++++++++++++++++++++++++++++++++++++++++-
> > >  include/acpi/actypes.h         |   3 +-
> > >  6 files changed, 163 insertions(+), 8 deletions(-)
> > > --
> > > 2.27.0
> > >