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From: Asmaa Mnebhi <>
To: Andrew Lunn <>
Cc: Linus Walleij <>,
	Andy Shevchenko <>,
	"open list:GPIO SUBSYSTEM" <>,
	netdev <>,
	linux-kernel <>,
	ACPI Devel Maling List <>,
	Jakub Kicinski <>,
	Bartosz Golaszewski <>,
	"David S. Miller" <>,
	"Rafael J. Wysocki" <>,
	David Thompson <>
Subject: RE: [PATCH v3 1/2] gpio: mlxbf2: Introduce IRQ support
Date: Tue, 28 Sep 2021 15:02:02 +0000	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <YVHbo/>

> So the PHY is level based. The PHY is combing multiple interrupt sources 
> into one external interrupt. If any of those internal interrupt sources are
> active, the external interrupt is active. If there are > multiple active sources
> at once, the interrupt stays low, until they are all cleared. This means
> there is not an edge per interrupt. There is one edge when the first internal
> source occurs, and no more edges, > even if there are more internal interrupts.

> The general flow in the PHY interrupt handler is to read the interrupt status
> register, which tells you which internal interrupts have fired. You then
> address these internal interrupts one by one.

In KSZ9031, Register MII_KSZPHY_INTCS=0x1B reports all interrupt events and
clear on read. So if there are 4 different interrupts, once it is read once, all 4 clear at once.
The micrel.c driver has defined ack_interrupt to read the above reg and is called every time the
interrupt handler phy_interrupt is called. So in this case, we should be good.
The code flow in our case would look like this:
- 2 interrupt sources (for example, link down followed by link up) set in MII_KSZPHY_INTCS
- interrupt handler (phy_interrupt) reads MII_KSZPHY_INT which automatically clears both
- another internal source triggers and sets the register.
- The second edge will be caught accordingly by the GPIO.

> This can take some time, MDIO is a slow bus etc. While handling these interrupt sources,
> it could be another internal interrupt source triggers. This new internal interrupt source
> keeps the external interrupt active. But there has not been an edge, since the interrupt 
> handler is still clearing the sources which caused the first interrupt. With level interrupts,
> this is not an issue. When the interrupt handler exits, the interrupt is re-enabled. Since it
> is still active, due to the unhandled internal interrupt sources, the level interrupt
> immediately fires again. the handler then sees this new interrupt and handles it.
> At that point the level interrupt goes inactive.

  parent reply	other threads:[~2021-09-28 15:02 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-23 20:22 [PATCH v3 0/2] gpio: mlxbf2: Introduce proper interrupt handling Asmaa Mnebhi
2021-09-23 20:22 ` [PATCH v3 1/2] gpio: mlxbf2: Introduce IRQ support Asmaa Mnebhi
2021-09-24 11:46   ` Andrew Lunn
2021-09-24 23:48     ` Linus Walleij
2021-09-27 14:04       ` Asmaa Mnebhi
2021-09-27 14:08         ` Andrew Lunn
2021-09-27 14:19           ` Asmaa Mnebhi
2021-09-27 14:26             ` Asmaa Mnebhi
2021-09-27 14:56             ` Andrew Lunn
2021-09-27 15:52               ` Asmaa Mnebhi
2021-09-27 19:10                 ` Andrew Lunn
2021-09-29 19:14                   ` Asmaa Mnebhi
2021-09-28 15:02               ` Asmaa Mnebhi [this message]
2021-09-29 20:24                 ` Andrew Lunn
2021-10-08 14:47                   ` Asmaa Mnebhi
2021-09-23 20:22 ` [PATCH v3 2/2] net: mellanox: mlxbf_gige: Replace non-standard interrupt handling Asmaa Mnebhi
  -- strict thread matches above, loose matches on Subject: below --
2021-09-23 20:18 [PATCH v3 0/2] gpio: mlxbf2: Introduce proper " Asmaa Mnebhi
2021-09-23 20:18 ` [PATCH v3 1/2] gpio: mlxbf2: Introduce IRQ support Asmaa Mnebhi

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