From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: chengwei <foxfly.lai.tw@gmail.com>,
lee@kernel.org, broonie@kernel.org, rafael@kernel.org,
mika.westerberg@linux.intel.com, brgl@bgdev.pl,
linux-kernel@vger.kernel.org, gregkh@linuxfoundation.org,
lenb@kernel.org, linux-acpi@vger.kernel.org,
linux-gpio@vger.kernel.org, GaryWang@aaeon.com.tw,
musa.lin@yunjingtech.com, jack.chang@yunjingtech.com,
chengwei <larry.lai@yunjingtech.com>,
Javier Arteaga <javier@emutex.com>,
Nicola Lunghi <nicola.lunghi@emutex.com>
Subject: Re: [PATCH 5/5] pinctrl: Add support pin control for UP board CPLD/FPGA
Date: Fri, 21 Oct 2022 13:55:12 +0300 [thread overview]
Message-ID: <Y1J6kJ/sL4qqok16@smile.fi.intel.com> (raw)
In-Reply-To: <CACRpkdYfPT6-gt2RCxzPfy+GdkLYo8KP02CLLC+uY512AqPwNw@mail.gmail.com>
On Fri, Oct 21, 2022 at 11:09:27AM +0200, Linus Walleij wrote:
> On Wed, Oct 19, 2022 at 4:26 AM chengwei <foxfly.lai.tw@gmail.com> wrote:
> > The UP Squared board <http://www.upboard.com> implements certain
> > features (pin control) through an on-board FPGA.
> I am a bit confused by this driver. Andy pointed out some obvious nits that
> need to be fixed but the overall architecture here is also a bit puzzling.
>
> This seems to want to be compatible to Raspberry Pi (RPi), then which one?
>
> The driver seems to translate GPIO calls to "native GPIO" in some cases,
> which GPIO controller is that?
There is an SoC level GPIO (Apollo Lake I believe) and there is a discrete
component between it and user visible header (connector). This driver AFAIU
is about controlling that discrete component.
> Also I don't see why, normally a pin control
> driver is an agnostic back-end for a GPIO controller, so the GPIO driver
> should be the same (whatever "native") means, and this driver should
> not even implement a gpio chip, just let the GPIO driver do its job
> and call back into the pin control back-end whenever it needs it.
>
> Also we already have a driver that collects existing GPIOs to a new
> GPIO chip, the GPIO aggregator:
> drivers/gpio/gpio-aggregator.c
>
> Maybe if you can explain a bit about how this hardware works and why
> you have to do indirect calls to another GPIO controller, things will
> be easier to understand?
--
With Best Regards,
Andy Shevchenko
prev parent reply other threads:[~2022-10-21 10:55 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-19 2:24 [PATCH 0/5] Add support control UP board CPLD/FPGA pin control chengwei
2022-10-19 2:24 ` [PATCH 1/5] mfd: Add support for UP board CPLD/FPGA chengwei
2022-10-31 14:58 ` Lee Jones
[not found] ` <SG2PR06MB37422173908A6584B3D6D349F93F9@SG2PR06MB3742.apcprd06.prod.outlook.com>
2022-11-08 15:53 ` 回覆: " gregkh
[not found] ` <SG2PR06MB3742D3714B6A255914DC73E4F93F9@SG2PR06MB3742.apcprd06.prod.outlook.com>
2022-11-08 17:24 ` gregkh
2022-11-14 10:09 ` Lee Jones
2022-10-19 2:24 ` [PATCH 2/5] regmap: Expose regmap_writeable function to check if a register is writable chengwei
2022-10-19 11:57 ` Mark Brown
2022-10-19 2:24 ` [PATCH 3/5] ACPI: acpi_node_add_pin_mapping added to header file chengwei
2022-10-19 13:32 ` Andy Shevchenko
2022-10-19 2:24 ` [PATCH 4/5] GPIO ACPI: Add support to map GPIO resources to ranges chengwei
2022-10-19 13:36 ` Andy Shevchenko
2022-10-19 2:24 ` [PATCH 5/5] pinctrl: Add support pin control for UP board CPLD/FPGA chengwei
2022-10-20 16:58 ` Andy Shevchenko
2022-10-21 9:09 ` Linus Walleij
2022-10-21 10:55 ` Andy Shevchenko [this message]
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