[PATCH 0/5] Thermal zone configuration for Meson8/Meson8b/Meson8m2

[PATCH 0/5] Thermal zone configuration for Meson8/Meson8b/Meson8m2

[Martin Blumenstingl]

This adds the thermal zone configuration on Meson8/Meson8b/Meson8m2
SoCs. The thermal sensor reading is taken from SAR ADC. With
"generic-adc-thermal" it is then used to configure the thermal zone.

CPU and GPU frequencies can both be managed. The vendor kernel also
manages the number of active GPU pixel processor cores. This is not
supported yet so we skip it.


Martin Blumenstingl (5):
  ARM: dts: meson: move iio-hwmon for the SoC temperature to meson.dtsi
  ARM: dts: meson: add the ADC thermal sensor to meson.dtsi
  ARM: dts: meson8: add the thermal-zones with cooling configuration
  ARM: dts: meson8b: add the thermal-zones with cooling configuration
  ARM: multi_v7_defconfig: Enable support for the ADC thermal sensor

 arch/arm/boot/dts/meson.dtsi              | 12 +++++
 arch/arm/boot/dts/meson8.dtsi             | 54 +++++++++++++++++++++++
 arch/arm/boot/dts/meson8b-ec100.dts       |  5 ---
 arch/arm/boot/dts/meson8b-mxq.dts         |  5 ---
 arch/arm/boot/dts/meson8b-odroidc1.dts    |  5 ---
 arch/arm/boot/dts/meson8b.dtsi            | 54 +++++++++++++++++++++++
 arch/arm/boot/dts/meson8m2-mxiii-plus.dts |  5 ---
 arch/arm/configs/multi_v7_defconfig       |  1 +
 8 files changed, 121 insertions(+), 20 deletions(-)

-- 
2.29.2


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[PATCH 1/5] ARM: dts: meson: move iio-hwmon for the SoC temperature to meson.dtsi

[Martin Blumenstingl]

The SoC temperature can be retrieved from ADC channel 8 on all 32-bit
SoCs (Meson6, Meson8, Meson8b and Meson8m2). Move the iio-hwmon instance
to meson.dtsi instead of duplicating it in all board.dts.
If the temperature sensor calibration data is missing for a board then
iio-hwmon will simply not probe.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson.dtsi              | 5 +++++
 arch/arm/boot/dts/meson8b-ec100.dts       | 5 -----
 arch/arm/boot/dts/meson8b-mxq.dts         | 5 -----
 arch/arm/boot/dts/meson8b-odroidc1.dts    | 5 -----
 arch/arm/boot/dts/meson8m2-mxiii-plus.dts | 5 -----
 5 files changed, 5 insertions(+), 20 deletions(-)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index 7649dd1e0b9e..5f074f7aa1a2 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -11,6 +11,11 @@ / {
 	#size-cells = <1>;
 	interrupt-parent = <&gic>;
 
+	iio-hwmon {
+		compatible = "iio-hwmon";
+		io-channels = <&saradc 8>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts
index ed06102a4014..8e48ccc6b634 100644
--- a/arch/arm/boot/dts/meson8b-ec100.dts
+++ b/arch/arm/boot/dts/meson8b-ec100.dts
@@ -70,11 +70,6 @@ gpio-poweroff {
 		timeout-ms = <20000>;
 	};
 
-	iio-hwmon {
-		compatible = "iio-hwmon";
-		io-channels = <&saradc 8>;
-	};
-
 	leds {
 		compatible = "gpio-leds";
 
diff --git a/arch/arm/boot/dts/meson8b-mxq.dts b/arch/arm/boot/dts/meson8b-mxq.dts
index 33037ef62d0a..f3937d55472d 100644
--- a/arch/arm/boot/dts/meson8b-mxq.dts
+++ b/arch/arm/boot/dts/meson8b-mxq.dts
@@ -27,11 +27,6 @@ memory {
 		reg = <0x40000000 0x40000000>;
 	};
 
-	iio-hwmon {
-		compatible = "iio-hwmon";
-		io-channels = <&saradc 8>;
-	};
-
 	vcck: regulator-vcck {
 		compatible = "pwm-regulator";
 
diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts
index 5963566dbcc9..c440ef94e082 100644
--- a/arch/arm/boot/dts/meson8b-odroidc1.dts
+++ b/arch/arm/boot/dts/meson8b-odroidc1.dts
@@ -85,11 +85,6 @@ tf_io: gpio-regulator-tf_io {
 			  1800000 1>;
 	};
 
-	iio-hwmon {
-		compatible = "iio-hwmon";
-		io-channels = <&saradc 8>;
-	};
-
 	rtc32k_xtal: rtc32k-xtal-clk {
 		/* X3 in the schematics */
 		compatible = "fixed-clock";
diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
index 8f4eb1ed4581..fa6d55f1cfb9 100644
--- a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
+++ b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
@@ -45,11 +45,6 @@ button-function {
 		};
 	};
 
-	iio-hwmon {
-		compatible = "iio-hwmon";
-		io-channels = <&saradc 8>;
-	};
-
 	vcc_3v3: regulator-vcc3v3 {
 		compatible = "regulator-fixed";
 		regulator-name = "VCC3V3";
-- 
2.29.2


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Re: [PATCH 1/5] ARM: dts: meson: move iio-hwmon for the SoC temperature to meson.dtsi

[Neil Armstrong]

On 21/12/2020 19:13, Martin Blumenstingl wrote:
> The SoC temperature can be retrieved from ADC channel 8 on all 32-bit
> SoCs (Meson6, Meson8, Meson8b and Meson8m2). Move the iio-hwmon instance
> to meson.dtsi instead of duplicating it in all board.dts.
> If the temperature sensor calibration data is missing for a board then
> iio-hwmon will simply not probe.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  arch/arm/boot/dts/meson.dtsi              | 5 +++++
>  arch/arm/boot/dts/meson8b-ec100.dts       | 5 -----
>  arch/arm/boot/dts/meson8b-mxq.dts         | 5 -----
>  arch/arm/boot/dts/meson8b-odroidc1.dts    | 5 -----
>  arch/arm/boot/dts/meson8m2-mxiii-plus.dts | 5 -----
>  5 files changed, 5 insertions(+), 20 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
> index 7649dd1e0b9e..5f074f7aa1a2 100644
> --- a/arch/arm/boot/dts/meson.dtsi
> +++ b/arch/arm/boot/dts/meson.dtsi
> @@ -11,6 +11,11 @@ / {
>  	#size-cells = <1>;
>  	interrupt-parent = <&gic>;
>  
> +	iio-hwmon {
> +		compatible = "iio-hwmon";
> +		io-channels = <&saradc 8>;
> +	};
> +
>  	soc {
>  		compatible = "simple-bus";
>  		#address-cells = <1>;
> diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts
> index ed06102a4014..8e48ccc6b634 100644
> --- a/arch/arm/boot/dts/meson8b-ec100.dts
> +++ b/arch/arm/boot/dts/meson8b-ec100.dts
> @@ -70,11 +70,6 @@ gpio-poweroff {
>  		timeout-ms = <20000>;
>  	};
>  
> -	iio-hwmon {
> -		compatible = "iio-hwmon";
> -		io-channels = <&saradc 8>;
> -	};
> -
>  	leds {
>  		compatible = "gpio-leds";
>  
> diff --git a/arch/arm/boot/dts/meson8b-mxq.dts b/arch/arm/boot/dts/meson8b-mxq.dts
> index 33037ef62d0a..f3937d55472d 100644
> --- a/arch/arm/boot/dts/meson8b-mxq.dts
> +++ b/arch/arm/boot/dts/meson8b-mxq.dts
> @@ -27,11 +27,6 @@ memory {
>  		reg = <0x40000000 0x40000000>;
>  	};
>  
> -	iio-hwmon {
> -		compatible = "iio-hwmon";
> -		io-channels = <&saradc 8>;
> -	};
> -
>  	vcck: regulator-vcck {
>  		compatible = "pwm-regulator";
>  
> diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts
> index 5963566dbcc9..c440ef94e082 100644
> --- a/arch/arm/boot/dts/meson8b-odroidc1.dts
> +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts
> @@ -85,11 +85,6 @@ tf_io: gpio-regulator-tf_io {
>  			  1800000 1>;
>  	};
>  
> -	iio-hwmon {
> -		compatible = "iio-hwmon";
> -		io-channels = <&saradc 8>;
> -	};
> -
>  	rtc32k_xtal: rtc32k-xtal-clk {
>  		/* X3 in the schematics */
>  		compatible = "fixed-clock";
> diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
> index 8f4eb1ed4581..fa6d55f1cfb9 100644
> --- a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
> +++ b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
> @@ -45,11 +45,6 @@ button-function {
>  		};
>  	};
>  
> -	iio-hwmon {
> -		compatible = "iio-hwmon";
> -		io-channels = <&saradc 8>;
> -	};
> -
>  	vcc_3v3: regulator-vcc3v3 {
>  		compatible = "regulator-fixed";
>  		regulator-name = "VCC3V3";
> 

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

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[PATCH 2/5] ARM: dts: meson: add the ADC thermal sensor to meson.dtsi

[Martin Blumenstingl]

The SoC temperature can be retrieved from ADC channel 8 on all 32-bit
SoCs (Meson6, Meson8, Meson8b and Meson8m2). Add a "generic-adc-thermal"
instance to meson.dtsi so the thermal sensor is available for all SoCs.
If the temperature sensor calibration data is missing for a board then
the "generic-adc-thermal" will not probe and not register a thermal
sensor.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index 5f074f7aa1a2..e0ca5f08d07d 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -298,6 +298,13 @@ efuse: nvmem@0 {
 		};
 	};
 
+	thermal_sensor: thermal-sensor {
+		compatible = "generic-adc-thermal";
+		#thermal-sensor-cells = <0>;
+		io-channels = <&saradc 8>;
+		io-channel-names = "sensor-channel";
+	};
+
 	xtal: xtal-clk {
 		compatible = "fixed-clock";
 		clock-frequency = <24000000>;
-- 
2.29.2


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Re: [PATCH 2/5] ARM: dts: meson: add the ADC thermal sensor to meson.dtsi

[Neil Armstrong]

On 21/12/2020 19:13, Martin Blumenstingl wrote:
> The SoC temperature can be retrieved from ADC channel 8 on all 32-bit
> SoCs (Meson6, Meson8, Meson8b and Meson8m2). Add a "generic-adc-thermal"
> instance to meson.dtsi so the thermal sensor is available for all SoCs.
> If the temperature sensor calibration data is missing for a board then
> the "generic-adc-thermal" will not probe and not register a thermal
> sensor.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  arch/arm/boot/dts/meson.dtsi | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
> index 5f074f7aa1a2..e0ca5f08d07d 100644
> --- a/arch/arm/boot/dts/meson.dtsi
> +++ b/arch/arm/boot/dts/meson.dtsi
> @@ -298,6 +298,13 @@ efuse: nvmem@0 {
>  		};
>  	};
>  
> +	thermal_sensor: thermal-sensor {
> +		compatible = "generic-adc-thermal";
> +		#thermal-sensor-cells = <0>;
> +		io-channels = <&saradc 8>;
> +		io-channel-names = "sensor-channel";
> +	};
> +
>  	xtal: xtal-clk {
>  		compatible = "fixed-clock";
>  		clock-frequency = <24000000>;
> 

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

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[PATCH 3/5] ARM: dts: meson8: add the thermal-zones with cooling configuration

[Martin Blumenstingl]

The vendor kernel uses the following thermal-zone settings:
<= 70°C:
- CPU frequency limited to 1.608GHz
- GPU limited to 511MHz and 5 cores (pixel processors)

<= 80°C:
- CPU frequency limited to 1.2GHz
- GPU limited to 435MHz and 4 cores (pixel processors)

<= 90°C:
- CPU frequency limited to 0.804GHz
- GPU limited to 328MHz and 3 cores (pixel processors)

Add simplified thermal configuration which is taken from the
GXBB/GXL/GXM SoC family (which uses the same manufacturing process and
has the same maximum junction temperature of 125°C). With this the
thermal framework will try to keep the SoC temperature at or below 80°C
which is identical to the vendor kernel (with the exception of one GPU
pixel processor).

The number of GPU cores are not taken into account as this is not
supported.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8.dtsi | 54 +++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 04688e8abce2..420324ea2ad7 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/power/meson8-power.h>
 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
+#include <dt-bindings/thermal/thermal.h>
 #include "meson.dtsi"
 
 / {
@@ -28,6 +29,7 @@ cpu0: cpu@200 {
 			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
 			operating-points-v2 = <&cpu_opp_table>;
 			clocks = <&clkc CLKID_CPUCLK>;
+			#cooling-cells = <2>; /* min followed by max */
 		};
 
 		cpu1: cpu@201 {
@@ -39,6 +41,7 @@ cpu1: cpu@201 {
 			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
 			operating-points-v2 = <&cpu_opp_table>;
 			clocks = <&clkc CLKID_CPUCLK>;
+			#cooling-cells = <2>; /* min followed by max */
 		};
 
 		cpu2: cpu@202 {
@@ -50,6 +53,7 @@ cpu2: cpu@202 {
 			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
 			operating-points-v2 = <&cpu_opp_table>;
 			clocks = <&clkc CLKID_CPUCLK>;
+			#cooling-cells = <2>; /* min followed by max */
 		};
 
 		cpu3: cpu@203 {
@@ -61,6 +65,7 @@ cpu3: cpu@203 {
 			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
 			operating-points-v2 = <&cpu_opp_table>;
 			clocks = <&clkc CLKID_CPUCLK>;
+			#cooling-cells = <2>; /* min followed by max */
 		};
 	};
 
@@ -190,6 +195,54 @@ power-firmware@4f00000 {
 		};
 	};
 
+	thermal-zones {
+		soc {
+			polling-delay-passive = <250>; /* milliseconds */
+			polling-delay = <1000>; /* milliseconds */
+			thermal-sensors = <&thermal_sensor>;
+
+			cooling-maps {
+				map0 {
+					trip = <&soc_passive>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map1 {
+					trip = <&soc_hot>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+
+			trips {
+				soc_passive: soc-passive {
+					temperature = <80000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "passive";
+				};
+
+				soc_hot: soc-hot {
+					temperature = <90000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "hot";
+				};
+
+				soc_critical: soc-critical {
+					temperature = <110000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "critical";
+				};
+			};
+		};
+	};
+
 	mmcbus: bus@c8000000 {
 		compatible = "simple-bus";
 		reg = <0xc8000000 0x8000>;
@@ -254,6 +307,7 @@ mali: gpu@c0000 {
 			clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
 			clock-names = "bus", "core";
 			operating-points-v2 = <&gpu_opp_table>;
+			#cooling-cells = <2>; /* min followed by max */
 		};
 	};
 }; /* end of / */
-- 
2.29.2


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Re: [PATCH 3/5] ARM: dts: meson8: add the thermal-zones with cooling configuration

[Neil Armstrong]

On 21/12/2020 19:13, Martin Blumenstingl wrote:
> The vendor kernel uses the following thermal-zone settings:
> <= 70°C:
> - CPU frequency limited to 1.608GHz
> - GPU limited to 511MHz and 5 cores (pixel processors)
> 
> <= 80°C:
> - CPU frequency limited to 1.2GHz
> - GPU limited to 435MHz and 4 cores (pixel processors)
> 
> <= 90°C:
> - CPU frequency limited to 0.804GHz
> - GPU limited to 328MHz and 3 cores (pixel processors)
> 
> Add simplified thermal configuration which is taken from the
> GXBB/GXL/GXM SoC family (which uses the same manufacturing process and
> has the same maximum junction temperature of 125°C). With this the
> thermal framework will try to keep the SoC temperature at or below 80°C
> which is identical to the vendor kernel (with the exception of one GPU
> pixel processor).
> 
> The number of GPU cores are not taken into account as this is not
> supported.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  arch/arm/boot/dts/meson8.dtsi | 54 +++++++++++++++++++++++++++++++++++
>  1 file changed, 54 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
> index 04688e8abce2..420324ea2ad7 100644
> --- a/arch/arm/boot/dts/meson8.dtsi
> +++ b/arch/arm/boot/dts/meson8.dtsi
> @@ -9,6 +9,7 @@
>  #include <dt-bindings/power/meson8-power.h>
>  #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
>  #include <dt-bindings/reset/amlogic,meson8b-reset.h>
> +#include <dt-bindings/thermal/thermal.h>
>  #include "meson.dtsi"
>  
>  / {
> @@ -28,6 +29,7 @@ cpu0: cpu@200 {
>  			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
>  			operating-points-v2 = <&cpu_opp_table>;
>  			clocks = <&clkc CLKID_CPUCLK>;
> +			#cooling-cells = <2>; /* min followed by max */
>  		};
>  
>  		cpu1: cpu@201 {
> @@ -39,6 +41,7 @@ cpu1: cpu@201 {
>  			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
>  			operating-points-v2 = <&cpu_opp_table>;
>  			clocks = <&clkc CLKID_CPUCLK>;
> +			#cooling-cells = <2>; /* min followed by max */
>  		};
>  
>  		cpu2: cpu@202 {
> @@ -50,6 +53,7 @@ cpu2: cpu@202 {
>  			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
>  			operating-points-v2 = <&cpu_opp_table>;
>  			clocks = <&clkc CLKID_CPUCLK>;
> +			#cooling-cells = <2>; /* min followed by max */
>  		};
>  
>  		cpu3: cpu@203 {
> @@ -61,6 +65,7 @@ cpu3: cpu@203 {
>  			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
>  			operating-points-v2 = <&cpu_opp_table>;
>  			clocks = <&clkc CLKID_CPUCLK>;
> +			#cooling-cells = <2>; /* min followed by max */
>  		};
>  	};
>  
> @@ -190,6 +195,54 @@ power-firmware@4f00000 {
>  		};
>  	};
>  
> +	thermal-zones {
> +		soc {
> +			polling-delay-passive = <250>; /* milliseconds */
> +			polling-delay = <1000>; /* milliseconds */
> +			thermal-sensors = <&thermal_sensor>;
> +
> +			cooling-maps {
> +				map0 {
> +					trip = <&soc_passive>;
> +					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +
> +				map1 {
> +					trip = <&soc_hot>;
> +					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +			};
> +
> +			trips {
> +				soc_passive: soc-passive {
> +					temperature = <80000>; /* millicelsius */
> +					hysteresis = <2000>; /* millicelsius */
> +					type = "passive";
> +				};
> +
> +				soc_hot: soc-hot {
> +					temperature = <90000>; /* millicelsius */
> +					hysteresis = <2000>; /* millicelsius */
> +					type = "hot";
> +				};
> +
> +				soc_critical: soc-critical {
> +					temperature = <110000>; /* millicelsius */
> +					hysteresis = <2000>; /* millicelsius */
> +					type = "critical";
> +				};
> +			};
> +		};
> +	};
> +
>  	mmcbus: bus@c8000000 {
>  		compatible = "simple-bus";
>  		reg = <0xc8000000 0x8000>;
> @@ -254,6 +307,7 @@ mali: gpu@c0000 {
>  			clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
>  			clock-names = "bus", "core";
>  			operating-points-v2 = <&gpu_opp_table>;
> +			#cooling-cells = <2>; /* min followed by max */
>  		};
>  	};
>  }; /* end of / */
> 

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

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[PATCH 4/5] ARM: dts: meson8b: add the thermal-zones with cooling configuration

[Martin Blumenstingl]

The vendor kernel uses the following thermal-zone settings:
<= 70°C:
- CPU frequency limited to 1.488GHz
- GPU limited to 511MHz and 2 cores (pixel processors)

<= 80°C:
- CPU frequency limited to 1.2GHz
- GPU limited to 435MHz and 2 cores (pixel processors)

<= 90°C:
- CPU frequency limited to 0.804GHz
- GPU limited to 328MHz and 1 core (pixel processor)

Add simplified thermal configuration which is taken from the
GXBB/GXL/GXM SoC family (which uses the same manufacturing process and
has the same maximum junction temperature of 125°C). With this the
thermal framework will try to keep the SoC temperature at or below 80°C
which is identical to the vendor kernel (with the exception of one CPU
frequency step from 1.488GHz to 1.536GHz).

The number of GPU cores are not taken into account as this is not
supported.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8b.dtsi | 54 ++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 2401cdf5f751..dbf7963b6c87 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -10,6 +10,7 @@
 #include <dt-bindings/power/meson8-power.h>
 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
+#include <dt-bindings/thermal/thermal.h>
 #include "meson.dtsi"
 
 / {
@@ -26,6 +27,7 @@ cpu0: cpu@200 {
 			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
 			operating-points-v2 = <&cpu_opp_table>;
 			clocks = <&clkc CLKID_CPUCLK>;
+			#cooling-cells = <2>; /* min followed by max */
 		};
 
 		cpu1: cpu@201 {
@@ -37,6 +39,7 @@ cpu1: cpu@201 {
 			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
 			operating-points-v2 = <&cpu_opp_table>;
 			clocks = <&clkc CLKID_CPUCLK>;
+			#cooling-cells = <2>; /* min followed by max */
 		};
 
 		cpu2: cpu@202 {
@@ -48,6 +51,7 @@ cpu2: cpu@202 {
 			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
 			operating-points-v2 = <&cpu_opp_table>;
 			clocks = <&clkc CLKID_CPUCLK>;
+			#cooling-cells = <2>; /* min followed by max */
 		};
 
 		cpu3: cpu@203 {
@@ -59,6 +63,7 @@ cpu3: cpu@203 {
 			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
 			operating-points-v2 = <&cpu_opp_table>;
 			clocks = <&clkc CLKID_CPUCLK>;
+			#cooling-cells = <2>; /* min followed by max */
 		};
 	};
 
@@ -167,6 +172,54 @@ hwrom@0 {
 		};
 	};
 
+	thermal-zones {
+		soc {
+			polling-delay-passive = <250>; /* milliseconds */
+			polling-delay = <1000>; /* milliseconds */
+			thermal-sensors = <&thermal_sensor>;
+
+			cooling-maps {
+				map0 {
+					trip = <&soc_passive>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map1 {
+					trip = <&soc_hot>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+
+			trips {
+				soc_passive: soc-passive {
+					temperature = <80000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "passive";
+				};
+
+				soc_hot: soc-hot {
+					temperature = <90000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "hot";
+				};
+
+				soc_critical: soc-critical {
+					temperature = <110000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "critical";
+				};
+			};
+		};
+	};
+
 	mmcbus: bus@c8000000 {
 		compatible = "simple-bus";
 		reg = <0xc8000000 0x8000>;
@@ -221,6 +274,7 @@ mali: gpu@c0000 {
 			clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
 			clock-names = "bus", "core";
 			operating-points-v2 = <&gpu_opp_table>;
+			#cooling-cells = <2>; /* min followed by max */
 		};
 	};
 }; /* end of / */
-- 
2.29.2


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Re: [PATCH 4/5] ARM: dts: meson8b: add the thermal-zones with cooling configuration

[Neil Armstrong]

On 21/12/2020 19:13, Martin Blumenstingl wrote:
> The vendor kernel uses the following thermal-zone settings:
> <= 70°C:
> - CPU frequency limited to 1.488GHz
> - GPU limited to 511MHz and 2 cores (pixel processors)
> 
> <= 80°C:
> - CPU frequency limited to 1.2GHz
> - GPU limited to 435MHz and 2 cores (pixel processors)
> 
> <= 90°C:
> - CPU frequency limited to 0.804GHz
> - GPU limited to 328MHz and 1 core (pixel processor)
> 
> Add simplified thermal configuration which is taken from the
> GXBB/GXL/GXM SoC family (which uses the same manufacturing process and
> has the same maximum junction temperature of 125°C). With this the
> thermal framework will try to keep the SoC temperature at or below 80°C
> which is identical to the vendor kernel (with the exception of one CPU
> frequency step from 1.488GHz to 1.536GHz).
> 
> The number of GPU cores are not taken into account as this is not
> supported.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  arch/arm/boot/dts/meson8b.dtsi | 54 ++++++++++++++++++++++++++++++++++
>  1 file changed, 54 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
> index 2401cdf5f751..dbf7963b6c87 100644
> --- a/arch/arm/boot/dts/meson8b.dtsi
> +++ b/arch/arm/boot/dts/meson8b.dtsi
> @@ -10,6 +10,7 @@
>  #include <dt-bindings/power/meson8-power.h>
>  #include <dt-bindings/reset/amlogic,meson8b-reset.h>
>  #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
> +#include <dt-bindings/thermal/thermal.h>
>  #include "meson.dtsi"
>  
>  / {
> @@ -26,6 +27,7 @@ cpu0: cpu@200 {
>  			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
>  			operating-points-v2 = <&cpu_opp_table>;
>  			clocks = <&clkc CLKID_CPUCLK>;
> +			#cooling-cells = <2>; /* min followed by max */
>  		};
>  
>  		cpu1: cpu@201 {
> @@ -37,6 +39,7 @@ cpu1: cpu@201 {
>  			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
>  			operating-points-v2 = <&cpu_opp_table>;
>  			clocks = <&clkc CLKID_CPUCLK>;
> +			#cooling-cells = <2>; /* min followed by max */
>  		};
>  
>  		cpu2: cpu@202 {
> @@ -48,6 +51,7 @@ cpu2: cpu@202 {
>  			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
>  			operating-points-v2 = <&cpu_opp_table>;
>  			clocks = <&clkc CLKID_CPUCLK>;
> +			#cooling-cells = <2>; /* min followed by max */
>  		};
>  
>  		cpu3: cpu@203 {
> @@ -59,6 +63,7 @@ cpu3: cpu@203 {
>  			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
>  			operating-points-v2 = <&cpu_opp_table>;
>  			clocks = <&clkc CLKID_CPUCLK>;
> +			#cooling-cells = <2>; /* min followed by max */
>  		};
>  	};
>  
> @@ -167,6 +172,54 @@ hwrom@0 {
>  		};
>  	};
>  
> +	thermal-zones {
> +		soc {
> +			polling-delay-passive = <250>; /* milliseconds */
> +			polling-delay = <1000>; /* milliseconds */
> +			thermal-sensors = <&thermal_sensor>;
> +
> +			cooling-maps {
> +				map0 {
> +					trip = <&soc_passive>;
> +					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +
> +				map1 {
> +					trip = <&soc_hot>;
> +					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +			};
> +
> +			trips {
> +				soc_passive: soc-passive {
> +					temperature = <80000>; /* millicelsius */
> +					hysteresis = <2000>; /* millicelsius */
> +					type = "passive";
> +				};
> +
> +				soc_hot: soc-hot {
> +					temperature = <90000>; /* millicelsius */
> +					hysteresis = <2000>; /* millicelsius */
> +					type = "hot";
> +				};
> +
> +				soc_critical: soc-critical {
> +					temperature = <110000>; /* millicelsius */
> +					hysteresis = <2000>; /* millicelsius */
> +					type = "critical";
> +				};
> +			};
> +		};
> +	};
> +
>  	mmcbus: bus@c8000000 {
>  		compatible = "simple-bus";
>  		reg = <0xc8000000 0x8000>;
> @@ -221,6 +274,7 @@ mali: gpu@c0000 {
>  			clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
>  			clock-names = "bus", "core";
>  			operating-points-v2 = <&gpu_opp_table>;
> +			#cooling-cells = <2>; /* min followed by max */
>  		};
>  	};
>  }; /* end of / */
> 

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

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[PATCH 5/5] ARM: multi_v7_defconfig: Enable support for the ADC thermal sensor

[Martin Blumenstingl]

32-bit Amlogic Meson platforms are using a special ADC channel to read
the SoC temperature. Enable the "generic ADC thermal" driver so this
data can be used to cool the SoC for example by reduing the maximum CPU
and GPU frequencies temporarily.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/configs/multi_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index c5f25710fedc..0a55240ce2fc 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -515,6 +515,7 @@ CONFIG_ARMADA_THERMAL=y
 CONFIG_BCM2711_THERMAL=m
 CONFIG_BCM2835_THERMAL=m
 CONFIG_BRCMSTB_THERMAL=m
+CONFIG_GENERIC_ADC_THERMAL=m
 CONFIG_ST_THERMAL_MEMMAP=y
 CONFIG_UNIPHIER_THERMAL=y
 CONFIG_DA9063_WATCHDOG=m
-- 
2.29.2


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Re: [PATCH 0/5] Thermal zone configuration for Meson8/Meson8b/Meson8m2

[Kevin Hilman]

On Mon, 21 Dec 2020 19:13:01 +0100, Martin Blumenstingl wrote:
> This adds the thermal zone configuration on Meson8/Meson8b/Meson8m2
> SoCs. The thermal sensor reading is taken from SAR ADC. With
> "generic-adc-thermal" it is then used to configure the thermal zone.
> 
> CPU and GPU frequencies can both be managed. The vendor kernel also
> manages the number of active GPU pixel processor cores. This is not
> supported yet so we skip it.
> 
> [...]

Applied, thanks!

[1/5] ARM: dts: meson: move iio-hwmon for the SoC temperature to meson.dtsi
      commit: e9ced25e41588a2ff95280b4d3dabf3a0865513b
[2/5] ARM: dts: meson: add the ADC thermal sensor to meson.dtsi
      commit: c8559511107120403f7810428f50fc68fd77ed5a
[3/5] ARM: dts: meson8: add the thermal-zones with cooling configuration
      commit: ecdb744b1f819949f783508331ff6ff8a6a45730
[4/5] ARM: dts: meson8b: add the thermal-zones with cooling configuration
      commit: 9073f694efd8733b0e7c97d3396d81161bd05582
[5/5] ARM: multi_v7_defconfig: Enable support for the ADC thermal sensor
      commit: 726731566a862fa375de44313f601e49c4d40377

Best regards,
-- 
Kevin Hilman <khilman@baylibre.com>

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