* [PATCH 1/2] clk: meson: axg: Remove MIPI enable clock gate
2020-03-09 21:01 [PATCH 0/2] clk: meson: axg: Remove MIPI enable clock gate Remi Pommarel
@ 2020-03-09 21:01 ` Remi Pommarel
2020-03-09 21:01 ` [PATCH 2/2] clk: meson-axg: remove CLKID_MIPI_ENABLE Remi Pommarel
2020-03-10 8:05 ` [PATCH 0/2] clk: meson: axg: Remove MIPI enable clock gate Jerome Brunet
2 siblings, 0 replies; 5+ messages in thread
From: Remi Pommarel @ 2020-03-09 21:01 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Michael Turquette, Stephen Boyd,
Kevin Hilman, Rob Herring, Mark Rutland
Cc: linux-amlogic, Remi Pommarel, linux-clk, linux-arm-kernel, linux-kernel
On AXG platforms HHI_MIPI_CNTL0 is part of the MIPI/PCIe analog PHY
region and is not related to clock one and can be removed from it.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
---
drivers/clk/meson/axg.c | 3 ---
drivers/clk/meson/axg.h | 1 -
2 files changed, 4 deletions(-)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 13fc0006f63d..870e90a863fa 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -1141,7 +1141,6 @@ static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
-static MESON_GATE(axg_mipi_enable, HHI_MIPI_CNTL0, 29);
/* Always On (AO) domain gates */
@@ -1236,7 +1235,6 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = {
[CLKID_PCIE_REF] = &axg_pcie_ref.hw,
[CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
[CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
- [CLKID_MIPI_ENABLE] = &axg_mipi_enable.hw,
[CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
[CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
[CLKID_GEN_CLK] = &axg_gen_clk.hw,
@@ -1331,7 +1329,6 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
&axg_pcie_ref,
&axg_pcie_cml_en0,
&axg_pcie_cml_en1,
- &axg_mipi_enable,
&axg_gen_clk_sel,
&axg_gen_clk_div,
&axg_gen_clk,
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h
index 0431dabac629..fafe31739d0d 100644
--- a/drivers/clk/meson/axg.h
+++ b/drivers/clk/meson/axg.h
@@ -16,7 +16,6 @@
* Register offsets from the data sheet must be multiplied by 4 before
* adding them to the base address to get the right value.
*/
-#define HHI_MIPI_CNTL0 0x00
#define HHI_GP0_PLL_CNTL 0x40
#define HHI_GP0_PLL_CNTL2 0x44
#define HHI_GP0_PLL_CNTL3 0x48
--
2.25.0
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^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/2] clk: meson-axg: remove CLKID_MIPI_ENABLE
2020-03-09 21:01 [PATCH 0/2] clk: meson: axg: Remove MIPI enable clock gate Remi Pommarel
2020-03-09 21:01 ` [PATCH 1/2] " Remi Pommarel
@ 2020-03-09 21:01 ` Remi Pommarel
2020-03-10 8:05 ` [PATCH 0/2] clk: meson: axg: Remove MIPI enable clock gate Jerome Brunet
2 siblings, 0 replies; 5+ messages in thread
From: Remi Pommarel @ 2020-03-09 21:01 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Michael Turquette, Stephen Boyd,
Kevin Hilman, Rob Herring, Mark Rutland
Cc: linux-amlogic, Remi Pommarel, linux-clk, linux-arm-kernel, linux-kernel
CLKID_MIPI_ENABLE is not handled by the AXG clock driver anymore but by
the MIPI/PCIe PHY driver.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
---
include/dt-bindings/clock/axg-clkc.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h
index fd1f938c38d1..ab04b3a94959 100644
--- a/include/dt-bindings/clock/axg-clkc.h
+++ b/include/dt-bindings/clock/axg-clkc.h
@@ -70,7 +70,6 @@
#define CLKID_HIFI_PLL 69
#define CLKID_PCIE_CML_EN0 79
#define CLKID_PCIE_CML_EN1 80
-#define CLKID_MIPI_ENABLE 81
#define CLKID_GEN_CLK 84
#endif /* __AXG_CLKC_H */
--
2.25.0
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 0/2] clk: meson: axg: Remove MIPI enable clock gate
2020-03-09 21:01 [PATCH 0/2] clk: meson: axg: Remove MIPI enable clock gate Remi Pommarel
2020-03-09 21:01 ` [PATCH 1/2] " Remi Pommarel
2020-03-09 21:01 ` [PATCH 2/2] clk: meson-axg: remove CLKID_MIPI_ENABLE Remi Pommarel
@ 2020-03-10 8:05 ` Jerome Brunet
2021-01-04 11:42 ` Jerome Brunet
2 siblings, 1 reply; 5+ messages in thread
From: Jerome Brunet @ 2020-03-10 8:05 UTC (permalink / raw)
To: Remi Pommarel, Neil Armstrong, Michael Turquette, Stephen Boyd,
Kevin Hilman, Rob Herring, Mark Rutland
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel
On Mon 09 Mar 2020 at 22:01, Remi Pommarel <repk@triplefau.lt> wrote:
> As discussed here [0], HHI_MIPI_CNTL0 is part of the MIPI/PCIe analog
> PHY region and is not related to clock one. Since MIPI/PCIe PHY driver
> has been added with [1], this region can be removed from the clock
> driver.
>
> Please not that this serie depends on [1] to be merged first.
>
> [0] https://lkml.org/lkml/2019/12/16/119
> [1] https://lkml.org/lkml/2020/1/23/945
Series look good. Will apply after v5.7-rc1
>
> Remi Pommarel (2):
> clk: meson: axg: Remove MIPI enable clock gate
> clk: meson-axg: remove CLKID_MIPI_ENABLE
>
> drivers/clk/meson/axg.c | 3 ---
> drivers/clk/meson/axg.h | 1 -
> include/dt-bindings/clock/axg-clkc.h | 1 -
> 3 files changed, 5 deletions(-)
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^ permalink raw reply [flat|nested] 5+ messages in thread