* [PATCH v3 2/4] ARM: dts: meson: switch to the generic Ethernet PHY reset bindings
2019-06-15 10:38 [PATCH v3 0/4] Ethernet PHY reset GPIO updates for Amlogic SoCs Martin Blumenstingl
2019-06-15 10:38 ` [PATCH v3 1/4] arm64: dts: meson: g12a: x96-max: fix the Ethernet PHY reset line Martin Blumenstingl
@ 2019-06-15 10:38 ` Martin Blumenstingl
2019-06-15 10:38 ` [PATCH v3 3/4] arm64: dts: meson: use the generic Ethernet PHY reset GPIO bindings Martin Blumenstingl
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Martin Blumenstingl @ 2019-06-15 10:38 UTC (permalink / raw)
To: linux-amlogic, khilman
Cc: andrew, narmstrong, Martin Blumenstingl, netdev, linus.walleij,
linux-kernel, robin.murphy, linux-arm-kernel
The snps,reset-gpio bindings are deprecated in favour of the generic
"Ethernet PHY reset" bindings.
Replace snps,reset-gpio from the ðmac node with reset-gpios in the
ethernet-phy node. The old snps,reset-active-low property is now encoded
directly as GPIO flag inside the reset-gpios property.
snps,reset-delays-us is converted to reset-assert-us and
reset-deassert-us. reset-assert-us is the second cell from
snps,reset-delays-us while reset-deassert-us was the third cell.
Instead of blindly copying the old values (which seems strange since
they gave the PHY one second to come out of reset) over this also
updates the delays based on the datasheets:
- RTL8211F PHY on the Odroid-C1 and MXIII-Plus needs a 10ms assert
delay (the datasheet mentions: "For a complete PHY reset, this pin
must be asserted low for at least 10ms") and a 30ms deassert delay
(the datasheet mentions: "Wait for a further 30ms (for internal
circuits settling time) before accessing the PHY register"). The
old settings used 10ms for assert and 1000ms for deassert.
- IP101GR PHY on the EC-100 and MXQ needs a 10ms assert delay (the
datasheet mentions: "Trst | Reset period | 10ms") and a 10ms deassert
delay as well (the datasheet mentions: "Tclk_MII_rdy | MII/RMII clock
output ready after reset released | 10ms")). The old settings used
10ms for assert and 1000ms for deassert.
No functional changes intended.
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm/boot/dts/meson8b-ec100.dts | 9 +++++----
arch/arm/boot/dts/meson8b-mxq.dts | 9 +++++----
arch/arm/boot/dts/meson8b-odroidc1.dts | 9 +++++----
arch/arm/boot/dts/meson8m2-mxiii-plus.dts | 8 ++++----
4 files changed, 19 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts
index 9bf4249cb60d..96d239d8334e 100644
--- a/arch/arm/boot/dts/meson8b-ec100.dts
+++ b/arch/arm/boot/dts/meson8b-ec100.dts
@@ -234,10 +234,6 @@
phy-handle = <ð_phy0>;
phy-mode = "rmii";
- snps,reset-gpio = <&gpio GPIOH_4 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
@@ -246,6 +242,11 @@
eth_phy0: ethernet-phy@0 {
/* IC Plus IP101A/G (0x02430c54) */
reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <10000>;
+ reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
+
icplus,select-interrupt;
interrupt-parent = <&gpio_intc>;
/* GPIOH_3 */
diff --git a/arch/arm/boot/dts/meson8b-mxq.dts b/arch/arm/boot/dts/meson8b-mxq.dts
index ef602ab45efd..bb27b34eb346 100644
--- a/arch/arm/boot/dts/meson8b-mxq.dts
+++ b/arch/arm/boot/dts/meson8b-mxq.dts
@@ -91,10 +91,6 @@
phy-handle = <ð_phy0>;
phy-mode = "rmii";
- snps,reset-gpio = <&gpio GPIOH_4 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
@@ -103,6 +99,11 @@
eth_phy0: ethernet-phy@0 {
/* IC Plus IP101A/G (0x02430c54) */
reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <10000>;
+ reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
+
icplus,select-interrupt;
interrupt-parent = <&gpio_intc>;
/* GPIOH_3 */
diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts
index 018695b2b83a..86c4614e0a38 100644
--- a/arch/arm/boot/dts/meson8b-odroidc1.dts
+++ b/arch/arm/boot/dts/meson8b-odroidc1.dts
@@ -176,10 +176,6 @@
ðmac {
status = "okay";
- snps,reset-gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 30000>;
-
pinctrl-0 = <ð_rgmii_pins>;
pinctrl-names = "default";
@@ -195,6 +191,11 @@
/* Realtek RTL8211F (0x001cc916) */
eth_phy: ethernet-phy@0 {
reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
+
interrupt-parent = <&gpio_intc>;
/* GPIOH_3 */
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
index 59b07a55e461..d54477b1001c 100644
--- a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
+++ b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
@@ -73,10 +73,6 @@
amlogic,tx-delay-ns = <4>;
- snps,reset-gpio = <&gpio GPIOH_4 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
@@ -85,6 +81,10 @@
eth_phy0: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
};
};
};
--
2.22.0
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 3/4] arm64: dts: meson: use the generic Ethernet PHY reset GPIO bindings
2019-06-15 10:38 [PATCH v3 0/4] Ethernet PHY reset GPIO updates for Amlogic SoCs Martin Blumenstingl
2019-06-15 10:38 ` [PATCH v3 1/4] arm64: dts: meson: g12a: x96-max: fix the Ethernet PHY reset line Martin Blumenstingl
2019-06-15 10:38 ` [PATCH v3 2/4] ARM: dts: meson: switch to the generic Ethernet PHY reset bindings Martin Blumenstingl
@ 2019-06-15 10:38 ` Martin Blumenstingl
2019-06-15 10:38 ` [PATCH v3 4/4] arm64: dts: meson: g12b: odroid-n2: add the Ethernet PHY reset line Martin Blumenstingl
2019-06-20 3:35 ` [PATCH v3 0/4] Ethernet PHY reset GPIO updates for Amlogic SoCs Kevin Hilman
4 siblings, 0 replies; 6+ messages in thread
From: Martin Blumenstingl @ 2019-06-15 10:38 UTC (permalink / raw)
To: linux-amlogic, khilman
Cc: andrew, narmstrong, Martin Blumenstingl, netdev, linus.walleij,
linux-kernel, robin.murphy, linux-arm-kernel
The snps,reset-gpio bindings are deprecated in favour of the generic
"Ethernet PHY reset" bindings.
Replace snps,reset-gpio from the ðmac node with reset-gpios in the
ethernet-phy node. The old snps,reset-active-low property is now encoded
directly as GPIO flag inside the reset-gpios property.
snps,reset-delays-us is converted to reset-assert-us and
reset-deassert-us. reset-assert-us is the second cell from
snps,reset-delays-us while reset-deassert-us was the third cell.
Instead of blindly copying the old values (which seems strange since
they gave the PHY one second to come out of reset) over this also
updates the delays based on the datasheets:
- the Realtek RTL8211F PHY needs a 10ms assert delay (the datasheet
mentions: "For a complete PHY reset, this pin must be asserted low
for at least 10ms") and a 30ms deassert delay (the datasheet
mentions: "Wait for a further 30ms (for internal circuits settling
time) before accessing the PHY register". This applies to the
following boards: GXBB NanoPi K2, GXBB Odroid-C2, GXBB Vega S95
variants, GXBB Wetek variants, GXL P230, GXM Khadas VIM2, GXM Nexbox
A1, GXM Q200, GXM RBox Pro boards.
- the ICPlus IP101GR PHY needs a 10ms assert delay (the datasheet
mentions: "Trst | Reset period | 10ms") and a deassert delay of 10ms
as well (the datasheet mentions: "Tclk_MII_rdy | MII/RMII clock
output ready after reset released | 10ms"). This applies to the GXBB
Nexbox A95X board.
- the Micrel KSZ9031 seems to require a 100us delay but use the same
(seemingly safe) values from RTL8211F due to lack of a board to verify
this. This applies to the GXBB P200 board.
The GXBB P201 board is left out from this conversion because it doesn't
have a dedicated PHY node (because it's not clear which PHY is used on
that board).
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts | 9 +++++----
.../arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 8 ++++----
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 9 +++++----
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 9 +++++----
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 9 +++++----
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi | 8 ++++----
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts | 11 ++++++-----
arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 10 +++++-----
arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 8 ++++----
arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts | 11 ++++++-----
arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts | 8 ++++----
11 files changed, 53 insertions(+), 47 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
index 849c01650c4d..c34c1c90ccb6 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
@@ -154,10 +154,6 @@
amlogic,tx-delay-ns = <2>;
- snps,reset-gpio = <&gpio GPIOZ_14 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
@@ -166,6 +162,11 @@
eth_phy0: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_15 */
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
index 3c54f26eef15..b636912a2715 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
@@ -162,10 +162,6 @@
phy-handle = <ð_phy0>;
phy-mode = "rmii";
- snps,reset-gpio = <&gpio GPIOZ_14 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
@@ -174,6 +170,10 @@
eth_phy0: ethernet-phy@0 {
/* IC Plus IP101GR (0x02430c54) */
reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <10000>;
+ reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
};
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
index 5a139e7b1c60..9972b1515da6 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
@@ -126,10 +126,6 @@
phy-handle = <ð_phy0>;
phy-mode = "rgmii";
- snps,reset-gpio = <&gpio GPIOZ_14 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
amlogic,tx-delay-ns = <2>;
mdio {
@@ -140,6 +136,11 @@
eth_phy0: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_15 */
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts
index 9d2406a7c4fa..3c93d1898b40 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts
@@ -68,10 +68,6 @@
amlogic,tx-delay-ns = <2>;
- snps,reset-gpio = <&gpio GPIOZ_14 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
@@ -80,6 +76,11 @@
eth_phy0: ethernet-phy@3 {
/* Micrel KSZ9031 (0x00221620) */
reg = <3>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_15 */
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
index 18856f28fd60..43b11e3dfe11 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
@@ -116,10 +116,6 @@
amlogic,tx-delay-ns = <2>;
- snps,reset-gpio = <&gpio GPIOZ_14 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
@@ -128,6 +124,11 @@
eth_phy0: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_15 */
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi
index 9ef6858779c1..4c539881fbb7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi
@@ -137,10 +137,6 @@
amlogic,tx-delay-ns = <2>;
- snps,reset-gpio = <&gpio GPIOZ_14 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
@@ -149,6 +145,10 @@
eth_phy0: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
};
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
index 767b1763a612..b08c4537f260 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
@@ -70,11 +70,6 @@
amlogic,tx-delay-ns = <2>;
- /* External PHY reset is shared with internal PHY Led signals */
- snps,reset-gpio = <&gpio GPIOZ_14 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
/* External PHY is in RGMII */
phy-mode = "rgmii";
};
@@ -84,6 +79,12 @@
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
max-speed = <1000>;
+
+ /* External PHY reset is shared with internal PHY Led signal */
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
interrupt-parent = <&gpio_intc>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
eee-broken-1000t;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
index ff4f0780824d..989d33ac6eae 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
@@ -239,11 +239,6 @@
amlogic,tx-delay-ns = <2>;
- /* External PHY reset is shared with internal PHY Led signals */
- snps,reset-gpio = <&gpio GPIOZ_14 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
/* External PHY is in RGMII */
phy-mode = "rgmii";
@@ -254,6 +249,11 @@
external_phy: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_15 */
interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
index 29715eae14a9..c2bd4dbbf38c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
@@ -101,10 +101,6 @@
amlogic,tx-delay-ns = <2>;
- snps,reset-gpio = <&gpio GPIOZ_14 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
/* External PHY is in RGMII */
phy-mode = "rgmii";
};
@@ -114,6 +110,10 @@
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
max-speed = <1000>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
index 8939c0fc5b62..ea45ae0c71b7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
@@ -52,11 +52,6 @@
amlogic,tx-delay-ns = <2>;
- /* External PHY reset is shared with internal PHY Led signals */
- snps,reset-gpio = <&gpio GPIOZ_14 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
/* External PHY is in RGMII */
phy-mode = "rgmii";
};
@@ -66,6 +61,12 @@
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
max-speed = <1000>;
+
+ /* External PHY reset is shared with internal PHY Led signal */
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_15 */
interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
index 13de1e8f58b5..5cd4d35006d0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
@@ -101,10 +101,6 @@
/* Select external PHY by default */
phy-handle = <&external_phy>;
- snps,reset-gpio = <&gpio GPIOZ_14 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
amlogic,tx-delay-ns = <2>;
/* External PHY is in RGMII */
@@ -116,6 +112,10 @@
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
max-speed = <1000>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
};
};
--
2.22.0
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