From: Jian Hu <jian.hu@amlogic.com>
To: Jerome Brunet <jbrunet@baylibre.com>,
Neil Armstrong <narmstrong@baylibre.com>
Cc: Rob Herring <robh@kernel.org>,
Victor Wan <victor.wan@amlogic.com>,
Jianxin Pan <jianxin.pan@amlogic.com>,
devicetree@vger.kernel.org,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Kevin Hilman <khilman@baylibre.com>,
Michael Turquette <mturquette@baylibre.com>,
linux-kernel@vger.kernel.org, Stephen Boyd <sboyd@kernel.org>,
Jian Hu <jian.hu@amlogic.com>,
linux-arm-kernel@lists.infradead.org,
Qiufang Dai <qiufang.dai@amlogic.com>,
linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
Chandle Zou <chandle.zou@amlogic.com>
Subject: [PATCH v3 1/7] dt-bindings: clock: meson: add A1 PLL clock controller bindings
Date: Fri, 29 Nov 2019 22:45:59 +0800 [thread overview]
Message-ID: <20191129144605.182774-2-jian.hu@amlogic.com> (raw)
In-Reply-To: <20191129144605.182774-1-jian.hu@amlogic.com>
Add the documentation to support Amlogic A1 PLL clock driver,
and add A1 PLL clock controller bindings.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
---
.../bindings/clock/amlogic,a1-pll-clkc.yaml | 56 +++++++++++++++++++
include/dt-bindings/clock/a1-pll-clkc.h | 16 ++++++
2 files changed, 72 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
new file mode 100644
index 000000000000..d008bfeb3c3a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic Meson A/C serials PLL Clock Control Unit Device Tree Bindings
+
+maintainers:
+ - Neil Armstrong <narmstrong@baylibre.com>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Jian Hu <jian.hu@jian.hu.com>
+
+properties:
+ compatible:
+ - enum:
+ - amlogic,a1-pll-clkc
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+clocks:
+ minItems: 2
+ maxItems: 2
+ items:
+ - description: Input xtal_fixpll
+ - description: Input xtal_hifipll
+
+clock-names:
+ minItems: 2
+ maxItems: 2
+ items:
+ - const: xtal_fixpll
+ - const: xtal_hifipll
+
+required:
+ - compatible
+ - "#clock-cells"
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ clkc_pll: pll-clock-controller {
+ compatible = "amlogic,a1-pll-clkc";
+ reg = <0 0x7c80 0 0x18c>;
+ #clock-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/a1-pll-clkc.h b/include/dt-bindings/clock/a1-pll-clkc.h
new file mode 100644
index 000000000000..58eae237e503
--- /dev/null
+++ b/include/dt-bindings/clock/a1-pll-clkc.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __A1_PLL_CLKC_H
+#define __A1_PLL_CLKC_H
+
+#define CLKID_FIXED_PLL 1
+#define CLKID_FCLK_DIV2 6
+#define CLKID_FCLK_DIV3 7
+#define CLKID_FCLK_DIV5 8
+#define CLKID_FCLK_DIV7 9
+#define CLKID_HIFI_PLL 10
+
+#endif /* __A1_PLL_CLKC_H */
--
2.24.0
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next prev parent reply other threads:[~2019-11-29 14:47 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-29 14:45 [PATCH v3 0/7] add Amlogic A1 clock controller driver Jian Hu
2019-11-29 14:45 ` Jian Hu [this message]
2019-11-29 14:46 ` [PATCH v3 2/7] clk: meson: add support for A1 PLL clock ops Jian Hu
2019-11-29 14:46 ` [PATCH v3 3/7] clk: meson: eeclk: refactor eeclk common driver to support A1 Jian Hu
2019-11-29 14:46 ` [PATCH v3 4/7] clk: meson: a1: add support for Amlogic A1 PLL clock driver Jian Hu
2019-11-29 14:46 ` [PATCH v3 5/7] dt-bindings: clock: meson: add A1 peripheral clock controller bindings Jian Hu
2019-11-29 14:46 ` [PATCH v3 6/7] clk: meson: a1: add support for Amlogic A1 Peripheral clock driver Jian Hu
2019-11-29 14:46 ` [PATCH v3 7/7] arm64: dts: meson: add A1 PLL and periphs clock controller Jian Hu
2019-11-29 15:28 ` [PATCH v3 0/7] add Amlogic A1 clock controller driver Jerome Brunet
2019-12-02 6:01 ` Jian Hu
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