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From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: jbrunet@baylibre.com, linux-amlogic@lists.infradead.org
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, narmstrong@baylibre.com
Subject: [PATCH 0/2] clk: meson8b: add two missing gate clocks
Date: Mon, 29 Jun 2020 22:39:02 +0200	[thread overview]
Message-ID: <20200629203904.2989007-1-martin.blumenstingl@googlemail.com> (raw)

While trying to figure out how to set up the video clocks on the 32-bit
SoCs I found that the current clock tree is missing two gates. This adds
the missing gates based on evidence found in the public S805 datasheet,
the GXBB clock driver and 3.10 vendor kernel.

I didn't add any Fixes tag because this clock tree is still read-only
and the HDMI PLL (the top-most clock in this tree) needs more work as
well.


Martin Blumenstingl (2):
  clk: meson: meson8b: add the vclk_en gate clock
  clk: meson: meson8b: add the vclk2_en gate clock

 drivers/clk/meson/meson8b.c | 60 ++++++++++++++++++++++++++++++-------
 drivers/clk/meson/meson8b.h |  4 ++-
 2 files changed, 53 insertions(+), 11 deletions(-)

-- 
2.27.0


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             reply	other threads:[~2020-06-29 20:39 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-29 20:39 Martin Blumenstingl [this message]
2020-06-29 20:39 ` [PATCH 1/2] clk: meson: meson8b: add the vclk_en gate clock Martin Blumenstingl
2020-06-29 20:39 ` [PATCH 2/2] clk: meson: meson8b: add the vclk2_en " Martin Blumenstingl
2020-07-09 17:16 ` [PATCH 0/2] clk: meson8b: add two missing gate clocks Jerome Brunet
2020-08-17 17:48 ` patchwork-bot+linux-amlogic

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