* [PATCH] net: stmmac: dwmac-meson8b: add calibration registers
@ 2020-09-25 21:56 Martin Blumenstingl
2020-09-25 23:26 ` David Miller
0 siblings, 1 reply; 2+ messages in thread
From: Martin Blumenstingl @ 2020-09-25 21:56 UTC (permalink / raw)
To: davem, netdev, linux-amlogic
Cc: alexandre.torgue, Martin Blumenstingl, linux-kernel, joabreu,
peppe.cavallaro, linux-arm-kernel
The Amlogic dwmac Ethernet IP glue has two registers:
- PRG_ETH0 with various configuration bits
- PRG_ETH1 with various calibration and information related bits
Add the register definitions with comments from different drivers in
Amlogic's vendor u-boot and Linux.
The most important part is PRG_ETH1_AUTO_CALI_IDX_VAL which is needed on
G12A (and later: G12B, SM1) with RGMII PHYs. Ethernet is only working up
to 100Mbit/s speeds if u-boot does not initialize these bits correctly.
On 1Gbit/s links no traffic is flowing (similar to when the RGMII delays
are set incorrectly). The logic to write this register will be added
later.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index 5afcf05bbf9c..9a898d2a1e08 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -69,6 +69,34 @@
*/
#define PRG_ETH0_ADJ_SKEW GENMASK(24, 20)
+#define PRG_ETH0_START_CALIBRATION BIT(25)
+
+/* 0: falling edge, 1: rising edge */
+#define PRG_ETH0_TEST_EDGE BIT(26)
+
+/* Select one signal from {RXDV, RXD[3:0]} to calibrate */
+#define PRG_ETH0_SIGNAL_TO_CALIBRATE GENMASK(29, 27)
+
+#define PRG_ETH1 0x4
+
+/* Signal switch position in 1ns resolution */
+#define PRG_ETH1_SIGNAL_SWITCH_POSITION GENMASK(4, 0)
+
+/* RXC (RX clock) length in 1ns resolution */
+#define PRG_ETH1_RX_CLK_LENGTH GENMASK(9, 5)
+
+#define PRG_ETH1_CALI_WAITING_FOR_EVENT BIT(10)
+
+#define PRG_ETH1_SIGNAL_UNDER_TEST GENMASK(13, 11)
+
+/* 0: falling edge, 1: rising edge */
+#define PRG_ETH1_RESULT_EDGE BIT(14)
+
+#define PRG_ETH1_RESULT_IS_VALID BIT(15)
+
+/* undocumented - only valid on G12A and later */
+#define PRG_ETH1_AUTO_CALI_IDX_VAL GENMASK(19, 16)
+
struct meson8b_dwmac;
struct meson8b_dwmac_data {
--
2.28.0
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] net: stmmac: dwmac-meson8b: add calibration registers
2020-09-25 21:56 [PATCH] net: stmmac: dwmac-meson8b: add calibration registers Martin Blumenstingl
@ 2020-09-25 23:26 ` David Miller
0 siblings, 0 replies; 2+ messages in thread
From: David Miller @ 2020-09-25 23:26 UTC (permalink / raw)
To: martin.blumenstingl
Cc: alexandre.torgue, netdev, linux-kernel, joabreu, linux-amlogic,
peppe.cavallaro, linux-arm-kernel
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Date: Fri, 25 Sep 2020 23:56:29 +0200
> The Amlogic dwmac Ethernet IP glue has two registers:
> - PRG_ETH0 with various configuration bits
> - PRG_ETH1 with various calibration and information related bits
>
> Add the register definitions with comments from different drivers in
> Amlogic's vendor u-boot and Linux.
>
> The most important part is PRG_ETH1_AUTO_CALI_IDX_VAL which is needed on
> G12A (and later: G12B, SM1) with RGMII PHYs. Ethernet is only working up
> to 100Mbit/s speeds if u-boot does not initialize these bits correctly.
> On 1Gbit/s links no traffic is flowing (similar to when the RGMII delays
> are set incorrectly). The logic to write this register will be added
> later.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Please add these definitions alongside actual uses of them.
Thank you.
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linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
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