* [PATCH v8 00/11] add Amlogic A1 clock controller drivers
@ 2022-12-01 22:56 Dmitry Rokosov
2022-12-01 22:56 ` [PATCH v8 01/11] dt-bindings: clock: meson: add A1 PLL clock controller bindings Dmitry Rokosov
` (10 more replies)
0 siblings, 11 replies; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-01 22:56 UTC (permalink / raw)
To: neil.armstrong, jbrunet, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Dmitry Rokosov
A1 SoC has four clock controllers on the board: PLL, Peripherals, CPU,
and Audio. The audio clock controller is different from others, but the
rest are very similar from a functional and regmap point of view.
This patch series add support for Amlogic A1 PLL and Peripherals clock
drivers.
It blocks all A1 peripherals mainline support and a couple of patch series,
which were already reviewed and acked, but weren't merged due to pending
clock controller drivers series, e.g.
https://lore.kernel.org/linux-amlogic/7hd09cw9oh.fsf@baylibre.com/
The previous v7 version [8] had several logic and style problems, all of
them are resolved in this version. Original Jian Hu v7 patches are not
touched, and all additional fixes are implemented in separate patches.
Patch "clk: meson: add support for A1 PLL clock ops" is removed, because
a1-pll clk driver inherits all stuff from clk-pll base driver, just
implements custom init/enable/disable/is_enabled callbacks.
TODO: CPU and Audio clock controllers are not included in this patch
series, it will be sent later. The following clks from these controllers
are not supported for now:
* Audio clks - vad, mclk_vad, mclk_d, resample_a, locker_in, mclk_b,
pdmdclk, pdmsysclk, eqdrc, spdifin, mclk_a, audio2_toaudiotop,
audio2_tovad, audio2_toddr_vad, audio2_tdmin_vad, audio2_pdm,
audio2_ddr_arb, audio_audiolocker, audio_eqdrc, audio_resamplea,
audio_spdifin, audio_toddrb, audio_toddra, audio_frddrb, audio_frddra,
audio_tdmoutb, audio_tdmouta, audio_loopbacka, audio_tdminlb,
audio_tdminb, audio_tdmina, audio_ddr_arb, mclk_c
* CPU clks: cpu_fixed_source_sel0, cpu_fixed_source_div0,
cpu_fixed_source_sel1, cpu_fixed_source_div1, cpu_clk
Changes v7->v8:
- introduced a1-clkc common driver for all A1 clock controllers
- exported meson_clk_pll_wait_lock symbol
- supported meson-a1-clkc common driver in the a1-pll and a1 clkc
- inherited a1-pll from the base clk-pll driver, implemented own
version of init/enable/disable/enabled routines; rate calculating
logic is fully the same
- aligned CLKID-related definitions with CLKID list from order
perspective to remove holes and permutations
- corrected Kconfig dependencies and types
- provided correct MODULE_AUTHORs()
- optimized and fixed up some clock relationships
- removed unused register offset definitions
- fixed up A1 PLL and Peripherals clkc dtb_check errors
- fixed clk_summary kernel panic due to missing a1_pad_ctrl
clk_regmap definition
- included PLL and Peripherals clk controllers to the base a1 dts
Changes since v6 at [7]:
- fix 'dt_binding_check' compiling error
- add acked-by
Changes since v5 at [6]:
- fix yaml file
- add rst/current_en/l_detect parm detection
- remove 'meson_eeclkc_data' in a1.c and a1-pll.c
Changes since v4 at [5]:
- change yaml GPL
- drop meson-eeclk.c patch, add probe function in each driver
- add CLK_IS_CRITICAL for sys_clk clock, drop the flag for sys_a
and sys_b
- add new parm for pll, add protection for rst parm
- drop flag for a1_fixed_pll
- remove the same comment for fclk_div, add "refer to"
- add critical flag for a1_sys_clk
- remove rtc table
- rename a1_dspa_en_dspa and a1_dspb_en_dspb
- remove useless comment
Changes since v3 at [3]:
- fix reparenting orphan failed, it depends on jerome's patch [4]
- fix changelist in v3 about reparenting orphan
- remove the dts patch
Changes since v2 at [2]:
- add probe function for A1
- separate the clock driver into two patch
- change some clock flags and ops
- add support for a1 PLL ops
- add A1 clock node
- fix reparenting orphan clock failed, registering xtal_fixpll
and xtal_hifipll after the provider registration, it is not
a best way.
Changes since v1 at [1]:
- place A1 config alphabetically
- add actual reason for RO ops, CLK_IS_CRITICAL, CLK_IGNORE_UNUSED
- separate the driver into two driver: peripheral and pll driver
- delete CLK_IGNORE_UNUSED flag for pwm b/c/d/e/f clock, dsp clock
- delete the change in Kconfig.platforms, address to Kevin alone
- remove the useless comments
- modify the meson pll driver to support A1 PLLs
[1] https://lkml.kernel.org/r/1569411888-98116-1-git-send-email-jian.hu@amlogic.com
[2] https://lkml.kernel.org/r/1571382865-41978-1-git-send-email-jian.hu@amlogic.com
[3] https://lkml.kernel.org/r/20191129144605.182774-1-jian.hu@amlogic.com
[4] https://lkml.kernel.org/r/20191203080805.104628-1-jbrunet@baylibre.com
[5] https://lkml.kernel.org/r/20191206074052.15557-1-jian.hu@amlogic.com
[6] https://lkml.kernel.org/r/20191227094606.143637-1-jian.hu@amlogic.com
[7] https://lkml.kernel.org/r/20200116080440.118679-1-jian.hu@amlogic.com
[8] https://lore.kernel.org/linux-amlogic/20200120034937.128600-1-jian.hu@amlogic.com/
Dmitry Rokosov (7):
clk: meson: pll: export meson_clk_pll_wait_lock symbol
clk: meson: introduce a1-clkc common driver for all A1 clock
controllers
clk: meson: a1: redesign Amlogic A1 PLL clock controller
dt-bindings: clock: meson: fixup A1 PLL clkc dtb_check errors
clk: meson: redesign A1 Peripherals CLK controller
dt-bindings: clock: meson: fixup A1 peripherals clkc dtb_check errors
arm64: dts: meson: a1: introduce PLL and Peripherals clk controllers
Jian Hu (4):
dt-bindings: clock: meson: add A1 PLL clock controller bindings
clk: meson: a1: add support for Amlogic A1 PLL clock driver
dt-bindings: clock: meson: add A1 peripheral clock controller bindings
clk: meson: a1: add support for Amlogic A1 Peripheral clock driver
.../bindings/clock/amlogic,a1-clkc.yaml | 73 +
.../bindings/clock/amlogic,a1-pll-clkc.yaml | 59 +
MAINTAINERS | 1 +
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 27 +-
drivers/clk/meson/Kconfig | 24 +
drivers/clk/meson/Makefile | 3 +
drivers/clk/meson/a1-pll.c | 451 ++++
drivers/clk/meson/a1-pll.h | 59 +
drivers/clk/meson/a1.c | 2222 +++++++++++++++++
drivers/clk/meson/a1.h | 116 +
drivers/clk/meson/clk-pll.c | 3 +-
drivers/clk/meson/clk-pll.h | 2 +
drivers/clk/meson/meson-a1-clkc.c | 63 +
drivers/clk/meson/meson-a1-clkc.h | 25 +
include/dt-bindings/clock/a1-clkc.h | 98 +
include/dt-bindings/clock/a1-pll-clkc.h | 16 +
16 files changed, 3240 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
create mode 100644 drivers/clk/meson/a1-pll.c
create mode 100644 drivers/clk/meson/a1-pll.h
create mode 100644 drivers/clk/meson/a1.c
create mode 100644 drivers/clk/meson/a1.h
create mode 100644 drivers/clk/meson/meson-a1-clkc.c
create mode 100644 drivers/clk/meson/meson-a1-clkc.h
create mode 100644 include/dt-bindings/clock/a1-clkc.h
create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h
--
2.36.0
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH v8 01/11] dt-bindings: clock: meson: add A1 PLL clock controller bindings
2022-12-01 22:56 [PATCH v8 00/11] add Amlogic A1 clock controller drivers Dmitry Rokosov
@ 2022-12-01 22:56 ` Dmitry Rokosov
2022-12-02 4:10 ` Rob Herring
` (2 more replies)
2022-12-01 22:56 ` [PATCH v8 02/11] clk: meson: a1: add support for Amlogic A1 PLL clock driver Dmitry Rokosov
` (9 subsequent siblings)
10 siblings, 3 replies; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-01 22:56 UTC (permalink / raw)
To: neil.armstrong, jbrunet, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Dmitry Rokosov
From: Jian Hu <jian.hu@amlogic.com>
Add the documentation to support Amlogic A1 PLL clock driver,
and add A1 PLL clock controller bindings.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
---
.../bindings/clock/amlogic,a1-pll-clkc.yaml | 52 +++++++++++++++++++
include/dt-bindings/clock/a1-pll-clkc.h | 16 ++++++
2 files changed, 68 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
new file mode 100644
index 000000000000..d67250fbeece
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/amlogic,a1-pll-clkc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic Meson A/C serials PLL Clock Control Unit Device Tree Bindings
+
+maintainers:
+ - Neil Armstrong <narmstrong@baylibre.com>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Jian Hu <jian.hu@jian.hu.com>
+
+properties:
+ compatible:
+ const: amlogic,a1-pll-clkc
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: input xtal_fixpll
+ - description: input xtal_hifipll
+
+ clock-names:
+ items:
+ - const: xtal_fixpll
+ - const: xtal_hifipll
+
+required:
+ - compatible
+ - "#clock-cells"
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ clkc_pll: pll-clock-controller@7c80 {
+ compatible = "amlogic,a1-pll-clkc";
+ reg = <0 0x7c80 0 0x18c>;
+ #clock-cells = <1>;
+ clocks = <&clkc_periphs 1>,
+ <&clkc_periphs 4>;
+ clock-names = "xtal_fixpll", "xtal_hifipll";
+ };
diff --git a/include/dt-bindings/clock/a1-pll-clkc.h b/include/dt-bindings/clock/a1-pll-clkc.h
new file mode 100644
index 000000000000..58eae237e503
--- /dev/null
+++ b/include/dt-bindings/clock/a1-pll-clkc.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __A1_PLL_CLKC_H
+#define __A1_PLL_CLKC_H
+
+#define CLKID_FIXED_PLL 1
+#define CLKID_FCLK_DIV2 6
+#define CLKID_FCLK_DIV3 7
+#define CLKID_FCLK_DIV5 8
+#define CLKID_FCLK_DIV7 9
+#define CLKID_HIFI_PLL 10
+
+#endif /* __A1_PLL_CLKC_H */
--
2.36.0
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v8 02/11] clk: meson: a1: add support for Amlogic A1 PLL clock driver
2022-12-01 22:56 [PATCH v8 00/11] add Amlogic A1 clock controller drivers Dmitry Rokosov
2022-12-01 22:56 ` [PATCH v8 01/11] dt-bindings: clock: meson: add A1 PLL clock controller bindings Dmitry Rokosov
@ 2022-12-01 22:56 ` Dmitry Rokosov
2022-12-02 11:16 ` Jerome Brunet
2022-12-01 22:56 ` [PATCH v8 03/11] dt-bindings: clock: meson: add A1 peripheral clock controller bindings Dmitry Rokosov
` (8 subsequent siblings)
10 siblings, 1 reply; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-01 22:56 UTC (permalink / raw)
To: neil.armstrong, jbrunet, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Dmitry Rokosov
From: Jian Hu <jian.hu@amlogic.com>
The Amlogic A1 clock includes three drivers:
pll clocks, peripheral clocks, CPU clocks.
sys pll and CPU clocks will be sent in next patch.
Unlike the previous series, there is no EE/AO domain
in A1 CLK controllers.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
---
drivers/clk/meson/Kconfig | 9 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/a1-pll.c | 360 +++++++++++++++++++++++++++++++++++++
drivers/clk/meson/a1-pll.h | 56 ++++++
4 files changed, 426 insertions(+)
create mode 100644 drivers/clk/meson/a1-pll.c
create mode 100644 drivers/clk/meson/a1-pll.h
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index fc002c155bc3..ab34662b24f0 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -99,6 +99,15 @@ config COMMON_CLK_AXG_AUDIO
Support for the audio clock controller on AmLogic A113D devices,
aka axg, Say Y if you want audio subsystem to work.
+config COMMON_CLK_A1_PLL
+ bool
+ depends on ARCH_MESON
+ select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_MESON_PLL
+ help
+ Support for the PLL clock controller on Amlogic A113L device,
+ aka a1. Say Y if you want PLL to work.
+
config COMMON_CLK_G12A
tristate "G12 and SM1 SoC clock controllers support"
depends on ARM64
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 6eca2a406ee3..2f17f475a48f 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o
obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
+obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c
new file mode 100644
index 000000000000..69c1ca07d041
--- /dev/null
+++ b/drivers/clk/meson/a1-pll.c
@@ -0,0 +1,360 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ * Author: Jian Hu <jian.hu@amlogic.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include "a1-pll.h"
+#include "clk-pll.h"
+#include "clk-regmap.h"
+
+static struct clk_regmap a1_fixed_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = ANACTRL_FIXPLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = ANACTRL_FIXPLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = ANACTRL_FIXPLL_CTRL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .frac = {
+ .reg_off = ANACTRL_FIXPLL_CTRL1,
+ .shift = 0,
+ .width = 19,
+ },
+ .l = {
+ .reg_off = ANACTRL_FIXPLL_STS,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = ANACTRL_FIXPLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fixed_pll_dco",
+ .ops = &meson_clk_pll_ro_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal_fixpll",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_fixed_pll = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = ANACTRL_FIXPLL_CTRL0,
+ .bit_idx = 20,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "fixed_pll",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_fixed_pll_dco.hw
+ },
+ .num_parents = 1,
+ /*
+ * It is enough that the fdiv leaf has critical flag,
+ * No critical or unused flag here.
+ */
+ },
+};
+
+static const struct pll_mult_range a1_hifi_pll_mult_range = {
+ .min = 32,
+ .max = 64,
+};
+
+static const struct reg_sequence a1_hifi_init_regs[] = {
+ { .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x01800000 },
+ { .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00001100 },
+ { .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x100a1100 },
+ { .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x00302000 },
+ { .reg = ANACTRL_HIFIPLL_CTRL0, .def = 0x01f18440 },
+};
+
+static struct clk_regmap a1_hifi_pll = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .frac = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL1,
+ .shift = 0,
+ .width = 19,
+ },
+ .l = {
+ .reg_off = ANACTRL_HIFIPLL_STS,
+ .shift = 31,
+ .width = 1,
+ },
+ .current_en = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 26,
+ .width = 1,
+ },
+ .l_detect = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL2,
+ .shift = 6,
+ .width = 1,
+ },
+ .range = &a1_hifi_pll_mult_range,
+ .init_regs = a1_hifi_init_regs,
+ .init_count = ARRAY_SIZE(a1_hifi_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "hifi_pll",
+ .ops = &meson_clk_pll_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal_hifipll",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor a1_fclk_div2_div = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div2_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_fixed_pll.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_fclk_div2 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = ANACTRL_FIXPLL_CTRL0,
+ .bit_idx = 21,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div2",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_fclk_div2_div.hw
+ },
+ .num_parents = 1,
+ /*
+ * This clock is used by DDR clock in BL2 firmware
+ * and is required by the platform to operate correctly.
+ * Until the following condition are met, we need this clock to
+ * be marked as critical:
+ * a) Mark the clock used by a firmware resource, if possible
+ * b) CCF has a clock hand-off mechanism to make the sure the
+ * clock stays on until the proper driver comes along
+ */
+ .flags = CLK_IS_CRITICAL,
+ },
+};
+
+static struct clk_fixed_factor a1_fclk_div3_div = {
+ .mult = 1,
+ .div = 3,
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div3_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_fixed_pll.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_fclk_div3 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = ANACTRL_FIXPLL_CTRL0,
+ .bit_idx = 22,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div3",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_fclk_div3_div.hw
+ },
+ .num_parents = 1,
+ /*
+ * This clock is used by APB bus which is set in boot ROM code
+ * and is required by the platform to operate correctly.
+ * About critical, refer to a1_fclk_div2.
+ */
+ .flags = CLK_IS_CRITICAL,
+ },
+};
+
+static struct clk_fixed_factor a1_fclk_div5_div = {
+ .mult = 1,
+ .div = 5,
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div5_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_fixed_pll.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_fclk_div5 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = ANACTRL_FIXPLL_CTRL0,
+ .bit_idx = 23,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div5",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_fclk_div5_div.hw
+ },
+ .num_parents = 1,
+ /*
+ * This clock is used by AXI bus which setted in Romcode
+ * and is required by the platform to operate correctly.
+ * About critical, refer to a1_fclk_div2.
+ */
+ .flags = CLK_IS_CRITICAL,
+ },
+};
+
+static struct clk_fixed_factor a1_fclk_div7_div = {
+ .mult = 1,
+ .div = 7,
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div7_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_fixed_pll.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_fclk_div7 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = ANACTRL_FIXPLL_CTRL0,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div7",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_fclk_div7_div.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+/* Array of all clocks provided by this provider */
+static struct clk_hw_onecell_data a1_pll_hw_onecell_data = {
+ .hws = {
+ [CLKID_FIXED_PLL_DCO] = &a1_fixed_pll_dco.hw,
+ [CLKID_FIXED_PLL] = &a1_fixed_pll.hw,
+ [CLKID_HIFI_PLL] = &a1_hifi_pll.hw,
+ [CLKID_FCLK_DIV2] = &a1_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &a1_fclk_div3.hw,
+ [CLKID_FCLK_DIV5] = &a1_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &a1_fclk_div7.hw,
+ [CLKID_FCLK_DIV2_DIV] = &a1_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &a1_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &a1_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &a1_fclk_div7_div.hw,
+ [NR_PLL_CLKS] = NULL,
+ },
+ .num = NR_PLL_CLKS,
+};
+
+static struct clk_regmap *const a1_pll_regmaps[] = {
+ &a1_fixed_pll_dco,
+ &a1_fixed_pll,
+ &a1_hifi_pll,
+ &a1_fclk_div2,
+ &a1_fclk_div3,
+ &a1_fclk_div5,
+ &a1_fclk_div7,
+};
+
+static struct regmap_config clkc_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
+static int meson_a1_pll_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ void __iomem *base;
+ struct regmap *map;
+ int ret, i;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ map = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
+ if (IS_ERR(map))
+ return PTR_ERR(map);
+
+ /* Populate regmap for the regmap backed clocks */
+ for (i = 0; i < ARRAY_SIZE(a1_pll_regmaps); i++)
+ a1_pll_regmaps[i]->map = map;
+
+ for (i = 0; i < a1_pll_hw_onecell_data.num; i++) {
+ /* array might be sparse */
+ if (!a1_pll_hw_onecell_data.hws[i])
+ continue;
+
+ ret = devm_clk_hw_register(dev, a1_pll_hw_onecell_data.hws[i]);
+ if (ret) {
+ dev_err(dev, "Clock registration failed\n");
+ return ret;
+ }
+ }
+
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+ &a1_pll_hw_onecell_data);
+}
+
+static const struct of_device_id clkc_match_table[] = {
+ { .compatible = "amlogic,a1-pll-clkc", },
+ {}
+};
+
+static struct platform_driver a1_pll_driver = {
+ .probe = meson_a1_pll_probe,
+ .driver = {
+ .name = "a1-pll-clkc",
+ .of_match_table = clkc_match_table,
+ },
+};
+
+builtin_platform_driver(a1_pll_driver);
diff --git a/drivers/clk/meson/a1-pll.h b/drivers/clk/meson/a1-pll.h
new file mode 100644
index 000000000000..8ded267061ad
--- /dev/null
+++ b/drivers/clk/meson/a1-pll.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __A1_PLL_H
+#define __A1_PLL_H
+
+/* PLL register offset */
+#define ANACTRL_FIXPLL_CTRL0 0x0
+#define ANACTRL_FIXPLL_CTRL1 0x4
+#define ANACTRL_FIXPLL_CTRL2 0x8
+#define ANACTRL_FIXPLL_CTRL3 0xc
+#define ANACTRL_FIXPLL_CTRL4 0x10
+#define ANACTRL_FIXPLL_STS 0x14
+#define ANACTRL_SYSPLL_CTRL0 0x80
+#define ANACTRL_SYSPLL_CTRL1 0x84
+#define ANACTRL_SYSPLL_CTRL2 0x88
+#define ANACTRL_SYSPLL_CTRL3 0x8c
+#define ANACTRL_SYSPLL_CTRL4 0x90
+#define ANACTRL_SYSPLL_STS 0x94
+#define ANACTRL_HIFIPLL_CTRL0 0xc0
+#define ANACTRL_HIFIPLL_CTRL1 0xc4
+#define ANACTRL_HIFIPLL_CTRL2 0xc8
+#define ANACTRL_HIFIPLL_CTRL3 0xcc
+#define ANACTRL_HIFIPLL_CTRL4 0xd0
+#define ANACTRL_HIFIPLL_STS 0xd4
+#define ANACTRL_AUDDDS_CTRL0 0x100
+#define ANACTRL_AUDDDS_CTRL1 0x104
+#define ANACTRL_AUDDDS_CTRL2 0x108
+#define ANACTRL_AUDDDS_CTRL3 0x10c
+#define ANACTRL_AUDDDS_CTRL4 0x110
+#define ANACTRL_AUDDDS_STS 0x114
+#define ANACTRL_MISCTOP_CTRL0 0x140
+#define ANACTRL_POR_CNTL 0x188
+
+/*
+ * CLKID index values
+ *
+ * These indices are entirely contrived and do not map onto the hardware.
+ * It has now been decided to expose everything by default in the DT header:
+ * include/dt-bindings/clock/a1-pll-clkc.h. Only the clocks ids we don't want
+ * to expose, such as the internal muxes and dividers of composite clocks,
+ * will remain defined here.
+ */
+#define CLKID_FIXED_PLL_DCO 0
+#define CLKID_FCLK_DIV2_DIV 2
+#define CLKID_FCLK_DIV3_DIV 3
+#define CLKID_FCLK_DIV5_DIV 4
+#define CLKID_FCLK_DIV7_DIV 5
+#define NR_PLL_CLKS 11
+
+/* include the CLKIDs that have been made part of the DT binding */
+#include <dt-bindings/clock/a1-pll-clkc.h>
+
+#endif /* __A1_PLL_H */
--
2.36.0
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v8 03/11] dt-bindings: clock: meson: add A1 peripheral clock controller bindings
2022-12-01 22:56 [PATCH v8 00/11] add Amlogic A1 clock controller drivers Dmitry Rokosov
2022-12-01 22:56 ` [PATCH v8 01/11] dt-bindings: clock: meson: add A1 PLL clock controller bindings Dmitry Rokosov
2022-12-01 22:56 ` [PATCH v8 02/11] clk: meson: a1: add support for Amlogic A1 PLL clock driver Dmitry Rokosov
@ 2022-12-01 22:56 ` Dmitry Rokosov
2022-12-02 4:10 ` Rob Herring
2022-12-02 10:43 ` Krzysztof Kozlowski
2022-12-01 22:56 ` [PATCH v8 04/11] clk: meson: a1: add support for Amlogic A1 Peripheral clock driver Dmitry Rokosov
` (7 subsequent siblings)
10 siblings, 2 replies; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-01 22:56 UTC (permalink / raw)
To: neil.armstrong, jbrunet, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Dmitry Rokosov
From: Jian Hu <jian.hu@amlogic.com>
Add the documentation to support Amlogic A1 peripheral clock driver,
and add A1 peripheral clock controller bindings.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
---
.../bindings/clock/amlogic,a1-clkc.yaml | 65 ++++++++++++
include/dt-bindings/clock/a1-clkc.h | 98 +++++++++++++++++++
2 files changed, 163 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
create mode 100644 include/dt-bindings/clock/a1-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
new file mode 100644
index 000000000000..7729850046cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
@@ -0,0 +1,65 @@
+#SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/amlogic,a1-clkc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic Meson A/C serials Peripheral Clock Control Unit Device Tree Bindings
+
+maintainers:
+ - Neil Armstrong <narmstrong@baylibre.com>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Jian Hu <jian.hu@jian.hu.com>
+
+properties:
+ compatible:
+ const: amlogic,a1-periphs-clkc
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: input fixed pll div2
+ - description: input fixed pll div3
+ - description: input fixed pll div5
+ - description: input fixed pll div7
+ - description: input hifi pll
+ - description: input oscillator (usually at 24MHz)
+
+ clock-names:
+ items:
+ - const: fclk_div2
+ - const: fclk_div3
+ - const: fclk_div5
+ - const: fclk_div7
+ - const: hifi_pll
+ - const: xtal
+
+required:
+ - compatible
+ - "#clock-cells"
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ clkc_periphs: periphs-clock-controller {
+ compatible = "amlogic,a1-periphs-clkc";
+ reg = <0 0x800 0 0x104>;
+ #clock-cells = <1>;
+ clocks = <&clkc_pll 6>,
+ <&clkc_pll 7>,
+ <&clkc_pll 8>,
+ <&clkc_pll 9>,
+ <&clkc_pll 10>,
+ <&xtal>;
+ clock-names = "fclk_div2", "fclk_div3", "fclk_div5",
+ "fclk_div7", "hifi_pll", "xtal";
+ };
diff --git a/include/dt-bindings/clock/a1-clkc.h b/include/dt-bindings/clock/a1-clkc.h
new file mode 100644
index 000000000000..9bb36fca86dd
--- /dev/null
+++ b/include/dt-bindings/clock/a1-clkc.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __A1_CLKC_H
+#define __A1_CLKC_H
+
+#define CLKID_XTAL_FIXPLL 1
+#define CLKID_XTAL_USB_PHY 2
+#define CLKID_XTAL_USB_CTRL 3
+#define CLKID_XTAL_HIFIPLL 4
+#define CLKID_XTAL_SYSPLL 5
+#define CLKID_XTAL_DDS 6
+#define CLKID_SYS_CLK 7
+#define CLKID_CLKTREE 8
+#define CLKID_RESET_CTRL 9
+#define CLKID_ANALOG_CTRL 10
+#define CLKID_PWR_CTRL 11
+#define CLKID_PAD_CTRL 12
+#define CLKID_SYS_CTRL 13
+#define CLKID_TEMP_SENSOR 14
+#define CLKID_AM2AXI_DIV 15
+#define CLKID_SPICC_B 16
+#define CLKID_SPICC_A 17
+#define CLKID_CLK_MSR 18
+#define CLKID_AUDIO 19
+#define CLKID_JTAG_CTRL 20
+#define CLKID_SARADC 21
+#define CLKID_PWM_EF 22
+#define CLKID_PWM_CD 23
+#define CLKID_PWM_AB 24
+#define CLKID_CEC 25
+#define CLKID_I2C_S 26
+#define CLKID_IR_CTRL 27
+#define CLKID_I2C_M_D 28
+#define CLKID_I2C_M_C 29
+#define CLKID_I2C_M_B 30
+#define CLKID_I2C_M_A 31
+#define CLKID_ACODEC 32
+#define CLKID_OTP 33
+#define CLKID_SD_EMMC_A 34
+#define CLKID_USB_PHY 35
+#define CLKID_USB_CTRL 36
+#define CLKID_SYS_DSPB 37
+#define CLKID_SYS_DSPA 38
+#define CLKID_DMA 39
+#define CLKID_IRQ_CTRL 40
+#define CLKID_NIC 41
+#define CLKID_GIC 42
+#define CLKID_UART_C 43
+#define CLKID_UART_B 44
+#define CLKID_UART_A 45
+#define CLKID_SYS_PSRAM 46
+#define CLKID_RSA 47
+#define CLKID_CORESIGHT 48
+#define CLKID_AM2AXI_VAD 49
+#define CLKID_AUDIO_VAD 50
+#define CLKID_AXI_DMC 51
+#define CLKID_AXI_PSRAM 52
+#define CLKID_RAMB 53
+#define CLKID_RAMA 54
+#define CLKID_AXI_SPIFC 55
+#define CLKID_AXI_NIC 56
+#define CLKID_AXI_DMA 57
+#define CLKID_CPU_CTRL 58
+#define CLKID_ROM 59
+#define CLKID_PROC_I2C 60
+#define CLKID_DSPA_SEL 61
+#define CLKID_DSPB_SEL 62
+#define CLKID_DSPA_EN 63
+#define CLKID_DSPA_EN_NIC 64
+#define CLKID_DSPB_EN 65
+#define CLKID_DSPB_EN_NIC 66
+#define CLKID_RTC_CLK 67
+#define CLKID_CECA_32K 68
+#define CLKID_CECB_32K 69
+#define CLKID_24M 70
+#define CLKID_12M 71
+#define CLKID_FCLK_DIV2_DIVN 72
+#define CLKID_GEN 73
+#define CLKID_SARADC_SEL 74
+#define CLKID_SARADC_CLK 75
+#define CLKID_PWM_A 76
+#define CLKID_PWM_B 77
+#define CLKID_PWM_C 78
+#define CLKID_PWM_D 79
+#define CLKID_PWM_E 80
+#define CLKID_PWM_F 81
+#define CLKID_SPICC 82
+#define CLKID_TS 83
+#define CLKID_SPIFC 84
+#define CLKID_USB_BUS 85
+#define CLKID_SD_EMMC 86
+#define CLKID_PSRAM 87
+#define CLKID_DMC 88
+
+#endif /* __A1_CLKC_H */
--
2.36.0
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v8 04/11] clk: meson: a1: add support for Amlogic A1 Peripheral clock driver
2022-12-01 22:56 [PATCH v8 00/11] add Amlogic A1 clock controller drivers Dmitry Rokosov
` (2 preceding siblings ...)
2022-12-01 22:56 ` [PATCH v8 03/11] dt-bindings: clock: meson: add A1 peripheral clock controller bindings Dmitry Rokosov
@ 2022-12-01 22:56 ` Dmitry Rokosov
2022-12-02 11:19 ` Jerome Brunet
2022-12-01 22:56 ` [PATCH v8 05/11] clk: meson: pll: export meson_clk_pll_wait_lock symbol Dmitry Rokosov
` (6 subsequent siblings)
10 siblings, 1 reply; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-01 22:56 UTC (permalink / raw)
To: neil.armstrong, jbrunet, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Dmitry Rokosov
From: Jian Hu <jian.hu@amlogic.com>
Add Amlogic Meson A1 peripheral clock driver, it depends
on the A1 PLL driver.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
---
drivers/clk/meson/Kconfig | 9 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/a1.c | 2249 ++++++++++++++++++++++++++++++++++++
drivers/clk/meson/a1.h | 120 ++
4 files changed, 2379 insertions(+)
create mode 100644 drivers/clk/meson/a1.c
create mode 100644 drivers/clk/meson/a1.h
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index ab34662b24f0..bd44ba47200e 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -108,6 +108,15 @@ config COMMON_CLK_A1_PLL
Support for the PLL clock controller on Amlogic A113L device,
aka a1. Say Y if you want PLL to work.
+config COMMON_CLK_A1
+ bool
+ depends on ARCH_MESON
+ select COMMON_CLK_MESON_DUALDIV
+ select COMMON_CLK_MESON_REGMAP
+ help
+ Support for the Peripheral clock controller on Amlogic A113L device,
+ aka a1. Say Y if you want Peripherals to work.
+
config COMMON_CLK_G12A
tristate "G12 and SM1 SoC clock controllers support"
depends on ARM64
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 2f17f475a48f..0e6f293c05d4 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o
obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o
+obj-$(CONFIG_COMMON_CLK_A1) += a1.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c
new file mode 100644
index 000000000000..2cf20ae1db75
--- /dev/null
+++ b/drivers/clk/meson/a1.c
@@ -0,0 +1,2249 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ * Author: Jian Hu <jian.hu@amlogic.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include "a1.h"
+#include "clk-dualdiv.h"
+#include "clk-regmap.h"
+
+static struct clk_regmap a1_xtal_clktree = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_OSCIN_CTRL,
+ .bit_idx = 0,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "xtal_clktree",
+ .ops = &clk_regmap_gate_ro_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_xtal_fixpll = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_OSCIN_CTRL,
+ .bit_idx = 1,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "xtal_fixpll",
+ .ops = &clk_regmap_gate_ro_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_xtal_usb_phy = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_OSCIN_CTRL,
+ .bit_idx = 2,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "xtal_usb_phy",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_xtal_usb_ctrl = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_OSCIN_CTRL,
+ .bit_idx = 3,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "xtal_usb_ctrl",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_xtal_hifipll = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_OSCIN_CTRL,
+ .bit_idx = 4,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "xtal_hifipll",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_xtal_syspll = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_OSCIN_CTRL,
+ .bit_idx = 5,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "xtal_syspll",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_xtal_dds = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_OSCIN_CTRL,
+ .bit_idx = 6,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "xtal_dds",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct clk_parent_data sys_clk_parents[] = {
+ { .fw_name = "xtal" },
+ { .fw_name = "fclk_div2" },
+ { .fw_name = "fclk_div3" },
+ { .fw_name = "fclk_div5" },
+};
+
+static struct clk_regmap a1_sys_b_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = SYS_CLK_CTRL0,
+ .mask = 0x7,
+ .shift = 26,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "sys_b_sel",
+ .ops = &clk_regmap_mux_ro_ops,
+ .parent_data = sys_clk_parents,
+ .num_parents = ARRAY_SIZE(sys_clk_parents),
+ },
+};
+
+static struct clk_regmap a1_sys_b_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = SYS_CLK_CTRL0,
+ .shift = 16,
+ .width = 10,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "sys_b_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_sys_b_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_sys_b = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_CLK_CTRL0,
+ .bit_idx = 29,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sys_b",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_sys_b_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_sys_a_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = SYS_CLK_CTRL0,
+ .mask = 0x7,
+ .shift = 10,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "sys_a_sel",
+ .ops = &clk_regmap_mux_ro_ops,
+ .parent_data = sys_clk_parents,
+ .num_parents = ARRAY_SIZE(sys_clk_parents),
+ },
+};
+
+static struct clk_regmap a1_sys_a_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = SYS_CLK_CTRL0,
+ .shift = 0,
+ .width = 10,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "sys_a_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_sys_a_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_sys_a = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SYS_CLK_CTRL0,
+ .bit_idx = 13,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sys_a",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_sys_a_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_sys_clk = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = SYS_CLK_CTRL0,
+ .mask = 0x1,
+ .shift = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "sys_clk",
+ .ops = &clk_regmap_mux_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_sys_a.hw, &a1_sys_b.hw,
+ },
+ .num_parents = 2,
+ /*
+ * This clock is used by APB bus which is set in boot ROM code
+ * and is required by the platform to operate correctly.
+ * Until the following condition are met, we need this clock to
+ * be marked as critical:
+ * a) Mark the clock used by a firmware resource, if possible
+ * b) CCF has a clock hand-off mechanism to make the sure the
+ * clock stays on until the proper driver comes along
+ */
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ },
+};
+
+static struct clk_regmap a1_rtc_32k_clkin = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = RTC_BY_OSCIN_CTRL0,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_32k_clkin",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct meson_clk_dualdiv_param a1_32k_div_table[] = {
+ {
+ .dual = 1,
+ .n1 = 733,
+ .m1 = 8,
+ .n2 = 732,
+ .m2 = 11,
+ },
+ {}
+};
+
+static struct clk_regmap a1_rtc_32k_div = {
+ .data = &(struct meson_clk_dualdiv_data){
+ .n1 = {
+ .reg_off = RTC_BY_OSCIN_CTRL0,
+ .shift = 0,
+ .width = 12,
+ },
+ .n2 = {
+ .reg_off = RTC_BY_OSCIN_CTRL0,
+ .shift = 12,
+ .width = 12,
+ },
+ .m1 = {
+ .reg_off = RTC_BY_OSCIN_CTRL1,
+ .shift = 0,
+ .width = 12,
+ },
+ .m2 = {
+ .reg_off = RTC_BY_OSCIN_CTRL1,
+ .shift = 12,
+ .width = 12,
+ },
+ .dual = {
+ .reg_off = RTC_BY_OSCIN_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .table = a1_32k_div_table,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "rtc_32k_div",
+ .ops = &meson_clk_dualdiv_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_rtc_32k_clkin.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_rtc_32k_xtal = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = RTC_BY_OSCIN_CTRL1,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_32k_xtal",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_rtc_32k_clkin.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_rtc_32k_sel = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = RTC_CTRL,
+ .mask = 0x3,
+ .shift = 0,
+ .flags = CLK_MUX_ROUND_CLOSEST,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "rtc_32k_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_rtc_32k_xtal.hw,
+ &a1_rtc_32k_div.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+struct clk_regmap a1_rtc_clk = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = RTC_BY_OSCIN_CTRL0,
+ .bit_idx = 30,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "rtc_clk",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_rtc_32k_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static u32 mux_table_dsp_ab[] = { 0, 1, 2, 3, 4, 7 };
+static const struct clk_parent_data dsp_ab_clk_parent_data[] = {
+ { .fw_name = "xtal", },
+ { .fw_name = "fclk_div2", },
+ { .fw_name = "fclk_div3", },
+ { .fw_name = "fclk_div5", },
+ { .fw_name = "hifi_pll", },
+ { .hw = &a1_rtc_clk.hw },
+};
+
+static struct clk_regmap a1_dspa_a_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = DSPA_CLK_CTRL0,
+ .mask = 0x7,
+ .shift = 10,
+ .table = mux_table_dsp_ab,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dspa_a_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = dsp_ab_clk_parent_data,
+ .num_parents = ARRAY_SIZE(dsp_ab_clk_parent_data),
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_dspa_a_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = DSPA_CLK_CTRL0,
+ .shift = 0,
+ .width = 10,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dspa_a_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_dspa_a_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_dspa_a = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = DSPA_CLK_CTRL0,
+ .bit_idx = 13,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspa_a",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_dspa_a_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_dspa_b_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = DSPA_CLK_CTRL0,
+ .mask = 0x7,
+ .shift = 26,
+ .table = mux_table_dsp_ab,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dspa_b_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = dsp_ab_clk_parent_data,
+ .num_parents = ARRAY_SIZE(dsp_ab_clk_parent_data),
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_dspa_b_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = DSPA_CLK_CTRL0,
+ .shift = 16,
+ .width = 10,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dspa_b_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_dspa_b_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_dspa_b = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = DSPA_CLK_CTRL0,
+ .bit_idx = 29,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspa_b",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_dspa_b_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_dspa_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = DSPA_CLK_CTRL0,
+ .mask = 0x1,
+ .shift = 15,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dspa_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .hw = &a1_dspa_a.hw },
+ { .hw = &a1_dspa_b.hw },
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_dspa_en = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = DSPA_CLK_EN,
+ .bit_idx = 1,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspa_en",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_dspa_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_dspa_en_nic = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = DSPA_CLK_EN,
+ .bit_idx = 0,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspa_en_nic",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_dspa_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_dspb_a_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = DSPB_CLK_CTRL0,
+ .mask = 0x7,
+ .shift = 10,
+ .table = mux_table_dsp_ab,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dspb_a_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = dsp_ab_clk_parent_data,
+ .num_parents = ARRAY_SIZE(dsp_ab_clk_parent_data),
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_dspb_a_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = DSPB_CLK_CTRL0,
+ .shift = 0,
+ .width = 10,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dspb_a_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_dspb_a_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_dspb_a = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = DSPB_CLK_CTRL0,
+ .bit_idx = 13,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspb_a",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_dspb_a_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_regmap a1_dspb_b_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = DSPB_CLK_CTRL0,
+ .mask = 0x7,
+ .shift = 26,
+ .table = mux_table_dsp_ab,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dspb_b_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = dsp_ab_clk_parent_data,
+ .num_parents = ARRAY_SIZE(dsp_ab_clk_parent_data),
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_dspb_b_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = DSPB_CLK_CTRL0,
+ .shift = 16,
+ .width = 10,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dspb_b_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_dspb_b_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_dspb_b = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = DSPB_CLK_CTRL0,
+ .bit_idx = 29,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspb_b",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_dspb_b_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_regmap a1_dspb_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = DSPB_CLK_CTRL0,
+ .mask = 0x1,
+ .shift = 15,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dspb_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_dspb_a.hw, &a1_dspb_b.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_dspb_en = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = DSPB_CLK_EN,
+ .bit_idx = 1,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspb_en",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_dspb_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_regmap a1_dspb_en_nic = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = DSPB_CLK_EN,
+ .bit_idx = 0,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspb_en_nic",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_dspb_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_regmap a1_24m = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = CLK12_24_CTRL,
+ .bit_idx = 11,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "24m",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor a1_24m_div2 = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "24m_div2",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_24m.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_12m = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = CLK12_24_CTRL,
+ .bit_idx = 10,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "12m",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_24m_div2.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_fclk_div2_divn_pre = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = CLK12_24_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div2_divn_pre",
+ .ops = &clk_regmap_divider_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "fclk_div2",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_fclk_div2_divn = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = CLK12_24_CTRL,
+ .bit_idx = 12,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div2_divn",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_fclk_div2_divn_pre.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+/*
+ * the index 2 is sys_pll_div16, it will complete in the CPU clock,
+ * the index 4 is the clock measurement source, it relies on
+ * the clock measurement register configuration.
+ */
+static u32 gen_clk_table[] = { 0, 1, 3, 5, 6, 7, 8 };
+static const struct clk_parent_data gen_clk_parent_data[] = {
+ { .fw_name = "xtal", },
+ { .hw = &a1_rtc_clk.hw },
+ { .fw_name = "hifi_pll", },
+ { .fw_name = "fclk_div2", },
+ { .fw_name = "fclk_div3", },
+ { .fw_name = "fclk_div5", },
+ { .fw_name = "fclk_div7", },
+};
+
+static struct clk_regmap a1_gen_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = GEN_CLK_CTRL,
+ .mask = 0xf,
+ .shift = 12,
+ .table = gen_clk_table,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "gen_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = gen_clk_parent_data,
+ .num_parents = ARRAY_SIZE(gen_clk_parent_data),
+ },
+};
+
+static struct clk_regmap a1_gen_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = GEN_CLK_CTRL,
+ .shift = 0,
+ .width = 11,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "gen_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_gen_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_gen = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = GEN_CLK_CTRL,
+ .bit_idx = 11,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "gen",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_gen_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_saradc_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = SAR_ADC_CLK_CTRL,
+ .mask = 0x1,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "saradc_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xtal", },
+ { .hw = &a1_sys_clk.hw, },
+ },
+ .num_parents = 2,
+ },
+};
+
+static struct clk_regmap a1_saradc_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = SAR_ADC_CLK_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "saradc_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_saradc_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_saradc_clk = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SAR_ADC_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "saradc_clk",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_saradc_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_pwm_a_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = PWM_CLK_AB_CTRL,
+ .mask = 0x1,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pwm_a_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xtal", },
+ { .hw = &a1_sys_clk.hw, },
+ },
+ .num_parents = 2,
+ },
+};
+
+static struct clk_regmap a1_pwm_a_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = PWM_CLK_AB_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pwm_a_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_pwm_a_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_pwm_a = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = PWM_CLK_AB_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_a",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_pwm_a_div.hw
+ },
+ .num_parents = 1,
+ /*
+ * The CPU working voltage is controlled by pwm_a
+ * in BL2 firmware. The clock is required by the platform
+ * to operate correctly. Add the CLK_IS_CRITICAL flag to
+ * avoid changing at runtime.
+ * About critical, refer to a1_sys_clk
+ */
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ },
+};
+
+static struct clk_regmap a1_pwm_b_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = PWM_CLK_AB_CTRL,
+ .mask = 0x1,
+ .shift = 25,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pwm_b_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xtal", },
+ { .hw = &a1_sys_clk.hw, },
+ },
+ .num_parents = 2,
+ },
+};
+
+static struct clk_regmap a1_pwm_b_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = PWM_CLK_AB_CTRL,
+ .shift = 16,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pwm_b_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_pwm_b_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_pwm_b = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = PWM_CLK_AB_CTRL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_b",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_pwm_b_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_pwm_c_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = PWM_CLK_CD_CTRL,
+ .mask = 0x1,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pwm_c_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xtal", },
+ { .hw = &a1_sys_clk.hw, },
+ },
+ .num_parents = 2,
+ },
+};
+
+static struct clk_regmap a1_pwm_c_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = PWM_CLK_CD_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pwm_c_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_pwm_c_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_pwm_c = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = PWM_CLK_CD_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_c",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_pwm_c_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_pwm_d_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = PWM_CLK_CD_CTRL,
+ .mask = 0x1,
+ .shift = 25,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pwm_d_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xtal", },
+ { .hw = &a1_sys_clk.hw, },
+ },
+ .num_parents = 2,
+ },
+};
+
+static struct clk_regmap a1_pwm_d_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = PWM_CLK_CD_CTRL,
+ .shift = 16,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pwm_d_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_pwm_d_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_pwm_d = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = PWM_CLK_CD_CTRL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_d",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_pwm_d_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data pwm_ef_parent_data[] = {
+ { .fw_name = "xtal", },
+ { .hw = &a1_sys_clk.hw },
+ { .fw_name = "fclk_div5", },
+ { .hw = &a1_rtc_clk.hw },
+};
+
+static struct clk_regmap a1_pwm_e_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = PWM_CLK_EF_CTRL,
+ .mask = 0x3,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pwm_e_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = pwm_ef_parent_data,
+ .num_parents = ARRAY_SIZE(pwm_ef_parent_data),
+ },
+};
+
+static struct clk_regmap a1_pwm_e_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = PWM_CLK_EF_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pwm_e_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_pwm_e_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_pwm_e = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = PWM_CLK_EF_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_e",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_pwm_e_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_pwm_f_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = PWM_CLK_EF_CTRL,
+ .mask = 0x3,
+ .shift = 25,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pwm_f_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = pwm_ef_parent_data,
+ .num_parents = ARRAY_SIZE(pwm_ef_parent_data),
+ },
+};
+
+static struct clk_regmap a1_pwm_f_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = PWM_CLK_EF_CTRL,
+ .shift = 16,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pwm_f_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_pwm_f_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_pwm_f = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = PWM_CLK_EF_CTRL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "pwm_f",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_pwm_f_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+/*
+ * spicc clk
+ * fdiv2 |\ |\ _____
+ * ---------| |---DIV--| | | | spicc out
+ * ---------| | | |-----|GATE |---------
+ * ..... |/ | / |_____|
+ * --------------------|/
+ * 24M
+ */
+static const struct clk_parent_data spicc_parents[] = {
+ { .fw_name = "fclk_div2"},
+ { .fw_name = "fclk_div3"},
+ { .fw_name = "fclk_div5"},
+ { .fw_name = "hifi_pll" },
+};
+
+static struct clk_regmap a1_spicc_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = SPICC_CLK_CTRL,
+ .mask = 0x3,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "spicc_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = spicc_parents,
+ .num_parents = 4,
+ },
+};
+
+static struct clk_regmap a1_spicc_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = SPICC_CLK_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "spicc_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_spicc_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_spicc_sel2 = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = SPICC_CLK_CTRL,
+ .mask = 0x1,
+ .shift = 15,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "spicc_sel2",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .hw = &a1_spicc_div.hw },
+ { .fw_name = "xtal", },
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_spicc = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SPICC_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "spicc",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_spicc_sel2.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_ts_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = TS_CLK_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ts_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_ts = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = TS_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "ts",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_ts_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_spifc_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = SPIFC_CLK_CTRL,
+ .mask = 0x3,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "spifc_sel",
+ .ops = &clk_regmap_mux_ops,
+ /* the same parent with spicc */
+ .parent_data = spicc_parents,
+ .num_parents = 4,
+ },
+};
+
+static struct clk_regmap a1_spifc_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = SPIFC_CLK_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "spifc_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_spifc_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_spifc_sel2 = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = SPIFC_CLK_CTRL,
+ .mask = 0x1,
+ .shift = 15,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "spifc_sel2",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .hw = &a1_spifc_div.hw },
+ { .fw_name = "xtal", },
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_spifc = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SPIFC_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "spifc",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_spifc_sel2.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data usb_bus_parent_data[] = {
+ { .fw_name = "xtal", },
+ { .hw = &a1_sys_clk.hw },
+ { .fw_name = "fclk_div3", },
+ { .fw_name = "fclk_div5", },
+};
+
+static struct clk_regmap a1_usb_bus_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = USB_BUSCLK_CTRL,
+ .mask = 0x3,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "usb_bus_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = usb_bus_parent_data,
+ .num_parents = ARRAY_SIZE(usb_bus_parent_data),
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_usb_bus_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = USB_BUSCLK_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "usb_bus_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_usb_bus_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_usb_bus = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = USB_BUSCLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "usb_bus",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_usb_bus_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data sd_emmc_parents[] = {
+ { .fw_name = "fclk_div2", },
+ { .fw_name = "fclk_div3", },
+ { .fw_name = "fclk_div5", },
+ { .fw_name = "hifi_pll", },
+};
+
+static struct clk_regmap a1_sd_emmc_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = SD_EMMC_CLK_CTRL,
+ .mask = 0x3,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "sd_emmc_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = sd_emmc_parents,
+ .num_parents = 4,
+ },
+};
+
+static struct clk_regmap a1_sd_emmc_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = SD_EMMC_CLK_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "sd_emmc_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_sd_emmc_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_sd_emmc_sel2 = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = SD_EMMC_CLK_CTRL,
+ .mask = 0x1,
+ .shift = 15,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "sd_emmc_sel2",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .hw = &a1_sd_emmc_div.hw },
+ { .fw_name = "xtal", },
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_sd_emmc = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = SD_EMMC_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "sd_emmc",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_sd_emmc_sel2.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_psram_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = PSRAM_CLK_CTRL,
+ .mask = 0x3,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "psram_sel",
+ .ops = &clk_regmap_mux_ops,
+ /* the same parent with sd_emmc */
+ .parent_data = sd_emmc_parents,
+ .num_parents = 4,
+ },
+};
+
+static struct clk_regmap a1_psram_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = PSRAM_CLK_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "psram_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_psram_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_psram_sel2 = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = PSRAM_CLK_CTRL,
+ .mask = 0x1,
+ .shift = 15,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "psram_sel2",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .hw = &a1_psram_div.hw },
+ { .fw_name = "xtal", },
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_psram = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = PSRAM_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "psram",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_psram_sel2.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_dmc_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = DMC_CLK_CTRL,
+ .mask = 0x3,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dmc_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = sd_emmc_parents,
+ .num_parents = 4,
+ },
+};
+
+static struct clk_regmap a1_dmc_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = DMC_CLK_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dmc_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_dmc_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_dmc_sel2 = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = DMC_CLK_CTRL,
+ .mask = 0x1,
+ .shift = 15,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dmc_sel2",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .hw = &a1_dmc_div.hw },
+ { .fw_name = "xtal", },
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_dmc = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = DMC_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dmc",
+ .ops = &clk_regmap_gate_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_dmc_sel2.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_ceca_32k_clkin = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = CECA_CLK_CTRL0,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "ceca_32k_clkin",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_ceca_32k_div = {
+ .data = &(struct meson_clk_dualdiv_data){
+ .n1 = {
+ .reg_off = CECA_CLK_CTRL0,
+ .shift = 0,
+ .width = 12,
+ },
+ .n2 = {
+ .reg_off = CECA_CLK_CTRL0,
+ .shift = 12,
+ .width = 12,
+ },
+ .m1 = {
+ .reg_off = CECA_CLK_CTRL1,
+ .shift = 0,
+ .width = 12,
+ },
+ .m2 = {
+ .reg_off = CECA_CLK_CTRL1,
+ .shift = 12,
+ .width = 12,
+ },
+ .dual = {
+ .reg_off = CECA_CLK_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .table = a1_32k_div_table,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ceca_32k_div",
+ .ops = &meson_clk_dualdiv_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_ceca_32k_clkin.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_ceca_32k_sel_pre = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CECA_CLK_CTRL1,
+ .mask = 0x1,
+ .shift = 24,
+ .flags = CLK_MUX_ROUND_CLOSEST,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ceca_32k_sel_pre",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_ceca_32k_div.hw,
+ &a1_ceca_32k_clkin.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_ceca_32k_sel = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CECA_CLK_CTRL1,
+ .mask = 0x1,
+ .shift = 31,
+ .flags = CLK_MUX_ROUND_CLOSEST,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ceca_32k_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_ceca_32k_sel_pre.hw,
+ &a1_rtc_clk.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_ceca_32k_clkout = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = CECA_CLK_CTRL0,
+ .bit_idx = 30,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ceca_32k_clkout",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_ceca_32k_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_cecb_32k_clkin = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = CECB_CLK_CTRL0,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "cecb_32k_clkin",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_cecb_32k_div = {
+ .data = &(struct meson_clk_dualdiv_data){
+ .n1 = {
+ .reg_off = CECB_CLK_CTRL0,
+ .shift = 0,
+ .width = 12,
+ },
+ .n2 = {
+ .reg_off = CECB_CLK_CTRL0,
+ .shift = 12,
+ .width = 12,
+ },
+ .m1 = {
+ .reg_off = CECB_CLK_CTRL1,
+ .shift = 0,
+ .width = 12,
+ },
+ .m2 = {
+ .reg_off = CECB_CLK_CTRL1,
+ .shift = 12,
+ .width = 12,
+ },
+ .dual = {
+ .reg_off = CECB_CLK_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .table = a1_32k_div_table,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "cecb_32k_div",
+ .ops = &meson_clk_dualdiv_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_cecb_32k_clkin.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_cecb_32k_sel_pre = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CECB_CLK_CTRL1,
+ .mask = 0x1,
+ .shift = 24,
+ .flags = CLK_MUX_ROUND_CLOSEST,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "cecb_32k_sel_pre",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_cecb_32k_div.hw,
+ &a1_cecb_32k_clkin.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_cecb_32k_sel = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CECB_CLK_CTRL1,
+ .mask = 0x1,
+ .shift = 31,
+ .flags = CLK_MUX_ROUND_CLOSEST,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "cecb_32k_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_cecb_32k_sel_pre.hw,
+ &a1_rtc_clk.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a1_cecb_32k_clkout = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = CECB_CLK_CTRL0,
+ .bit_idx = 30,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "cecb_32k_clkout",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_cecb_32k_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+#define MESON_GATE(_name, _reg, _bit) \
+ MESON_PCLK(_name, _reg, _bit, &a1_sys_clk.hw)
+
+static MESON_GATE(a1_clk_tree, SYS_CLK_EN0, 0);
+static MESON_GATE(a1_reset_ctrl, SYS_CLK_EN0, 1);
+static MESON_GATE(a1_analog_ctrl, SYS_CLK_EN0, 2);
+static MESON_GATE(a1_pwr_ctrl, SYS_CLK_EN0, 3);
+static MESON_GATE(a1_pad_ctrl, SYS_CLK_EN0, 4);
+static MESON_GATE(a1_sys_ctrl, SYS_CLK_EN0, 5);
+static MESON_GATE(a1_temp_sensor, SYS_CLK_EN0, 6);
+static MESON_GATE(a1_am2axi_dev, SYS_CLK_EN0, 7);
+static MESON_GATE(a1_spicc_b, SYS_CLK_EN0, 8);
+static MESON_GATE(a1_spicc_a, SYS_CLK_EN0, 9);
+static MESON_GATE(a1_clk_msr, SYS_CLK_EN0, 10);
+static MESON_GATE(a1_audio, SYS_CLK_EN0, 11);
+static MESON_GATE(a1_jtag_ctrl, SYS_CLK_EN0, 12);
+static MESON_GATE(a1_saradc, SYS_CLK_EN0, 13);
+static MESON_GATE(a1_pwm_ef, SYS_CLK_EN0, 14);
+static MESON_GATE(a1_pwm_cd, SYS_CLK_EN0, 15);
+static MESON_GATE(a1_pwm_ab, SYS_CLK_EN0, 16);
+static MESON_GATE(a1_cec, SYS_CLK_EN0, 17);
+static MESON_GATE(a1_i2c_s, SYS_CLK_EN0, 18);
+static MESON_GATE(a1_ir_ctrl, SYS_CLK_EN0, 19);
+static MESON_GATE(a1_i2c_m_d, SYS_CLK_EN0, 20);
+static MESON_GATE(a1_i2c_m_c, SYS_CLK_EN0, 21);
+static MESON_GATE(a1_i2c_m_b, SYS_CLK_EN0, 22);
+static MESON_GATE(a1_i2c_m_a, SYS_CLK_EN0, 23);
+static MESON_GATE(a1_acodec, SYS_CLK_EN0, 24);
+static MESON_GATE(a1_otp, SYS_CLK_EN0, 25);
+static MESON_GATE(a1_sd_emmc_a, SYS_CLK_EN0, 26);
+static MESON_GATE(a1_usb_phy, SYS_CLK_EN0, 27);
+static MESON_GATE(a1_usb_ctrl, SYS_CLK_EN0, 28);
+static MESON_GATE(a1_sys_dspb, SYS_CLK_EN0, 29);
+static MESON_GATE(a1_sys_dspa, SYS_CLK_EN0, 30);
+static MESON_GATE(a1_dma, SYS_CLK_EN0, 31);
+static MESON_GATE(a1_irq_ctrl, SYS_CLK_EN1, 0);
+static MESON_GATE(a1_nic, SYS_CLK_EN1, 1);
+static MESON_GATE(a1_gic, SYS_CLK_EN1, 2);
+static MESON_GATE(a1_uart_c, SYS_CLK_EN1, 3);
+static MESON_GATE(a1_uart_b, SYS_CLK_EN1, 4);
+static MESON_GATE(a1_uart_a, SYS_CLK_EN1, 5);
+static MESON_GATE(a1_sys_psram, SYS_CLK_EN1, 6);
+static MESON_GATE(a1_rsa, SYS_CLK_EN1, 8);
+static MESON_GATE(a1_coresight, SYS_CLK_EN1, 9);
+static MESON_GATE(a1_am2axi_vad, AXI_CLK_EN, 0);
+static MESON_GATE(a1_audio_vad, AXI_CLK_EN, 1);
+static MESON_GATE(a1_axi_dmc, AXI_CLK_EN, 3);
+static MESON_GATE(a1_axi_psram, AXI_CLK_EN, 4);
+static MESON_GATE(a1_ramb, AXI_CLK_EN, 5);
+static MESON_GATE(a1_rama, AXI_CLK_EN, 6);
+static MESON_GATE(a1_axi_spifc, AXI_CLK_EN, 7);
+static MESON_GATE(a1_axi_nic, AXI_CLK_EN, 8);
+static MESON_GATE(a1_axi_dma, AXI_CLK_EN, 9);
+static MESON_GATE(a1_cpu_ctrl, AXI_CLK_EN, 10);
+static MESON_GATE(a1_rom, AXI_CLK_EN, 11);
+static MESON_GATE(a1_prod_i2c, AXI_CLK_EN, 12);
+
+/* Array of all clocks provided by this provider */
+static struct clk_hw_onecell_data a1_periphs_hw_onecell_data = {
+ .hws = {
+ [CLKID_SYS_B_SEL] = &a1_sys_b_sel.hw,
+ [CLKID_SYS_B_DIV] = &a1_sys_b_div.hw,
+ [CLKID_SYS_B] = &a1_sys_b.hw,
+ [CLKID_SYS_A_SEL] = &a1_sys_a_sel.hw,
+ [CLKID_SYS_A_DIV] = &a1_sys_a_div.hw,
+ [CLKID_SYS_A] = &a1_sys_a.hw,
+ [CLKID_SYS_CLK] = &a1_sys_clk.hw,
+ [CLKID_XTAL_CLKTREE] = &a1_xtal_clktree.hw,
+ [CLKID_XTAL_FIXPLL] = &a1_xtal_fixpll.hw,
+ [CLKID_XTAL_USB_PHY] = &a1_xtal_usb_phy.hw,
+ [CLKID_XTAL_USB_CTRL] = &a1_xtal_usb_ctrl.hw,
+ [CLKID_XTAL_HIFIPLL] = &a1_xtal_hifipll.hw,
+ [CLKID_XTAL_SYSPLL] = &a1_xtal_syspll.hw,
+ [CLKID_XTAL_DDS] = &a1_xtal_dds.hw,
+ [CLKID_CLKTREE] = &a1_clk_tree.hw,
+ [CLKID_RESET_CTRL] = &a1_reset_ctrl.hw,
+ [CLKID_ANALOG_CTRL] = &a1_analog_ctrl.hw,
+ [CLKID_PWR_CTRL] = &a1_pwr_ctrl.hw,
+ [CLKID_PAD_CTRL] = &a1_pad_ctrl.hw,
+ [CLKID_SYS_CTRL] = &a1_sys_ctrl.hw,
+ [CLKID_TEMP_SENSOR] = &a1_temp_sensor.hw,
+ [CLKID_AM2AXI_DIV] = &a1_am2axi_dev.hw,
+ [CLKID_SPICC_B] = &a1_spicc_b.hw,
+ [CLKID_SPICC_A] = &a1_spicc_a.hw,
+ [CLKID_CLK_MSR] = &a1_clk_msr.hw,
+ [CLKID_AUDIO] = &a1_audio.hw,
+ [CLKID_JTAG_CTRL] = &a1_jtag_ctrl.hw,
+ [CLKID_SARADC] = &a1_saradc.hw,
+ [CLKID_PWM_EF] = &a1_pwm_ef.hw,
+ [CLKID_PWM_CD] = &a1_pwm_cd.hw,
+ [CLKID_PWM_AB] = &a1_pwm_ab.hw,
+ [CLKID_CEC] = &a1_cec.hw,
+ [CLKID_I2C_S] = &a1_i2c_s.hw,
+ [CLKID_IR_CTRL] = &a1_ir_ctrl.hw,
+ [CLKID_I2C_M_D] = &a1_i2c_m_d.hw,
+ [CLKID_I2C_M_C] = &a1_i2c_m_c.hw,
+ [CLKID_I2C_M_B] = &a1_i2c_m_b.hw,
+ [CLKID_I2C_M_A] = &a1_i2c_m_a.hw,
+ [CLKID_ACODEC] = &a1_acodec.hw,
+ [CLKID_OTP] = &a1_otp.hw,
+ [CLKID_SD_EMMC_A] = &a1_sd_emmc_a.hw,
+ [CLKID_USB_PHY] = &a1_usb_phy.hw,
+ [CLKID_USB_CTRL] = &a1_usb_ctrl.hw,
+ [CLKID_SYS_DSPB] = &a1_sys_dspb.hw,
+ [CLKID_SYS_DSPA] = &a1_sys_dspa.hw,
+ [CLKID_DMA] = &a1_dma.hw,
+ [CLKID_IRQ_CTRL] = &a1_irq_ctrl.hw,
+ [CLKID_NIC] = &a1_nic.hw,
+ [CLKID_GIC] = &a1_gic.hw,
+ [CLKID_UART_C] = &a1_uart_c.hw,
+ [CLKID_UART_B] = &a1_uart_b.hw,
+ [CLKID_UART_A] = &a1_uart_a.hw,
+ [CLKID_SYS_PSRAM] = &a1_sys_psram.hw,
+ [CLKID_RSA] = &a1_rsa.hw,
+ [CLKID_CORESIGHT] = &a1_coresight.hw,
+ [CLKID_AM2AXI_VAD] = &a1_am2axi_vad.hw,
+ [CLKID_AUDIO_VAD] = &a1_audio_vad.hw,
+ [CLKID_AXI_DMC] = &a1_axi_dmc.hw,
+ [CLKID_AXI_PSRAM] = &a1_axi_psram.hw,
+ [CLKID_RAMB] = &a1_ramb.hw,
+ [CLKID_RAMA] = &a1_rama.hw,
+ [CLKID_AXI_SPIFC] = &a1_axi_spifc.hw,
+ [CLKID_AXI_NIC] = &a1_axi_nic.hw,
+ [CLKID_AXI_DMA] = &a1_axi_dma.hw,
+ [CLKID_CPU_CTRL] = &a1_cpu_ctrl.hw,
+ [CLKID_ROM] = &a1_rom.hw,
+ [CLKID_PROC_I2C] = &a1_prod_i2c.hw,
+ [CLKID_DSPA_A_SEL] = &a1_dspa_a_sel.hw,
+ [CLKID_DSPA_A_DIV] = &a1_dspa_a_div.hw,
+ [CLKID_DSPA_A] = &a1_dspa_a.hw,
+ [CLKID_DSPA_B_SEL] = &a1_dspa_b_sel.hw,
+ [CLKID_DSPA_B_DIV] = &a1_dspa_b_div.hw,
+ [CLKID_DSPA_B] = &a1_dspa_b.hw,
+ [CLKID_DSPA_SEL] = &a1_dspa_sel.hw,
+ [CLKID_DSPB_A_SEL] = &a1_dspb_a_sel.hw,
+ [CLKID_DSPB_A_DIV] = &a1_dspb_a_div.hw,
+ [CLKID_DSPB_A] = &a1_dspb_a.hw,
+ [CLKID_DSPB_B_SEL] = &a1_dspb_b_sel.hw,
+ [CLKID_DSPB_B_DIV] = &a1_dspb_b_div.hw,
+ [CLKID_DSPB_B] = &a1_dspb_b.hw,
+ [CLKID_DSPB_SEL] = &a1_dspb_sel.hw,
+ [CLKID_DSPA_EN] = &a1_dspa_en.hw,
+ [CLKID_DSPA_EN_NIC] = &a1_dspa_en_nic.hw,
+ [CLKID_DSPB_EN] = &a1_dspb_en.hw,
+ [CLKID_DSPB_EN_NIC] = &a1_dspb_en_nic.hw,
+ [CLKID_24M] = &a1_24m.hw,
+ [CLKID_24M_DIV2] = &a1_24m_div2.hw,
+ [CLKID_12M] = &a1_12m.hw,
+ [CLKID_DIV2_PRE] = &a1_fclk_div2_divn_pre.hw,
+ [CLKID_FCLK_DIV2_DIVN] = &a1_fclk_div2_divn.hw,
+ [CLKID_GEN_SEL] = &a1_gen_sel.hw,
+ [CLKID_GEN_DIV] = &a1_gen_div.hw,
+ [CLKID_GEN] = &a1_gen.hw,
+ [CLKID_SARADC_SEL] = &a1_saradc_sel.hw,
+ [CLKID_SARADC_DIV] = &a1_saradc_div.hw,
+ [CLKID_SARADC_CLK] = &a1_saradc_clk.hw,
+ [CLKID_PWM_A_SEL] = &a1_pwm_a_sel.hw,
+ [CLKID_PWM_A_DIV] = &a1_pwm_a_div.hw,
+ [CLKID_PWM_A] = &a1_pwm_a.hw,
+ [CLKID_PWM_B_SEL] = &a1_pwm_b_sel.hw,
+ [CLKID_PWM_B_DIV] = &a1_pwm_b_div.hw,
+ [CLKID_PWM_B] = &a1_pwm_b.hw,
+ [CLKID_PWM_C_SEL] = &a1_pwm_c_sel.hw,
+ [CLKID_PWM_C_DIV] = &a1_pwm_c_div.hw,
+ [CLKID_PWM_C] = &a1_pwm_c.hw,
+ [CLKID_PWM_D_SEL] = &a1_pwm_d_sel.hw,
+ [CLKID_PWM_D_DIV] = &a1_pwm_d_div.hw,
+ [CLKID_PWM_D] = &a1_pwm_d.hw,
+ [CLKID_PWM_E_SEL] = &a1_pwm_e_sel.hw,
+ [CLKID_PWM_E_DIV] = &a1_pwm_e_div.hw,
+ [CLKID_PWM_E] = &a1_pwm_e.hw,
+ [CLKID_PWM_F_SEL] = &a1_pwm_f_sel.hw,
+ [CLKID_PWM_F_DIV] = &a1_pwm_f_div.hw,
+ [CLKID_PWM_F] = &a1_pwm_f.hw,
+ [CLKID_SPICC_SEL] = &a1_spicc_sel.hw,
+ [CLKID_SPICC_DIV] = &a1_spicc_div.hw,
+ [CLKID_SPICC_SEL2] = &a1_spicc_sel2.hw,
+ [CLKID_SPICC] = &a1_spicc.hw,
+ [CLKID_TS_DIV] = &a1_ts_div.hw,
+ [CLKID_TS] = &a1_ts.hw,
+ [CLKID_SPIFC_SEL] = &a1_spifc_sel.hw,
+ [CLKID_SPIFC_DIV] = &a1_spifc_div.hw,
+ [CLKID_SPIFC_SEL2] = &a1_spifc_sel2.hw,
+ [CLKID_SPIFC] = &a1_spifc.hw,
+ [CLKID_USB_BUS_SEL] = &a1_usb_bus_sel.hw,
+ [CLKID_USB_BUS_DIV] = &a1_usb_bus_div.hw,
+ [CLKID_USB_BUS] = &a1_usb_bus.hw,
+ [CLKID_SD_EMMC_SEL] = &a1_sd_emmc_sel.hw,
+ [CLKID_SD_EMMC_DIV] = &a1_sd_emmc_div.hw,
+ [CLKID_SD_EMMC_SEL2] = &a1_sd_emmc_sel2.hw,
+ [CLKID_SD_EMMC] = &a1_sd_emmc.hw,
+ [CLKID_PSRAM_SEL] = &a1_psram_sel.hw,
+ [CLKID_PSRAM_DIV] = &a1_psram_div.hw,
+ [CLKID_PSRAM_SEL2] = &a1_psram_sel2.hw,
+ [CLKID_PSRAM] = &a1_psram.hw,
+ [CLKID_DMC_SEL] = &a1_dmc_sel.hw,
+ [CLKID_DMC_DIV] = &a1_dmc_div.hw,
+ [CLKID_DMC_SEL2] = &a1_dmc_sel2.hw,
+ [CLKID_DMC] = &a1_dmc.hw,
+ [CLKID_RTC_32K_CLKIN] = &a1_rtc_32k_clkin.hw,
+ [CLKID_RTC_32K_DIV] = &a1_rtc_32k_div.hw,
+ [CLKID_RTC_32K_XTAL] = &a1_rtc_32k_xtal.hw,
+ [CLKID_RTC_32K_SEL] = &a1_rtc_32k_sel.hw,
+ [CLKID_RTC_CLK] = &a1_rtc_clk.hw,
+ [CLKID_CECA_32K_CLKIN] = &a1_ceca_32k_clkin.hw,
+ [CLKID_CECA_32K_DIV] = &a1_ceca_32k_div.hw,
+ [CLKID_CECA_32K_SEL_PRE] = &a1_ceca_32k_sel_pre.hw,
+ [CLKID_CECA_32K_SEL] = &a1_ceca_32k_sel.hw,
+ [CLKID_CECA_32K] = &a1_ceca_32k_clkout.hw,
+ [CLKID_CECB_32K_CLKIN] = &a1_cecb_32k_clkin.hw,
+ [CLKID_CECB_32K_DIV] = &a1_cecb_32k_div.hw,
+ [CLKID_CECB_32K_SEL_PRE] = &a1_cecb_32k_sel_pre.hw,
+ [CLKID_CECB_32K_SEL] = &a1_cecb_32k_sel.hw,
+ [CLKID_CECB_32K] = &a1_cecb_32k_clkout.hw,
+ [NR_CLKS] = NULL,
+ },
+ .num = NR_CLKS,
+};
+
+/* Convenience table to populate regmap in .probe */
+static struct clk_regmap *const a1_periphs_regmaps[] = {
+ &a1_xtal_clktree,
+ &a1_xtal_fixpll,
+ &a1_xtal_usb_phy,
+ &a1_xtal_usb_ctrl,
+ &a1_xtal_hifipll,
+ &a1_xtal_syspll,
+ &a1_xtal_dds,
+ &a1_clk_tree,
+ &a1_reset_ctrl,
+ &a1_analog_ctrl,
+ &a1_pwr_ctrl,
+ &a1_sys_ctrl,
+ &a1_temp_sensor,
+ &a1_am2axi_dev,
+ &a1_spicc_b,
+ &a1_spicc_a,
+ &a1_clk_msr,
+ &a1_audio,
+ &a1_jtag_ctrl,
+ &a1_saradc,
+ &a1_pwm_ef,
+ &a1_pwm_cd,
+ &a1_pwm_ab,
+ &a1_cec,
+ &a1_i2c_s,
+ &a1_ir_ctrl,
+ &a1_i2c_m_d,
+ &a1_i2c_m_c,
+ &a1_i2c_m_b,
+ &a1_i2c_m_a,
+ &a1_acodec,
+ &a1_otp,
+ &a1_sd_emmc_a,
+ &a1_usb_phy,
+ &a1_usb_ctrl,
+ &a1_sys_dspb,
+ &a1_sys_dspa,
+ &a1_dma,
+ &a1_irq_ctrl,
+ &a1_nic,
+ &a1_gic,
+ &a1_uart_c,
+ &a1_uart_b,
+ &a1_uart_a,
+ &a1_sys_psram,
+ &a1_rsa,
+ &a1_coresight,
+ &a1_am2axi_vad,
+ &a1_audio_vad,
+ &a1_axi_dmc,
+ &a1_axi_psram,
+ &a1_ramb,
+ &a1_rama,
+ &a1_axi_spifc,
+ &a1_axi_nic,
+ &a1_axi_dma,
+ &a1_cpu_ctrl,
+ &a1_rom,
+ &a1_prod_i2c,
+ &a1_dspa_a_sel,
+ &a1_dspa_a_div,
+ &a1_dspa_a,
+ &a1_dspa_b_sel,
+ &a1_dspa_b_div,
+ &a1_dspa_b,
+ &a1_dspa_sel,
+ &a1_dspb_a_sel,
+ &a1_dspb_a_div,
+ &a1_dspb_a,
+ &a1_dspb_b_sel,
+ &a1_dspb_b_div,
+ &a1_dspb_b,
+ &a1_dspb_sel,
+ &a1_dspa_en,
+ &a1_dspa_en_nic,
+ &a1_dspb_en,
+ &a1_dspb_en_nic,
+ &a1_24m,
+ &a1_12m,
+ &a1_fclk_div2_divn_pre,
+ &a1_fclk_div2_divn,
+ &a1_gen_sel,
+ &a1_gen_div,
+ &a1_gen,
+ &a1_saradc_sel,
+ &a1_saradc_div,
+ &a1_saradc_clk,
+ &a1_pwm_a_sel,
+ &a1_pwm_a_div,
+ &a1_pwm_a,
+ &a1_pwm_b_sel,
+ &a1_pwm_b_div,
+ &a1_pwm_b,
+ &a1_pwm_c_sel,
+ &a1_pwm_c_div,
+ &a1_pwm_c,
+ &a1_pwm_d_sel,
+ &a1_pwm_d_div,
+ &a1_pwm_d,
+ &a1_pwm_e_sel,
+ &a1_pwm_e_div,
+ &a1_pwm_e,
+ &a1_pwm_f_sel,
+ &a1_pwm_f_div,
+ &a1_pwm_f,
+ &a1_spicc_sel,
+ &a1_spicc_div,
+ &a1_spicc_sel2,
+ &a1_spicc,
+ &a1_ts_div,
+ &a1_ts,
+ &a1_spifc_sel,
+ &a1_spifc_div,
+ &a1_spifc_sel2,
+ &a1_spifc,
+ &a1_usb_bus_sel,
+ &a1_usb_bus_div,
+ &a1_usb_bus,
+ &a1_sd_emmc_sel,
+ &a1_sd_emmc_div,
+ &a1_sd_emmc_sel2,
+ &a1_sd_emmc,
+ &a1_psram_sel,
+ &a1_psram_div,
+ &a1_psram_sel2,
+ &a1_psram,
+ &a1_dmc_sel,
+ &a1_dmc_div,
+ &a1_dmc_sel2,
+ &a1_dmc,
+ &a1_sys_b_sel,
+ &a1_sys_b_div,
+ &a1_sys_b,
+ &a1_sys_a_sel,
+ &a1_sys_a_div,
+ &a1_sys_a,
+ &a1_sys_clk,
+ &a1_rtc_32k_clkin,
+ &a1_rtc_32k_div,
+ &a1_rtc_32k_xtal,
+ &a1_rtc_32k_sel,
+ &a1_rtc_clk,
+ &a1_ceca_32k_clkin,
+ &a1_ceca_32k_div,
+ &a1_ceca_32k_sel_pre,
+ &a1_ceca_32k_sel,
+ &a1_ceca_32k_clkout,
+ &a1_cecb_32k_clkin,
+ &a1_cecb_32k_div,
+ &a1_cecb_32k_sel_pre,
+ &a1_cecb_32k_sel,
+ &a1_cecb_32k_clkout,
+};
+
+static struct regmap_config clkc_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
+static int meson_a1_periphs_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ void __iomem *base;
+ struct regmap *map;
+ int ret, i;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ map = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
+ if (IS_ERR(map))
+ return PTR_ERR(map);
+
+ /* Populate regmap for the regmap backed clocks */
+ for (i = 0; i < ARRAY_SIZE(a1_periphs_regmaps); i++)
+ a1_periphs_regmaps[i]->map = map;
+
+ for (i = 0; i < a1_periphs_hw_onecell_data.num; i++) {
+ /* array might be sparse */
+ if (!a1_periphs_hw_onecell_data.hws[i])
+ continue;
+
+ ret = devm_clk_hw_register(dev,
+ a1_periphs_hw_onecell_data.hws[i]);
+ if (ret) {
+ dev_err(dev, "Clock registration failed\n");
+ return ret;
+ }
+ }
+
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+ &a1_periphs_hw_onecell_data);
+}
+
+static const struct of_device_id clkc_match_table[] = {
+ { .compatible = "amlogic,a1-periphs-clkc", },
+ {}
+};
+
+static struct platform_driver a1_periphs_driver = {
+ .probe = meson_a1_periphs_probe,
+ .driver = {
+ .name = "a1-periphs-clkc",
+ .of_match_table = clkc_match_table,
+ },
+};
+
+builtin_platform_driver(a1_periphs_driver);
diff --git a/drivers/clk/meson/a1.h b/drivers/clk/meson/a1.h
new file mode 100644
index 000000000000..1ae5e04848d6
--- /dev/null
+++ b/drivers/clk/meson/a1.h
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __A1_H
+#define __A1_H
+
+/* peripheral clock controller register offset */
+#define SYS_OSCIN_CTRL 0x0
+#define RTC_BY_OSCIN_CTRL0 0x4
+#define RTC_BY_OSCIN_CTRL1 0x8
+#define RTC_CTRL 0xc
+#define SYS_CLK_CTRL0 0x10
+#define AXI_CLK_CTRL0 0x14
+#define SYS_CLK_EN0 0x1c
+#define SYS_CLK_EN1 0x20
+#define AXI_CLK_EN 0x24
+#define DSPA_CLK_EN 0x28
+#define DSPB_CLK_EN 0x2c
+#define DSPA_CLK_CTRL0 0x30
+#define DSPB_CLK_CTRL0 0x34
+#define CLK12_24_CTRL 0x38
+#define GEN_CLK_CTRL 0x3c
+#define TIMESTAMP_CTRL0 0x40
+#define TIMESTAMP_CTRL1 0x44
+#define TIMESTAMP_CTRL2 0x48
+#define TIMESTAMP_VAL0 0x4c
+#define TIMESTAMP_VAL1 0x50
+#define TIMEBASE_CTRL0 0x54
+#define TIMEBASE_CTRL1 0x58
+#define SAR_ADC_CLK_CTRL 0xc0
+#define PWM_CLK_AB_CTRL 0xc4
+#define PWM_CLK_CD_CTRL 0xc8
+#define PWM_CLK_EF_CTRL 0xcc
+#define SPICC_CLK_CTRL 0xd0
+#define TS_CLK_CTRL 0xd4
+#define SPIFC_CLK_CTRL 0xd8
+#define USB_BUSCLK_CTRL 0xdc
+#define SD_EMMC_CLK_CTRL 0xe0
+#define CECA_CLK_CTRL0 0xe4
+#define CECA_CLK_CTRL1 0xe8
+#define CECB_CLK_CTRL0 0xec
+#define CECB_CLK_CTRL1 0xf0
+#define PSRAM_CLK_CTRL 0xf4
+#define DMC_CLK_CTRL 0xf8
+#define FCLK_DIV1_SEL 0xfc
+#define TST_CTRL 0x100
+
+#define CLKID_XTAL_CLKTREE 0
+#define CLKID_SYS_A_SEL 89
+#define CLKID_SYS_A_DIV 90
+#define CLKID_SYS_A 91
+#define CLKID_SYS_B_SEL 92
+#define CLKID_SYS_B_DIV 93
+#define CLKID_SYS_B 94
+#define CLKID_DSPA_A_SEL 95
+#define CLKID_DSPA_A_DIV 96
+#define CLKID_DSPA_A 97
+#define CLKID_DSPA_B_SEL 98
+#define CLKID_DSPA_B_DIV 99
+#define CLKID_DSPA_B 100
+#define CLKID_DSPB_A_SEL 101
+#define CLKID_DSPB_A_DIV 102
+#define CLKID_DSPB_A 103
+#define CLKID_DSPB_B_SEL 104
+#define CLKID_DSPB_B_DIV 105
+#define CLKID_DSPB_B 106
+#define CLKID_RTC_32K_CLKIN 107
+#define CLKID_RTC_32K_DIV 108
+#define CLKID_RTC_32K_XTAL 109
+#define CLKID_RTC_32K_SEL 110
+#define CLKID_CECB_32K_CLKIN 111
+#define CLKID_CECB_32K_DIV 112
+#define CLKID_CECB_32K_SEL_PRE 113
+#define CLKID_CECB_32K_SEL 114
+#define CLKID_CECA_32K_CLKIN 115
+#define CLKID_CECA_32K_DIV 116
+#define CLKID_CECA_32K_SEL_PRE 117
+#define CLKID_CECA_32K_SEL 118
+#define CLKID_DIV2_PRE 119
+#define CLKID_24M_DIV2 120
+#define CLKID_GEN_SEL 121
+#define CLKID_GEN_DIV 122
+#define CLKID_SARADC_DIV 123
+#define CLKID_PWM_A_SEL 124
+#define CLKID_PWM_A_DIV 125
+#define CLKID_PWM_B_SEL 126
+#define CLKID_PWM_B_DIV 127
+#define CLKID_PWM_C_SEL 128
+#define CLKID_PWM_C_DIV 129
+#define CLKID_PWM_D_SEL 130
+#define CLKID_PWM_D_DIV 131
+#define CLKID_PWM_E_SEL 132
+#define CLKID_PWM_E_DIV 133
+#define CLKID_PWM_F_SEL 134
+#define CLKID_PWM_F_DIV 135
+#define CLKID_SPICC_SEL 136
+#define CLKID_SPICC_DIV 137
+#define CLKID_SPICC_SEL2 138
+#define CLKID_TS_DIV 139
+#define CLKID_SPIFC_SEL 140
+#define CLKID_SPIFC_DIV 141
+#define CLKID_SPIFC_SEL2 142
+#define CLKID_USB_BUS_SEL 143
+#define CLKID_USB_BUS_DIV 144
+#define CLKID_SD_EMMC_SEL 145
+#define CLKID_SD_EMMC_DIV 146
+#define CLKID_SD_EMMC_SEL2 147
+#define CLKID_PSRAM_SEL 148
+#define CLKID_PSRAM_DIV 149
+#define CLKID_PSRAM_SEL2 150
+#define CLKID_DMC_SEL 151
+#define CLKID_DMC_DIV 152
+#define CLKID_DMC_SEL2 153
+#define NR_CLKS 154
+
+#include <dt-bindings/clock/a1-clkc.h>
+
+#endif /* __A1_H */
--
2.36.0
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v8 05/11] clk: meson: pll: export meson_clk_pll_wait_lock symbol
2022-12-01 22:56 [PATCH v8 00/11] add Amlogic A1 clock controller drivers Dmitry Rokosov
` (3 preceding siblings ...)
2022-12-01 22:56 ` [PATCH v8 04/11] clk: meson: a1: add support for Amlogic A1 Peripheral clock driver Dmitry Rokosov
@ 2022-12-01 22:56 ` Dmitry Rokosov
2022-12-01 22:56 ` [PATCH v8 06/11] clk: meson: introduce a1-clkc common driver for all A1 clock controllers Dmitry Rokosov
` (5 subsequent siblings)
10 siblings, 0 replies; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-01 22:56 UTC (permalink / raw)
To: neil.armstrong, jbrunet, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Dmitry Rokosov
Modern meson PLL IPs are a little bit different from early known PLLs.
The main difference is located in the init/enable/disable sequences; the
rate logic is the same. So drivers for the new PLLs can be inherited
from the clk-pll driver and redefine init/enable/disable routines only.
For that purpose we need to have meson_clk_pll_wait_lock() in the export
symbols list, because each lock operation should be ended with wait
cycles.
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
---
drivers/clk/meson/clk-pll.c | 3 ++-
drivers/clk/meson/clk-pll.h | 2 ++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 9e55617bc3b4..81c810d57a48 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -273,7 +273,7 @@ static int meson_clk_pll_determine_rate(struct clk_hw *hw,
return 0;
}
-static int meson_clk_pll_wait_lock(struct clk_hw *hw)
+int meson_clk_pll_wait_lock(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
@@ -289,6 +289,7 @@ static int meson_clk_pll_wait_lock(struct clk_hw *hw)
return -ETIMEDOUT;
}
+EXPORT_SYMBOL_GPL(meson_clk_pll_wait_lock);
static int meson_clk_pll_init(struct clk_hw *hw)
{
diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h
index 367efd0f6410..85fec18c4b8a 100644
--- a/drivers/clk/meson/clk-pll.h
+++ b/drivers/clk/meson/clk-pll.h
@@ -47,4 +47,6 @@ extern const struct clk_ops meson_clk_pll_ro_ops;
extern const struct clk_ops meson_clk_pll_ops;
extern const struct clk_ops meson_clk_pcie_pll_ops;
+int meson_clk_pll_wait_lock(struct clk_hw *hw);
+
#endif /* __MESON_CLK_PLL_H */
--
2.36.0
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v8 06/11] clk: meson: introduce a1-clkc common driver for all A1 clock controllers
2022-12-01 22:56 [PATCH v8 00/11] add Amlogic A1 clock controller drivers Dmitry Rokosov
` (4 preceding siblings ...)
2022-12-01 22:56 ` [PATCH v8 05/11] clk: meson: pll: export meson_clk_pll_wait_lock symbol Dmitry Rokosov
@ 2022-12-01 22:56 ` Dmitry Rokosov
2022-12-02 11:36 ` Jerome Brunet
2022-12-01 22:56 ` [PATCH v8 07/11] clk: meson: a1: redesign Amlogic A1 PLL clock controller Dmitry Rokosov
` (4 subsequent siblings)
10 siblings, 1 reply; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-01 22:56 UTC (permalink / raw)
To: neil.armstrong, jbrunet, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Dmitry Rokosov
Generally, A1 SoC has four clock controllers on the board: PLL,
Peripherals, CPU, and Audio. The audio clock controller is different
from others, but the rest are very similar from a functional and regmap
point of view. So a it's good idea to generalize some routines for all
of them. Exactly, meson-a1-clkc driver contains the common probe() flow.
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
---
drivers/clk/meson/Kconfig | 4 ++
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/meson-a1-clkc.c | 63 +++++++++++++++++++++++++++++++
drivers/clk/meson/meson-a1-clkc.h | 25 ++++++++++++
4 files changed, 93 insertions(+)
create mode 100644 drivers/clk/meson/meson-a1-clkc.c
create mode 100644 drivers/clk/meson/meson-a1-clkc.h
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index bd44ba47200e..1c885541c3a9 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -43,6 +43,10 @@ config COMMON_CLK_MESON_CPU_DYNDIV
tristate
select COMMON_CLK_MESON_REGMAP
+config COMMON_CLK_MESON_A1_CLKC
+ tristate
+ select COMMON_CLK_MESON_REGMAP
+
config COMMON_CLK_MESON8B
bool "Meson8 SoC Clock controller support"
depends on ARM
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 0e6f293c05d4..15136d861a65 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o
obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o
obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o
obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o
+obj-$(CONFIG_COMMON_CLK_MESON_A1_CLKC) += meson-a1-clkc.o
# Amlogic Clock controllers
diff --git a/drivers/clk/meson/meson-a1-clkc.c b/drivers/clk/meson/meson-a1-clkc.c
new file mode 100644
index 000000000000..2fe320a0e16e
--- /dev/null
+++ b/drivers/clk/meson/meson-a1-clkc.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Amlogic Meson-A1 Clock Controller Driver
+ *
+ * Copyright (c) 2022, SberDevices. All Rights Reserved.
+ * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
+ */
+
+#include <linux/of_device.h>
+#include "meson-a1-clkc.h"
+
+static struct regmap_config clkc_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
+int meson_a1_clkc_probe(struct platform_device *pdev)
+{
+ struct meson_a1_clkc_data *clkc;
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ void __iomem *base;
+ struct regmap *map;
+ int clkid, i, err;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return dev_err_probe(dev, -ENXIO, "can't get IO resource\n");
+
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return dev_err_probe(dev, PTR_ERR(base),
+ "can't ioremap resource %pr\n", res);
+
+ map = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
+ if (IS_ERR(map))
+ return dev_err_probe(dev, PTR_ERR(map),
+ "can't init regmap mmio region\n");
+
+ clkc = (struct meson_a1_clkc_data *)of_device_get_match_data(dev);
+ if (!clkc)
+ return dev_err_probe(dev, -ENODEV,
+ "can't get A1 clkc driver data\n");
+
+ /* Populate regmap for the regmap backed clocks */
+ for (i = 0; i < clkc->num_regs; i++)
+ clkc->regs[i]->map = map;
+
+ for (clkid = 0; clkid < clkc->hw->num; clkid++) {
+ err = devm_clk_hw_register(dev, clkc->hw->hws[clkid]);
+ if (err)
+ return dev_err_probe(dev, err,
+ "clock registration failed\n");
+ }
+
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+ (void *)clkc->hw);
+}
+EXPORT_SYMBOL_GPL(meson_a1_clkc_probe);
+
+MODULE_AUTHOR("Dmitry Rokosov <ddrokosov@sberdevices.ru>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/meson/meson-a1-clkc.h b/drivers/clk/meson/meson-a1-clkc.h
new file mode 100644
index 000000000000..503eca0f6cb5
--- /dev/null
+++ b/drivers/clk/meson/meson-a1-clkc.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Amlogic Meson-A1 Clock Controller driver
+ *
+ * Copyright (c) 2022, SberDevices. All Rights Reserved.
+ * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
+ */
+
+#ifndef __MESON_A1_CLKC_H__
+#define __MESON_A1_CLKC_H__
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "clk-regmap.h"
+
+struct meson_a1_clkc_data {
+ const struct clk_hw_onecell_data *hw;
+ struct clk_regmap *const *regs;
+ size_t num_regs;
+};
+
+int meson_a1_clkc_probe(struct platform_device *pdev);
+#endif
--
2.36.0
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v8 07/11] clk: meson: a1: redesign Amlogic A1 PLL clock controller
2022-12-01 22:56 [PATCH v8 00/11] add Amlogic A1 clock controller drivers Dmitry Rokosov
` (5 preceding siblings ...)
2022-12-01 22:56 ` [PATCH v8 06/11] clk: meson: introduce a1-clkc common driver for all A1 clock controllers Dmitry Rokosov
@ 2022-12-01 22:56 ` Dmitry Rokosov
2022-12-02 11:42 ` Jerome Brunet
2022-12-01 22:57 ` [PATCH v8 08/11] dt-bindings: clock: meson: fixup A1 PLL clkc dtb_check errors Dmitry Rokosov
` (3 subsequent siblings)
10 siblings, 1 reply; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-01 22:56 UTC (permalink / raw)
To: neil.armstrong, jbrunet, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Dmitry Rokosov
Summary changes:
- supported meson-a1-clkc common driver
- inherited from the base clk-pll driver, implemented own version of
init/enable/disable/enabled routines; rate calculating logic is
fully the same
- aligned CLKID-related definitions with CLKID list from order
perspective to remove holes and permutations
- corrected Kconfig dependencies and types
- provided correct MODULE_AUTHORs() and MODULE_LICENSE()
- optimized and fix up some clock relationships
- removed unused register offset definitions (ANACTRL_* group)
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
---
drivers/clk/meson/Kconfig | 5 +-
drivers/clk/meson/a1-pll.c | 267 +++++++++++++++++++++++++------------
drivers/clk/meson/a1-pll.h | 37 ++---
3 files changed, 202 insertions(+), 107 deletions(-)
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 1c885541c3a9..deb273673ec1 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -104,10 +104,11 @@ config COMMON_CLK_AXG_AUDIO
aka axg, Say Y if you want audio subsystem to work.
config COMMON_CLK_A1_PLL
- bool
- depends on ARCH_MESON
+ tristate "Meson A1 SoC PLL controller support"
+ depends on ARM64
select COMMON_CLK_MESON_REGMAP
select COMMON_CLK_MESON_PLL
+ select COMMON_CLK_MESON_A1_CLKC
help
Support for the PLL clock controller on Amlogic A113L device,
aka a1. Say Y if you want PLL to work.
diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c
index 69c1ca07d041..23487ca797b3 100644
--- a/drivers/clk/meson/a1-pll.c
+++ b/drivers/clk/meson/a1-pll.c
@@ -2,15 +2,133 @@
/*
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
* Author: Jian Hu <jian.hu@amlogic.com>
+ *
+ * Copyright (c) 2022, SberDevices. All Rights Reserved.
+ * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
*/
#include <linux/clk-provider.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
+#include "meson-a1-clkc.h"
#include "a1-pll.h"
-#include "clk-pll.h"
#include "clk-regmap.h"
+static inline
+struct meson_a1_pll_data *meson_a1_pll_data(struct clk_regmap *clk)
+{
+ return (struct meson_a1_pll_data *)clk->data;
+}
+
+static int meson_a1_pll_init(struct clk_hw *hw)
+{
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_a1_pll_data *pll = meson_a1_pll_data(clk);
+
+ regmap_multi_reg_write(clk->map, pll->base.init_regs,
+ pll->base.init_count);
+
+ return 0;
+}
+
+static int meson_a1_pll_is_enabled(struct clk_hw *hw)
+{
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_a1_pll_data *pll = meson_a1_pll_data(clk);
+
+ if (MESON_PARM_APPLICABLE(&pll->base.rst) &&
+ meson_parm_read(clk->map, &pll->base.rst))
+ return 0;
+
+ if (!meson_parm_read(clk->map, &pll->base.en) ||
+ !meson_parm_read(clk->map, &pll->base.l))
+ return 0;
+
+ return 1;
+}
+
+static int meson_a1_pll_enable(struct clk_hw *hw)
+{
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_a1_pll_data *pll = meson_a1_pll_data(clk);
+
+ /* Do nothing if the PLL is already enabled */
+ if (clk_hw_is_enabled(hw))
+ return 0;
+
+ /* Enable the pll */
+ meson_parm_write(clk->map, &pll->base.en, 1);
+
+ /*
+ * Compared with the previous SoCs, self-adaption current module
+ * is newly added for A1, keep the new power-on sequence to enable the
+ * PLL. The sequence is:
+ * 1. enable the pll, delay for 10us
+ * 2. enable the pll self-adaption current module, delay for 40us
+ * 3. enable the lock detect module
+ */
+ usleep_range(10, 20);
+ meson_parm_write(clk->map, &pll->current_en, 1);
+ usleep_range(40, 50);
+
+ meson_parm_write(clk->map, &pll->l_detect, 1);
+ meson_parm_write(clk->map, &pll->l_detect, 0);
+
+ if (meson_clk_pll_wait_lock(hw))
+ return -EIO;
+
+ return 0;
+}
+
+static void meson_a1_pll_disable(struct clk_hw *hw)
+{
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_a1_pll_data *pll = meson_a1_pll_data(clk);
+
+ /* Disable the pll */
+ meson_parm_write(clk->map, &pll->base.en, 0);
+
+ /* Disable PLL internal self-adaption current module */
+ meson_parm_write(clk->map, &pll->current_en, 0);
+}
+
+/*
+ * A1 PLL clock controller driver is based on meson clk_pll driver,
+ * so some rate calculating routines are reused
+ */
+static unsigned long meson_a1_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return meson_clk_pll_ops.recalc_rate(hw, parent_rate);
+}
+
+static int meson_a1_pll_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ return meson_clk_pll_ops.determine_rate(hw, req);
+}
+
+static int meson_a1_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ return meson_clk_pll_ops.set_rate(hw, rate, parent_rate);
+}
+
+static const struct clk_ops meson_a1_pll_ops = {
+ .init = meson_a1_pll_init,
+ .recalc_rate = meson_a1_pll_recalc_rate,
+ .determine_rate = meson_a1_pll_determine_rate,
+ .set_rate = meson_a1_pll_set_rate,
+ .is_enabled = meson_a1_pll_is_enabled,
+ .enable = meson_a1_pll_enable,
+ .disable = meson_a1_pll_disable
+};
+
+static const struct clk_ops meson_a1_pll_ro_ops = {
+ .recalc_rate = meson_a1_pll_recalc_rate,
+ .is_enabled = meson_a1_pll_is_enabled,
+};
+
static struct clk_regmap a1_fixed_pll_dco = {
.data = &(struct meson_clk_pll_data){
.en = {
@@ -46,7 +164,7 @@ static struct clk_regmap a1_fixed_pll_dco = {
},
.hw.init = &(struct clk_init_data){
.name = "fixed_pll_dco",
- .ops = &meson_clk_pll_ro_ops,
+ .ops = &meson_a1_pll_ro_ops,
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal_fixpll",
},
@@ -87,31 +205,36 @@ static const struct reg_sequence a1_hifi_init_regs[] = {
};
static struct clk_regmap a1_hifi_pll = {
- .data = &(struct meson_clk_pll_data){
- .en = {
- .reg_off = ANACTRL_HIFIPLL_CTRL0,
- .shift = 28,
- .width = 1,
- },
- .m = {
- .reg_off = ANACTRL_HIFIPLL_CTRL0,
- .shift = 0,
- .width = 8,
- },
- .n = {
- .reg_off = ANACTRL_HIFIPLL_CTRL0,
- .shift = 10,
- .width = 5,
- },
- .frac = {
- .reg_off = ANACTRL_HIFIPLL_CTRL1,
- .shift = 0,
- .width = 19,
- },
- .l = {
- .reg_off = ANACTRL_HIFIPLL_STS,
- .shift = 31,
- .width = 1,
+ .data = &(struct meson_a1_pll_data){
+ .base = {
+ .en = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .frac = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL1,
+ .shift = 0,
+ .width = 19,
+ },
+ .l = {
+ .reg_off = ANACTRL_HIFIPLL_STS,
+ .shift = 31,
+ .width = 1,
+ },
+ .range = &a1_hifi_pll_mult_range,
+ .init_regs = a1_hifi_init_regs,
+ .init_count = ARRAY_SIZE(a1_hifi_init_regs),
},
.current_en = {
.reg_off = ANACTRL_HIFIPLL_CTRL0,
@@ -123,13 +246,10 @@ static struct clk_regmap a1_hifi_pll = {
.shift = 6,
.width = 1,
},
- .range = &a1_hifi_pll_mult_range,
- .init_regs = a1_hifi_init_regs,
- .init_count = ARRAY_SIZE(a1_hifi_init_regs),
},
.hw.init = &(struct clk_init_data){
.name = "hifi_pll",
- .ops = &meson_clk_pll_ops,
+ .ops = &meson_a1_pll_ops,
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal_hifipll",
},
@@ -276,15 +396,15 @@ static struct clk_hw_onecell_data a1_pll_hw_onecell_data = {
.hws = {
[CLKID_FIXED_PLL_DCO] = &a1_fixed_pll_dco.hw,
[CLKID_FIXED_PLL] = &a1_fixed_pll.hw,
- [CLKID_HIFI_PLL] = &a1_hifi_pll.hw,
- [CLKID_FCLK_DIV2] = &a1_fclk_div2.hw,
- [CLKID_FCLK_DIV3] = &a1_fclk_div3.hw,
- [CLKID_FCLK_DIV5] = &a1_fclk_div5.hw,
- [CLKID_FCLK_DIV7] = &a1_fclk_div7.hw,
[CLKID_FCLK_DIV2_DIV] = &a1_fclk_div2_div.hw,
[CLKID_FCLK_DIV3_DIV] = &a1_fclk_div3_div.hw,
[CLKID_FCLK_DIV5_DIV] = &a1_fclk_div5_div.hw,
[CLKID_FCLK_DIV7_DIV] = &a1_fclk_div7_div.hw,
+ [CLKID_FCLK_DIV2] = &a1_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &a1_fclk_div3.hw,
+ [CLKID_FCLK_DIV5] = &a1_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &a1_fclk_div7.hw,
+ [CLKID_HIFI_PLL] = &a1_hifi_pll.hw,
[NR_PLL_CLKS] = NULL,
},
.num = NR_PLL_CLKS,
@@ -293,68 +413,39 @@ static struct clk_hw_onecell_data a1_pll_hw_onecell_data = {
static struct clk_regmap *const a1_pll_regmaps[] = {
&a1_fixed_pll_dco,
&a1_fixed_pll,
- &a1_hifi_pll,
&a1_fclk_div2,
&a1_fclk_div3,
&a1_fclk_div5,
&a1_fclk_div7,
+ &a1_hifi_pll,
};
-static struct regmap_config clkc_regmap_config = {
- .reg_bits = 32,
- .val_bits = 32,
- .reg_stride = 4,
+static const struct meson_a1_clkc_data a1_pll_clkc __maybe_unused = {
+ .hw = &a1_pll_hw_onecell_data,
+ .regs = a1_pll_regmaps,
+ .num_regs = ARRAY_SIZE(a1_pll_regmaps),
};
-static int meson_a1_pll_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct resource *res;
- void __iomem *base;
- struct regmap *map;
- int ret, i;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-
- base = devm_ioremap_resource(dev, res);
- if (IS_ERR(base))
- return PTR_ERR(base);
-
- map = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
- if (IS_ERR(map))
- return PTR_ERR(map);
-
- /* Populate regmap for the regmap backed clocks */
- for (i = 0; i < ARRAY_SIZE(a1_pll_regmaps); i++)
- a1_pll_regmaps[i]->map = map;
-
- for (i = 0; i < a1_pll_hw_onecell_data.num; i++) {
- /* array might be sparse */
- if (!a1_pll_hw_onecell_data.hws[i])
- continue;
-
- ret = devm_clk_hw_register(dev, a1_pll_hw_onecell_data.hws[i]);
- if (ret) {
- dev_err(dev, "Clock registration failed\n");
- return ret;
- }
- }
-
- return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
- &a1_pll_hw_onecell_data);
-}
-
-static const struct of_device_id clkc_match_table[] = {
- { .compatible = "amlogic,a1-pll-clkc", },
- {}
+#ifdef CONFIG_OF
+static const struct of_device_id a1_pll_clkc_match_table[] = {
+ {
+ .compatible = "amlogic,a1-pll-clkc",
+ .data = &a1_pll_clkc,
+ },
+ {},
};
+MODULE_DEVICE_TABLE(of, a1_pll_clkc_match_table);
+#endif /* CONFIG_OF */
-static struct platform_driver a1_pll_driver = {
- .probe = meson_a1_pll_probe,
- .driver = {
- .name = "a1-pll-clkc",
- .of_match_table = clkc_match_table,
+static struct platform_driver a1_pll_clkc_driver = {
+ .probe = meson_a1_clkc_probe,
+ .driver = {
+ .name = "a1-pll-clkc",
+ .of_match_table = of_match_ptr(a1_pll_clkc_match_table),
},
};
-builtin_platform_driver(a1_pll_driver);
+module_platform_driver(a1_pll_clkc_driver);
+MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>");
+MODULE_AUTHOR("Dmitry Rokosov <ddrokosov@sberdevices.ru>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/meson/a1-pll.h b/drivers/clk/meson/a1-pll.h
index 8ded267061ad..2ff5a2042a97 100644
--- a/drivers/clk/meson/a1-pll.h
+++ b/drivers/clk/meson/a1-pll.h
@@ -1,38 +1,29 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
+ * Amlogic Meson-A1 PLL Clock Controller internals
+ *
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ * Author: Jian Hu <jian.hu@amlogic.com>
+ *
+ * Copyright (c) 2022, SberDevices. All Rights Reserved.
+ * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
*/
#ifndef __A1_PLL_H
#define __A1_PLL_H
+#include "clk-pll.h"
+
/* PLL register offset */
#define ANACTRL_FIXPLL_CTRL0 0x0
#define ANACTRL_FIXPLL_CTRL1 0x4
-#define ANACTRL_FIXPLL_CTRL2 0x8
-#define ANACTRL_FIXPLL_CTRL3 0xc
-#define ANACTRL_FIXPLL_CTRL4 0x10
#define ANACTRL_FIXPLL_STS 0x14
-#define ANACTRL_SYSPLL_CTRL0 0x80
-#define ANACTRL_SYSPLL_CTRL1 0x84
-#define ANACTRL_SYSPLL_CTRL2 0x88
-#define ANACTRL_SYSPLL_CTRL3 0x8c
-#define ANACTRL_SYSPLL_CTRL4 0x90
-#define ANACTRL_SYSPLL_STS 0x94
#define ANACTRL_HIFIPLL_CTRL0 0xc0
#define ANACTRL_HIFIPLL_CTRL1 0xc4
#define ANACTRL_HIFIPLL_CTRL2 0xc8
#define ANACTRL_HIFIPLL_CTRL3 0xcc
#define ANACTRL_HIFIPLL_CTRL4 0xd0
#define ANACTRL_HIFIPLL_STS 0xd4
-#define ANACTRL_AUDDDS_CTRL0 0x100
-#define ANACTRL_AUDDDS_CTRL1 0x104
-#define ANACTRL_AUDDDS_CTRL2 0x108
-#define ANACTRL_AUDDDS_CTRL3 0x10c
-#define ANACTRL_AUDDDS_CTRL4 0x110
-#define ANACTRL_AUDDDS_STS 0x114
-#define ANACTRL_MISCTOP_CTRL0 0x140
-#define ANACTRL_POR_CNTL 0x188
/*
* CLKID index values
@@ -53,4 +44,16 @@
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/a1-pll-clkc.h>
+/**
+ * struct meson_a1_pll_data - A1 PLL state
+ * @base: Basic CLK PLL state
+ * @current_en: Enable or disable the PLL self-adaption current module
+ * @l_detect: Enable or disable the lock detect module
+ */
+struct meson_a1_pll_data {
+ struct meson_clk_pll_data base;
+ struct parm current_en;
+ struct parm l_detect;
+};
+
#endif /* __A1_PLL_H */
--
2.36.0
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v8 08/11] dt-bindings: clock: meson: fixup A1 PLL clkc dtb_check errors
2022-12-01 22:56 [PATCH v8 00/11] add Amlogic A1 clock controller drivers Dmitry Rokosov
` (6 preceding siblings ...)
2022-12-01 22:56 ` [PATCH v8 07/11] clk: meson: a1: redesign Amlogic A1 PLL clock controller Dmitry Rokosov
@ 2022-12-01 22:57 ` Dmitry Rokosov
2022-12-02 10:40 ` Krzysztof Kozlowski
2022-12-01 22:57 ` [PATCH v8 09/11] clk: meson: redesign A1 Peripherals CLK controller Dmitry Rokosov
` (2 subsequent siblings)
10 siblings, 1 reply; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-01 22:57 UTC (permalink / raw)
To: neil.armstrong, jbrunet, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Dmitry Rokosov
During running dtbs_check and dt_binding_check checkers the following
problems were found and resolved:
- $id is not correct, it has wrong url path
- CLKIDs aren't applied by names, just magic int constants there
- address and size cells are required for long reg definition
- wrong indentations
Also this patch adds new A1 clk controllers dt bindings to MAINTAINERS.
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
---
.../bindings/clock/amlogic,a1-pll-clkc.yaml | 27 ++++++++++++-------
MAINTAINERS | 1 +
2 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
index d67250fbeece..83f98a73c04e 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/amlogic,a1-pll-clkc.yaml#"
+$id: "http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Amlogic Meson A/C serials PLL Clock Control Unit Device Tree Bindings
@@ -10,6 +10,7 @@ maintainers:
- Neil Armstrong <narmstrong@baylibre.com>
- Jerome Brunet <jbrunet@baylibre.com>
- Jian Hu <jian.hu@jian.hu.com>
+ - Dmitry Rokosov <ddrokosov@sberdevices.ru>
properties:
compatible:
@@ -23,8 +24,8 @@ properties:
clocks:
items:
- - description: input xtal_fixpll
- - description: input xtal_hifipll
+ - description: input xtal_fixpll
+ - description: input xtal_hifipll
clock-names:
items:
@@ -42,11 +43,17 @@ additionalProperties: false
examples:
- |
- clkc_pll: pll-clock-controller@7c80 {
- compatible = "amlogic,a1-pll-clkc";
- reg = <0 0x7c80 0 0x18c>;
- #clock-cells = <1>;
- clocks = <&clkc_periphs 1>,
- <&clkc_periphs 4>;
- clock-names = "xtal_fixpll", "xtal_hifipll";
+ #include <dt-bindings/clock/a1-clkc.h>
+ apb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clkc_pll: pll-clock-controller@7c80 {
+ compatible = "amlogic,a1-pll-clkc";
+ reg = <0 0x7c80 0 0x18c>;
+ #clock-cells = <1>;
+ clocks = <&clkc_periphs CLKID_XTAL_FIXPLL>,
+ <&clkc_periphs CLKID_XTAL_HIFIPLL>;
+ clock-names = "xtal_fixpll", "xtal_hifipll";
+ };
};
diff --git a/MAINTAINERS b/MAINTAINERS
index e04d944005ba..a02d81edeb4b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1837,6 +1837,7 @@ L: linux-amlogic@lists.infradead.org
S: Maintained
F: Documentation/devicetree/bindings/clock/amlogic*
F: drivers/clk/meson/
+F: include/dt-bindings/clock/a1*
F: include/dt-bindings/clock/gxbb*
F: include/dt-bindings/clock/meson*
--
2.36.0
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v8 09/11] clk: meson: redesign A1 Peripherals CLK controller
2022-12-01 22:56 [PATCH v8 00/11] add Amlogic A1 clock controller drivers Dmitry Rokosov
` (7 preceding siblings ...)
2022-12-01 22:57 ` [PATCH v8 08/11] dt-bindings: clock: meson: fixup A1 PLL clkc dtb_check errors Dmitry Rokosov
@ 2022-12-01 22:57 ` Dmitry Rokosov
2022-12-02 12:01 ` Jerome Brunet
2022-12-01 22:57 ` [PATCH v8 10/11] dt-bindings: clock: meson: fixup A1 peripherals clkc dtb_check errors Dmitry Rokosov
2022-12-01 22:57 ` [PATCH v8 11/11] arm64: dts: meson: a1: introduce PLL and Peripherals clk controllers Dmitry Rokosov
10 siblings, 1 reply; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-01 22:57 UTC (permalink / raw)
To: neil.armstrong, jbrunet, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Dmitry Rokosov
Summary changes:
- fixed up clk_summary kernel panic due to missing a1_pad_ctrl
clk_regmap definition
- supported meson-a1-clkc common driver
- aligned CLKID-related definitions with CLKID list from order
perspective to remove holes and permutations
- corrected Kconfig dependencies and types
- provided correct MODULE_AUTHORs() and MODULE_LICENSE()
- optimized and fix up some clock relationships and parents
references
- removed unused register offset definitions
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
---
drivers/clk/meson/Kconfig | 7 +-
drivers/clk/meson/a1.c | 591 ++++++++++++++++++--------------------
drivers/clk/meson/a1.h | 16 +-
3 files changed, 292 insertions(+), 322 deletions(-)
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index deb273673ec1..cabe63bf23f5 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -114,13 +114,14 @@ config COMMON_CLK_A1_PLL
aka a1. Say Y if you want PLL to work.
config COMMON_CLK_A1
- bool
- depends on ARCH_MESON
+ tristate "Meson A1 SoC clock controller support"
+ depends on ARM64
select COMMON_CLK_MESON_DUALDIV
select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_MESON_A1_CLKC
help
Support for the Peripheral clock controller on Amlogic A113L device,
- aka a1. Say Y if you want Peripherals to work.
+ aka a1. Say Y if you want clock peripherals controller to work.
config COMMON_CLK_G12A
tristate "G12 and SM1 SoC clock controllers support"
diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c
index 2cf20ae1db75..c9b7f09823f8 100644
--- a/drivers/clk/meson/a1.c
+++ b/drivers/clk/meson/a1.c
@@ -2,6 +2,9 @@
/*
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
* Author: Jian Hu <jian.hu@amlogic.com>
+ *
+ * Copyright (c) 2022, SberDevices. All Rights Reserved.
+ * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
*/
#include <linux/clk-provider.h>
@@ -10,6 +13,7 @@
#include "a1.h"
#include "clk-dualdiv.h"
#include "clk-regmap.h"
+#include "meson-a1-clkc.h"
static struct clk_regmap a1_xtal_clktree = {
.data = &(struct clk_regmap_gate_data){
@@ -116,11 +120,128 @@ static struct clk_regmap a1_xtal_dds = {
},
};
+static struct clk_regmap a1_rtc_32k_clkin = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = RTC_BY_OSCIN_CTRL0,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_32k_clkin",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct meson_clk_dualdiv_param a1_32k_div_table[] = {
+ {
+ .dual = 1,
+ .n1 = 733,
+ .m1 = 8,
+ .n2 = 732,
+ .m2 = 11,
+ },
+ {}
+};
+
+static struct clk_regmap a1_rtc_32k_div = {
+ .data = &(struct meson_clk_dualdiv_data){
+ .n1 = {
+ .reg_off = RTC_BY_OSCIN_CTRL0,
+ .shift = 0,
+ .width = 12,
+ },
+ .n2 = {
+ .reg_off = RTC_BY_OSCIN_CTRL0,
+ .shift = 12,
+ .width = 12,
+ },
+ .m1 = {
+ .reg_off = RTC_BY_OSCIN_CTRL1,
+ .shift = 0,
+ .width = 12,
+ },
+ .m2 = {
+ .reg_off = RTC_BY_OSCIN_CTRL1,
+ .shift = 12,
+ .width = 12,
+ },
+ .dual = {
+ .reg_off = RTC_BY_OSCIN_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .table = a1_32k_div_table,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "rtc_32k_div",
+ .ops = &meson_clk_dualdiv_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_rtc_32k_clkin.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_rtc_32k_xtal = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = RTC_BY_OSCIN_CTRL1,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_32k_xtal",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_rtc_32k_clkin.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a1_rtc_32k_sel = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = RTC_CTRL,
+ .mask = 0x3,
+ .shift = 0,
+ .flags = CLK_MUX_ROUND_CLOSEST,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "rtc_32k_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_rtc_32k_xtal.hw,
+ &a1_rtc_32k_div.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+struct clk_regmap a1_rtc_clk = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = RTC_BY_OSCIN_CTRL0,
+ .bit_idx = 30,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "rtc_clk",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_rtc_32k_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static u32 mux_table_sys_clk[] = { 0, 1, 2, 3, 7 };
static const struct clk_parent_data sys_clk_parents[] = {
{ .fw_name = "xtal" },
{ .fw_name = "fclk_div2" },
{ .fw_name = "fclk_div3" },
{ .fw_name = "fclk_div5" },
+ { .hw = &a1_rtc_clk.hw },
};
static struct clk_regmap a1_sys_b_sel = {
@@ -128,6 +249,7 @@ static struct clk_regmap a1_sys_b_sel = {
.offset = SYS_CLK_CTRL0,
.mask = 0x7,
.shift = 26,
+ .table = mux_table_sys_clk,
},
.hw.init = &(struct clk_init_data){
.name = "sys_b_sel",
@@ -175,6 +297,7 @@ static struct clk_regmap a1_sys_a_sel = {
.offset = SYS_CLK_CTRL0,
.mask = 0x7,
.shift = 10,
+ .table = mux_table_sys_clk,
},
.hw.init = &(struct clk_init_data){
.name = "sys_a_sel",
@@ -227,7 +350,8 @@ static struct clk_regmap a1_sys_clk = {
.name = "sys_clk",
.ops = &clk_regmap_mux_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
- &a1_sys_a.hw, &a1_sys_b.hw,
+ &a1_sys_a.hw,
+ &a1_sys_b.hw,
},
.num_parents = 2,
/*
@@ -243,121 +367,6 @@ static struct clk_regmap a1_sys_clk = {
},
};
-static struct clk_regmap a1_rtc_32k_clkin = {
- .data = &(struct clk_regmap_gate_data){
- .offset = RTC_BY_OSCIN_CTRL0,
- .bit_idx = 31,
- },
- .hw.init = &(struct clk_init_data) {
- .name = "rtc_32k_clkin",
- .ops = &clk_regmap_gate_ops,
- .parent_data = &(const struct clk_parent_data) {
- .fw_name = "xtal",
- },
- .num_parents = 1,
- },
-};
-
-static const struct meson_clk_dualdiv_param a1_32k_div_table[] = {
- {
- .dual = 1,
- .n1 = 733,
- .m1 = 8,
- .n2 = 732,
- .m2 = 11,
- },
- {}
-};
-
-static struct clk_regmap a1_rtc_32k_div = {
- .data = &(struct meson_clk_dualdiv_data){
- .n1 = {
- .reg_off = RTC_BY_OSCIN_CTRL0,
- .shift = 0,
- .width = 12,
- },
- .n2 = {
- .reg_off = RTC_BY_OSCIN_CTRL0,
- .shift = 12,
- .width = 12,
- },
- .m1 = {
- .reg_off = RTC_BY_OSCIN_CTRL1,
- .shift = 0,
- .width = 12,
- },
- .m2 = {
- .reg_off = RTC_BY_OSCIN_CTRL1,
- .shift = 12,
- .width = 12,
- },
- .dual = {
- .reg_off = RTC_BY_OSCIN_CTRL0,
- .shift = 28,
- .width = 1,
- },
- .table = a1_32k_div_table,
- },
- .hw.init = &(struct clk_init_data){
- .name = "rtc_32k_div",
- .ops = &meson_clk_dualdiv_ops,
- .parent_hws = (const struct clk_hw *[]) {
- &a1_rtc_32k_clkin.hw
- },
- .num_parents = 1,
- },
-};
-
-static struct clk_regmap a1_rtc_32k_xtal = {
- .data = &(struct clk_regmap_gate_data){
- .offset = RTC_BY_OSCIN_CTRL1,
- .bit_idx = 24,
- },
- .hw.init = &(struct clk_init_data) {
- .name = "rtc_32k_xtal",
- .ops = &clk_regmap_gate_ops,
- .parent_hws = (const struct clk_hw *[]) {
- &a1_rtc_32k_clkin.hw
- },
- .num_parents = 1,
- },
-};
-
-static struct clk_regmap a1_rtc_32k_sel = {
- .data = &(struct clk_regmap_mux_data) {
- .offset = RTC_CTRL,
- .mask = 0x3,
- .shift = 0,
- .flags = CLK_MUX_ROUND_CLOSEST,
- },
- .hw.init = &(struct clk_init_data){
- .name = "rtc_32k_sel",
- .ops = &clk_regmap_mux_ops,
- .parent_hws = (const struct clk_hw *[]) {
- &a1_rtc_32k_xtal.hw,
- &a1_rtc_32k_div.hw,
- },
- .num_parents = 2,
- .flags = CLK_SET_RATE_PARENT,
- },
-};
-
-struct clk_regmap a1_rtc_clk = {
- .data = &(struct clk_regmap_gate_data){
- .offset = RTC_BY_OSCIN_CTRL0,
- .bit_idx = 30,
- },
- .hw.init = &(struct clk_init_data){
- .name = "rtc_clk",
- .ops = &clk_regmap_gate_ops,
- .parent_hws = (const struct clk_hw *[]) {
- &a1_rtc_32k_sel.hw
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- },
-};
-
static u32 mux_table_dsp_ab[] = { 0, 1, 2, 3, 4, 7 };
static const struct clk_parent_data dsp_ab_clk_parent_data[] = {
{ .fw_name = "xtal", },
@@ -475,9 +484,9 @@ static struct clk_regmap a1_dspa_sel = {
.hw.init = &(struct clk_init_data){
.name = "dspa_sel",
.ops = &clk_regmap_mux_ops,
- .parent_data = (const struct clk_parent_data []) {
- { .hw = &a1_dspa_a.hw },
- { .hw = &a1_dspa_b.hw },
+ .parent_hws = (const struct clk_hw *[]) {
+ &a1_dspa_a.hw,
+ &a1_dspa_b.hw,
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
@@ -624,7 +633,8 @@ static struct clk_regmap a1_dspb_sel = {
.name = "dspb_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
- &a1_dspb_a.hw, &a1_dspb_b.hw,
+ &a1_dspb_a.hw,
+ &a1_dspb_b.hw,
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
@@ -852,6 +862,12 @@ static struct clk_regmap a1_saradc_clk = {
},
};
+static const struct clk_parent_data pwm_abcd_parents[] = {
+ { .fw_name = "xtal", },
+ { .hw = &a1_sys_clk.hw },
+ { .hw = &a1_rtc_clk.hw },
+};
+
static struct clk_regmap a1_pwm_a_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = PWM_CLK_AB_CTRL,
@@ -861,11 +877,8 @@ static struct clk_regmap a1_pwm_a_sel = {
.hw.init = &(struct clk_init_data){
.name = "pwm_a_sel",
.ops = &clk_regmap_mux_ops,
- .parent_data = (const struct clk_parent_data []) {
- { .fw_name = "xtal", },
- { .hw = &a1_sys_clk.hw, },
- },
- .num_parents = 2,
+ .parent_data = pwm_abcd_parents,
+ .num_parents = ARRAY_SIZE(pwm_abcd_parents),
},
};
@@ -918,11 +931,8 @@ static struct clk_regmap a1_pwm_b_sel = {
.hw.init = &(struct clk_init_data){
.name = "pwm_b_sel",
.ops = &clk_regmap_mux_ops,
- .parent_data = (const struct clk_parent_data []) {
- { .fw_name = "xtal", },
- { .hw = &a1_sys_clk.hw, },
- },
- .num_parents = 2,
+ .parent_data = pwm_abcd_parents,
+ .num_parents = ARRAY_SIZE(pwm_abcd_parents),
},
};
@@ -968,11 +978,8 @@ static struct clk_regmap a1_pwm_c_sel = {
.hw.init = &(struct clk_init_data){
.name = "pwm_c_sel",
.ops = &clk_regmap_mux_ops,
- .parent_data = (const struct clk_parent_data []) {
- { .fw_name = "xtal", },
- { .hw = &a1_sys_clk.hw, },
- },
- .num_parents = 2,
+ .parent_data = pwm_abcd_parents,
+ .num_parents = ARRAY_SIZE(pwm_abcd_parents),
},
};
@@ -1018,11 +1025,8 @@ static struct clk_regmap a1_pwm_d_sel = {
.hw.init = &(struct clk_init_data){
.name = "pwm_d_sel",
.ops = &clk_regmap_mux_ops,
- .parent_data = (const struct clk_parent_data []) {
- { .fw_name = "xtal", },
- { .hw = &a1_sys_clk.hw, },
- },
- .num_parents = 2,
+ .parent_data = pwm_abcd_parents,
+ .num_parents = ARRAY_SIZE(pwm_abcd_parents),
},
};
@@ -1059,7 +1063,7 @@ static struct clk_regmap a1_pwm_d = {
},
};
-static const struct clk_parent_data pwm_ef_parent_data[] = {
+static const struct clk_parent_data pwm_ef_parents[] = {
{ .fw_name = "xtal", },
{ .hw = &a1_sys_clk.hw },
{ .fw_name = "fclk_div5", },
@@ -1075,8 +1079,8 @@ static struct clk_regmap a1_pwm_e_sel = {
.hw.init = &(struct clk_init_data){
.name = "pwm_e_sel",
.ops = &clk_regmap_mux_ops,
- .parent_data = pwm_ef_parent_data,
- .num_parents = ARRAY_SIZE(pwm_ef_parent_data),
+ .parent_data = pwm_ef_parents,
+ .num_parents = ARRAY_SIZE(pwm_ef_parents),
},
};
@@ -1122,8 +1126,8 @@ static struct clk_regmap a1_pwm_f_sel = {
.hw.init = &(struct clk_init_data){
.name = "pwm_f_sel",
.ops = &clk_regmap_mux_ops,
- .parent_data = pwm_ef_parent_data,
- .num_parents = ARRAY_SIZE(pwm_ef_parent_data),
+ .parent_data = pwm_ef_parents,
+ .num_parents = ARRAY_SIZE(pwm_ef_parents),
},
};
@@ -1169,7 +1173,7 @@ static struct clk_regmap a1_pwm_f = {
* --------------------|/
* 24M
*/
-static const struct clk_parent_data spicc_parents[] = {
+static const struct clk_parent_data spicc_spifc_parents[] = {
{ .fw_name = "fclk_div2"},
{ .fw_name = "fclk_div3"},
{ .fw_name = "fclk_div5"},
@@ -1185,8 +1189,8 @@ static struct clk_regmap a1_spicc_sel = {
.hw.init = &(struct clk_init_data){
.name = "spicc_sel",
.ops = &clk_regmap_mux_ops,
- .parent_data = spicc_parents,
- .num_parents = 4,
+ .parent_data = spicc_spifc_parents,
+ .num_parents = ARRAY_SIZE(spicc_spifc_parents),
},
};
@@ -1282,9 +1286,8 @@ static struct clk_regmap a1_spifc_sel = {
.hw.init = &(struct clk_init_data){
.name = "spifc_sel",
.ops = &clk_regmap_mux_ops,
- /* the same parent with spicc */
- .parent_data = spicc_parents,
- .num_parents = 4,
+ .parent_data = spicc_spifc_parents,
+ .num_parents = ARRAY_SIZE(spicc_spifc_parents),
},
};
@@ -1339,7 +1342,7 @@ static struct clk_regmap a1_spifc = {
},
};
-static const struct clk_parent_data usb_bus_parent_data[] = {
+static const struct clk_parent_data usb_bus_parents[] = {
{ .fw_name = "xtal", },
{ .hw = &a1_sys_clk.hw },
{ .fw_name = "fclk_div3", },
@@ -1355,8 +1358,8 @@ static struct clk_regmap a1_usb_bus_sel = {
.hw.init = &(struct clk_init_data){
.name = "usb_bus_sel",
.ops = &clk_regmap_mux_ops,
- .parent_data = usb_bus_parent_data,
- .num_parents = ARRAY_SIZE(usb_bus_parent_data),
+ .parent_data = usb_bus_parents,
+ .num_parents = ARRAY_SIZE(usb_bus_parents),
.flags = CLK_SET_RATE_PARENT,
},
};
@@ -1394,7 +1397,7 @@ static struct clk_regmap a1_usb_bus = {
},
};
-static const struct clk_parent_data sd_emmc_parents[] = {
+static const struct clk_parent_data sd_emmc_psram_dmc_parents[] = {
{ .fw_name = "fclk_div2", },
{ .fw_name = "fclk_div3", },
{ .fw_name = "fclk_div5", },
@@ -1410,8 +1413,8 @@ static struct clk_regmap a1_sd_emmc_sel = {
.hw.init = &(struct clk_init_data){
.name = "sd_emmc_sel",
.ops = &clk_regmap_mux_ops,
- .parent_data = sd_emmc_parents,
- .num_parents = 4,
+ .parent_data = sd_emmc_psram_dmc_parents,
+ .num_parents = ARRAY_SIZE(sd_emmc_psram_dmc_parents),
},
};
@@ -1475,9 +1478,8 @@ static struct clk_regmap a1_psram_sel = {
.hw.init = &(struct clk_init_data){
.name = "psram_sel",
.ops = &clk_regmap_mux_ops,
- /* the same parent with sd_emmc */
- .parent_data = sd_emmc_parents,
- .num_parents = 4,
+ .parent_data = sd_emmc_psram_dmc_parents,
+ .num_parents = ARRAY_SIZE(sd_emmc_psram_dmc_parents),
},
};
@@ -1541,8 +1543,8 @@ static struct clk_regmap a1_dmc_sel = {
.hw.init = &(struct clk_init_data){
.name = "dmc_sel",
.ops = &clk_regmap_mux_ops,
- .parent_data = sd_emmc_parents,
- .num_parents = 4,
+ .parent_data = sd_emmc_psram_dmc_parents,
+ .num_parents = ARRAY_SIZE(sd_emmc_psram_dmc_parents),
},
};
@@ -1873,13 +1875,6 @@ static MESON_GATE(a1_prod_i2c, AXI_CLK_EN, 12);
/* Array of all clocks provided by this provider */
static struct clk_hw_onecell_data a1_periphs_hw_onecell_data = {
.hws = {
- [CLKID_SYS_B_SEL] = &a1_sys_b_sel.hw,
- [CLKID_SYS_B_DIV] = &a1_sys_b_div.hw,
- [CLKID_SYS_B] = &a1_sys_b.hw,
- [CLKID_SYS_A_SEL] = &a1_sys_a_sel.hw,
- [CLKID_SYS_A_DIV] = &a1_sys_a_div.hw,
- [CLKID_SYS_A] = &a1_sys_a.hw,
- [CLKID_SYS_CLK] = &a1_sys_clk.hw,
[CLKID_XTAL_CLKTREE] = &a1_xtal_clktree.hw,
[CLKID_XTAL_FIXPLL] = &a1_xtal_fixpll.hw,
[CLKID_XTAL_USB_PHY] = &a1_xtal_usb_phy.hw,
@@ -1887,6 +1882,7 @@ static struct clk_hw_onecell_data a1_periphs_hw_onecell_data = {
[CLKID_XTAL_HIFIPLL] = &a1_xtal_hifipll.hw,
[CLKID_XTAL_SYSPLL] = &a1_xtal_syspll.hw,
[CLKID_XTAL_DDS] = &a1_xtal_dds.hw,
+ [CLKID_SYS_CLK] = &a1_sys_clk.hw,
[CLKID_CLKTREE] = &a1_clk_tree.hw,
[CLKID_RESET_CTRL] = &a1_reset_ctrl.hw,
[CLKID_ANALOG_CTRL] = &a1_analog_ctrl.hw,
@@ -1940,93 +1936,99 @@ static struct clk_hw_onecell_data a1_periphs_hw_onecell_data = {
[CLKID_CPU_CTRL] = &a1_cpu_ctrl.hw,
[CLKID_ROM] = &a1_rom.hw,
[CLKID_PROC_I2C] = &a1_prod_i2c.hw,
+ [CLKID_DSPA_SEL] = &a1_dspa_sel.hw,
+ [CLKID_DSPB_SEL] = &a1_dspb_sel.hw,
+ [CLKID_DSPA_EN] = &a1_dspa_en.hw,
+ [CLKID_DSPA_EN_NIC] = &a1_dspa_en_nic.hw,
+ [CLKID_DSPB_EN] = &a1_dspb_en.hw,
+ [CLKID_DSPB_EN_NIC] = &a1_dspb_en_nic.hw,
+ [CLKID_RTC_CLK] = &a1_rtc_clk.hw,
+ [CLKID_CECA_32K] = &a1_ceca_32k_clkout.hw,
+ [CLKID_CECB_32K] = &a1_cecb_32k_clkout.hw,
+ [CLKID_24M] = &a1_24m.hw,
+ [CLKID_12M] = &a1_12m.hw,
+ [CLKID_FCLK_DIV2_DIVN] = &a1_fclk_div2_divn.hw,
+ [CLKID_GEN] = &a1_gen.hw,
+ [CLKID_SARADC_SEL] = &a1_saradc_sel.hw,
+ [CLKID_SARADC_CLK] = &a1_saradc_clk.hw,
+ [CLKID_PWM_A] = &a1_pwm_a.hw,
+ [CLKID_PWM_B] = &a1_pwm_b.hw,
+ [CLKID_PWM_C] = &a1_pwm_c.hw,
+ [CLKID_PWM_D] = &a1_pwm_d.hw,
+ [CLKID_PWM_E] = &a1_pwm_e.hw,
+ [CLKID_PWM_F] = &a1_pwm_f.hw,
+ [CLKID_SPICC] = &a1_spicc.hw,
+ [CLKID_TS] = &a1_ts.hw,
+ [CLKID_SPIFC] = &a1_spifc.hw,
+ [CLKID_USB_BUS] = &a1_usb_bus.hw,
+ [CLKID_SD_EMMC] = &a1_sd_emmc.hw,
+ [CLKID_PSRAM] = &a1_psram.hw,
+ [CLKID_DMC] = &a1_dmc.hw,
+ [CLKID_SYS_A_SEL] = &a1_sys_a_sel.hw,
+ [CLKID_SYS_A_DIV] = &a1_sys_a_div.hw,
+ [CLKID_SYS_A] = &a1_sys_a.hw,
+ [CLKID_SYS_B_SEL] = &a1_sys_b_sel.hw,
+ [CLKID_SYS_B_DIV] = &a1_sys_b_div.hw,
+ [CLKID_SYS_B] = &a1_sys_b.hw,
[CLKID_DSPA_A_SEL] = &a1_dspa_a_sel.hw,
[CLKID_DSPA_A_DIV] = &a1_dspa_a_div.hw,
[CLKID_DSPA_A] = &a1_dspa_a.hw,
[CLKID_DSPA_B_SEL] = &a1_dspa_b_sel.hw,
[CLKID_DSPA_B_DIV] = &a1_dspa_b_div.hw,
[CLKID_DSPA_B] = &a1_dspa_b.hw,
- [CLKID_DSPA_SEL] = &a1_dspa_sel.hw,
[CLKID_DSPB_A_SEL] = &a1_dspb_a_sel.hw,
[CLKID_DSPB_A_DIV] = &a1_dspb_a_div.hw,
[CLKID_DSPB_A] = &a1_dspb_a.hw,
[CLKID_DSPB_B_SEL] = &a1_dspb_b_sel.hw,
[CLKID_DSPB_B_DIV] = &a1_dspb_b_div.hw,
[CLKID_DSPB_B] = &a1_dspb_b.hw,
- [CLKID_DSPB_SEL] = &a1_dspb_sel.hw,
- [CLKID_DSPA_EN] = &a1_dspa_en.hw,
- [CLKID_DSPA_EN_NIC] = &a1_dspa_en_nic.hw,
- [CLKID_DSPB_EN] = &a1_dspb_en.hw,
- [CLKID_DSPB_EN_NIC] = &a1_dspb_en_nic.hw,
- [CLKID_24M] = &a1_24m.hw,
- [CLKID_24M_DIV2] = &a1_24m_div2.hw,
- [CLKID_12M] = &a1_12m.hw,
+ [CLKID_RTC_32K_CLKIN] = &a1_rtc_32k_clkin.hw,
+ [CLKID_RTC_32K_DIV] = &a1_rtc_32k_div.hw,
+ [CLKID_RTC_32K_XTAL] = &a1_rtc_32k_xtal.hw,
+ [CLKID_RTC_32K_SEL] = &a1_rtc_32k_sel.hw,
+ [CLKID_CECB_32K_CLKIN] = &a1_cecb_32k_clkin.hw,
+ [CLKID_CECB_32K_DIV] = &a1_cecb_32k_div.hw,
+ [CLKID_CECB_32K_SEL_PRE] = &a1_cecb_32k_sel_pre.hw,
+ [CLKID_CECB_32K_SEL] = &a1_cecb_32k_sel.hw,
+ [CLKID_CECA_32K_CLKIN] = &a1_ceca_32k_clkin.hw,
+ [CLKID_CECA_32K_DIV] = &a1_ceca_32k_div.hw,
+ [CLKID_CECA_32K_SEL_PRE] = &a1_ceca_32k_sel_pre.hw,
+ [CLKID_CECA_32K_SEL] = &a1_ceca_32k_sel.hw,
[CLKID_DIV2_PRE] = &a1_fclk_div2_divn_pre.hw,
- [CLKID_FCLK_DIV2_DIVN] = &a1_fclk_div2_divn.hw,
+ [CLKID_24M_DIV2] = &a1_24m_div2.hw,
[CLKID_GEN_SEL] = &a1_gen_sel.hw,
[CLKID_GEN_DIV] = &a1_gen_div.hw,
- [CLKID_GEN] = &a1_gen.hw,
- [CLKID_SARADC_SEL] = &a1_saradc_sel.hw,
[CLKID_SARADC_DIV] = &a1_saradc_div.hw,
- [CLKID_SARADC_CLK] = &a1_saradc_clk.hw,
[CLKID_PWM_A_SEL] = &a1_pwm_a_sel.hw,
[CLKID_PWM_A_DIV] = &a1_pwm_a_div.hw,
- [CLKID_PWM_A] = &a1_pwm_a.hw,
[CLKID_PWM_B_SEL] = &a1_pwm_b_sel.hw,
[CLKID_PWM_B_DIV] = &a1_pwm_b_div.hw,
- [CLKID_PWM_B] = &a1_pwm_b.hw,
[CLKID_PWM_C_SEL] = &a1_pwm_c_sel.hw,
[CLKID_PWM_C_DIV] = &a1_pwm_c_div.hw,
- [CLKID_PWM_C] = &a1_pwm_c.hw,
[CLKID_PWM_D_SEL] = &a1_pwm_d_sel.hw,
[CLKID_PWM_D_DIV] = &a1_pwm_d_div.hw,
- [CLKID_PWM_D] = &a1_pwm_d.hw,
[CLKID_PWM_E_SEL] = &a1_pwm_e_sel.hw,
[CLKID_PWM_E_DIV] = &a1_pwm_e_div.hw,
- [CLKID_PWM_E] = &a1_pwm_e.hw,
[CLKID_PWM_F_SEL] = &a1_pwm_f_sel.hw,
[CLKID_PWM_F_DIV] = &a1_pwm_f_div.hw,
- [CLKID_PWM_F] = &a1_pwm_f.hw,
[CLKID_SPICC_SEL] = &a1_spicc_sel.hw,
[CLKID_SPICC_DIV] = &a1_spicc_div.hw,
[CLKID_SPICC_SEL2] = &a1_spicc_sel2.hw,
- [CLKID_SPICC] = &a1_spicc.hw,
[CLKID_TS_DIV] = &a1_ts_div.hw,
- [CLKID_TS] = &a1_ts.hw,
[CLKID_SPIFC_SEL] = &a1_spifc_sel.hw,
[CLKID_SPIFC_DIV] = &a1_spifc_div.hw,
[CLKID_SPIFC_SEL2] = &a1_spifc_sel2.hw,
- [CLKID_SPIFC] = &a1_spifc.hw,
[CLKID_USB_BUS_SEL] = &a1_usb_bus_sel.hw,
[CLKID_USB_BUS_DIV] = &a1_usb_bus_div.hw,
- [CLKID_USB_BUS] = &a1_usb_bus.hw,
[CLKID_SD_EMMC_SEL] = &a1_sd_emmc_sel.hw,
[CLKID_SD_EMMC_DIV] = &a1_sd_emmc_div.hw,
[CLKID_SD_EMMC_SEL2] = &a1_sd_emmc_sel2.hw,
- [CLKID_SD_EMMC] = &a1_sd_emmc.hw,
[CLKID_PSRAM_SEL] = &a1_psram_sel.hw,
[CLKID_PSRAM_DIV] = &a1_psram_div.hw,
[CLKID_PSRAM_SEL2] = &a1_psram_sel2.hw,
- [CLKID_PSRAM] = &a1_psram.hw,
[CLKID_DMC_SEL] = &a1_dmc_sel.hw,
[CLKID_DMC_DIV] = &a1_dmc_div.hw,
[CLKID_DMC_SEL2] = &a1_dmc_sel2.hw,
- [CLKID_DMC] = &a1_dmc.hw,
- [CLKID_RTC_32K_CLKIN] = &a1_rtc_32k_clkin.hw,
- [CLKID_RTC_32K_DIV] = &a1_rtc_32k_div.hw,
- [CLKID_RTC_32K_XTAL] = &a1_rtc_32k_xtal.hw,
- [CLKID_RTC_32K_SEL] = &a1_rtc_32k_sel.hw,
- [CLKID_RTC_CLK] = &a1_rtc_clk.hw,
- [CLKID_CECA_32K_CLKIN] = &a1_ceca_32k_clkin.hw,
- [CLKID_CECA_32K_DIV] = &a1_ceca_32k_div.hw,
- [CLKID_CECA_32K_SEL_PRE] = &a1_ceca_32k_sel_pre.hw,
- [CLKID_CECA_32K_SEL] = &a1_ceca_32k_sel.hw,
- [CLKID_CECA_32K] = &a1_ceca_32k_clkout.hw,
- [CLKID_CECB_32K_CLKIN] = &a1_cecb_32k_clkin.hw,
- [CLKID_CECB_32K_DIV] = &a1_cecb_32k_div.hw,
- [CLKID_CECB_32K_SEL_PRE] = &a1_cecb_32k_sel_pre.hw,
- [CLKID_CECB_32K_SEL] = &a1_cecb_32k_sel.hw,
- [CLKID_CECB_32K] = &a1_cecb_32k_clkout.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -2041,10 +2043,12 @@ static struct clk_regmap *const a1_periphs_regmaps[] = {
&a1_xtal_hifipll,
&a1_xtal_syspll,
&a1_xtal_dds,
+ &a1_sys_clk,
&a1_clk_tree,
&a1_reset_ctrl,
&a1_analog_ctrl,
&a1_pwr_ctrl,
+ &a1_pad_ctrl,
&a1_sys_ctrl,
&a1_temp_sensor,
&a1_am2axi_dev,
@@ -2093,157 +2097,126 @@ static struct clk_regmap *const a1_periphs_regmaps[] = {
&a1_cpu_ctrl,
&a1_rom,
&a1_prod_i2c,
+ &a1_dspa_sel,
+ &a1_dspb_sel,
+ &a1_dspa_en,
+ &a1_dspa_en_nic,
+ &a1_dspb_en,
+ &a1_dspb_en_nic,
+ &a1_rtc_clk,
+ &a1_ceca_32k_clkout,
+ &a1_cecb_32k_clkout,
+ &a1_24m,
+ &a1_12m,
+ &a1_fclk_div2_divn,
+ &a1_gen,
+ &a1_saradc_sel,
+ &a1_saradc_clk,
+ &a1_pwm_a,
+ &a1_pwm_b,
+ &a1_pwm_c,
+ &a1_pwm_d,
+ &a1_pwm_e,
+ &a1_pwm_f,
+ &a1_spicc,
+ &a1_ts,
+ &a1_spifc,
+ &a1_usb_bus,
+ &a1_sd_emmc,
+ &a1_psram,
+ &a1_dmc,
+ &a1_sys_a_sel,
+ &a1_sys_a_div,
+ &a1_sys_a,
+ &a1_sys_b_sel,
+ &a1_sys_b_div,
+ &a1_sys_b,
&a1_dspa_a_sel,
&a1_dspa_a_div,
&a1_dspa_a,
&a1_dspa_b_sel,
&a1_dspa_b_div,
&a1_dspa_b,
- &a1_dspa_sel,
&a1_dspb_a_sel,
&a1_dspb_a_div,
&a1_dspb_a,
&a1_dspb_b_sel,
&a1_dspb_b_div,
&a1_dspb_b,
- &a1_dspb_sel,
- &a1_dspa_en,
- &a1_dspa_en_nic,
- &a1_dspb_en,
- &a1_dspb_en_nic,
- &a1_24m,
- &a1_12m,
+ &a1_rtc_32k_clkin,
+ &a1_rtc_32k_div,
+ &a1_rtc_32k_xtal,
+ &a1_rtc_32k_sel,
+ &a1_cecb_32k_clkin,
+ &a1_cecb_32k_div,
+ &a1_cecb_32k_sel_pre,
+ &a1_cecb_32k_sel,
+ &a1_ceca_32k_clkin,
+ &a1_ceca_32k_div,
+ &a1_ceca_32k_sel_pre,
+ &a1_ceca_32k_sel,
&a1_fclk_div2_divn_pre,
- &a1_fclk_div2_divn,
&a1_gen_sel,
&a1_gen_div,
- &a1_gen,
- &a1_saradc_sel,
&a1_saradc_div,
- &a1_saradc_clk,
&a1_pwm_a_sel,
&a1_pwm_a_div,
- &a1_pwm_a,
&a1_pwm_b_sel,
&a1_pwm_b_div,
- &a1_pwm_b,
&a1_pwm_c_sel,
&a1_pwm_c_div,
- &a1_pwm_c,
&a1_pwm_d_sel,
&a1_pwm_d_div,
- &a1_pwm_d,
&a1_pwm_e_sel,
&a1_pwm_e_div,
- &a1_pwm_e,
&a1_pwm_f_sel,
&a1_pwm_f_div,
- &a1_pwm_f,
&a1_spicc_sel,
&a1_spicc_div,
&a1_spicc_sel2,
- &a1_spicc,
&a1_ts_div,
- &a1_ts,
&a1_spifc_sel,
&a1_spifc_div,
&a1_spifc_sel2,
- &a1_spifc,
&a1_usb_bus_sel,
&a1_usb_bus_div,
- &a1_usb_bus,
&a1_sd_emmc_sel,
&a1_sd_emmc_div,
&a1_sd_emmc_sel2,
- &a1_sd_emmc,
&a1_psram_sel,
&a1_psram_div,
&a1_psram_sel2,
- &a1_psram,
&a1_dmc_sel,
&a1_dmc_div,
&a1_dmc_sel2,
- &a1_dmc,
- &a1_sys_b_sel,
- &a1_sys_b_div,
- &a1_sys_b,
- &a1_sys_a_sel,
- &a1_sys_a_div,
- &a1_sys_a,
- &a1_sys_clk,
- &a1_rtc_32k_clkin,
- &a1_rtc_32k_div,
- &a1_rtc_32k_xtal,
- &a1_rtc_32k_sel,
- &a1_rtc_clk,
- &a1_ceca_32k_clkin,
- &a1_ceca_32k_div,
- &a1_ceca_32k_sel_pre,
- &a1_ceca_32k_sel,
- &a1_ceca_32k_clkout,
- &a1_cecb_32k_clkin,
- &a1_cecb_32k_div,
- &a1_cecb_32k_sel_pre,
- &a1_cecb_32k_sel,
- &a1_cecb_32k_clkout,
};
-static struct regmap_config clkc_regmap_config = {
- .reg_bits = 32,
- .val_bits = 32,
- .reg_stride = 4,
+static const struct meson_a1_clkc_data a1_periphs_clkc __maybe_unused = {
+ .hw = &a1_periphs_hw_onecell_data,
+ .regs = a1_periphs_regmaps,
+ .num_regs = ARRAY_SIZE(a1_periphs_regmaps),
};
-static int meson_a1_periphs_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct resource *res;
- void __iomem *base;
- struct regmap *map;
- int ret, i;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-
- base = devm_ioremap_resource(dev, res);
- if (IS_ERR(base))
- return PTR_ERR(base);
-
- map = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
- if (IS_ERR(map))
- return PTR_ERR(map);
-
- /* Populate regmap for the regmap backed clocks */
- for (i = 0; i < ARRAY_SIZE(a1_periphs_regmaps); i++)
- a1_periphs_regmaps[i]->map = map;
-
- for (i = 0; i < a1_periphs_hw_onecell_data.num; i++) {
- /* array might be sparse */
- if (!a1_periphs_hw_onecell_data.hws[i])
- continue;
-
- ret = devm_clk_hw_register(dev,
- a1_periphs_hw_onecell_data.hws[i]);
- if (ret) {
- dev_err(dev, "Clock registration failed\n");
- return ret;
- }
- }
-
- return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
- &a1_periphs_hw_onecell_data);
-}
-
-static const struct of_device_id clkc_match_table[] = {
- { .compatible = "amlogic,a1-periphs-clkc", },
- {}
+#ifdef CONFIG_OF
+static const struct of_device_id a1_periphs_clkc_match_table[] = {
+ {
+ .compatible = "amlogic,a1-periphs-clkc",
+ .data = &a1_periphs_clkc,
+ },
+ {},
};
+MODULE_DEVICE_TABLE(of, a1_periphs_clkc_match_table);
+#endif /* CONFIG_OF */
-static struct platform_driver a1_periphs_driver = {
- .probe = meson_a1_periphs_probe,
- .driver = {
- .name = "a1-periphs-clkc",
- .of_match_table = clkc_match_table,
+static struct platform_driver a1_periphs_clkc_driver = {
+ .probe = meson_a1_clkc_probe,
+ .driver = {
+ .name = "a1-periphs-clkc",
+ .of_match_table = of_match_ptr(a1_periphs_clkc_match_table),
},
};
-builtin_platform_driver(a1_periphs_driver);
+module_platform_driver(a1_periphs_clkc_driver);
+MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>");
+MODULE_AUTHOR("Dmitry Rokosov <ddrokosov@sberdevices.ru>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/meson/a1.h b/drivers/clk/meson/a1.h
index 1ae5e04848d6..94b155e33568 100644
--- a/drivers/clk/meson/a1.h
+++ b/drivers/clk/meson/a1.h
@@ -1,6 +1,12 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
+ * Amlogic Meson-A1 Peripheral Clock Controller internals
+ *
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ * Author: Jian Hu <jian.hu@amlogic.com>
+ *
+ * Copyright (c) 2022, SberDevices. All Rights Reserved.
+ * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
*/
#ifndef __A1_H
@@ -12,7 +18,6 @@
#define RTC_BY_OSCIN_CTRL1 0x8
#define RTC_CTRL 0xc
#define SYS_CLK_CTRL0 0x10
-#define AXI_CLK_CTRL0 0x14
#define SYS_CLK_EN0 0x1c
#define SYS_CLK_EN1 0x20
#define AXI_CLK_EN 0x24
@@ -22,13 +27,6 @@
#define DSPB_CLK_CTRL0 0x34
#define CLK12_24_CTRL 0x38
#define GEN_CLK_CTRL 0x3c
-#define TIMESTAMP_CTRL0 0x40
-#define TIMESTAMP_CTRL1 0x44
-#define TIMESTAMP_CTRL2 0x48
-#define TIMESTAMP_VAL0 0x4c
-#define TIMESTAMP_VAL1 0x50
-#define TIMEBASE_CTRL0 0x54
-#define TIMEBASE_CTRL1 0x58
#define SAR_ADC_CLK_CTRL 0xc0
#define PWM_CLK_AB_CTRL 0xc4
#define PWM_CLK_CD_CTRL 0xc8
@@ -44,8 +42,6 @@
#define CECB_CLK_CTRL1 0xf0
#define PSRAM_CLK_CTRL 0xf4
#define DMC_CLK_CTRL 0xf8
-#define FCLK_DIV1_SEL 0xfc
-#define TST_CTRL 0x100
#define CLKID_XTAL_CLKTREE 0
#define CLKID_SYS_A_SEL 89
--
2.36.0
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v8 10/11] dt-bindings: clock: meson: fixup A1 peripherals clkc dtb_check errors
2022-12-01 22:56 [PATCH v8 00/11] add Amlogic A1 clock controller drivers Dmitry Rokosov
` (8 preceding siblings ...)
2022-12-01 22:57 ` [PATCH v8 09/11] clk: meson: redesign A1 Peripherals CLK controller Dmitry Rokosov
@ 2022-12-01 22:57 ` Dmitry Rokosov
2022-12-02 10:40 ` Krzysztof Kozlowski
2022-12-01 22:57 ` [PATCH v8 11/11] arm64: dts: meson: a1: introduce PLL and Peripherals clk controllers Dmitry Rokosov
10 siblings, 1 reply; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-01 22:57 UTC (permalink / raw)
To: neil.armstrong, jbrunet, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Dmitry Rokosov
During running dtbs_check and dt_binding_check checkers the following
problems were found and resolved:
- $id is not correct, it has wrong url path
- no base offset in the dt node definition
- CLKIDs aren't applied by names, just magic int constants there
- address and size cells are required for long reg definition
- wrong indentations
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
---
.../bindings/clock/amlogic,a1-clkc.yaml | 36 +++++++++++--------
1 file changed, 22 insertions(+), 14 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
index 7729850046cf..b0249ab21466 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
@@ -1,7 +1,7 @@
-#SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/amlogic,a1-clkc.yaml#"
+$id: "http://devicetree.org/schemas/clock/amlogic,a1-clkc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Amlogic Meson A/C serials Peripheral Clock Control Unit Device Tree Bindings
@@ -10,6 +10,7 @@ maintainers:
- Neil Armstrong <narmstrong@baylibre.com>
- Jerome Brunet <jbrunet@baylibre.com>
- Jian Hu <jian.hu@jian.hu.com>
+ - Dmitry Rokosov <ddrokosov@sberdevices.ru>
properties:
compatible:
@@ -50,16 +51,23 @@ additionalProperties: false
examples:
- |
- clkc_periphs: periphs-clock-controller {
- compatible = "amlogic,a1-periphs-clkc";
- reg = <0 0x800 0 0x104>;
- #clock-cells = <1>;
- clocks = <&clkc_pll 6>,
- <&clkc_pll 7>,
- <&clkc_pll 8>,
- <&clkc_pll 9>,
- <&clkc_pll 10>,
- <&xtal>;
- clock-names = "fclk_div2", "fclk_div3", "fclk_div5",
- "fclk_div7", "hifi_pll", "xtal";
+ #include <dt-bindings/clock/a1-pll-clkc.h>
+ apb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clkc_periphs: periphs-clock-controller@800 {
+ compatible = "amlogic,a1-periphs-clkc";
+ reg = <0 0x800 0 0x104>;
+ #clock-cells = <1>;
+ clocks = <&clkc_pll CLKID_FCLK_DIV2>,
+ <&clkc_pll CLKID_FCLK_DIV3>,
+ <&clkc_pll CLKID_FCLK_DIV5>,
+ <&clkc_pll CLKID_FCLK_DIV7>,
+ <&clkc_pll CLKID_HIFI_PLL>,
+ <&xtal>;
+ clock-names = "fclk_div2", "fclk_div3",
+ "fclk_div5", "fclk_div7",
+ "hifi_pll", "xtal";
+ };
};
--
2.36.0
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v8 11/11] arm64: dts: meson: a1: introduce PLL and Peripherals clk controllers
2022-12-01 22:56 [PATCH v8 00/11] add Amlogic A1 clock controller drivers Dmitry Rokosov
` (9 preceding siblings ...)
2022-12-01 22:57 ` [PATCH v8 10/11] dt-bindings: clock: meson: fixup A1 peripherals clkc dtb_check errors Dmitry Rokosov
@ 2022-12-01 22:57 ` Dmitry Rokosov
2022-12-02 10:43 ` Krzysztof Kozlowski
2022-12-02 12:03 ` Jerome Brunet
10 siblings, 2 replies; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-01 22:57 UTC (permalink / raw)
To: neil.armstrong, jbrunet, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Dmitry Rokosov
This patch adds clkc_periphs and clkc_pll dts nodes to A1 SoC main dtsi.
The first one clk controller is responsible for all SoC peripherals
clocks excluding audio clocks. The second one clk controller is used by
A1 SoC PLLs. Actually, there are two different APB heads, so we have two
different drivers.
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 27 ++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index b4000cf65a9a..38e6517c603c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -6,6 +6,8 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/meson-a1-gpio.h>
+#include <dt-bindings/clock/a1-pll-clkc.h>
+#include <dt-bindings/clock/a1-clkc.h>
/ {
compatible = "amlogic,a1";
@@ -81,7 +83,6 @@ apb: bus@fe000000 {
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
-
reset: reset-controller@0 {
compatible = "amlogic,meson-a1-reset";
reg = <0x0 0x0 0x0 0x8c>;
@@ -124,6 +125,30 @@ uart_AO_B: serial@2000 {
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
+
+ clkc_periphs: periphs-clock-controller@800 {
+ compatible = "amlogic,a1-periphs-clkc";
+ reg = <0 0x800 0 0x104>;
+ #clock-cells = <1>;
+ clocks = <&clkc_pll CLKID_FCLK_DIV2>,
+ <&clkc_pll CLKID_FCLK_DIV3>,
+ <&clkc_pll CLKID_FCLK_DIV5>,
+ <&clkc_pll CLKID_FCLK_DIV7>,
+ <&clkc_pll CLKID_HIFI_PLL>,
+ <&xtal>;
+ clock-names = "fclk_div2", "fclk_div3",
+ "fclk_div5", "fclk_div7",
+ "hifi_pll", "xtal";
+ };
+
+ clkc_pll: pll-clock-controller@7c80 {
+ compatible = "amlogic,a1-pll-clkc";
+ reg = <0 0x7c80 0 0x18c>;
+ #clock-cells = <1>;
+ clocks = <&clkc_periphs CLKID_XTAL_FIXPLL>,
+ <&clkc_periphs CLKID_XTAL_HIFIPLL>;
+ clock-names = "xtal_fixpll", "xtal_hifipll";
+ };
};
gic: interrupt-controller@ff901000 {
--
2.36.0
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 45+ messages in thread
* Re: [PATCH v8 01/11] dt-bindings: clock: meson: add A1 PLL clock controller bindings
2022-12-01 22:56 ` [PATCH v8 01/11] dt-bindings: clock: meson: add A1 PLL clock controller bindings Dmitry Rokosov
@ 2022-12-02 4:10 ` Rob Herring
2022-12-02 9:51 ` Dmitry Rokosov
2022-12-02 10:42 ` Krzysztof Kozlowski
2022-12-02 11:11 ` Jerome Brunet
2 siblings, 1 reply; 45+ messages in thread
From: Rob Herring @ 2022-12-02 4:10 UTC (permalink / raw)
To: Dmitry Rokosov
Cc: devicetree, sboyd, khilman, kernel, robh+dt, martin.blumenstingl,
linux-arm-kernel, jian.hu, linux-kernel, krzysztof.kozlowski+dt,
linux-amlogic, jbrunet, rockosov, mturquette, linux-clk,
neil.armstrong
On Fri, 02 Dec 2022 01:56:53 +0300, Dmitry Rokosov wrote:
> From: Jian Hu <jian.hu@amlogic.com>
>
> Add the documentation to support Amlogic A1 PLL clock driver,
> and add A1 PLL clock controller bindings.
>
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> ---
> .../bindings/clock/amlogic,a1-pll-clkc.yaml | 52 +++++++++++++++++++
> include/dt-bindings/clock/a1-pll-clkc.h | 16 ++++++
> 2 files changed, 68 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
> create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
./Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml:26:6: [warning] wrong indentation: expected 6 but found 5 (indentation)
dtschema/dtc warnings/errors:
./Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml: $id: relative path/filename doesn't match actual path or filename
expected: http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.example.dtb: pll-clock-controller@7c80: reg: [[0, 31872], [0, 396]] is too long
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20221201225703.6507-2-ddrokosov@sberdevices.ru
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 03/11] dt-bindings: clock: meson: add A1 peripheral clock controller bindings
2022-12-01 22:56 ` [PATCH v8 03/11] dt-bindings: clock: meson: add A1 peripheral clock controller bindings Dmitry Rokosov
@ 2022-12-02 4:10 ` Rob Herring
2022-12-02 9:49 ` Dmitry Rokosov
2022-12-02 10:43 ` Krzysztof Kozlowski
1 sibling, 1 reply; 45+ messages in thread
From: Rob Herring @ 2022-12-02 4:10 UTC (permalink / raw)
To: Dmitry Rokosov
Cc: martin.blumenstingl, linux-arm-kernel, krzysztof.kozlowski+dt,
khilman, jian.hu, jbrunet, mturquette, linux-amlogic, devicetree,
linux-kernel, linux-clk, rockosov, kernel, neil.armstrong,
robh+dt, sboyd
On Fri, 02 Dec 2022 01:56:55 +0300, Dmitry Rokosov wrote:
> From: Jian Hu <jian.hu@amlogic.com>
>
> Add the documentation to support Amlogic A1 peripheral clock driver,
> and add A1 peripheral clock controller bindings.
>
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> ---
> .../bindings/clock/amlogic,a1-clkc.yaml | 65 ++++++++++++
> include/dt-bindings/clock/a1-clkc.h | 98 +++++++++++++++++++
> 2 files changed, 163 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
> create mode 100644 include/dt-bindings/clock/a1-clkc.h
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
./Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml: $id: relative path/filename doesn't match actual path or filename
expected: http://devicetree.org/schemas/clock/amlogic,a1-clkc.yaml#
Documentation/devicetree/bindings/clock/amlogic,a1-clkc.example.dts:18.48-30.11: Warning (unit_address_vs_reg): /example-0/periphs-clock-controller: node has a reg or ranges property, but no unit name
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.example.dtb: periphs-clock-controller: reg: [[0, 2048], [0, 260]] is too long
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20221201225703.6507-4-ddrokosov@sberdevices.ru
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 03/11] dt-bindings: clock: meson: add A1 peripheral clock controller bindings
2022-12-02 4:10 ` Rob Herring
@ 2022-12-02 9:49 ` Dmitry Rokosov
2022-12-02 10:39 ` Krzysztof Kozlowski
0 siblings, 1 reply; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-02 9:49 UTC (permalink / raw)
To: Rob Herring
Cc: martin.blumenstingl, linux-arm-kernel, krzysztof.kozlowski+dt,
khilman, jian.hu, jbrunet, mturquette, linux-amlogic, devicetree,
linux-kernel, linux-clk, rockosov, kernel, neil.armstrong,
robh+dt, sboyd
On Thu, Dec 01, 2022 at 10:10:04PM -0600, Rob Herring wrote:
>
> On Fri, 02 Dec 2022 01:56:55 +0300, Dmitry Rokosov wrote:
> > From: Jian Hu <jian.hu@amlogic.com>
> >
> > Add the documentation to support Amlogic A1 peripheral clock driver,
> > and add A1 peripheral clock controller bindings.
> >
> > Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> > Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> > ---
> > .../bindings/clock/amlogic,a1-clkc.yaml | 65 ++++++++++++
> > include/dt-bindings/clock/a1-clkc.h | 98 +++++++++++++++++++
> > 2 files changed, 163 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
> > create mode 100644 include/dt-bindings/clock/a1-clkc.h
> >
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> ./Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml: $id: relative path/filename doesn't match actual path or filename
> expected: http://devicetree.org/schemas/clock/amlogic,a1-clkc.yaml#
> Documentation/devicetree/bindings/clock/amlogic,a1-clkc.example.dts:18.48-30.11: Warning (unit_address_vs_reg): /example-0/periphs-clock-controller: node has a reg or ranges property, but no unit name
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.example.dtb: periphs-clock-controller: reg: [[0, 2048], [0, 260]] is too long
> From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
>
> doc reference errors (make refcheckdocs):
>
> See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20221201225703.6507-4-ddrokosov@sberdevices.ru
>
> The base for the series is generally the latest rc1. A different dependency
> should be noted in *this* patch.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit after running the above command yourself. Note
> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> your schema. However, it must be unset to test all examples with your schema.
>
That's totally right warnings and errors. All of them are fixed in the
my "fixup" patch of Jian's original dt_binding schema:
https://lore.kernel.org/linux-amlogic/20221201225703.6507-11-ddrokosov@sberdevices.ru/
--
Thank you,
Dmitry
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 01/11] dt-bindings: clock: meson: add A1 PLL clock controller bindings
2022-12-02 4:10 ` Rob Herring
@ 2022-12-02 9:51 ` Dmitry Rokosov
2022-12-02 10:39 ` Krzysztof Kozlowski
0 siblings, 1 reply; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-02 9:51 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, sboyd, khilman, kernel, robh+dt, martin.blumenstingl,
linux-arm-kernel, jian.hu, linux-kernel, krzysztof.kozlowski+dt,
linux-amlogic, jbrunet, rockosov, mturquette, linux-clk,
neil.armstrong
On Thu, Dec 01, 2022 at 10:10:04PM -0600, Rob Herring wrote:
>
> On Fri, 02 Dec 2022 01:56:53 +0300, Dmitry Rokosov wrote:
> > From: Jian Hu <jian.hu@amlogic.com>
> >
> > Add the documentation to support Amlogic A1 PLL clock driver,
> > and add A1 PLL clock controller bindings.
> >
> > Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> > Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> > ---
> > .../bindings/clock/amlogic,a1-pll-clkc.yaml | 52 +++++++++++++++++++
> > include/dt-bindings/clock/a1-pll-clkc.h | 16 ++++++
> > 2 files changed, 68 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
> > create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h
> >
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
> ./Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml:26:6: [warning] wrong indentation: expected 6 but found 5 (indentation)
>
> dtschema/dtc warnings/errors:
> ./Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml: $id: relative path/filename doesn't match actual path or filename
> expected: http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.example.dtb: pll-clock-controller@7c80: reg: [[0, 31872], [0, 396]] is too long
> From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
>
> doc reference errors (make refcheckdocs):
>
> See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20221201225703.6507-2-ddrokosov@sberdevices.ru
>
> The base for the series is generally the latest rc1. A different dependency
> should be noted in *this* patch.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit after running the above command yourself. Note
> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> your schema. However, it must be unset to test all examples with your schema.
>
Please find all fixes of above warnings and errors in the my patch
located at the link:
https://lore.kernel.org/linux-amlogic/20221201225703.6507-9-ddrokosov@sberdevices.ru/
--
Thank you,
Dmitry
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 01/11] dt-bindings: clock: meson: add A1 PLL clock controller bindings
2022-12-02 9:51 ` Dmitry Rokosov
@ 2022-12-02 10:39 ` Krzysztof Kozlowski
2022-12-02 11:04 ` Jerome Brunet
0 siblings, 1 reply; 45+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-02 10:39 UTC (permalink / raw)
To: Dmitry Rokosov, Rob Herring
Cc: devicetree, sboyd, khilman, kernel, robh+dt, martin.blumenstingl,
linux-arm-kernel, jian.hu, linux-kernel, krzysztof.kozlowski+dt,
linux-amlogic, jbrunet, rockosov, mturquette, linux-clk,
neil.armstrong
On 02/12/2022 10:51, Dmitry Rokosov wrote:
> On Thu, Dec 01, 2022 at 10:10:04PM -0600, Rob Herring wrote:
>>
>> On Fri, 02 Dec 2022 01:56:53 +0300, Dmitry Rokosov wrote:
>>> From: Jian Hu <jian.hu@amlogic.com>
>>>
>>> Add the documentation to support Amlogic A1 PLL clock driver,
>>> and add A1 PLL clock controller bindings.
>>>
>>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>>> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
>>> ---
>>> .../bindings/clock/amlogic,a1-pll-clkc.yaml | 52 +++++++++++++++++++
>>> include/dt-bindings/clock/a1-pll-clkc.h | 16 ++++++
>>> 2 files changed, 68 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
>>> create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h
>>>
>>
>> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
>> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>>
>> yamllint warnings/errors:
>> ./Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml:26:6: [warning] wrong indentation: expected 6 but found 5 (indentation)
>>
>> dtschema/dtc warnings/errors:
>> ./Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml: $id: relative path/filename doesn't match actual path or filename
>> expected: http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml#
>> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.example.dtb: pll-clock-controller@7c80: reg: [[0, 31872], [0, 396]] is too long
>> From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
>>
>> doc reference errors (make refcheckdocs):
>>
>> See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20221201225703.6507-2-ddrokosov@sberdevices.ru
>>
>> The base for the series is generally the latest rc1. A different dependency
>> should be noted in *this* patch.
>>
>> If you already ran 'make dt_binding_check' and didn't see the above
>> error(s), then make sure 'yamllint' is installed and dt-schema is up to
>> date:
>>
>> pip3 install dtschema --upgrade
>>
>> Please check and re-submit after running the above command yourself. Note
>> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
>> your schema. However, it must be unset to test all examples with your schema.
>>
>
> Please find all fixes of above warnings and errors in the my patch
> located at the link:
>
> https://lore.kernel.org/linux-amlogic/20221201225703.6507-9-ddrokosov@sberdevices.ru/
Why? This patch here is broken and it should be fixed. Don't apply
broken patches...
Best regards,
Krzysztof
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 03/11] dt-bindings: clock: meson: add A1 peripheral clock controller bindings
2022-12-02 9:49 ` Dmitry Rokosov
@ 2022-12-02 10:39 ` Krzysztof Kozlowski
2022-12-02 10:58 ` Dmitry Rokosov
0 siblings, 1 reply; 45+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-02 10:39 UTC (permalink / raw)
To: Dmitry Rokosov, Rob Herring
Cc: martin.blumenstingl, linux-arm-kernel, krzysztof.kozlowski+dt,
khilman, jian.hu, jbrunet, mturquette, linux-amlogic, devicetree,
linux-kernel, linux-clk, rockosov, kernel, neil.armstrong,
robh+dt, sboyd
On 02/12/2022 10:49, Dmitry Rokosov wrote:
> On Thu, Dec 01, 2022 at 10:10:04PM -0600, Rob Herring wrote:
>>
>> On Fri, 02 Dec 2022 01:56:55 +0300, Dmitry Rokosov wrote:
>>> From: Jian Hu <jian.hu@amlogic.com>
>>>
>>> Add the documentation to support Amlogic A1 peripheral clock driver,
>>> and add A1 peripheral clock controller bindings.
>>>
>>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>>> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
>>> ---
>>> .../bindings/clock/amlogic,a1-clkc.yaml | 65 ++++++++++++
>>> include/dt-bindings/clock/a1-clkc.h | 98 +++++++++++++++++++
>>> 2 files changed, 163 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
>>> create mode 100644 include/dt-bindings/clock/a1-clkc.h
>>>
>>
>> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
>> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>>
>> yamllint warnings/errors:
>>
>> dtschema/dtc warnings/errors:
>> ./Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml: $id: relative path/filename doesn't match actual path or filename
>> expected: http://devicetree.org/schemas/clock/amlogic,a1-clkc.yaml#
>> Documentation/devicetree/bindings/clock/amlogic,a1-clkc.example.dts:18.48-30.11: Warning (unit_address_vs_reg): /example-0/periphs-clock-controller: node has a reg or ranges property, but no unit name
>> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.example.dtb: periphs-clock-controller: reg: [[0, 2048], [0, 260]] is too long
>> From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
>>
>> doc reference errors (make refcheckdocs):
>>
>> See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20221201225703.6507-4-ddrokosov@sberdevices.ru
>>
>> The base for the series is generally the latest rc1. A different dependency
>> should be noted in *this* patch.
>>
>> If you already ran 'make dt_binding_check' and didn't see the above
>> error(s), then make sure 'yamllint' is installed and dt-schema is up to
>> date:
>>
>> pip3 install dtschema --upgrade
>>
>> Please check and re-submit after running the above command yourself. Note
>> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
>> your schema. However, it must be unset to test all examples with your schema.
>>
>
> That's totally right warnings and errors. All of them are fixed in the
> my "fixup" patch of Jian's original dt_binding schema:
>
> https://lore.kernel.org/linux-amlogic/20221201225703.6507-11-ddrokosov@sberdevices.ru/
No, this patch must be fixed. It's not correct.
Best regards,
Krzysztof
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 08/11] dt-bindings: clock: meson: fixup A1 PLL clkc dtb_check errors
2022-12-01 22:57 ` [PATCH v8 08/11] dt-bindings: clock: meson: fixup A1 PLL clkc dtb_check errors Dmitry Rokosov
@ 2022-12-02 10:40 ` Krzysztof Kozlowski
0 siblings, 0 replies; 45+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-02 10:40 UTC (permalink / raw)
To: Dmitry Rokosov, neil.armstrong, jbrunet, mturquette, sboyd,
robh+dt, krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
On 01/12/2022 23:57, Dmitry Rokosov wrote:
> During running dtbs_check and dt_binding_check checkers the following
> problems were found and resolved:
> - $id is not correct, it has wrong url path
> - CLKIDs aren't applied by names, just magic int constants there
> - address and size cells are required for long reg definition
> - wrong indentations
>
> Also this patch adds new A1 clk controllers dt bindings to MAINTAINERS.
>
> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> ---
> .../bindings/clock/amlogic,a1-pll-clkc.yaml | 27 ++++++++++++-------
> MAINTAINERS | 1 +
> 2 files changed, 18 insertions(+), 10 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
> index d67250fbeece..83f98a73c04e 100644
> --- a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
> +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
> @@ -1,7 +1,7 @@
> # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> %YAML 1.2
> ---
> -$id: "http://devicetree.org/schemas/amlogic,a1-pll-clkc.yaml#"
> +$id: "http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml#"
> $schema: "http://devicetree.org/meta-schemas/core.yaml#"
>
> title: Amlogic Meson A/C serials PLL Clock Control Unit Device Tree Bindings
NAK.
This must be squashed.
Best regards,
Krzysztof
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 10/11] dt-bindings: clock: meson: fixup A1 peripherals clkc dtb_check errors
2022-12-01 22:57 ` [PATCH v8 10/11] dt-bindings: clock: meson: fixup A1 peripherals clkc dtb_check errors Dmitry Rokosov
@ 2022-12-02 10:40 ` Krzysztof Kozlowski
0 siblings, 0 replies; 45+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-02 10:40 UTC (permalink / raw)
To: Dmitry Rokosov, neil.armstrong, jbrunet, mturquette, sboyd,
robh+dt, krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
On 01/12/2022 23:57, Dmitry Rokosov wrote:
> During running dtbs_check and dt_binding_check checkers the following
> problems were found and resolved:
> - $id is not correct, it has wrong url path
> - no base offset in the dt node definition
> - CLKIDs aren't applied by names, just magic int constants there
> - address and size cells are required for long reg definition
> - wrong indentations
>
> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> ---
> .../bindings/clock/amlogic,a1-clkc.yaml | 36 +++++++++++--------
> 1 file changed, 22 insertions(+), 14 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
> index 7729850046cf..b0249ab21466 100644
> --- a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
> +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
> @@ -1,7 +1,7 @@
> -#SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> %YAML 1.2
> ---
> -$id: "http://devicetree.org/schemas/amlogic,a1-clkc.yaml#"
> +$id: "http://devicetree.org/schemas/clock/amlogic,a1-clkc.yaml#"
> $schema: "http://devicetree.org/meta-schemas/core.yaml#"
>
NAK. This must be squashed.
Best regards,
Krzysztof
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 01/11] dt-bindings: clock: meson: add A1 PLL clock controller bindings
2022-12-01 22:56 ` [PATCH v8 01/11] dt-bindings: clock: meson: add A1 PLL clock controller bindings Dmitry Rokosov
2022-12-02 4:10 ` Rob Herring
@ 2022-12-02 10:42 ` Krzysztof Kozlowski
2022-12-02 11:18 ` Dmitry Rokosov
2022-12-02 11:11 ` Jerome Brunet
2 siblings, 1 reply; 45+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-02 10:42 UTC (permalink / raw)
To: Dmitry Rokosov, neil.armstrong, jbrunet, mturquette, sboyd,
robh+dt, krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
On 01/12/2022 23:56, Dmitry Rokosov wrote:
> From: Jian Hu <jian.hu@amlogic.com>
>
> Add the documentation to support Amlogic A1 PLL clock driver,
> and add A1 PLL clock controller bindings.
>
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> ---
> .../bindings/clock/amlogic,a1-pll-clkc.yaml | 52 +++++++++++++++++++
> include/dt-bindings/clock/a1-pll-clkc.h | 16 ++++++
> 2 files changed, 68 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
> create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h
>
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
> new file mode 100644
> index 000000000000..d67250fbeece
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
> @@ -0,0 +1,52 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/amlogic,a1-pll-clkc.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
Drop quotes from both.
> +
> +title: Amlogic Meson A/C serials PLL Clock Control Unit Device Tree Bindings
Drop "Device Tree Bindings"
> +
> +maintainers:
> + - Neil Armstrong <narmstrong@baylibre.com>
Not correct email address.
> + - Jerome Brunet <jbrunet@baylibre.com>
> + - Jian Hu <jian.hu@jian.hu.com>
> +
> +properties:
> + compatible:
> + const: amlogic,a1-pll-clkc
> +
> + "#clock-cells":
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: input xtal_fixpll
> + - description: input xtal_hifipll
As pointed already - this patch cannot work and must not be merged.
> +
> + clock-names:
> + items:
> + - const: xtal_fixpll
> + - const: xtal_hifipll
> +
> +required:
> + - compatible
> + - "#clock-cells"
> + - reg
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clkc_pll: pll-clock-controller@7c80 {
Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + compatible = "amlogic,a1-pll-clkc";
Use 4 spaces for example indentation.
> + reg = <0 0x7c80 0 0x18c>;
> + #clock-cells = <1>;
> + clocks = <&clkc_periphs 1>,
> + <&clkc_periphs 4>;
> + clock-names = "xtal_fixpll", "xtal_hifipll";
> + };
> diff --git a/include/dt-bindings/clock/a1-pll-clkc.h b/include/dt-bindings/clock/a1-pll-clkc.h
> new file mode 100644
> index 000000000000..58eae237e503
> --- /dev/null
> +++ b/include/dt-bindings/clock/a1-pll-clkc.h
Filename matching compatible / bindings file.
> @@ -0,0 +1,16 @@
Best regards,
Krzysztof
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 03/11] dt-bindings: clock: meson: add A1 peripheral clock controller bindings
2022-12-01 22:56 ` [PATCH v8 03/11] dt-bindings: clock: meson: add A1 peripheral clock controller bindings Dmitry Rokosov
2022-12-02 4:10 ` Rob Herring
@ 2022-12-02 10:43 ` Krzysztof Kozlowski
1 sibling, 0 replies; 45+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-02 10:43 UTC (permalink / raw)
To: Dmitry Rokosov, neil.armstrong, jbrunet, mturquette, sboyd,
robh+dt, krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
On 01/12/2022 23:56, Dmitry Rokosov wrote:
> From: Jian Hu <jian.hu@amlogic.com>
>
> Add the documentation to support Amlogic A1 peripheral clock driver,
> and add A1 peripheral clock controller bindings.
>
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> ---
> .../bindings/clock/amlogic,a1-clkc.yaml | 65 ++++++++++++
> include/dt-bindings/clock/a1-clkc.h | 98 +++++++++++++++++++
> 2 files changed, 163 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
> create mode 100644 include/dt-bindings/clock/a1-clkc.h
>
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
> new file mode 100644
> index 000000000000..7729850046cf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
> @@ -0,0 +1,65 @@
> +#SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/amlogic,a1-clkc.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Amlogic Meson A/C serials Peripheral Clock Control Unit Device Tree Bindings
Same comments as with previous patch. All of them.
Best regards,
Krzysztof
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 11/11] arm64: dts: meson: a1: introduce PLL and Peripherals clk controllers
2022-12-01 22:57 ` [PATCH v8 11/11] arm64: dts: meson: a1: introduce PLL and Peripherals clk controllers Dmitry Rokosov
@ 2022-12-02 10:43 ` Krzysztof Kozlowski
2022-12-02 12:03 ` Jerome Brunet
1 sibling, 0 replies; 45+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-02 10:43 UTC (permalink / raw)
To: Dmitry Rokosov, neil.armstrong, jbrunet, mturquette, sboyd,
robh+dt, krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
On 01/12/2022 23:57, Dmitry Rokosov wrote:
> This patch adds clkc_periphs and clkc_pll dts nodes to A1 SoC main dtsi.
> The first one clk controller is responsible for all SoC peripherals
> clocks excluding audio clocks. The second one clk controller is used by
> A1 SoC PLLs. Actually, there are two different APB heads, so we have two
> different drivers.
>
> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> ---
> arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 27 ++++++++++++++++++++++-
> 1 file changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> index b4000cf65a9a..38e6517c603c 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> @@ -6,6 +6,8 @@
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/gpio/meson-a1-gpio.h>
> +#include <dt-bindings/clock/a1-pll-clkc.h>
> +#include <dt-bindings/clock/a1-clkc.h>
>
> / {
> compatible = "amlogic,a1";
> @@ -81,7 +83,6 @@ apb: bus@fe000000 {
> #size-cells = <2>;
> ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
>
> -
> reset: reset-controller@0 {
> compatible = "amlogic,meson-a1-reset";
> reg = <0x0 0x0 0x0 0x8c>;
> @@ -124,6 +125,30 @@ uart_AO_B: serial@2000 {
> clock-names = "xtal", "pclk", "baud";
> status = "disabled";
> };
> +
> + clkc_periphs: periphs-clock-controller@800 {
Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + compatible = "amlogic,a1-periphs-clkc";
> + reg = <0 0x800 0 0x104>;
> + #clock-cells = <1>;
> + clocks = <&clkc_pll CLKID_FCLK_DIV2>,
> + <&clkc_pll CLKID_FCLK_DIV3>,
> + <&clkc_pll CLKID_FCLK_DIV5>,
> + <&clkc_pll CLKID_FCLK_DIV7>,
> + <&clkc_pll CLKID_HIFI_PLL>,
> + <&xtal>;
> + clock-names = "fclk_div2", "fclk_div3",
> + "fclk_div5", "fclk_div7",
> + "hifi_pll", "xtal";
> + };
> +
> + clkc_pll: pll-clock-controller@7c80 {
Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + compatible = "amlogic,a1-pll-clkc";
Best regards,
Krzysztof
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 03/11] dt-bindings: clock: meson: add A1 peripheral clock controller bindings
2022-12-02 10:39 ` Krzysztof Kozlowski
@ 2022-12-02 10:58 ` Dmitry Rokosov
0 siblings, 0 replies; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-02 10:58 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, martin.blumenstingl, linux-arm-kernel,
krzysztof.kozlowski+dt, khilman, jian.hu, jbrunet, mturquette,
linux-amlogic, devicetree, linux-kernel, linux-clk, rockosov,
kernel, neil.armstrong, robh+dt, sboyd
Hello Krzysztof,
Thank you for quick review. Let me explain you why I sent Jian broken
patches and applied my fixup patches above.
I've found several versions of A1 clkc drivers from Jian Hu Amlogic engineer,
the last one version was a couple years ago.
I've reworked the last (v7) version and didn't know the correct way to apply
all fixes.
From my point of view I thought about two options:
1) Merge all my changes with Jian Hu patches and leave Jian Hu SoB
2) Don't touch Jian Hu v7 patches and apply my changes above.
I have chosen the second option, because it looks like respect Jian Hu's
effort. I don't want to "stealing" his patches, just want to fix all
broken things.
So I'm sorry for misunderstanding here and please correct
me what's right workflow in such situation.
On Fri, Dec 02, 2022 at 11:39:47AM +0100, Krzysztof Kozlowski wrote:
> On 02/12/2022 10:49, Dmitry Rokosov wrote:
> > On Thu, Dec 01, 2022 at 10:10:04PM -0600, Rob Herring wrote:
> >>
> >> On Fri, 02 Dec 2022 01:56:55 +0300, Dmitry Rokosov wrote:
> >>> From: Jian Hu <jian.hu@amlogic.com>
> >>>
> >>> Add the documentation to support Amlogic A1 peripheral clock driver,
> >>> and add A1 peripheral clock controller bindings.
> >>>
> >>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> >>> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> >>> ---
> >>> .../bindings/clock/amlogic,a1-clkc.yaml | 65 ++++++++++++
> >>> include/dt-bindings/clock/a1-clkc.h | 98 +++++++++++++++++++
> >>> 2 files changed, 163 insertions(+)
> >>> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
> >>> create mode 100644 include/dt-bindings/clock/a1-clkc.h
> >>>
> >>
> >> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> >> on your patch (DT_CHECKER_FLAGS is new in v5.13):
> >>
> >> yamllint warnings/errors:
> >>
> >> dtschema/dtc warnings/errors:
> >> ./Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml: $id: relative path/filename doesn't match actual path or filename
> >> expected: http://devicetree.org/schemas/clock/amlogic,a1-clkc.yaml#
> >> Documentation/devicetree/bindings/clock/amlogic,a1-clkc.example.dts:18.48-30.11: Warning (unit_address_vs_reg): /example-0/periphs-clock-controller: node has a reg or ranges property, but no unit name
> >> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.example.dtb: periphs-clock-controller: reg: [[0, 2048], [0, 260]] is too long
> >> From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
> >>
> >> doc reference errors (make refcheckdocs):
> >>
> >> See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20221201225703.6507-4-ddrokosov@sberdevices.ru
> >>
> >> The base for the series is generally the latest rc1. A different dependency
> >> should be noted in *this* patch.
> >>
> >> If you already ran 'make dt_binding_check' and didn't see the above
> >> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> >> date:
> >>
> >> pip3 install dtschema --upgrade
> >>
> >> Please check and re-submit after running the above command yourself. Note
> >> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> >> your schema. However, it must be unset to test all examples with your schema.
> >>
> >
> > That's totally right warnings and errors. All of them are fixed in the
> > my "fixup" patch of Jian's original dt_binding schema:
> >
> > https://lore.kernel.org/linux-amlogic/20221201225703.6507-11-ddrokosov@sberdevices.ru/
>
> No, this patch must be fixed. It's not correct.
>
> Best regards,
> Krzysztof
>
--
Thank you,
Dmitry
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 01/11] dt-bindings: clock: meson: add A1 PLL clock controller bindings
2022-12-02 10:39 ` Krzysztof Kozlowski
@ 2022-12-02 11:04 ` Jerome Brunet
2022-12-02 11:16 ` Krzysztof Kozlowski
0 siblings, 1 reply; 45+ messages in thread
From: Jerome Brunet @ 2022-12-02 11:04 UTC (permalink / raw)
To: Krzysztof Kozlowski, Dmitry Rokosov, Rob Herring
Cc: devicetree, sboyd, khilman, kernel, robh+dt, martin.blumenstingl,
linux-arm-kernel, jian.hu, linux-kernel, krzysztof.kozlowski+dt,
linux-amlogic, rockosov, mturquette, linux-clk, neil.armstrong
On Fri 02 Dec 2022 at 11:39, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
> On 02/12/2022 10:51, Dmitry Rokosov wrote:
>> On Thu, Dec 01, 2022 at 10:10:04PM -0600, Rob Herring wrote:
>>>
>>> On Fri, 02 Dec 2022 01:56:53 +0300, Dmitry Rokosov wrote:
>>>> From: Jian Hu <jian.hu@amlogic.com>
>>>>
>>>> Add the documentation to support Amlogic A1 PLL clock driver,
>>>> and add A1 PLL clock controller bindings.
>>>>
>>>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>>>> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
>>>> ---
>>>> .../bindings/clock/amlogic,a1-pll-clkc.yaml | 52 +++++++++++++++++++
>>>> include/dt-bindings/clock/a1-pll-clkc.h | 16 ++++++
>>>> 2 files changed, 68 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
>>>> create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h
>>>>
>>>
>>> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
>>> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>>>
>>> yamllint warnings/errors:
>>> ./Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml:26:6: [warning] wrong indentation: expected 6 but found 5 (indentation)
>>>
>>> dtschema/dtc warnings/errors:
>>> ./Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml: $id: relative path/filename doesn't match actual path or filename
>>> expected: http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml#
>>> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.example.dtb: pll-clock-controller@7c80: reg: [[0, 31872], [0, 396]] is too long
>>> From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
>>>
>>> doc reference errors (make refcheckdocs):
>>>
>>> See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20221201225703.6507-2-ddrokosov@sberdevices.ru
>>>
>>> The base for the series is generally the latest rc1. A different dependency
>>> should be noted in *this* patch.
>>>
>>> If you already ran 'make dt_binding_check' and didn't see the above
>>> error(s), then make sure 'yamllint' is installed and dt-schema is up to
>>> date:
>>>
>>> pip3 install dtschema --upgrade
>>>
>>> Please check and re-submit after running the above command yourself. Note
>>> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
>>> your schema. However, it must be unset to test all examples with your schema.
>>>
>>
>> Please find all fixes of above warnings and errors in the my patch
>> located at the link:
>>
>> https://lore.kernel.org/linux-amlogic/20221201225703.6507-9-ddrokosov@sberdevices.ru/
>
> Why? This patch here is broken and it should be fixed. Don't apply
> broken patches...
Dmitry is ressurecting a series that is several years old and not his to
begin with.
He was unsure about take the code of somebody else.
To be fair, he even asked for advice on IRC about to proceed.
Dmitry, as you may have guessed, for next revision, please fix Jian Hu
original patches in place, not with fixup patches.
If your fixes are minor (not complete rewrite), please keep the original
author and add your SoB
>
> Best regards,
> Krzysztof
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 01/11] dt-bindings: clock: meson: add A1 PLL clock controller bindings
2022-12-01 22:56 ` [PATCH v8 01/11] dt-bindings: clock: meson: add A1 PLL clock controller bindings Dmitry Rokosov
2022-12-02 4:10 ` Rob Herring
2022-12-02 10:42 ` Krzysztof Kozlowski
@ 2022-12-02 11:11 ` Jerome Brunet
2022-12-02 12:26 ` Dmitry Rokosov
2 siblings, 1 reply; 45+ messages in thread
From: Jerome Brunet @ 2022-12-02 11:11 UTC (permalink / raw)
To: Dmitry Rokosov, neil.armstrong, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
On Fri 02 Dec 2022 at 01:56, Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
> From: Jian Hu <jian.hu@amlogic.com>
>
> Add the documentation to support Amlogic A1 PLL clock driver,
> and add A1 PLL clock controller bindings.
>
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> ---
> .../bindings/clock/amlogic,a1-pll-clkc.yaml | 52 +++++++++++++++++++
> include/dt-bindings/clock/a1-pll-clkc.h | 16 ++++++
> 2 files changed, 68 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
> create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h
>
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
> new file mode 100644
> index 000000000000..d67250fbeece
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
> @@ -0,0 +1,52 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/amlogic,a1-pll-clkc.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Amlogic Meson A/C serials PLL Clock Control Unit Device Tree Bindings
> +
> +maintainers:
> + - Neil Armstrong <narmstrong@baylibre.com>
> + - Jerome Brunet <jbrunet@baylibre.com>
> + - Jian Hu <jian.hu@jian.hu.com>
> +
> +properties:
> + compatible:
> + const: amlogic,a1-pll-clkc
> +
> + "#clock-cells":
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: input xtal_fixpll
> + - description: input xtal_hifipll
> +
> + clock-names:
> + items:
> + - const: xtal_fixpll
> + - const: xtal_hifipll
Do we really need the "xtal_" prefix ?
Seems like the clock is the PLL, not the xtal
> +
> +required:
> + - compatible
> + - "#clock-cells"
> + - reg
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clkc_pll: pll-clock-controller@7c80 {
> + compatible = "amlogic,a1-pll-clkc";
> + reg = <0 0x7c80 0 0x18c>;
> + #clock-cells = <1>;
> + clocks = <&clkc_periphs 1>,
> + <&clkc_periphs 4>;
> + clock-names = "xtal_fixpll", "xtal_hifipll";
> + };
> diff --git a/include/dt-bindings/clock/a1-pll-clkc.h b/include/dt-bindings/clock/a1-pll-clkc.h
> new file mode 100644
> index 000000000000..58eae237e503
> --- /dev/null
> +++ b/include/dt-bindings/clock/a1-pll-clkc.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
> + */
> +
> +#ifndef __A1_PLL_CLKC_H
> +#define __A1_PLL_CLKC_H
> +
> +#define CLKID_FIXED_PLL 1
> +#define CLKID_FCLK_DIV2 6
> +#define CLKID_FCLK_DIV3 7
> +#define CLKID_FCLK_DIV5 8
> +#define CLKID_FCLK_DIV7 9
> +#define CLKID_HIFI_PLL 10
> +
> +#endif /* __A1_PLL_CLKC_H */
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 02/11] clk: meson: a1: add support for Amlogic A1 PLL clock driver
2022-12-01 22:56 ` [PATCH v8 02/11] clk: meson: a1: add support for Amlogic A1 PLL clock driver Dmitry Rokosov
@ 2022-12-02 11:16 ` Jerome Brunet
2022-12-02 11:31 ` Dmitry Rokosov
0 siblings, 1 reply; 45+ messages in thread
From: Jerome Brunet @ 2022-12-02 11:16 UTC (permalink / raw)
To: Dmitry Rokosov, neil.armstrong, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
On Fri 02 Dec 2022 at 01:56, Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
> From: Jian Hu <jian.hu@amlogic.com>
>
> The Amlogic A1 clock includes three drivers:
> pll clocks, peripheral clocks, CPU clocks.
> sys pll and CPU clocks will be sent in next patch.
>
> Unlike the previous series, there is no EE/AO domain
> in A1 CLK controllers.
>
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> ---
> drivers/clk/meson/Kconfig | 9 +
> drivers/clk/meson/Makefile | 1 +
> drivers/clk/meson/a1-pll.c | 360 +++++++++++++++++++++++++++++++++++++
> drivers/clk/meson/a1-pll.h | 56 ++++++
> 4 files changed, 426 insertions(+)
> create mode 100644 drivers/clk/meson/a1-pll.c
> create mode 100644 drivers/clk/meson/a1-pll.h
>
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index fc002c155bc3..ab34662b24f0 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -99,6 +99,15 @@ config COMMON_CLK_AXG_AUDIO
> Support for the audio clock controller on AmLogic A113D devices,
> aka axg, Say Y if you want audio subsystem to work.
>
> +config COMMON_CLK_A1_PLL
> + bool
Could you add a tristate with some text please ?
> + depends on ARCH_MESON
> + select COMMON_CLK_MESON_REGMAP
> + select COMMON_CLK_MESON_PLL
> + help
> + Support for the PLL clock controller on Amlogic A113L device,
> + aka a1. Say Y if you want PLL to work.
> +
> config COMMON_CLK_G12A
> tristate "G12 and SM1 SoC clock controllers support"
> depends on ARM64
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index 6eca2a406ee3..2f17f475a48f 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -16,6 +16,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o
>
> obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
> obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
> +obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o
> obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
> obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
> obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
> diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c
> new file mode 100644
> index 000000000000..69c1ca07d041
> --- /dev/null
> +++ b/drivers/clk/meson/a1-pll.c
> @@ -0,0 +1,360 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
> + * Author: Jian Hu <jian.hu@amlogic.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include "a1-pll.h"
> +#include "clk-pll.h"
> +#include "clk-regmap.h"
> +
> +static struct clk_regmap a1_fixed_pll_dco = {
> + .data = &(struct meson_clk_pll_data){
> + .en = {
> + .reg_off = ANACTRL_FIXPLL_CTRL0,
> + .shift = 28,
> + .width = 1,
> + },
> + .m = {
> + .reg_off = ANACTRL_FIXPLL_CTRL0,
> + .shift = 0,
> + .width = 8,
> + },
> + .n = {
> + .reg_off = ANACTRL_FIXPLL_CTRL0,
> + .shift = 10,
> + .width = 5,
> + },
> + .frac = {
> + .reg_off = ANACTRL_FIXPLL_CTRL1,
> + .shift = 0,
> + .width = 19,
> + },
> + .l = {
> + .reg_off = ANACTRL_FIXPLL_STS,
> + .shift = 31,
> + .width = 1,
> + },
> + .rst = {
> + .reg_off = ANACTRL_FIXPLL_CTRL0,
> + .shift = 29,
> + .width = 1,
> + },
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fixed_pll_dco",
> + .ops = &meson_clk_pll_ro_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xtal_fixpll",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_fixed_pll = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL0,
> + .bit_idx = 20,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "fixed_pll",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_fixed_pll_dco.hw
> + },
> + .num_parents = 1,
> + /*
> + * It is enough that the fdiv leaf has critical flag,
> + * No critical or unused flag here.
> + */
> + },
> +};
> +
> +static const struct pll_mult_range a1_hifi_pll_mult_range = {
> + .min = 32,
> + .max = 64,
> +};
> +
> +static const struct reg_sequence a1_hifi_init_regs[] = {
> + { .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x01800000 },
> + { .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00001100 },
> + { .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x100a1100 },
> + { .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x00302000 },
> + { .reg = ANACTRL_HIFIPLL_CTRL0, .def = 0x01f18440 },
> +};
> +
> +static struct clk_regmap a1_hifi_pll = {
> + .data = &(struct meson_clk_pll_data){
> + .en = {
> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
> + .shift = 28,
> + .width = 1,
> + },
> + .m = {
> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
> + .shift = 0,
> + .width = 8,
> + },
> + .n = {
> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
> + .shift = 10,
> + .width = 5,
> + },
> + .frac = {
> + .reg_off = ANACTRL_HIFIPLL_CTRL1,
> + .shift = 0,
> + .width = 19,
> + },
> + .l = {
> + .reg_off = ANACTRL_HIFIPLL_STS,
> + .shift = 31,
> + .width = 1,
> + },
> + .current_en = {
> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
> + .shift = 26,
> + .width = 1,
> + },
> + .l_detect = {
> + .reg_off = ANACTRL_HIFIPLL_CTRL2,
> + .shift = 6,
> + .width = 1,
> + },
> + .range = &a1_hifi_pll_mult_range,
> + .init_regs = a1_hifi_init_regs,
> + .init_count = ARRAY_SIZE(a1_hifi_init_regs),
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "hifi_pll",
> + .ops = &meson_clk_pll_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xtal_hifipll",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor a1_fclk_div2_div = {
> + .mult = 1,
> + .div = 2,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div2_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_fixed_pll.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_fclk_div2 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL0,
> + .bit_idx = 21,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div2",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_fclk_div2_div.hw
> + },
> + .num_parents = 1,
> + /*
> + * This clock is used by DDR clock in BL2 firmware
> + * and is required by the platform to operate correctly.
> + * Until the following condition are met, we need this clock to
> + * be marked as critical:
> + * a) Mark the clock used by a firmware resource, if possible
> + * b) CCF has a clock hand-off mechanism to make the sure the
> + * clock stays on until the proper driver comes along
> + */
> + .flags = CLK_IS_CRITICAL,
> + },
> +};
> +
> +static struct clk_fixed_factor a1_fclk_div3_div = {
> + .mult = 1,
> + .div = 3,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div3_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_fixed_pll.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_fclk_div3 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL0,
> + .bit_idx = 22,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div3",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_fclk_div3_div.hw
> + },
> + .num_parents = 1,
> + /*
> + * This clock is used by APB bus which is set in boot ROM code
> + * and is required by the platform to operate correctly.
> + * About critical, refer to a1_fclk_div2.
> + */
> + .flags = CLK_IS_CRITICAL,
> + },
> +};
> +
> +static struct clk_fixed_factor a1_fclk_div5_div = {
> + .mult = 1,
> + .div = 5,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div5_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_fixed_pll.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_fclk_div5 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL0,
> + .bit_idx = 23,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div5",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_fclk_div5_div.hw
> + },
> + .num_parents = 1,
> + /*
> + * This clock is used by AXI bus which setted in Romcode
> + * and is required by the platform to operate correctly.
> + * About critical, refer to a1_fclk_div2.
> + */
> + .flags = CLK_IS_CRITICAL,
> + },
> +};
> +
> +static struct clk_fixed_factor a1_fclk_div7_div = {
> + .mult = 1,
> + .div = 7,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div7_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_fixed_pll.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_fclk_div7 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL0,
> + .bit_idx = 24,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div7",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_fclk_div7_div.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +/* Array of all clocks provided by this provider */
> +static struct clk_hw_onecell_data a1_pll_hw_onecell_data = {
> + .hws = {
> + [CLKID_FIXED_PLL_DCO] = &a1_fixed_pll_dco.hw,
> + [CLKID_FIXED_PLL] = &a1_fixed_pll.hw,
> + [CLKID_HIFI_PLL] = &a1_hifi_pll.hw,
> + [CLKID_FCLK_DIV2] = &a1_fclk_div2.hw,
> + [CLKID_FCLK_DIV3] = &a1_fclk_div3.hw,
> + [CLKID_FCLK_DIV5] = &a1_fclk_div5.hw,
> + [CLKID_FCLK_DIV7] = &a1_fclk_div7.hw,
> + [CLKID_FCLK_DIV2_DIV] = &a1_fclk_div2_div.hw,
> + [CLKID_FCLK_DIV3_DIV] = &a1_fclk_div3_div.hw,
> + [CLKID_FCLK_DIV5_DIV] = &a1_fclk_div5_div.hw,
> + [CLKID_FCLK_DIV7_DIV] = &a1_fclk_div7_div.hw,
> + [NR_PLL_CLKS] = NULL,
> + },
> + .num = NR_PLL_CLKS,
> +};
> +
> +static struct clk_regmap *const a1_pll_regmaps[] = {
> + &a1_fixed_pll_dco,
> + &a1_fixed_pll,
> + &a1_hifi_pll,
> + &a1_fclk_div2,
> + &a1_fclk_div3,
> + &a1_fclk_div5,
> + &a1_fclk_div7,
> +};
> +
> +static struct regmap_config clkc_regmap_config = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> +};
> +
> +static int meson_a1_pll_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct resource *res;
> + void __iomem *base;
> + struct regmap *map;
> + int ret, i;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +
> + base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
devm_platform_ioremap_resource ?
> +
> + map = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
> + if (IS_ERR(map))
> + return PTR_ERR(map);
> +
> + /* Populate regmap for the regmap backed clocks */
> + for (i = 0; i < ARRAY_SIZE(a1_pll_regmaps); i++)
> + a1_pll_regmaps[i]->map = map;
> +
> + for (i = 0; i < a1_pll_hw_onecell_data.num; i++) {
> + /* array might be sparse */
> + if (!a1_pll_hw_onecell_data.hws[i])
> + continue;
> +
> + ret = devm_clk_hw_register(dev, a1_pll_hw_onecell_data.hws[i]);
> + if (ret) {
> + dev_err(dev, "Clock registration failed\n");
> + return ret;
> + }
> + }
> +
> + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> + &a1_pll_hw_onecell_data);
> +}
> +
> +static const struct of_device_id clkc_match_table[] = {
> + { .compatible = "amlogic,a1-pll-clkc", },
> + {}
> +};
> +
> +static struct platform_driver a1_pll_driver = {
> + .probe = meson_a1_pll_probe,
> + .driver = {
> + .name = "a1-pll-clkc",
> + .of_match_table = clkc_match_table,
> + },
> +};
> +
> +builtin_platform_driver(a1_pll_driver);
> diff --git a/drivers/clk/meson/a1-pll.h b/drivers/clk/meson/a1-pll.h
> new file mode 100644
> index 000000000000..8ded267061ad
> --- /dev/null
> +++ b/drivers/clk/meson/a1-pll.h
> @@ -0,0 +1,56 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
> + */
> +
> +#ifndef __A1_PLL_H
> +#define __A1_PLL_H
> +
> +/* PLL register offset */
> +#define ANACTRL_FIXPLL_CTRL0 0x0
> +#define ANACTRL_FIXPLL_CTRL1 0x4
> +#define ANACTRL_FIXPLL_CTRL2 0x8
> +#define ANACTRL_FIXPLL_CTRL3 0xc
> +#define ANACTRL_FIXPLL_CTRL4 0x10
> +#define ANACTRL_FIXPLL_STS 0x14
> +#define ANACTRL_SYSPLL_CTRL0 0x80
> +#define ANACTRL_SYSPLL_CTRL1 0x84
> +#define ANACTRL_SYSPLL_CTRL2 0x88
> +#define ANACTRL_SYSPLL_CTRL3 0x8c
> +#define ANACTRL_SYSPLL_CTRL4 0x90
> +#define ANACTRL_SYSPLL_STS 0x94
> +#define ANACTRL_HIFIPLL_CTRL0 0xc0
> +#define ANACTRL_HIFIPLL_CTRL1 0xc4
> +#define ANACTRL_HIFIPLL_CTRL2 0xc8
> +#define ANACTRL_HIFIPLL_CTRL3 0xcc
> +#define ANACTRL_HIFIPLL_CTRL4 0xd0
> +#define ANACTRL_HIFIPLL_STS 0xd4
> +#define ANACTRL_AUDDDS_CTRL0 0x100
> +#define ANACTRL_AUDDDS_CTRL1 0x104
> +#define ANACTRL_AUDDDS_CTRL2 0x108
> +#define ANACTRL_AUDDDS_CTRL3 0x10c
> +#define ANACTRL_AUDDDS_CTRL4 0x110
> +#define ANACTRL_AUDDDS_STS 0x114
> +#define ANACTRL_MISCTOP_CTRL0 0x140
> +#define ANACTRL_POR_CNTL 0x188
> +
> +/*
> + * CLKID index values
> + *
> + * These indices are entirely contrived and do not map onto the hardware.
> + * It has now been decided to expose everything by default in the DT header:
> + * include/dt-bindings/clock/a1-pll-clkc.h. Only the clocks ids we don't want
> + * to expose, such as the internal muxes and dividers of composite clocks,
> + * will remain defined here.
> + */
> +#define CLKID_FIXED_PLL_DCO 0
> +#define CLKID_FCLK_DIV2_DIV 2
> +#define CLKID_FCLK_DIV3_DIV 3
> +#define CLKID_FCLK_DIV5_DIV 4
> +#define CLKID_FCLK_DIV7_DIV 5
> +#define NR_PLL_CLKS 11
> +
> +/* include the CLKIDs that have been made part of the DT binding */
> +#include <dt-bindings/clock/a1-pll-clkc.h>
> +
> +#endif /* __A1_PLL_H */
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^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 01/11] dt-bindings: clock: meson: add A1 PLL clock controller bindings
2022-12-02 11:04 ` Jerome Brunet
@ 2022-12-02 11:16 ` Krzysztof Kozlowski
2022-12-02 11:28 ` Dmitry Rokosov
0 siblings, 1 reply; 45+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-02 11:16 UTC (permalink / raw)
To: Jerome Brunet, Dmitry Rokosov, Rob Herring
Cc: devicetree, sboyd, khilman, kernel, robh+dt, martin.blumenstingl,
linux-arm-kernel, jian.hu, linux-kernel, krzysztof.kozlowski+dt,
linux-amlogic, rockosov, mturquette, linux-clk, neil.armstrong
On 02/12/2022 12:04, Jerome Brunet wrote:
>
> On Fri 02 Dec 2022 at 11:39, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>
>> On 02/12/2022 10:51, Dmitry Rokosov wrote:
>>> On Thu, Dec 01, 2022 at 10:10:04PM -0600, Rob Herring wrote:
>>>>
>>>> On Fri, 02 Dec 2022 01:56:53 +0300, Dmitry Rokosov wrote:
>>>>> From: Jian Hu <jian.hu@amlogic.com>
>>>>>
>>>>> Add the documentation to support Amlogic A1 PLL clock driver,
>>>>> and add A1 PLL clock controller bindings.
>>>>>
>>>>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>>>>> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
>>>>> ---
>>>>> .../bindings/clock/amlogic,a1-pll-clkc.yaml | 52 +++++++++++++++++++
>>>>> include/dt-bindings/clock/a1-pll-clkc.h | 16 ++++++
>>>>> 2 files changed, 68 insertions(+)
>>>>> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
>>>>> create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h
>>>>>
>>>>
>>>> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
>>>> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>>>>
>>>> yamllint warnings/errors:
>>>> ./Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml:26:6: [warning] wrong indentation: expected 6 but found 5 (indentation)
>>>>
>>>> dtschema/dtc warnings/errors:
>>>> ./Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml: $id: relative path/filename doesn't match actual path or filename
>>>> expected: http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml#
>>>> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.example.dtb: pll-clock-controller@7c80: reg: [[0, 31872], [0, 396]] is too long
>>>> From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
>>>>
>>>> doc reference errors (make refcheckdocs):
>>>>
>>>> See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20221201225703.6507-2-ddrokosov@sberdevices.ru
>>>>
>>>> The base for the series is generally the latest rc1. A different dependency
>>>> should be noted in *this* patch.
>>>>
>>>> If you already ran 'make dt_binding_check' and didn't see the above
>>>> error(s), then make sure 'yamllint' is installed and dt-schema is up to
>>>> date:
>>>>
>>>> pip3 install dtschema --upgrade
>>>>
>>>> Please check and re-submit after running the above command yourself. Note
>>>> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
>>>> your schema. However, it must be unset to test all examples with your schema.
>>>>
>>>
>>> Please find all fixes of above warnings and errors in the my patch
>>> located at the link:
>>>
>>> https://lore.kernel.org/linux-amlogic/20221201225703.6507-9-ddrokosov@sberdevices.ru/
>>
>> Why? This patch here is broken and it should be fixed. Don't apply
>> broken patches...
>
> Dmitry is ressurecting a series that is several years old and not his to
> begin with.
>
> He was unsure about take the code of somebody else.
> To be fair, he even asked for advice on IRC about to proceed.
>
> Dmitry, as you may have guessed, for next revision, please fix Jian Hu
> original patches in place, not with fixup patches.
>
> If your fixes are minor (not complete rewrite), please keep the original
> author and add your SoB
We never take intentionally wrong patches, e.g. code which does not even
compile, and immediately fix it in next patch.
Can you imagine adding such drivers? Which are broken in the commit they
are added?
So the patchset is old or abandoned, take ownership, add co-developed
etc. Just don't add known broken code.
Best regards,
Krzysztof
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linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 01/11] dt-bindings: clock: meson: add A1 PLL clock controller bindings
2022-12-02 10:42 ` Krzysztof Kozlowski
@ 2022-12-02 11:18 ` Dmitry Rokosov
0 siblings, 0 replies; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-02 11:18 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: neil.armstrong, jbrunet, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl, jian.hu,
kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
>
> Node names should be generic.
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Thank you for the link, will change it in the next version.
>
> > + compatible = "amlogic,a1-pll-clkc";
>
> Use 4 spaces for example indentation.
Good point, I've fixed it in the my patches above. But as you mentioned
in the all changes, I have to squash them....
--
Thank you,
Dmitry
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http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 04/11] clk: meson: a1: add support for Amlogic A1 Peripheral clock driver
2022-12-01 22:56 ` [PATCH v8 04/11] clk: meson: a1: add support for Amlogic A1 Peripheral clock driver Dmitry Rokosov
@ 2022-12-02 11:19 ` Jerome Brunet
2022-12-02 12:33 ` Dmitry Rokosov
0 siblings, 1 reply; 45+ messages in thread
From: Jerome Brunet @ 2022-12-02 11:19 UTC (permalink / raw)
To: Dmitry Rokosov, neil.armstrong, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
On Fri 02 Dec 2022 at 01:56, Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
> From: Jian Hu <jian.hu@amlogic.com>
>
> Add Amlogic Meson A1 peripheral clock driver, it depends
> on the A1 PLL driver.
>
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> ---
> drivers/clk/meson/Kconfig | 9 +
> drivers/clk/meson/Makefile | 1 +
> drivers/clk/meson/a1.c | 2249 ++++++++++++++++++++++++++++++++++++
> drivers/clk/meson/a1.h | 120 ++
> 4 files changed, 2379 insertions(+)
> create mode 100644 drivers/clk/meson/a1.c
> create mode 100644 drivers/clk/meson/a1.h
>
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index ab34662b24f0..bd44ba47200e 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -108,6 +108,15 @@ config COMMON_CLK_A1_PLL
> Support for the PLL clock controller on Amlogic A113L device,
> aka a1. Say Y if you want PLL to work.
>
> +config COMMON_CLK_A1
> + bool
Same as the PLL driver
> + depends on ARCH_MESON
> + select COMMON_CLK_MESON_DUALDIV
> + select COMMON_CLK_MESON_REGMAP
> + help
> + Support for the Peripheral clock controller on Amlogic A113L device,
> + aka a1. Say Y if you want Peripherals to work.
> +
> config COMMON_CLK_G12A
> tristate "G12 and SM1 SoC clock controllers support"
> depends on ARM64
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index 2f17f475a48f..0e6f293c05d4 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -17,6 +17,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o
> obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
> obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
> obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o
> +obj-$(CONFIG_COMMON_CLK_A1) += a1.o
> obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
> obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
> obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
> diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c
> new file mode 100644
> index 000000000000..2cf20ae1db75
> --- /dev/null
> +++ b/drivers/clk/meson/a1.c
> @@ -0,0 +1,2249 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
> + * Author: Jian Hu <jian.hu@amlogic.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include "a1.h"
> +#include "clk-dualdiv.h"
> +#include "clk-regmap.h"
> +
> +static struct clk_regmap a1_xtal_clktree = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = SYS_OSCIN_CTRL,
> + .bit_idx = 0,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "xtal_clktree",
xtal_clktree feel weird.
"xtal_in" maybe ?
> + .ops = &clk_regmap_gate_ro_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xtal",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_xtal_fixpll = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = SYS_OSCIN_CTRL,
> + .bit_idx = 1,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "xtal_fixpll",
same here, this is not a crystal.
It is the fixpll input gate, what about "fixpll_in"
Same bellow - you get the idea ...
> + .ops = &clk_regmap_gate_ro_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xtal",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_xtal_usb_phy = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = SYS_OSCIN_CTRL,
> + .bit_idx = 2,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "xtal_usb_phy",
> + .ops = &clk_regmap_gate_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xtal",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_xtal_usb_ctrl = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = SYS_OSCIN_CTRL,
> + .bit_idx = 3,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "xtal_usb_ctrl",
> + .ops = &clk_regmap_gate_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xtal",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_xtal_hifipll = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = SYS_OSCIN_CTRL,
> + .bit_idx = 4,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "xtal_hifipll",
> + .ops = &clk_regmap_gate_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xtal",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_xtal_syspll = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = SYS_OSCIN_CTRL,
> + .bit_idx = 5,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "xtal_syspll",
> + .ops = &clk_regmap_gate_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xtal",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_xtal_dds = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = SYS_OSCIN_CTRL,
> + .bit_idx = 6,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "xtal_dds",
> + .ops = &clk_regmap_gate_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xtal",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static const struct clk_parent_data sys_clk_parents[] = {
> + { .fw_name = "xtal" },
> + { .fw_name = "fclk_div2" },
> + { .fw_name = "fclk_div3" },
> + { .fw_name = "fclk_div5" },
> +};
> +
> +static struct clk_regmap a1_sys_b_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = SYS_CLK_CTRL0,
> + .mask = 0x7,
> + .shift = 26,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "sys_b_sel",
> + .ops = &clk_regmap_mux_ro_ops,
> + .parent_data = sys_clk_parents,
> + .num_parents = ARRAY_SIZE(sys_clk_parents),
> + },
> +};
> +
> +static struct clk_regmap a1_sys_b_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = SYS_CLK_CTRL0,
> + .shift = 16,
> + .width = 10,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "sys_b_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_sys_b_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_sys_b = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = SYS_CLK_CTRL0,
> + .bit_idx = 29,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "sys_b",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_sys_b_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_sys_a_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = SYS_CLK_CTRL0,
> + .mask = 0x7,
> + .shift = 10,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "sys_a_sel",
> + .ops = &clk_regmap_mux_ro_ops,
> + .parent_data = sys_clk_parents,
> + .num_parents = ARRAY_SIZE(sys_clk_parents),
> + },
> +};
> +
> +static struct clk_regmap a1_sys_a_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = SYS_CLK_CTRL0,
> + .shift = 0,
> + .width = 10,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "sys_a_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_sys_a_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_sys_a = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = SYS_CLK_CTRL0,
> + .bit_idx = 13,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "sys_a",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_sys_a_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_sys_clk = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = SYS_CLK_CTRL0,
> + .mask = 0x1,
> + .shift = 31,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "sys_clk",
> + .ops = &clk_regmap_mux_ro_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_sys_a.hw, &a1_sys_b.hw,
> + },
> + .num_parents = 2,
> + /*
> + * This clock is used by APB bus which is set in boot ROM code
> + * and is required by the platform to operate correctly.
> + * Until the following condition are met, we need this clock to
> + * be marked as critical:
> + * a) Mark the clock used by a firmware resource, if possible
> + * b) CCF has a clock hand-off mechanism to make the sure the
> + * clock stays on until the proper driver comes along
> + */
> + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> + },
> +};
> +
> +static struct clk_regmap a1_rtc_32k_clkin = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = RTC_BY_OSCIN_CTRL0,
> + .bit_idx = 31,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "rtc_32k_clkin",
> + .ops = &clk_regmap_gate_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xtal",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static const struct meson_clk_dualdiv_param a1_32k_div_table[] = {
> + {
> + .dual = 1,
> + .n1 = 733,
> + .m1 = 8,
> + .n2 = 732,
> + .m2 = 11,
> + },
> + {}
> +};
> +
> +static struct clk_regmap a1_rtc_32k_div = {
> + .data = &(struct meson_clk_dualdiv_data){
> + .n1 = {
> + .reg_off = RTC_BY_OSCIN_CTRL0,
> + .shift = 0,
> + .width = 12,
> + },
> + .n2 = {
> + .reg_off = RTC_BY_OSCIN_CTRL0,
> + .shift = 12,
> + .width = 12,
> + },
> + .m1 = {
> + .reg_off = RTC_BY_OSCIN_CTRL1,
> + .shift = 0,
> + .width = 12,
> + },
> + .m2 = {
> + .reg_off = RTC_BY_OSCIN_CTRL1,
> + .shift = 12,
> + .width = 12,
> + },
> + .dual = {
> + .reg_off = RTC_BY_OSCIN_CTRL0,
> + .shift = 28,
> + .width = 1,
> + },
> + .table = a1_32k_div_table,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "rtc_32k_div",
> + .ops = &meson_clk_dualdiv_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_rtc_32k_clkin.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_rtc_32k_xtal = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = RTC_BY_OSCIN_CTRL1,
> + .bit_idx = 24,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "rtc_32k_xtal",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_rtc_32k_clkin.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_rtc_32k_sel = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = RTC_CTRL,
> + .mask = 0x3,
> + .shift = 0,
> + .flags = CLK_MUX_ROUND_CLOSEST,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "rtc_32k_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_rtc_32k_xtal.hw,
> + &a1_rtc_32k_div.hw,
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +struct clk_regmap a1_rtc_clk = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = RTC_BY_OSCIN_CTRL0,
> + .bit_idx = 30,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "rtc_clk",
Everytime there is an "_clk" suffix, you can remove it.
In this driver, we know we are going to get clocks ;)
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_rtc_32k_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static u32 mux_table_dsp_ab[] = { 0, 1, 2, 3, 4, 7 };
> +static const struct clk_parent_data dsp_ab_clk_parent_data[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "fclk_div2", },
> + { .fw_name = "fclk_div3", },
> + { .fw_name = "fclk_div5", },
> + { .fw_name = "hifi_pll", },
> + { .hw = &a1_rtc_clk.hw },
> +};
> +
> +static struct clk_regmap a1_dspa_a_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = DSPA_CLK_CTRL0,
> + .mask = 0x7,
> + .shift = 10,
> + .table = mux_table_dsp_ab,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dspa_a_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = dsp_ab_clk_parent_data,
> + .num_parents = ARRAY_SIZE(dsp_ab_clk_parent_data),
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_dspa_a_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = DSPA_CLK_CTRL0,
> + .shift = 0,
> + .width = 10,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dspa_a_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_dspa_a_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_dspa_a = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = DSPA_CLK_CTRL0,
> + .bit_idx = 13,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "dspa_a",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_dspa_a_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_dspa_b_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = DSPA_CLK_CTRL0,
> + .mask = 0x7,
> + .shift = 26,
> + .table = mux_table_dsp_ab,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dspa_b_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = dsp_ab_clk_parent_data,
> + .num_parents = ARRAY_SIZE(dsp_ab_clk_parent_data),
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_dspa_b_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = DSPA_CLK_CTRL0,
> + .shift = 16,
> + .width = 10,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dspa_b_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_dspa_b_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_dspa_b = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = DSPA_CLK_CTRL0,
> + .bit_idx = 29,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "dspa_b",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_dspa_b_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_dspa_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = DSPA_CLK_CTRL0,
> + .mask = 0x1,
> + .shift = 15,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dspa_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .hw = &a1_dspa_a.hw },
> + { .hw = &a1_dspa_b.hw },
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_dspa_en = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = DSPA_CLK_EN,
> + .bit_idx = 1,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "dspa_en",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_dspa_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
Maybe as a 2nd step, but I suspect a "CLK_SET_RATE_NOREPARENT" is going to
be needed here at some point.
> + },
> +};
> +
> +static struct clk_regmap a1_dspa_en_nic = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = DSPA_CLK_EN,
> + .bit_idx = 0,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "dspa_en_nic",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_dspa_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_dspb_a_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = DSPB_CLK_CTRL0,
> + .mask = 0x7,
> + .shift = 10,
> + .table = mux_table_dsp_ab,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dspb_a_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = dsp_ab_clk_parent_data,
> + .num_parents = ARRAY_SIZE(dsp_ab_clk_parent_data),
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_dspb_a_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = DSPB_CLK_CTRL0,
> + .shift = 0,
> + .width = 10,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dspb_a_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_dspb_a_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_dspb_a = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = DSPB_CLK_CTRL0,
> + .bit_idx = 13,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "dspb_a",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_dspb_a_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Any chance we can remove this CLK_IGNORE_UNUSED, or comment why it is
needed ?
> + },
> +};
> +
> +static struct clk_regmap a1_dspb_b_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = DSPB_CLK_CTRL0,
> + .mask = 0x7,
> + .shift = 26,
> + .table = mux_table_dsp_ab,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dspb_b_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = dsp_ab_clk_parent_data,
> + .num_parents = ARRAY_SIZE(dsp_ab_clk_parent_data),
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_dspb_b_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = DSPB_CLK_CTRL0,
> + .shift = 16,
> + .width = 10,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dspb_b_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_dspb_b_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_dspb_b = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = DSPB_CLK_CTRL0,
> + .bit_idx = 29,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "dspb_b",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_dspb_b_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Same and for the other ones
> + },
> +};
> +
> +static struct clk_regmap a1_dspb_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = DSPB_CLK_CTRL0,
> + .mask = 0x1,
> + .shift = 15,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dspb_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_dspb_a.hw, &a1_dspb_b.hw,
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_dspb_en = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = DSPB_CLK_EN,
> + .bit_idx = 1,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "dspb_en",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_dspb_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> + },
> +};
> +
> +static struct clk_regmap a1_dspb_en_nic = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = DSPB_CLK_EN,
> + .bit_idx = 0,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "dspb_en_nic",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_dspb_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> + },
> +};
> +
> +static struct clk_regmap a1_24m = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = CLK12_24_CTRL,
> + .bit_idx = 11,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "24m",
> + .ops = &clk_regmap_gate_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xtal",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor a1_24m_div2 = {
> + .mult = 1,
> + .div = 2,
> + .hw.init = &(struct clk_init_data){
> + .name = "24m_div2",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_24m.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_12m = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = CLK12_24_CTRL,
> + .bit_idx = 10,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "12m",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_24m_div2.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_fclk_div2_divn_pre = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = CLK12_24_CTRL,
> + .shift = 0,
> + .width = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div2_divn_pre",
> + .ops = &clk_regmap_divider_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "fclk_div2",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_fclk_div2_divn = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = CLK12_24_CTRL,
> + .bit_idx = 12,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div2_divn",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_fclk_div2_divn_pre.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +/*
> + * the index 2 is sys_pll_div16, it will complete in the CPU clock,
complete or compete ?
> + * the index 4 is the clock measurement source, it relies on
> + * the clock measurement register configuration.
> + */
> +static u32 gen_clk_table[] = { 0, 1, 3, 5, 6, 7, 8 };
> +static const struct clk_parent_data gen_clk_parent_data[] = {
> + { .fw_name = "xtal", },
> + { .hw = &a1_rtc_clk.hw },
> + { .fw_name = "hifi_pll", },
> + { .fw_name = "fclk_div2", },
> + { .fw_name = "fclk_div3", },
> + { .fw_name = "fclk_div5", },
> + { .fw_name = "fclk_div7", },
> +};
> +
> +static struct clk_regmap a1_gen_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = GEN_CLK_CTRL,
> + .mask = 0xf,
> + .shift = 12,
> + .table = gen_clk_table,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "gen_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = gen_clk_parent_data,
> + .num_parents = ARRAY_SIZE(gen_clk_parent_data),
> + },
> +};
> +
> +static struct clk_regmap a1_gen_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = GEN_CLK_CTRL,
> + .shift = 0,
> + .width = 11,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "gen_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_gen_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_gen = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = GEN_CLK_CTRL,
> + .bit_idx = 11,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "gen",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_gen_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_saradc_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = SAR_ADC_CLK_CTRL,
> + .mask = 0x1,
> + .shift = 9,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "saradc_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .fw_name = "xtal", },
> + { .hw = &a1_sys_clk.hw, },
> + },
> + .num_parents = 2,
> + },
> +};
> +
> +static struct clk_regmap a1_saradc_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = SAR_ADC_CLK_CTRL,
> + .shift = 0,
> + .width = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "saradc_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_saradc_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_saradc_clk = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = SAR_ADC_CLK_CTRL,
> + .bit_idx = 8,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "saradc_clk",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_saradc_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_pwm_a_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = PWM_CLK_AB_CTRL,
> + .mask = 0x1,
> + .shift = 9,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "pwm_a_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .fw_name = "xtal", },
> + { .hw = &a1_sys_clk.hw, },
> + },
> + .num_parents = 2,
> + },
> +};
> +
> +static struct clk_regmap a1_pwm_a_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = PWM_CLK_AB_CTRL,
> + .shift = 0,
> + .width = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "pwm_a_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_pwm_a_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_pwm_a = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = PWM_CLK_AB_CTRL,
> + .bit_idx = 8,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "pwm_a",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_pwm_a_div.hw
> + },
> + .num_parents = 1,
> + /*
> + * The CPU working voltage is controlled by pwm_a
> + * in BL2 firmware. The clock is required by the platform
> + * to operate correctly. Add the CLK_IS_CRITICAL flag to
> + * avoid changing at runtime.
> + * About critical, refer to a1_sys_clk
> + */
> + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> + },
> +};
> +
> +static struct clk_regmap a1_pwm_b_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = PWM_CLK_AB_CTRL,
> + .mask = 0x1,
> + .shift = 25,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "pwm_b_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .fw_name = "xtal", },
> + { .hw = &a1_sys_clk.hw, },
> + },
> + .num_parents = 2,
> + },
> +};
> +
> +static struct clk_regmap a1_pwm_b_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = PWM_CLK_AB_CTRL,
> + .shift = 16,
> + .width = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "pwm_b_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_pwm_b_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_pwm_b = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = PWM_CLK_AB_CTRL,
> + .bit_idx = 24,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "pwm_b",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_pwm_b_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_pwm_c_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = PWM_CLK_CD_CTRL,
> + .mask = 0x1,
> + .shift = 9,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "pwm_c_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .fw_name = "xtal", },
> + { .hw = &a1_sys_clk.hw, },
> + },
> + .num_parents = 2,
> + },
> +};
> +
> +static struct clk_regmap a1_pwm_c_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = PWM_CLK_CD_CTRL,
> + .shift = 0,
> + .width = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "pwm_c_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_pwm_c_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_pwm_c = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = PWM_CLK_CD_CTRL,
> + .bit_idx = 8,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "pwm_c",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_pwm_c_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_pwm_d_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = PWM_CLK_CD_CTRL,
> + .mask = 0x1,
> + .shift = 25,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "pwm_d_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .fw_name = "xtal", },
> + { .hw = &a1_sys_clk.hw, },
> + },
> + .num_parents = 2,
> + },
> +};
> +
> +static struct clk_regmap a1_pwm_d_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = PWM_CLK_CD_CTRL,
> + .shift = 16,
> + .width = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "pwm_d_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_pwm_d_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_pwm_d = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = PWM_CLK_CD_CTRL,
> + .bit_idx = 24,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "pwm_d",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_pwm_d_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static const struct clk_parent_data pwm_ef_parent_data[] = {
> + { .fw_name = "xtal", },
> + { .hw = &a1_sys_clk.hw },
> + { .fw_name = "fclk_div5", },
> + { .hw = &a1_rtc_clk.hw },
> +};
> +
> +static struct clk_regmap a1_pwm_e_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = PWM_CLK_EF_CTRL,
> + .mask = 0x3,
> + .shift = 9,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "pwm_e_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = pwm_ef_parent_data,
> + .num_parents = ARRAY_SIZE(pwm_ef_parent_data),
> + },
> +};
> +
> +static struct clk_regmap a1_pwm_e_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = PWM_CLK_EF_CTRL,
> + .shift = 0,
> + .width = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "pwm_e_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_pwm_e_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_pwm_e = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = PWM_CLK_EF_CTRL,
> + .bit_idx = 8,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "pwm_e",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_pwm_e_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_pwm_f_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = PWM_CLK_EF_CTRL,
> + .mask = 0x3,
> + .shift = 25,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "pwm_f_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = pwm_ef_parent_data,
> + .num_parents = ARRAY_SIZE(pwm_ef_parent_data),
> + },
> +};
> +
> +static struct clk_regmap a1_pwm_f_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = PWM_CLK_EF_CTRL,
> + .shift = 16,
> + .width = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "pwm_f_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_pwm_f_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_pwm_f = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = PWM_CLK_EF_CTRL,
> + .bit_idx = 24,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "pwm_f",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_pwm_f_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +/*
> + * spicc clk
> + * fdiv2 |\ |\ _____
> + * ---------| |---DIV--| | | | spicc out
> + * ---------| | | |-----|GATE |---------
> + * ..... |/ | / |_____|
> + * --------------------|/
> + * 24M
> + */
> +static const struct clk_parent_data spicc_parents[] = {
> + { .fw_name = "fclk_div2"},
> + { .fw_name = "fclk_div3"},
> + { .fw_name = "fclk_div5"},
> + { .fw_name = "hifi_pll" },
> +};
> +
> +static struct clk_regmap a1_spicc_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = SPICC_CLK_CTRL,
> + .mask = 0x3,
> + .shift = 9,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "spicc_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = spicc_parents,
> + .num_parents = 4,
> + },
> +};
> +
> +static struct clk_regmap a1_spicc_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = SPICC_CLK_CTRL,
> + .shift = 0,
> + .width = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "spicc_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_spicc_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_spicc_sel2 = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = SPICC_CLK_CTRL,
> + .mask = 0x1,
> + .shift = 15,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "spicc_sel2",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .hw = &a1_spicc_div.hw },
> + { .fw_name = "xtal", },
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_spicc = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = SPICC_CLK_CTRL,
> + .bit_idx = 8,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "spicc",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_spicc_sel2.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_ts_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = TS_CLK_CTRL,
> + .shift = 0,
> + .width = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "ts_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xtal",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_ts = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = TS_CLK_CTRL,
> + .bit_idx = 8,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "ts",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_ts_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_spifc_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = SPIFC_CLK_CTRL,
> + .mask = 0x3,
> + .shift = 9,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "spifc_sel",
> + .ops = &clk_regmap_mux_ops,
> + /* the same parent with spicc */
> + .parent_data = spicc_parents,
> + .num_parents = 4,
> + },
> +};
> +
> +static struct clk_regmap a1_spifc_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = SPIFC_CLK_CTRL,
> + .shift = 0,
> + .width = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "spifc_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_spifc_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_spifc_sel2 = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = SPIFC_CLK_CTRL,
> + .mask = 0x1,
> + .shift = 15,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "spifc_sel2",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .hw = &a1_spifc_div.hw },
> + { .fw_name = "xtal", },
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_spifc = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = SPIFC_CLK_CTRL,
> + .bit_idx = 8,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "spifc",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_spifc_sel2.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static const struct clk_parent_data usb_bus_parent_data[] = {
> + { .fw_name = "xtal", },
> + { .hw = &a1_sys_clk.hw },
> + { .fw_name = "fclk_div3", },
> + { .fw_name = "fclk_div5", },
> +};
> +
> +static struct clk_regmap a1_usb_bus_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = USB_BUSCLK_CTRL,
> + .mask = 0x3,
> + .shift = 9,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "usb_bus_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = usb_bus_parent_data,
> + .num_parents = ARRAY_SIZE(usb_bus_parent_data),
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_usb_bus_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = USB_BUSCLK_CTRL,
> + .shift = 0,
> + .width = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "usb_bus_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_usb_bus_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_usb_bus = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = USB_BUSCLK_CTRL,
> + .bit_idx = 8,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "usb_bus",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_usb_bus_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static const struct clk_parent_data sd_emmc_parents[] = {
> + { .fw_name = "fclk_div2", },
> + { .fw_name = "fclk_div3", },
> + { .fw_name = "fclk_div5", },
> + { .fw_name = "hifi_pll", },
> +};
> +
> +static struct clk_regmap a1_sd_emmc_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = SD_EMMC_CLK_CTRL,
> + .mask = 0x3,
> + .shift = 9,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "sd_emmc_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = sd_emmc_parents,
> + .num_parents = 4,
> + },
> +};
> +
> +static struct clk_regmap a1_sd_emmc_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = SD_EMMC_CLK_CTRL,
> + .shift = 0,
> + .width = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "sd_emmc_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_sd_emmc_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_sd_emmc_sel2 = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = SD_EMMC_CLK_CTRL,
> + .mask = 0x1,
> + .shift = 15,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "sd_emmc_sel2",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .hw = &a1_sd_emmc_div.hw },
> + { .fw_name = "xtal", },
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_sd_emmc = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = SD_EMMC_CLK_CTRL,
> + .bit_idx = 8,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "sd_emmc",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_sd_emmc_sel2.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_psram_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = PSRAM_CLK_CTRL,
> + .mask = 0x3,
> + .shift = 9,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "psram_sel",
> + .ops = &clk_regmap_mux_ops,
> + /* the same parent with sd_emmc */
> + .parent_data = sd_emmc_parents,
> + .num_parents = 4,
> + },
> +};
> +
> +static struct clk_regmap a1_psram_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = PSRAM_CLK_CTRL,
> + .shift = 0,
> + .width = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "psram_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_psram_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_psram_sel2 = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = PSRAM_CLK_CTRL,
> + .mask = 0x1,
> + .shift = 15,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "psram_sel2",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .hw = &a1_psram_div.hw },
> + { .fw_name = "xtal", },
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_psram = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = PSRAM_CLK_CTRL,
> + .bit_idx = 8,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "psram",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_psram_sel2.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_dmc_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = DMC_CLK_CTRL,
> + .mask = 0x3,
> + .shift = 9,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dmc_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = sd_emmc_parents,
> + .num_parents = 4,
> + },
> +};
> +
> +static struct clk_regmap a1_dmc_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = DMC_CLK_CTRL,
> + .shift = 0,
> + .width = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dmc_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_dmc_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_dmc_sel2 = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = DMC_CLK_CTRL,
> + .mask = 0x1,
> + .shift = 15,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "dmc_sel2",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .hw = &a1_dmc_div.hw },
> + { .fw_name = "xtal", },
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_dmc = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = DMC_CLK_CTRL,
> + .bit_idx = 8,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "dmc",
> + .ops = &clk_regmap_gate_ro_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_dmc_sel2.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_ceca_32k_clkin = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = CECA_CLK_CTRL0,
> + .bit_idx = 31,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "ceca_32k_clkin",
> + .ops = &clk_regmap_gate_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xtal",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_ceca_32k_div = {
> + .data = &(struct meson_clk_dualdiv_data){
> + .n1 = {
> + .reg_off = CECA_CLK_CTRL0,
> + .shift = 0,
> + .width = 12,
> + },
> + .n2 = {
> + .reg_off = CECA_CLK_CTRL0,
> + .shift = 12,
> + .width = 12,
> + },
> + .m1 = {
> + .reg_off = CECA_CLK_CTRL1,
> + .shift = 0,
> + .width = 12,
> + },
> + .m2 = {
> + .reg_off = CECA_CLK_CTRL1,
> + .shift = 12,
> + .width = 12,
> + },
> + .dual = {
> + .reg_off = CECA_CLK_CTRL0,
> + .shift = 28,
> + .width = 1,
> + },
> + .table = a1_32k_div_table,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "ceca_32k_div",
> + .ops = &meson_clk_dualdiv_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_ceca_32k_clkin.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_ceca_32k_sel_pre = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = CECA_CLK_CTRL1,
> + .mask = 0x1,
> + .shift = 24,
> + .flags = CLK_MUX_ROUND_CLOSEST,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "ceca_32k_sel_pre",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_ceca_32k_div.hw,
> + &a1_ceca_32k_clkin.hw,
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_ceca_32k_sel = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = CECA_CLK_CTRL1,
> + .mask = 0x1,
> + .shift = 31,
> + .flags = CLK_MUX_ROUND_CLOSEST,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "ceca_32k_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_ceca_32k_sel_pre.hw,
> + &a1_rtc_clk.hw,
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_ceca_32k_clkout = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = CECA_CLK_CTRL0,
> + .bit_idx = 30,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "ceca_32k_clkout",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_ceca_32k_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_cecb_32k_clkin = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = CECB_CLK_CTRL0,
> + .bit_idx = 31,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "cecb_32k_clkin",
> + .ops = &clk_regmap_gate_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xtal",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_cecb_32k_div = {
> + .data = &(struct meson_clk_dualdiv_data){
> + .n1 = {
> + .reg_off = CECB_CLK_CTRL0,
> + .shift = 0,
> + .width = 12,
> + },
> + .n2 = {
> + .reg_off = CECB_CLK_CTRL0,
> + .shift = 12,
> + .width = 12,
> + },
> + .m1 = {
> + .reg_off = CECB_CLK_CTRL1,
> + .shift = 0,
> + .width = 12,
> + },
> + .m2 = {
> + .reg_off = CECB_CLK_CTRL1,
> + .shift = 12,
> + .width = 12,
> + },
> + .dual = {
> + .reg_off = CECB_CLK_CTRL0,
> + .shift = 28,
> + .width = 1,
> + },
> + .table = a1_32k_div_table,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "cecb_32k_div",
> + .ops = &meson_clk_dualdiv_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_cecb_32k_clkin.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_cecb_32k_sel_pre = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = CECB_CLK_CTRL1,
> + .mask = 0x1,
> + .shift = 24,
> + .flags = CLK_MUX_ROUND_CLOSEST,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "cecb_32k_sel_pre",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_cecb_32k_div.hw,
> + &a1_cecb_32k_clkin.hw,
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_cecb_32k_sel = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = CECB_CLK_CTRL1,
> + .mask = 0x1,
> + .shift = 31,
> + .flags = CLK_MUX_ROUND_CLOSEST,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "cecb_32k_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_cecb_32k_sel_pre.hw,
> + &a1_rtc_clk.hw,
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap a1_cecb_32k_clkout = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = CECB_CLK_CTRL0,
> + .bit_idx = 30,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "cecb_32k_clkout",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_cecb_32k_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +#define MESON_GATE(_name, _reg, _bit) \
> + MESON_PCLK(_name, _reg, _bit, &a1_sys_clk.hw)
> +
> +static MESON_GATE(a1_clk_tree, SYS_CLK_EN0, 0);
> +static MESON_GATE(a1_reset_ctrl, SYS_CLK_EN0, 1);
> +static MESON_GATE(a1_analog_ctrl, SYS_CLK_EN0, 2);
> +static MESON_GATE(a1_pwr_ctrl, SYS_CLK_EN0, 3);
> +static MESON_GATE(a1_pad_ctrl, SYS_CLK_EN0, 4);
> +static MESON_GATE(a1_sys_ctrl, SYS_CLK_EN0, 5);
> +static MESON_GATE(a1_temp_sensor, SYS_CLK_EN0, 6);
> +static MESON_GATE(a1_am2axi_dev, SYS_CLK_EN0, 7);
> +static MESON_GATE(a1_spicc_b, SYS_CLK_EN0, 8);
> +static MESON_GATE(a1_spicc_a, SYS_CLK_EN0, 9);
> +static MESON_GATE(a1_clk_msr, SYS_CLK_EN0, 10);
> +static MESON_GATE(a1_audio, SYS_CLK_EN0, 11);
> +static MESON_GATE(a1_jtag_ctrl, SYS_CLK_EN0, 12);
> +static MESON_GATE(a1_saradc, SYS_CLK_EN0, 13);
> +static MESON_GATE(a1_pwm_ef, SYS_CLK_EN0, 14);
> +static MESON_GATE(a1_pwm_cd, SYS_CLK_EN0, 15);
> +static MESON_GATE(a1_pwm_ab, SYS_CLK_EN0, 16);
> +static MESON_GATE(a1_cec, SYS_CLK_EN0, 17);
> +static MESON_GATE(a1_i2c_s, SYS_CLK_EN0, 18);
> +static MESON_GATE(a1_ir_ctrl, SYS_CLK_EN0, 19);
> +static MESON_GATE(a1_i2c_m_d, SYS_CLK_EN0, 20);
> +static MESON_GATE(a1_i2c_m_c, SYS_CLK_EN0, 21);
> +static MESON_GATE(a1_i2c_m_b, SYS_CLK_EN0, 22);
> +static MESON_GATE(a1_i2c_m_a, SYS_CLK_EN0, 23);
> +static MESON_GATE(a1_acodec, SYS_CLK_EN0, 24);
> +static MESON_GATE(a1_otp, SYS_CLK_EN0, 25);
> +static MESON_GATE(a1_sd_emmc_a, SYS_CLK_EN0, 26);
> +static MESON_GATE(a1_usb_phy, SYS_CLK_EN0, 27);
> +static MESON_GATE(a1_usb_ctrl, SYS_CLK_EN0, 28);
> +static MESON_GATE(a1_sys_dspb, SYS_CLK_EN0, 29);
> +static MESON_GATE(a1_sys_dspa, SYS_CLK_EN0, 30);
> +static MESON_GATE(a1_dma, SYS_CLK_EN0, 31);
> +static MESON_GATE(a1_irq_ctrl, SYS_CLK_EN1, 0);
> +static MESON_GATE(a1_nic, SYS_CLK_EN1, 1);
> +static MESON_GATE(a1_gic, SYS_CLK_EN1, 2);
> +static MESON_GATE(a1_uart_c, SYS_CLK_EN1, 3);
> +static MESON_GATE(a1_uart_b, SYS_CLK_EN1, 4);
> +static MESON_GATE(a1_uart_a, SYS_CLK_EN1, 5);
> +static MESON_GATE(a1_sys_psram, SYS_CLK_EN1, 6);
> +static MESON_GATE(a1_rsa, SYS_CLK_EN1, 8);
> +static MESON_GATE(a1_coresight, SYS_CLK_EN1, 9);
> +static MESON_GATE(a1_am2axi_vad, AXI_CLK_EN, 0);
> +static MESON_GATE(a1_audio_vad, AXI_CLK_EN, 1);
> +static MESON_GATE(a1_axi_dmc, AXI_CLK_EN, 3);
> +static MESON_GATE(a1_axi_psram, AXI_CLK_EN, 4);
> +static MESON_GATE(a1_ramb, AXI_CLK_EN, 5);
> +static MESON_GATE(a1_rama, AXI_CLK_EN, 6);
> +static MESON_GATE(a1_axi_spifc, AXI_CLK_EN, 7);
> +static MESON_GATE(a1_axi_nic, AXI_CLK_EN, 8);
> +static MESON_GATE(a1_axi_dma, AXI_CLK_EN, 9);
> +static MESON_GATE(a1_cpu_ctrl, AXI_CLK_EN, 10);
> +static MESON_GATE(a1_rom, AXI_CLK_EN, 11);
> +static MESON_GATE(a1_prod_i2c, AXI_CLK_EN, 12);
> +
> +/* Array of all clocks provided by this provider */
> +static struct clk_hw_onecell_data a1_periphs_hw_onecell_data = {
> + .hws = {
> + [CLKID_SYS_B_SEL] = &a1_sys_b_sel.hw,
> + [CLKID_SYS_B_DIV] = &a1_sys_b_div.hw,
> + [CLKID_SYS_B] = &a1_sys_b.hw,
> + [CLKID_SYS_A_SEL] = &a1_sys_a_sel.hw,
> + [CLKID_SYS_A_DIV] = &a1_sys_a_div.hw,
> + [CLKID_SYS_A] = &a1_sys_a.hw,
> + [CLKID_SYS_CLK] = &a1_sys_clk.hw,
> + [CLKID_XTAL_CLKTREE] = &a1_xtal_clktree.hw,
> + [CLKID_XTAL_FIXPLL] = &a1_xtal_fixpll.hw,
> + [CLKID_XTAL_USB_PHY] = &a1_xtal_usb_phy.hw,
> + [CLKID_XTAL_USB_CTRL] = &a1_xtal_usb_ctrl.hw,
> + [CLKID_XTAL_HIFIPLL] = &a1_xtal_hifipll.hw,
> + [CLKID_XTAL_SYSPLL] = &a1_xtal_syspll.hw,
> + [CLKID_XTAL_DDS] = &a1_xtal_dds.hw,
> + [CLKID_CLKTREE] = &a1_clk_tree.hw,
> + [CLKID_RESET_CTRL] = &a1_reset_ctrl.hw,
> + [CLKID_ANALOG_CTRL] = &a1_analog_ctrl.hw,
> + [CLKID_PWR_CTRL] = &a1_pwr_ctrl.hw,
> + [CLKID_PAD_CTRL] = &a1_pad_ctrl.hw,
> + [CLKID_SYS_CTRL] = &a1_sys_ctrl.hw,
> + [CLKID_TEMP_SENSOR] = &a1_temp_sensor.hw,
> + [CLKID_AM2AXI_DIV] = &a1_am2axi_dev.hw,
> + [CLKID_SPICC_B] = &a1_spicc_b.hw,
> + [CLKID_SPICC_A] = &a1_spicc_a.hw,
> + [CLKID_CLK_MSR] = &a1_clk_msr.hw,
> + [CLKID_AUDIO] = &a1_audio.hw,
> + [CLKID_JTAG_CTRL] = &a1_jtag_ctrl.hw,
> + [CLKID_SARADC] = &a1_saradc.hw,
> + [CLKID_PWM_EF] = &a1_pwm_ef.hw,
> + [CLKID_PWM_CD] = &a1_pwm_cd.hw,
> + [CLKID_PWM_AB] = &a1_pwm_ab.hw,
> + [CLKID_CEC] = &a1_cec.hw,
> + [CLKID_I2C_S] = &a1_i2c_s.hw,
> + [CLKID_IR_CTRL] = &a1_ir_ctrl.hw,
> + [CLKID_I2C_M_D] = &a1_i2c_m_d.hw,
> + [CLKID_I2C_M_C] = &a1_i2c_m_c.hw,
> + [CLKID_I2C_M_B] = &a1_i2c_m_b.hw,
> + [CLKID_I2C_M_A] = &a1_i2c_m_a.hw,
> + [CLKID_ACODEC] = &a1_acodec.hw,
> + [CLKID_OTP] = &a1_otp.hw,
> + [CLKID_SD_EMMC_A] = &a1_sd_emmc_a.hw,
> + [CLKID_USB_PHY] = &a1_usb_phy.hw,
> + [CLKID_USB_CTRL] = &a1_usb_ctrl.hw,
> + [CLKID_SYS_DSPB] = &a1_sys_dspb.hw,
> + [CLKID_SYS_DSPA] = &a1_sys_dspa.hw,
> + [CLKID_DMA] = &a1_dma.hw,
> + [CLKID_IRQ_CTRL] = &a1_irq_ctrl.hw,
> + [CLKID_NIC] = &a1_nic.hw,
> + [CLKID_GIC] = &a1_gic.hw,
> + [CLKID_UART_C] = &a1_uart_c.hw,
> + [CLKID_UART_B] = &a1_uart_b.hw,
> + [CLKID_UART_A] = &a1_uart_a.hw,
> + [CLKID_SYS_PSRAM] = &a1_sys_psram.hw,
> + [CLKID_RSA] = &a1_rsa.hw,
> + [CLKID_CORESIGHT] = &a1_coresight.hw,
> + [CLKID_AM2AXI_VAD] = &a1_am2axi_vad.hw,
> + [CLKID_AUDIO_VAD] = &a1_audio_vad.hw,
> + [CLKID_AXI_DMC] = &a1_axi_dmc.hw,
> + [CLKID_AXI_PSRAM] = &a1_axi_psram.hw,
> + [CLKID_RAMB] = &a1_ramb.hw,
> + [CLKID_RAMA] = &a1_rama.hw,
> + [CLKID_AXI_SPIFC] = &a1_axi_spifc.hw,
> + [CLKID_AXI_NIC] = &a1_axi_nic.hw,
> + [CLKID_AXI_DMA] = &a1_axi_dma.hw,
> + [CLKID_CPU_CTRL] = &a1_cpu_ctrl.hw,
> + [CLKID_ROM] = &a1_rom.hw,
> + [CLKID_PROC_I2C] = &a1_prod_i2c.hw,
> + [CLKID_DSPA_A_SEL] = &a1_dspa_a_sel.hw,
> + [CLKID_DSPA_A_DIV] = &a1_dspa_a_div.hw,
> + [CLKID_DSPA_A] = &a1_dspa_a.hw,
> + [CLKID_DSPA_B_SEL] = &a1_dspa_b_sel.hw,
> + [CLKID_DSPA_B_DIV] = &a1_dspa_b_div.hw,
> + [CLKID_DSPA_B] = &a1_dspa_b.hw,
> + [CLKID_DSPA_SEL] = &a1_dspa_sel.hw,
> + [CLKID_DSPB_A_SEL] = &a1_dspb_a_sel.hw,
> + [CLKID_DSPB_A_DIV] = &a1_dspb_a_div.hw,
> + [CLKID_DSPB_A] = &a1_dspb_a.hw,
> + [CLKID_DSPB_B_SEL] = &a1_dspb_b_sel.hw,
> + [CLKID_DSPB_B_DIV] = &a1_dspb_b_div.hw,
> + [CLKID_DSPB_B] = &a1_dspb_b.hw,
> + [CLKID_DSPB_SEL] = &a1_dspb_sel.hw,
> + [CLKID_DSPA_EN] = &a1_dspa_en.hw,
> + [CLKID_DSPA_EN_NIC] = &a1_dspa_en_nic.hw,
> + [CLKID_DSPB_EN] = &a1_dspb_en.hw,
> + [CLKID_DSPB_EN_NIC] = &a1_dspb_en_nic.hw,
> + [CLKID_24M] = &a1_24m.hw,
> + [CLKID_24M_DIV2] = &a1_24m_div2.hw,
> + [CLKID_12M] = &a1_12m.hw,
> + [CLKID_DIV2_PRE] = &a1_fclk_div2_divn_pre.hw,
> + [CLKID_FCLK_DIV2_DIVN] = &a1_fclk_div2_divn.hw,
> + [CLKID_GEN_SEL] = &a1_gen_sel.hw,
> + [CLKID_GEN_DIV] = &a1_gen_div.hw,
> + [CLKID_GEN] = &a1_gen.hw,
> + [CLKID_SARADC_SEL] = &a1_saradc_sel.hw,
> + [CLKID_SARADC_DIV] = &a1_saradc_div.hw,
> + [CLKID_SARADC_CLK] = &a1_saradc_clk.hw,
> + [CLKID_PWM_A_SEL] = &a1_pwm_a_sel.hw,
> + [CLKID_PWM_A_DIV] = &a1_pwm_a_div.hw,
> + [CLKID_PWM_A] = &a1_pwm_a.hw,
> + [CLKID_PWM_B_SEL] = &a1_pwm_b_sel.hw,
> + [CLKID_PWM_B_DIV] = &a1_pwm_b_div.hw,
> + [CLKID_PWM_B] = &a1_pwm_b.hw,
> + [CLKID_PWM_C_SEL] = &a1_pwm_c_sel.hw,
> + [CLKID_PWM_C_DIV] = &a1_pwm_c_div.hw,
> + [CLKID_PWM_C] = &a1_pwm_c.hw,
> + [CLKID_PWM_D_SEL] = &a1_pwm_d_sel.hw,
> + [CLKID_PWM_D_DIV] = &a1_pwm_d_div.hw,
> + [CLKID_PWM_D] = &a1_pwm_d.hw,
> + [CLKID_PWM_E_SEL] = &a1_pwm_e_sel.hw,
> + [CLKID_PWM_E_DIV] = &a1_pwm_e_div.hw,
> + [CLKID_PWM_E] = &a1_pwm_e.hw,
> + [CLKID_PWM_F_SEL] = &a1_pwm_f_sel.hw,
> + [CLKID_PWM_F_DIV] = &a1_pwm_f_div.hw,
> + [CLKID_PWM_F] = &a1_pwm_f.hw,
> + [CLKID_SPICC_SEL] = &a1_spicc_sel.hw,
> + [CLKID_SPICC_DIV] = &a1_spicc_div.hw,
> + [CLKID_SPICC_SEL2] = &a1_spicc_sel2.hw,
> + [CLKID_SPICC] = &a1_spicc.hw,
> + [CLKID_TS_DIV] = &a1_ts_div.hw,
> + [CLKID_TS] = &a1_ts.hw,
> + [CLKID_SPIFC_SEL] = &a1_spifc_sel.hw,
> + [CLKID_SPIFC_DIV] = &a1_spifc_div.hw,
> + [CLKID_SPIFC_SEL2] = &a1_spifc_sel2.hw,
> + [CLKID_SPIFC] = &a1_spifc.hw,
> + [CLKID_USB_BUS_SEL] = &a1_usb_bus_sel.hw,
> + [CLKID_USB_BUS_DIV] = &a1_usb_bus_div.hw,
> + [CLKID_USB_BUS] = &a1_usb_bus.hw,
> + [CLKID_SD_EMMC_SEL] = &a1_sd_emmc_sel.hw,
> + [CLKID_SD_EMMC_DIV] = &a1_sd_emmc_div.hw,
> + [CLKID_SD_EMMC_SEL2] = &a1_sd_emmc_sel2.hw,
> + [CLKID_SD_EMMC] = &a1_sd_emmc.hw,
> + [CLKID_PSRAM_SEL] = &a1_psram_sel.hw,
> + [CLKID_PSRAM_DIV] = &a1_psram_div.hw,
> + [CLKID_PSRAM_SEL2] = &a1_psram_sel2.hw,
> + [CLKID_PSRAM] = &a1_psram.hw,
> + [CLKID_DMC_SEL] = &a1_dmc_sel.hw,
> + [CLKID_DMC_DIV] = &a1_dmc_div.hw,
> + [CLKID_DMC_SEL2] = &a1_dmc_sel2.hw,
> + [CLKID_DMC] = &a1_dmc.hw,
> + [CLKID_RTC_32K_CLKIN] = &a1_rtc_32k_clkin.hw,
> + [CLKID_RTC_32K_DIV] = &a1_rtc_32k_div.hw,
> + [CLKID_RTC_32K_XTAL] = &a1_rtc_32k_xtal.hw,
> + [CLKID_RTC_32K_SEL] = &a1_rtc_32k_sel.hw,
> + [CLKID_RTC_CLK] = &a1_rtc_clk.hw,
> + [CLKID_CECA_32K_CLKIN] = &a1_ceca_32k_clkin.hw,
> + [CLKID_CECA_32K_DIV] = &a1_ceca_32k_div.hw,
> + [CLKID_CECA_32K_SEL_PRE] = &a1_ceca_32k_sel_pre.hw,
> + [CLKID_CECA_32K_SEL] = &a1_ceca_32k_sel.hw,
> + [CLKID_CECA_32K] = &a1_ceca_32k_clkout.hw,
> + [CLKID_CECB_32K_CLKIN] = &a1_cecb_32k_clkin.hw,
> + [CLKID_CECB_32K_DIV] = &a1_cecb_32k_div.hw,
> + [CLKID_CECB_32K_SEL_PRE] = &a1_cecb_32k_sel_pre.hw,
> + [CLKID_CECB_32K_SEL] = &a1_cecb_32k_sel.hw,
> + [CLKID_CECB_32K] = &a1_cecb_32k_clkout.hw,
> + [NR_CLKS] = NULL,
> + },
> + .num = NR_CLKS,
> +};
> +
> +/* Convenience table to populate regmap in .probe */
> +static struct clk_regmap *const a1_periphs_regmaps[] = {
> + &a1_xtal_clktree,
> + &a1_xtal_fixpll,
> + &a1_xtal_usb_phy,
> + &a1_xtal_usb_ctrl,
> + &a1_xtal_hifipll,
> + &a1_xtal_syspll,
> + &a1_xtal_dds,
> + &a1_clk_tree,
> + &a1_reset_ctrl,
> + &a1_analog_ctrl,
> + &a1_pwr_ctrl,
> + &a1_sys_ctrl,
> + &a1_temp_sensor,
> + &a1_am2axi_dev,
> + &a1_spicc_b,
> + &a1_spicc_a,
> + &a1_clk_msr,
> + &a1_audio,
> + &a1_jtag_ctrl,
> + &a1_saradc,
> + &a1_pwm_ef,
> + &a1_pwm_cd,
> + &a1_pwm_ab,
> + &a1_cec,
> + &a1_i2c_s,
> + &a1_ir_ctrl,
> + &a1_i2c_m_d,
> + &a1_i2c_m_c,
> + &a1_i2c_m_b,
> + &a1_i2c_m_a,
> + &a1_acodec,
> + &a1_otp,
> + &a1_sd_emmc_a,
> + &a1_usb_phy,
> + &a1_usb_ctrl,
> + &a1_sys_dspb,
> + &a1_sys_dspa,
> + &a1_dma,
> + &a1_irq_ctrl,
> + &a1_nic,
> + &a1_gic,
> + &a1_uart_c,
> + &a1_uart_b,
> + &a1_uart_a,
> + &a1_sys_psram,
> + &a1_rsa,
> + &a1_coresight,
> + &a1_am2axi_vad,
> + &a1_audio_vad,
> + &a1_axi_dmc,
> + &a1_axi_psram,
> + &a1_ramb,
> + &a1_rama,
> + &a1_axi_spifc,
> + &a1_axi_nic,
> + &a1_axi_dma,
> + &a1_cpu_ctrl,
> + &a1_rom,
> + &a1_prod_i2c,
> + &a1_dspa_a_sel,
> + &a1_dspa_a_div,
> + &a1_dspa_a,
> + &a1_dspa_b_sel,
> + &a1_dspa_b_div,
> + &a1_dspa_b,
> + &a1_dspa_sel,
> + &a1_dspb_a_sel,
> + &a1_dspb_a_div,
> + &a1_dspb_a,
> + &a1_dspb_b_sel,
> + &a1_dspb_b_div,
> + &a1_dspb_b,
> + &a1_dspb_sel,
> + &a1_dspa_en,
> + &a1_dspa_en_nic,
> + &a1_dspb_en,
> + &a1_dspb_en_nic,
> + &a1_24m,
> + &a1_12m,
> + &a1_fclk_div2_divn_pre,
> + &a1_fclk_div2_divn,
> + &a1_gen_sel,
> + &a1_gen_div,
> + &a1_gen,
> + &a1_saradc_sel,
> + &a1_saradc_div,
> + &a1_saradc_clk,
> + &a1_pwm_a_sel,
> + &a1_pwm_a_div,
> + &a1_pwm_a,
> + &a1_pwm_b_sel,
> + &a1_pwm_b_div,
> + &a1_pwm_b,
> + &a1_pwm_c_sel,
> + &a1_pwm_c_div,
> + &a1_pwm_c,
> + &a1_pwm_d_sel,
> + &a1_pwm_d_div,
> + &a1_pwm_d,
> + &a1_pwm_e_sel,
> + &a1_pwm_e_div,
> + &a1_pwm_e,
> + &a1_pwm_f_sel,
> + &a1_pwm_f_div,
> + &a1_pwm_f,
> + &a1_spicc_sel,
> + &a1_spicc_div,
> + &a1_spicc_sel2,
> + &a1_spicc,
> + &a1_ts_div,
> + &a1_ts,
> + &a1_spifc_sel,
> + &a1_spifc_div,
> + &a1_spifc_sel2,
> + &a1_spifc,
> + &a1_usb_bus_sel,
> + &a1_usb_bus_div,
> + &a1_usb_bus,
> + &a1_sd_emmc_sel,
> + &a1_sd_emmc_div,
> + &a1_sd_emmc_sel2,
> + &a1_sd_emmc,
> + &a1_psram_sel,
> + &a1_psram_div,
> + &a1_psram_sel2,
> + &a1_psram,
> + &a1_dmc_sel,
> + &a1_dmc_div,
> + &a1_dmc_sel2,
> + &a1_dmc,
> + &a1_sys_b_sel,
> + &a1_sys_b_div,
> + &a1_sys_b,
> + &a1_sys_a_sel,
> + &a1_sys_a_div,
> + &a1_sys_a,
> + &a1_sys_clk,
> + &a1_rtc_32k_clkin,
> + &a1_rtc_32k_div,
> + &a1_rtc_32k_xtal,
> + &a1_rtc_32k_sel,
> + &a1_rtc_clk,
> + &a1_ceca_32k_clkin,
> + &a1_ceca_32k_div,
> + &a1_ceca_32k_sel_pre,
> + &a1_ceca_32k_sel,
> + &a1_ceca_32k_clkout,
> + &a1_cecb_32k_clkin,
> + &a1_cecb_32k_div,
> + &a1_cecb_32k_sel_pre,
> + &a1_cecb_32k_sel,
> + &a1_cecb_32k_clkout,
> +};
> +
> +static struct regmap_config clkc_regmap_config = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> +};
> +
> +static int meson_a1_periphs_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct resource *res;
> + void __iomem *base;
> + struct regmap *map;
> + int ret, i;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +
> + base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
Same comment as the PLL driver
> + map = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
> + if (IS_ERR(map))
> + return PTR_ERR(map);
> +
> + /* Populate regmap for the regmap backed clocks */
> + for (i = 0; i < ARRAY_SIZE(a1_periphs_regmaps); i++)
> + a1_periphs_regmaps[i]->map = map;
> +
> + for (i = 0; i < a1_periphs_hw_onecell_data.num; i++) {
> + /* array might be sparse */
> + if (!a1_periphs_hw_onecell_data.hws[i])
> + continue;
> +
> + ret = devm_clk_hw_register(dev,
> + a1_periphs_hw_onecell_data.hws[i]);
> + if (ret) {
> + dev_err(dev, "Clock registration failed\n");
> + return ret;
> + }
> + }
> +
> + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> + &a1_periphs_hw_onecell_data);
> +}
> +
> +static const struct of_device_id clkc_match_table[] = {
> + { .compatible = "amlogic,a1-periphs-clkc", },
> + {}
> +};
> +
> +static struct platform_driver a1_periphs_driver = {
> + .probe = meson_a1_periphs_probe,
> + .driver = {
> + .name = "a1-periphs-clkc",
> + .of_match_table = clkc_match_table,
> + },
> +};
> +
> +builtin_platform_driver(a1_periphs_driver);
> diff --git a/drivers/clk/meson/a1.h b/drivers/clk/meson/a1.h
> new file mode 100644
> index 000000000000..1ae5e04848d6
> --- /dev/null
> +++ b/drivers/clk/meson/a1.h
> @@ -0,0 +1,120 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
> + */
> +
> +#ifndef __A1_H
> +#define __A1_H
> +
> +/* peripheral clock controller register offset */
> +#define SYS_OSCIN_CTRL 0x0
> +#define RTC_BY_OSCIN_CTRL0 0x4
> +#define RTC_BY_OSCIN_CTRL1 0x8
> +#define RTC_CTRL 0xc
> +#define SYS_CLK_CTRL0 0x10
> +#define AXI_CLK_CTRL0 0x14
> +#define SYS_CLK_EN0 0x1c
> +#define SYS_CLK_EN1 0x20
> +#define AXI_CLK_EN 0x24
> +#define DSPA_CLK_EN 0x28
> +#define DSPB_CLK_EN 0x2c
> +#define DSPA_CLK_CTRL0 0x30
> +#define DSPB_CLK_CTRL0 0x34
> +#define CLK12_24_CTRL 0x38
> +#define GEN_CLK_CTRL 0x3c
> +#define TIMESTAMP_CTRL0 0x40
> +#define TIMESTAMP_CTRL1 0x44
> +#define TIMESTAMP_CTRL2 0x48
> +#define TIMESTAMP_VAL0 0x4c
> +#define TIMESTAMP_VAL1 0x50
> +#define TIMEBASE_CTRL0 0x54
> +#define TIMEBASE_CTRL1 0x58
> +#define SAR_ADC_CLK_CTRL 0xc0
> +#define PWM_CLK_AB_CTRL 0xc4
> +#define PWM_CLK_CD_CTRL 0xc8
> +#define PWM_CLK_EF_CTRL 0xcc
> +#define SPICC_CLK_CTRL 0xd0
> +#define TS_CLK_CTRL 0xd4
> +#define SPIFC_CLK_CTRL 0xd8
> +#define USB_BUSCLK_CTRL 0xdc
> +#define SD_EMMC_CLK_CTRL 0xe0
> +#define CECA_CLK_CTRL0 0xe4
> +#define CECA_CLK_CTRL1 0xe8
> +#define CECB_CLK_CTRL0 0xec
> +#define CECB_CLK_CTRL1 0xf0
> +#define PSRAM_CLK_CTRL 0xf4
> +#define DMC_CLK_CTRL 0xf8
> +#define FCLK_DIV1_SEL 0xfc
> +#define TST_CTRL 0x100
> +
> +#define CLKID_XTAL_CLKTREE 0
> +#define CLKID_SYS_A_SEL 89
> +#define CLKID_SYS_A_DIV 90
> +#define CLKID_SYS_A 91
> +#define CLKID_SYS_B_SEL 92
> +#define CLKID_SYS_B_DIV 93
> +#define CLKID_SYS_B 94
> +#define CLKID_DSPA_A_SEL 95
> +#define CLKID_DSPA_A_DIV 96
> +#define CLKID_DSPA_A 97
> +#define CLKID_DSPA_B_SEL 98
> +#define CLKID_DSPA_B_DIV 99
> +#define CLKID_DSPA_B 100
> +#define CLKID_DSPB_A_SEL 101
> +#define CLKID_DSPB_A_DIV 102
> +#define CLKID_DSPB_A 103
> +#define CLKID_DSPB_B_SEL 104
> +#define CLKID_DSPB_B_DIV 105
> +#define CLKID_DSPB_B 106
> +#define CLKID_RTC_32K_CLKIN 107
> +#define CLKID_RTC_32K_DIV 108
> +#define CLKID_RTC_32K_XTAL 109
> +#define CLKID_RTC_32K_SEL 110
> +#define CLKID_CECB_32K_CLKIN 111
> +#define CLKID_CECB_32K_DIV 112
> +#define CLKID_CECB_32K_SEL_PRE 113
> +#define CLKID_CECB_32K_SEL 114
> +#define CLKID_CECA_32K_CLKIN 115
> +#define CLKID_CECA_32K_DIV 116
> +#define CLKID_CECA_32K_SEL_PRE 117
> +#define CLKID_CECA_32K_SEL 118
> +#define CLKID_DIV2_PRE 119
> +#define CLKID_24M_DIV2 120
> +#define CLKID_GEN_SEL 121
> +#define CLKID_GEN_DIV 122
> +#define CLKID_SARADC_DIV 123
> +#define CLKID_PWM_A_SEL 124
> +#define CLKID_PWM_A_DIV 125
> +#define CLKID_PWM_B_SEL 126
> +#define CLKID_PWM_B_DIV 127
> +#define CLKID_PWM_C_SEL 128
> +#define CLKID_PWM_C_DIV 129
> +#define CLKID_PWM_D_SEL 130
> +#define CLKID_PWM_D_DIV 131
> +#define CLKID_PWM_E_SEL 132
> +#define CLKID_PWM_E_DIV 133
> +#define CLKID_PWM_F_SEL 134
> +#define CLKID_PWM_F_DIV 135
> +#define CLKID_SPICC_SEL 136
> +#define CLKID_SPICC_DIV 137
> +#define CLKID_SPICC_SEL2 138
> +#define CLKID_TS_DIV 139
> +#define CLKID_SPIFC_SEL 140
> +#define CLKID_SPIFC_DIV 141
> +#define CLKID_SPIFC_SEL2 142
> +#define CLKID_USB_BUS_SEL 143
> +#define CLKID_USB_BUS_DIV 144
> +#define CLKID_SD_EMMC_SEL 145
> +#define CLKID_SD_EMMC_DIV 146
> +#define CLKID_SD_EMMC_SEL2 147
> +#define CLKID_PSRAM_SEL 148
> +#define CLKID_PSRAM_DIV 149
> +#define CLKID_PSRAM_SEL2 150
> +#define CLKID_DMC_SEL 151
> +#define CLKID_DMC_DIV 152
> +#define CLKID_DMC_SEL2 153
> +#define NR_CLKS 154
> +
> +#include <dt-bindings/clock/a1-clkc.h>
> +
> +#endif /* __A1_H */
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^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 01/11] dt-bindings: clock: meson: add A1 PLL clock controller bindings
2022-12-02 11:16 ` Krzysztof Kozlowski
@ 2022-12-02 11:28 ` Dmitry Rokosov
2022-12-02 13:36 ` neil.armstrong
0 siblings, 1 reply; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-02 11:28 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Jerome Brunet, Rob Herring, devicetree, sboyd, khilman, kernel,
robh+dt, martin.blumenstingl, linux-arm-kernel, jian.hu,
linux-kernel, krzysztof.kozlowski+dt, linux-amlogic, rockosov,
mturquette, linux-clk, neil.armstrong
> >>>> On Fri, 02 Dec 2022 01:56:53 +0300, Dmitry Rokosov wrote:
> >>>>> From: Jian Hu <jian.hu@amlogic.com>
> >>>>>
> >>>>> Add the documentation to support Amlogic A1 PLL clock driver,
> >>>>> and add A1 PLL clock controller bindings.
> >>>>>
> >>>>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> >>>>> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> >>>>> ---
> >>>>> .../bindings/clock/amlogic,a1-pll-clkc.yaml | 52 +++++++++++++++++++
> >>>>> include/dt-bindings/clock/a1-pll-clkc.h | 16 ++++++
> >>>>> 2 files changed, 68 insertions(+)
> >>>>> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
> >>>>> create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h
> >>>>>
> >>>>
> >>>> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> >>>> on your patch (DT_CHECKER_FLAGS is new in v5.13):
> >>>>
> >>>> yamllint warnings/errors:
> >>>> ./Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml:26:6: [warning] wrong indentation: expected 6 but found 5 (indentation)
> >>>>
> >>>> dtschema/dtc warnings/errors:
> >>>> ./Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml: $id: relative path/filename doesn't match actual path or filename
...
> >>>
> >>> Please find all fixes of above warnings and errors in the my patch
> >>> located at the link:
> >>>
> >>> https://lore.kernel.org/linux-amlogic/20221201225703.6507-9-ddrokosov@sberdevices.ru/
> >>
> >> Why? This patch here is broken and it should be fixed. Don't apply
> >> broken patches...
> >
> > Dmitry is ressurecting a series that is several years old and not his to
> > begin with.
> >
> > He was unsure about take the code of somebody else.
> > To be fair, he even asked for advice on IRC about to proceed.
> >
> > Dmitry, as you may have guessed, for next revision, please fix Jian Hu
> > original patches in place, not with fixup patches.
> >
> > If your fixes are minor (not complete rewrite), please keep the original
> > author and add your SoB
>
> We never take intentionally wrong patches, e.g. code which does not even
> compile, and immediately fix it in next patch.
>
> Can you imagine adding such drivers? Which are broken in the commit they
> are added?
>
> So the patchset is old or abandoned, take ownership, add co-developed
> etc. Just don't add known broken code.
Okay, I've got your point. It's reasonable.
I will fix Jian Hu's patches (squash with mine) and mark all of them
with co-developed and SoB Jian Hu tags. Thank you for explanation.
--
Thank you,
Dmitry
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^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 02/11] clk: meson: a1: add support for Amlogic A1 PLL clock driver
2022-12-02 11:16 ` Jerome Brunet
@ 2022-12-02 11:31 ` Dmitry Rokosov
0 siblings, 0 replies; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-02 11:31 UTC (permalink / raw)
To: Jerome Brunet
Cc: neil.armstrong, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl, jian.hu,
kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
On Fri, Dec 02, 2022 at 12:16:12PM +0100, Jerome Brunet wrote:
> > drivers/clk/meson/Kconfig | 9 +
> > drivers/clk/meson/Makefile | 1 +
> > drivers/clk/meson/a1-pll.c | 360 +++++++++++++++++++++++++++++++++++++
> > drivers/clk/meson/a1-pll.h | 56 ++++++
> > 4 files changed, 426 insertions(+)
> > create mode 100644 drivers/clk/meson/a1-pll.c
> > create mode 100644 drivers/clk/meson/a1-pll.h
> >
> > diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> > index fc002c155bc3..ab34662b24f0 100644
> > --- a/drivers/clk/meson/Kconfig
> > +++ b/drivers/clk/meson/Kconfig
> > @@ -99,6 +99,15 @@ config COMMON_CLK_AXG_AUDIO
> > Support for the audio clock controller on AmLogic A113D devices,
> > aka axg, Say Y if you want audio subsystem to work.
> >
> > +config COMMON_CLK_A1_PLL
> > + bool
>
> Could you add a tristate with some text please ?
>
Yep... I did it in my fixup patches :-) Looks like it's better to review
the next version with already squashed patches.
--
Thank you,
Dmitry
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^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 06/11] clk: meson: introduce a1-clkc common driver for all A1 clock controllers
2022-12-01 22:56 ` [PATCH v8 06/11] clk: meson: introduce a1-clkc common driver for all A1 clock controllers Dmitry Rokosov
@ 2022-12-02 11:36 ` Jerome Brunet
2022-12-02 11:58 ` Dmitry Rokosov
0 siblings, 1 reply; 45+ messages in thread
From: Jerome Brunet @ 2022-12-02 11:36 UTC (permalink / raw)
To: Dmitry Rokosov, neil.armstrong, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
On Fri 02 Dec 2022 at 01:56, Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
> Generally, A1 SoC has four clock controllers on the board: PLL,
> Peripherals, CPU, and Audio. The audio clock controller is different
> from others, but the rest are very similar from a functional and regmap
> point of view. So a it's good idea to generalize some routines for all
> of them. Exactly, meson-a1-clkc driver contains the common probe() flow.
>
> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
I think you should leave this out for the initial submission. It makes
harder to review.
In some case, these factorizations actually the maitenance harder.
There is also the s4 that is coming up. It looks similar to the A1 as
well.
Let's wait for both them to land, see how it goes and then we'll decide
if a factorization is appropriate.
> ---
> drivers/clk/meson/Kconfig | 4 ++
> drivers/clk/meson/Makefile | 1 +
> drivers/clk/meson/meson-a1-clkc.c | 63 +++++++++++++++++++++++++++++++
> drivers/clk/meson/meson-a1-clkc.h | 25 ++++++++++++
> 4 files changed, 93 insertions(+)
> create mode 100644 drivers/clk/meson/meson-a1-clkc.c
> create mode 100644 drivers/clk/meson/meson-a1-clkc.h
>
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index bd44ba47200e..1c885541c3a9 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -43,6 +43,10 @@ config COMMON_CLK_MESON_CPU_DYNDIV
> tristate
> select COMMON_CLK_MESON_REGMAP
>
> +config COMMON_CLK_MESON_A1_CLKC
> + tristate
> + select COMMON_CLK_MESON_REGMAP
> +
> config COMMON_CLK_MESON8B
> bool "Meson8 SoC Clock controller support"
> depends on ARM
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index 0e6f293c05d4..15136d861a65 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -11,6 +11,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o
> obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o
> obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o
> obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o
> +obj-$(CONFIG_COMMON_CLK_MESON_A1_CLKC) += meson-a1-clkc.o
>
> # Amlogic Clock controllers
>
> diff --git a/drivers/clk/meson/meson-a1-clkc.c b/drivers/clk/meson/meson-a1-clkc.c
> new file mode 100644
> index 000000000000..2fe320a0e16e
> --- /dev/null
> +++ b/drivers/clk/meson/meson-a1-clkc.c
> @@ -0,0 +1,63 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Amlogic Meson-A1 Clock Controller Driver
> + *
> + * Copyright (c) 2022, SberDevices. All Rights Reserved.
> + * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> + */
> +
> +#include <linux/of_device.h>
> +#include "meson-a1-clkc.h"
> +
> +static struct regmap_config clkc_regmap_config = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> +};
> +
> +int meson_a1_clkc_probe(struct platform_device *pdev)
> +{
> + struct meson_a1_clkc_data *clkc;
> + struct device *dev = &pdev->dev;
> + struct resource *res;
> + void __iomem *base;
> + struct regmap *map;
> + int clkid, i, err;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res)
> + return dev_err_probe(dev, -ENXIO, "can't get IO resource\n");
> +
> + base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(base))
> + return dev_err_probe(dev, PTR_ERR(base),
> + "can't ioremap resource %pr\n", res);
> +
> + map = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
> + if (IS_ERR(map))
> + return dev_err_probe(dev, PTR_ERR(map),
> + "can't init regmap mmio region\n");
> +
> + clkc = (struct meson_a1_clkc_data *)of_device_get_match_data(dev);
> + if (!clkc)
> + return dev_err_probe(dev, -ENODEV,
> + "can't get A1 clkc driver data\n");
> +
> + /* Populate regmap for the regmap backed clocks */
> + for (i = 0; i < clkc->num_regs; i++)
> + clkc->regs[i]->map = map;
> +
> + for (clkid = 0; clkid < clkc->hw->num; clkid++) {
> + err = devm_clk_hw_register(dev, clkc->hw->hws[clkid]);
> + if (err)
> + return dev_err_probe(dev, err,
> + "clock registration failed\n");
> + }
> +
> + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> + (void *)clkc->hw);
> +}
> +EXPORT_SYMBOL_GPL(meson_a1_clkc_probe);
> +
> +MODULE_AUTHOR("Dmitry Rokosov <ddrokosov@sberdevices.ru>");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/clk/meson/meson-a1-clkc.h b/drivers/clk/meson/meson-a1-clkc.h
> new file mode 100644
> index 000000000000..503eca0f6cb5
> --- /dev/null
> +++ b/drivers/clk/meson/meson-a1-clkc.h
> @@ -0,0 +1,25 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Amlogic Meson-A1 Clock Controller driver
> + *
> + * Copyright (c) 2022, SberDevices. All Rights Reserved.
> + * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> + */
> +
> +#ifndef __MESON_A1_CLKC_H__
> +#define __MESON_A1_CLKC_H__
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include "clk-regmap.h"
> +
> +struct meson_a1_clkc_data {
> + const struct clk_hw_onecell_data *hw;
> + struct clk_regmap *const *regs;
> + size_t num_regs;
> +};
> +
> +int meson_a1_clkc_probe(struct platform_device *pdev);
> +#endif
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^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 07/11] clk: meson: a1: redesign Amlogic A1 PLL clock controller
2022-12-01 22:56 ` [PATCH v8 07/11] clk: meson: a1: redesign Amlogic A1 PLL clock controller Dmitry Rokosov
@ 2022-12-02 11:42 ` Jerome Brunet
2022-12-02 12:47 ` Dmitry Rokosov
0 siblings, 1 reply; 45+ messages in thread
From: Jerome Brunet @ 2022-12-02 11:42 UTC (permalink / raw)
To: Dmitry Rokosov, neil.armstrong, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
On Fri 02 Dec 2022 at 01:56, Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
> Summary changes:
> - supported meson-a1-clkc common driver
> - inherited from the base clk-pll driver, implemented own version of
> init/enable/disable/enabled routines; rate calculating logic is
> fully the same
> - aligned CLKID-related definitions with CLKID list from order
> perspective to remove holes and permutations
> - corrected Kconfig dependencies and types
> - provided correct MODULE_AUTHORs() and MODULE_LICENSE()
> - optimized and fix up some clock relationships
> - removed unused register offset definitions (ANACTRL_* group)
This patch mix PLL stuff, factorization change, etc ...
In general, when your commit description is a list, it is a hint that
you are doing more than one thing in it. It is unlikely to be OK then
>
> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> ---
> drivers/clk/meson/Kconfig | 5 +-
> drivers/clk/meson/a1-pll.c | 267 +++++++++++++++++++++++++------------
> drivers/clk/meson/a1-pll.h | 37 ++---
> 3 files changed, 202 insertions(+), 107 deletions(-)
>
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index 1c885541c3a9..deb273673ec1 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -104,10 +104,11 @@ config COMMON_CLK_AXG_AUDIO
> aka axg, Say Y if you want audio subsystem to work.
>
> config COMMON_CLK_A1_PLL
> - bool
> - depends on ARCH_MESON
> + tristate "Meson A1 SoC PLL controller support"
> + depends on ARM64
> select COMMON_CLK_MESON_REGMAP
> select COMMON_CLK_MESON_PLL
> + select COMMON_CLK_MESON_A1_CLKC
> help
> Support for the PLL clock controller on Amlogic A113L device,
> aka a1. Say Y if you want PLL to work.
> diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c
> index 69c1ca07d041..23487ca797b3 100644
> --- a/drivers/clk/meson/a1-pll.c
> +++ b/drivers/clk/meson/a1-pll.c
> @@ -2,15 +2,133 @@
> /*
> * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
> * Author: Jian Hu <jian.hu@amlogic.com>
> + *
> + * Copyright (c) 2022, SberDevices. All Rights Reserved.
> + * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> */
>
> #include <linux/clk-provider.h>
> #include <linux/of_device.h>
> #include <linux/platform_device.h>
> +#include "meson-a1-clkc.h"
> #include "a1-pll.h"
> -#include "clk-pll.h"
> #include "clk-regmap.h"
>
> +static inline
> +struct meson_a1_pll_data *meson_a1_pll_data(struct clk_regmap *clk)
> +{
> + return (struct meson_a1_pll_data *)clk->data;
> +}
> +
> +static int meson_a1_pll_init(struct clk_hw *hw)
> +{
> + struct clk_regmap *clk = to_clk_regmap(hw);
> + struct meson_a1_pll_data *pll = meson_a1_pll_data(clk);
> +
> + regmap_multi_reg_write(clk->map, pll->base.init_regs,
> + pll->base.init_count);
> +
> + return 0;
Looks the the default init mostly
Looks like you are trying the handle the absence of the rst bit.
I'm pretty sure the hifi PLL of the SoC as one but you really don't want
to poke, this can be in the generic driver, with MESON_PARM_APPLICABLE()
test.
No need to redefine this
> +}
> +
> +static int meson_a1_pll_is_enabled(struct clk_hw *hw)
> +{
> + struct clk_regmap *clk = to_clk_regmap(hw);
> + struct meson_a1_pll_data *pll = meson_a1_pll_data(clk);
> +
> + if (MESON_PARM_APPLICABLE(&pll->base.rst) &&
> + meson_parm_read(clk->map, &pll->base.rst))
> + return 0;
> +
> + if (!meson_parm_read(clk->map, &pll->base.en) ||
> + !meson_parm_read(clk->map, &pll->base.l))
> + return 0;
> +
Same here, pretty sure rst is there and the generic function works but
if this update is required, it seems safe to do in the generic driver.
> + return 1;
> +}
> +
> +static int meson_a1_pll_enable(struct clk_hw *hw)
> +{
> + struct clk_regmap *clk = to_clk_regmap(hw);
> + struct meson_a1_pll_data *pll = meson_a1_pll_data(clk);
> +
> + /* Do nothing if the PLL is already enabled */
> + if (clk_hw_is_enabled(hw))
> + return 0;
> +
> + /* Enable the pll */
> + meson_parm_write(clk->map, &pll->base.en, 1);
> +
> + /*
> + * Compared with the previous SoCs, self-adaption current module
> + * is newly added for A1, keep the new power-on sequence to enable the
> + * PLL. The sequence is:
> + * 1. enable the pll, delay for 10us
> + * 2. enable the pll self-adaption current module, delay for 40us
> + * 3. enable the lock detect module
> + */
> + usleep_range(10, 20);
> + meson_parm_write(clk->map, &pll->current_en, 1);
this base.en vs current_en needs some explanation.
Again I think there is room to handle this through the pll driver
> + usleep_range(40, 50);
> +
> + meson_parm_write(clk->map, &pll->l_detect, 1);
> + meson_parm_write(clk->map, &pll->l_detect, 0);
> +
> + if (meson_clk_pll_wait_lock(hw))
> + return -EIO;
> +
> + return 0;
> +}
> +
> +static void meson_a1_pll_disable(struct clk_hw *hw)
> +{
> + struct clk_regmap *clk = to_clk_regmap(hw);
> + struct meson_a1_pll_data *pll = meson_a1_pll_data(clk);
> +
> + /* Disable the pll */
> + meson_parm_write(clk->map, &pll->base.en, 0);
> +
> + /* Disable PLL internal self-adaption current module */
> + meson_parm_write(clk->map, &pll->current_en, 0);
> +}
> +
> +/*
> + * A1 PLL clock controller driver is based on meson clk_pll driver,
> + * so some rate calculating routines are reused
> + */
> +static unsigned long meson_a1_pll_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + return meson_clk_pll_ops.recalc_rate(hw, parent_rate);
> +}
> +
> +static int meson_a1_pll_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> +{
> + return meson_clk_pll_ops.determine_rate(hw, req);
> +}
> +
> +static int meson_a1_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + return meson_clk_pll_ops.set_rate(hw, rate, parent_rate);
> +}
> +
This really does not scale well
> +static const struct clk_ops meson_a1_pll_ops = {
> + .init = meson_a1_pll_init,
> + .recalc_rate = meson_a1_pll_recalc_rate,
> + .determine_rate = meson_a1_pll_determine_rate,
> + .set_rate = meson_a1_pll_set_rate,
> + .is_enabled = meson_a1_pll_is_enabled,
> + .enable = meson_a1_pll_enable,
> + .disable = meson_a1_pll_disable
> +};
> +
> +static const struct clk_ops meson_a1_pll_ro_ops = {
> + .recalc_rate = meson_a1_pll_recalc_rate,
> + .is_enabled = meson_a1_pll_is_enabled,
> +};
> +
> static struct clk_regmap a1_fixed_pll_dco = {
> .data = &(struct meson_clk_pll_data){
> .en = {
> @@ -46,7 +164,7 @@ static struct clk_regmap a1_fixed_pll_dco = {
> },
> .hw.init = &(struct clk_init_data){
> .name = "fixed_pll_dco",
> - .ops = &meson_clk_pll_ro_ops,
> + .ops = &meson_a1_pll_ro_ops,
> .parent_data = &(const struct clk_parent_data) {
> .fw_name = "xtal_fixpll",
> },
> @@ -87,31 +205,36 @@ static const struct reg_sequence a1_hifi_init_regs[] = {
> };
>
> static struct clk_regmap a1_hifi_pll = {
> - .data = &(struct meson_clk_pll_data){
> - .en = {
> - .reg_off = ANACTRL_HIFIPLL_CTRL0,
> - .shift = 28,
> - .width = 1,
> - },
> - .m = {
> - .reg_off = ANACTRL_HIFIPLL_CTRL0,
> - .shift = 0,
> - .width = 8,
> - },
> - .n = {
> - .reg_off = ANACTRL_HIFIPLL_CTRL0,
> - .shift = 10,
> - .width = 5,
> - },
> - .frac = {
> - .reg_off = ANACTRL_HIFIPLL_CTRL1,
> - .shift = 0,
> - .width = 19,
> - },
> - .l = {
> - .reg_off = ANACTRL_HIFIPLL_STS,
> - .shift = 31,
> - .width = 1,
> + .data = &(struct meson_a1_pll_data){
> + .base = {
> + .en = {
> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
> + .shift = 28,
> + .width = 1,
> + },
> + .m = {
> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
> + .shift = 0,
> + .width = 8,
> + },
> + .n = {
> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
> + .shift = 10,
> + .width = 5,
> + },
> + .frac = {
> + .reg_off = ANACTRL_HIFIPLL_CTRL1,
> + .shift = 0,
> + .width = 19,
> + },
> + .l = {
> + .reg_off = ANACTRL_HIFIPLL_STS,
> + .shift = 31,
> + .width = 1,
> + },
> + .range = &a1_hifi_pll_mult_range,
> + .init_regs = a1_hifi_init_regs,
> + .init_count = ARRAY_SIZE(a1_hifi_init_regs),
> },
> .current_en = {
> .reg_off = ANACTRL_HIFIPLL_CTRL0,
> @@ -123,13 +246,10 @@ static struct clk_regmap a1_hifi_pll = {
> .shift = 6,
> .width = 1,
> },
> - .range = &a1_hifi_pll_mult_range,
> - .init_regs = a1_hifi_init_regs,
> - .init_count = ARRAY_SIZE(a1_hifi_init_regs),
> },
> .hw.init = &(struct clk_init_data){
> .name = "hifi_pll",
> - .ops = &meson_clk_pll_ops,
> + .ops = &meson_a1_pll_ops,
> .parent_data = &(const struct clk_parent_data) {
> .fw_name = "xtal_hifipll",
> },
> @@ -276,15 +396,15 @@ static struct clk_hw_onecell_data a1_pll_hw_onecell_data = {
> .hws = {
> [CLKID_FIXED_PLL_DCO] = &a1_fixed_pll_dco.hw,
> [CLKID_FIXED_PLL] = &a1_fixed_pll.hw,
> - [CLKID_HIFI_PLL] = &a1_hifi_pll.hw,
> - [CLKID_FCLK_DIV2] = &a1_fclk_div2.hw,
> - [CLKID_FCLK_DIV3] = &a1_fclk_div3.hw,
> - [CLKID_FCLK_DIV5] = &a1_fclk_div5.hw,
> - [CLKID_FCLK_DIV7] = &a1_fclk_div7.hw,
> [CLKID_FCLK_DIV2_DIV] = &a1_fclk_div2_div.hw,
> [CLKID_FCLK_DIV3_DIV] = &a1_fclk_div3_div.hw,
> [CLKID_FCLK_DIV5_DIV] = &a1_fclk_div5_div.hw,
> [CLKID_FCLK_DIV7_DIV] = &a1_fclk_div7_div.hw,
> + [CLKID_FCLK_DIV2] = &a1_fclk_div2.hw,
> + [CLKID_FCLK_DIV3] = &a1_fclk_div3.hw,
> + [CLKID_FCLK_DIV5] = &a1_fclk_div5.hw,
> + [CLKID_FCLK_DIV7] = &a1_fclk_div7.hw,
> + [CLKID_HIFI_PLL] = &a1_hifi_pll.hw,
I get you are trying to do but keep the ID order here
> [NR_PLL_CLKS] = NULL,
> },
> .num = NR_PLL_CLKS,
> @@ -293,68 +413,39 @@ static struct clk_hw_onecell_data a1_pll_hw_onecell_data = {
> static struct clk_regmap *const a1_pll_regmaps[] = {
> &a1_fixed_pll_dco,
> &a1_fixed_pll,
> - &a1_hifi_pll,
> &a1_fclk_div2,
> &a1_fclk_div3,
> &a1_fclk_div5,
> &a1_fclk_div7,
> + &a1_hifi_pll,
?
> };
>
> -static struct regmap_config clkc_regmap_config = {
> - .reg_bits = 32,
> - .val_bits = 32,
> - .reg_stride = 4,
> +static const struct meson_a1_clkc_data a1_pll_clkc __maybe_unused = {
> + .hw = &a1_pll_hw_onecell_data,
> + .regs = a1_pll_regmaps,
> + .num_regs = ARRAY_SIZE(a1_pll_regmaps),
> };
>
> -static int meson_a1_pll_probe(struct platform_device *pdev)
> -{
> - struct device *dev = &pdev->dev;
> - struct resource *res;
> - void __iomem *base;
> - struct regmap *map;
> - int ret, i;
> -
> - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -
> - base = devm_ioremap_resource(dev, res);
> - if (IS_ERR(base))
> - return PTR_ERR(base);
> -
> - map = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
> - if (IS_ERR(map))
> - return PTR_ERR(map);
> -
> - /* Populate regmap for the regmap backed clocks */
> - for (i = 0; i < ARRAY_SIZE(a1_pll_regmaps); i++)
> - a1_pll_regmaps[i]->map = map;
> -
> - for (i = 0; i < a1_pll_hw_onecell_data.num; i++) {
> - /* array might be sparse */
> - if (!a1_pll_hw_onecell_data.hws[i])
> - continue;
> -
> - ret = devm_clk_hw_register(dev, a1_pll_hw_onecell_data.hws[i]);
> - if (ret) {
> - dev_err(dev, "Clock registration failed\n");
> - return ret;
> - }
> - }
> -
> - return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> - &a1_pll_hw_onecell_data);
> -}
> -
> -static const struct of_device_id clkc_match_table[] = {
> - { .compatible = "amlogic,a1-pll-clkc", },
> - {}
> +#ifdef CONFIG_OF
> +static const struct of_device_id a1_pll_clkc_match_table[] = {
> + {
> + .compatible = "amlogic,a1-pll-clkc",
> + .data = &a1_pll_clkc,
> + },
> + {},
> };
> +MODULE_DEVICE_TABLE(of, a1_pll_clkc_match_table);
> +#endif /* CONFIG_OF */
>
> -static struct platform_driver a1_pll_driver = {
> - .probe = meson_a1_pll_probe,
> - .driver = {
> - .name = "a1-pll-clkc",
> - .of_match_table = clkc_match_table,
> +static struct platform_driver a1_pll_clkc_driver = {
> + .probe = meson_a1_clkc_probe,
> + .driver = {
> + .name = "a1-pll-clkc",
> + .of_match_table = of_match_ptr(a1_pll_clkc_match_table),
> },
> };
>
> -builtin_platform_driver(a1_pll_driver);
> +module_platform_driver(a1_pll_clkc_driver);
> +MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>");
> +MODULE_AUTHOR("Dmitry Rokosov <ddrokosov@sberdevices.ru>");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/clk/meson/a1-pll.h b/drivers/clk/meson/a1-pll.h
> index 8ded267061ad..2ff5a2042a97 100644
> --- a/drivers/clk/meson/a1-pll.h
> +++ b/drivers/clk/meson/a1-pll.h
> @@ -1,38 +1,29 @@
> /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> /*
> + * Amlogic Meson-A1 PLL Clock Controller internals
> + *
> * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
> + * Author: Jian Hu <jian.hu@amlogic.com>
> + *
> + * Copyright (c) 2022, SberDevices. All Rights Reserved.
> + * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> */
>
> #ifndef __A1_PLL_H
> #define __A1_PLL_H
>
> +#include "clk-pll.h"
> +
> /* PLL register offset */
> #define ANACTRL_FIXPLL_CTRL0 0x0
> #define ANACTRL_FIXPLL_CTRL1 0x4
> -#define ANACTRL_FIXPLL_CTRL2 0x8
> -#define ANACTRL_FIXPLL_CTRL3 0xc
> -#define ANACTRL_FIXPLL_CTRL4 0x10
> #define ANACTRL_FIXPLL_STS 0x14
> -#define ANACTRL_SYSPLL_CTRL0 0x80
> -#define ANACTRL_SYSPLL_CTRL1 0x84
> -#define ANACTRL_SYSPLL_CTRL2 0x88
> -#define ANACTRL_SYSPLL_CTRL3 0x8c
> -#define ANACTRL_SYSPLL_CTRL4 0x90
> -#define ANACTRL_SYSPLL_STS 0x94
> #define ANACTRL_HIFIPLL_CTRL0 0xc0
> #define ANACTRL_HIFIPLL_CTRL1 0xc4
> #define ANACTRL_HIFIPLL_CTRL2 0xc8
> #define ANACTRL_HIFIPLL_CTRL3 0xcc
> #define ANACTRL_HIFIPLL_CTRL4 0xd0
> #define ANACTRL_HIFIPLL_STS 0xd4
> -#define ANACTRL_AUDDDS_CTRL0 0x100
> -#define ANACTRL_AUDDDS_CTRL1 0x104
> -#define ANACTRL_AUDDDS_CTRL2 0x108
> -#define ANACTRL_AUDDDS_CTRL3 0x10c
> -#define ANACTRL_AUDDDS_CTRL4 0x110
> -#define ANACTRL_AUDDDS_STS 0x114
> -#define ANACTRL_MISCTOP_CTRL0 0x140
> -#define ANACTRL_POR_CNTL 0x188
>
> /*
> * CLKID index values
> @@ -53,4 +44,16 @@
> /* include the CLKIDs that have been made part of the DT binding */
> #include <dt-bindings/clock/a1-pll-clkc.h>
>
> +/**
> + * struct meson_a1_pll_data - A1 PLL state
> + * @base: Basic CLK PLL state
> + * @current_en: Enable or disable the PLL self-adaption current module
> + * @l_detect: Enable or disable the lock detect module
> + */
> +struct meson_a1_pll_data {
> + struct meson_clk_pll_data base;
> + struct parm current_en;
> + struct parm l_detect;
> +};
> +
> #endif /* __A1_PLL_H */
_______________________________________________
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linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 06/11] clk: meson: introduce a1-clkc common driver for all A1 clock controllers
2022-12-02 11:36 ` Jerome Brunet
@ 2022-12-02 11:58 ` Dmitry Rokosov
0 siblings, 0 replies; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-02 11:58 UTC (permalink / raw)
To: Jerome Brunet
Cc: neil.armstrong, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl, jian.hu,
kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
On Fri, Dec 02, 2022 at 12:36:50PM +0100, Jerome Brunet wrote:
>
> On Fri 02 Dec 2022 at 01:56, Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
>
> > Generally, A1 SoC has four clock controllers on the board: PLL,
> > Peripherals, CPU, and Audio. The audio clock controller is different
> > from others, but the rest are very similar from a functional and regmap
> > point of view. So a it's good idea to generalize some routines for all
> > of them. Exactly, meson-a1-clkc driver contains the common probe() flow.
> >
> > Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
>
> I think you should leave this out for the initial submission. It makes
> harder to review.
>
> In some case, these factorizations actually the maitenance harder.
>
> There is also the s4 that is coming up. It looks similar to the A1 as
> well.
>
> Let's wait for both them to land, see how it goes and then we'll decide
> if a factorization is appropriate.
>
Jerome,
Sorry, let me double check a little bit that I get your point correctly.
Do you mean due to s4 development in parallel it's easier to have own
probe sequence for each driver in the first stage (until A1 and S4 clock
controllers not merged to upstream) and after think about some
"generalization", right?
...
--
Thank you,
Dmitry
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linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 09/11] clk: meson: redesign A1 Peripherals CLK controller
2022-12-01 22:57 ` [PATCH v8 09/11] clk: meson: redesign A1 Peripherals CLK controller Dmitry Rokosov
@ 2022-12-02 12:01 ` Jerome Brunet
2022-12-02 12:10 ` Dmitry Rokosov
0 siblings, 1 reply; 45+ messages in thread
From: Jerome Brunet @ 2022-12-02 12:01 UTC (permalink / raw)
To: Dmitry Rokosov, neil.armstrong, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
On Fri 02 Dec 2022 at 01:57, Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
> Summary changes:
> - fixed up clk_summary kernel panic due to missing a1_pad_ctrl
> clk_regmap definition
> - supported meson-a1-clkc common driver
> - aligned CLKID-related definitions with CLKID list from order
> perspective to remove holes and permutations
> - corrected Kconfig dependencies and types
> - provided correct MODULE_AUTHORs() and MODULE_LICENSE()
> - optimized and fix up some clock relationships and parents
> references
> - removed unused register offset definitions
again, list in commit description a hint things are mixed up
>
> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> ---
> drivers/clk/meson/Kconfig | 7 +-
> drivers/clk/meson/a1.c | 591 ++++++++++++++++++--------------------
> drivers/clk/meson/a1.h | 16 +-
> 3 files changed, 292 insertions(+), 322 deletions(-)
>
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index deb273673ec1..cabe63bf23f5 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -114,13 +114,14 @@ config COMMON_CLK_A1_PLL
> aka a1. Say Y if you want PLL to work.
>
> config COMMON_CLK_A1
> - bool
> - depends on ARCH_MESON
> + tristate "Meson A1 SoC clock controller support"
> + depends on ARM64
> select COMMON_CLK_MESON_DUALDIV
> select COMMON_CLK_MESON_REGMAP
> + select COMMON_CLK_MESON_A1_CLKC
> help
> Support for the Peripheral clock controller on Amlogic A113L device,
> - aka a1. Say Y if you want Peripherals to work.
> + aka a1. Say Y if you want clock peripherals controller to work.
>
> config COMMON_CLK_G12A
> tristate "G12 and SM1 SoC clock controllers support"
> diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c
> index 2cf20ae1db75..c9b7f09823f8 100644
> --- a/drivers/clk/meson/a1.c
> +++ b/drivers/clk/meson/a1.c
> @@ -2,6 +2,9 @@
> /*
> * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
> * Author: Jian Hu <jian.hu@amlogic.com>
> + *
> + * Copyright (c) 2022, SberDevices. All Rights Reserved.
> + * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> */
>
> #include <linux/clk-provider.h>
> @@ -10,6 +13,7 @@
> #include "a1.h"
> #include "clk-dualdiv.h"
> #include "clk-regmap.h"
> +#include "meson-a1-clkc.h"
>
> static struct clk_regmap a1_xtal_clktree = {
> .data = &(struct clk_regmap_gate_data){
> @@ -116,11 +120,128 @@ static struct clk_regmap a1_xtal_dds = {
> },
> };
>
> +static struct clk_regmap a1_rtc_32k_clkin = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = RTC_BY_OSCIN_CTRL0,
> + .bit_idx = 31,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "rtc_32k_clkin",
> + .ops = &clk_regmap_gate_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xtal",
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static const struct meson_clk_dualdiv_param a1_32k_div_table[] = {
> + {
> + .dual = 1,
> + .n1 = 733,
> + .m1 = 8,
> + .n2 = 732,
> + .m2 = 11,
> + },
> + {}
> +};
> +
> +static struct clk_regmap a1_rtc_32k_div = {
> + .data = &(struct meson_clk_dualdiv_data){
> + .n1 = {
> + .reg_off = RTC_BY_OSCIN_CTRL0,
> + .shift = 0,
> + .width = 12,
> + },
> + .n2 = {
> + .reg_off = RTC_BY_OSCIN_CTRL0,
> + .shift = 12,
> + .width = 12,
> + },
> + .m1 = {
> + .reg_off = RTC_BY_OSCIN_CTRL1,
> + .shift = 0,
> + .width = 12,
> + },
> + .m2 = {
> + .reg_off = RTC_BY_OSCIN_CTRL1,
> + .shift = 12,
> + .width = 12,
> + },
> + .dual = {
> + .reg_off = RTC_BY_OSCIN_CTRL0,
> + .shift = 28,
> + .width = 1,
> + },
> + .table = a1_32k_div_table,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "rtc_32k_div",
> + .ops = &meson_clk_dualdiv_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_rtc_32k_clkin.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_rtc_32k_xtal = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = RTC_BY_OSCIN_CTRL1,
> + .bit_idx = 24,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "rtc_32k_xtal",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_rtc_32k_clkin.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap a1_rtc_32k_sel = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = RTC_CTRL,
> + .mask = 0x3,
> + .shift = 0,
> + .flags = CLK_MUX_ROUND_CLOSEST,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "rtc_32k_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_rtc_32k_xtal.hw,
> + &a1_rtc_32k_div.hw,
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +struct clk_regmap a1_rtc_clk = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = RTC_BY_OSCIN_CTRL0,
> + .bit_idx = 30,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "rtc_clk",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_rtc_32k_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static u32 mux_table_sys_clk[] = { 0, 1, 2, 3, 7 };
> static const struct clk_parent_data sys_clk_parents[] = {
> { .fw_name = "xtal" },
> { .fw_name = "fclk_div2" },
> { .fw_name = "fclk_div3" },
> { .fw_name = "fclk_div5" },
> + { .hw = &a1_rtc_clk.hw },
> };
>
> static struct clk_regmap a1_sys_b_sel = {
> @@ -128,6 +249,7 @@ static struct clk_regmap a1_sys_b_sel = {
> .offset = SYS_CLK_CTRL0,
> .mask = 0x7,
> .shift = 26,
> + .table = mux_table_sys_clk,
> },
> .hw.init = &(struct clk_init_data){
> .name = "sys_b_sel",
> @@ -175,6 +297,7 @@ static struct clk_regmap a1_sys_a_sel = {
> .offset = SYS_CLK_CTRL0,
> .mask = 0x7,
> .shift = 10,
> + .table = mux_table_sys_clk,
> },
> .hw.init = &(struct clk_init_data){
> .name = "sys_a_sel",
> @@ -227,7 +350,8 @@ static struct clk_regmap a1_sys_clk = {
> .name = "sys_clk",
> .ops = &clk_regmap_mux_ro_ops,
> .parent_hws = (const struct clk_hw *[]) {
> - &a1_sys_a.hw, &a1_sys_b.hw,
> + &a1_sys_a.hw,
> + &a1_sys_b.hw,
> },
> .num_parents = 2,
> /*
> @@ -243,121 +367,6 @@ static struct clk_regmap a1_sys_clk = {
> },
> };
>
> -static struct clk_regmap a1_rtc_32k_clkin = {
> - .data = &(struct clk_regmap_gate_data){
> - .offset = RTC_BY_OSCIN_CTRL0,
> - .bit_idx = 31,
> - },
> - .hw.init = &(struct clk_init_data) {
> - .name = "rtc_32k_clkin",
> - .ops = &clk_regmap_gate_ops,
> - .parent_data = &(const struct clk_parent_data) {
> - .fw_name = "xtal",
> - },
> - .num_parents = 1,
> - },
> -};
> -
> -static const struct meson_clk_dualdiv_param a1_32k_div_table[] = {
> - {
> - .dual = 1,
> - .n1 = 733,
> - .m1 = 8,
> - .n2 = 732,
> - .m2 = 11,
> - },
> - {}
> -};
> -
> -static struct clk_regmap a1_rtc_32k_div = {
> - .data = &(struct meson_clk_dualdiv_data){
> - .n1 = {
> - .reg_off = RTC_BY_OSCIN_CTRL0,
> - .shift = 0,
> - .width = 12,
> - },
> - .n2 = {
> - .reg_off = RTC_BY_OSCIN_CTRL0,
> - .shift = 12,
> - .width = 12,
> - },
> - .m1 = {
> - .reg_off = RTC_BY_OSCIN_CTRL1,
> - .shift = 0,
> - .width = 12,
> - },
> - .m2 = {
> - .reg_off = RTC_BY_OSCIN_CTRL1,
> - .shift = 12,
> - .width = 12,
> - },
> - .dual = {
> - .reg_off = RTC_BY_OSCIN_CTRL0,
> - .shift = 28,
> - .width = 1,
> - },
> - .table = a1_32k_div_table,
> - },
> - .hw.init = &(struct clk_init_data){
> - .name = "rtc_32k_div",
> - .ops = &meson_clk_dualdiv_ops,
> - .parent_hws = (const struct clk_hw *[]) {
> - &a1_rtc_32k_clkin.hw
> - },
> - .num_parents = 1,
> - },
> -};
> -
> -static struct clk_regmap a1_rtc_32k_xtal = {
> - .data = &(struct clk_regmap_gate_data){
> - .offset = RTC_BY_OSCIN_CTRL1,
> - .bit_idx = 24,
> - },
> - .hw.init = &(struct clk_init_data) {
> - .name = "rtc_32k_xtal",
> - .ops = &clk_regmap_gate_ops,
> - .parent_hws = (const struct clk_hw *[]) {
> - &a1_rtc_32k_clkin.hw
> - },
> - .num_parents = 1,
> - },
> -};
> -
> -static struct clk_regmap a1_rtc_32k_sel = {
> - .data = &(struct clk_regmap_mux_data) {
> - .offset = RTC_CTRL,
> - .mask = 0x3,
> - .shift = 0,
> - .flags = CLK_MUX_ROUND_CLOSEST,
> - },
> - .hw.init = &(struct clk_init_data){
> - .name = "rtc_32k_sel",
> - .ops = &clk_regmap_mux_ops,
> - .parent_hws = (const struct clk_hw *[]) {
> - &a1_rtc_32k_xtal.hw,
> - &a1_rtc_32k_div.hw,
> - },
> - .num_parents = 2,
> - .flags = CLK_SET_RATE_PARENT,
> - },
> -};
> -
> -struct clk_regmap a1_rtc_clk = {
> - .data = &(struct clk_regmap_gate_data){
> - .offset = RTC_BY_OSCIN_CTRL0,
> - .bit_idx = 30,
> - },
> - .hw.init = &(struct clk_init_data){
> - .name = "rtc_clk",
> - .ops = &clk_regmap_gate_ops,
> - .parent_hws = (const struct clk_hw *[]) {
> - &a1_rtc_32k_sel.hw
> - },
> - .num_parents = 1,
> - .flags = CLK_SET_RATE_PARENT,
> - },
> -};
> -
> static u32 mux_table_dsp_ab[] = { 0, 1, 2, 3, 4, 7 };
> static const struct clk_parent_data dsp_ab_clk_parent_data[] = {
> { .fw_name = "xtal", },
> @@ -475,9 +484,9 @@ static struct clk_regmap a1_dspa_sel = {
> .hw.init = &(struct clk_init_data){
> .name = "dspa_sel",
> .ops = &clk_regmap_mux_ops,
> - .parent_data = (const struct clk_parent_data []) {
> - { .hw = &a1_dspa_a.hw },
> - { .hw = &a1_dspa_b.hw },
> + .parent_hws = (const struct clk_hw *[]) {
> + &a1_dspa_a.hw,
> + &a1_dspa_b.hw,
> },
> .num_parents = 2,
> .flags = CLK_SET_RATE_PARENT,
> @@ -624,7 +633,8 @@ static struct clk_regmap a1_dspb_sel = {
> .name = "dspb_sel",
> .ops = &clk_regmap_mux_ops,
> .parent_hws = (const struct clk_hw *[]) {
> - &a1_dspb_a.hw, &a1_dspb_b.hw,
> + &a1_dspb_a.hw,
> + &a1_dspb_b.hw,
> },
> .num_parents = 2,
> .flags = CLK_SET_RATE_PARENT,
> @@ -852,6 +862,12 @@ static struct clk_regmap a1_saradc_clk = {
> },
> };
>
> +static const struct clk_parent_data pwm_abcd_parents[] = {
> + { .fw_name = "xtal", },
> + { .hw = &a1_sys_clk.hw },
> + { .hw = &a1_rtc_clk.hw },
> +};
> +
> static struct clk_regmap a1_pwm_a_sel = {
> .data = &(struct clk_regmap_mux_data){
> .offset = PWM_CLK_AB_CTRL,
> @@ -861,11 +877,8 @@ static struct clk_regmap a1_pwm_a_sel = {
> .hw.init = &(struct clk_init_data){
> .name = "pwm_a_sel",
> .ops = &clk_regmap_mux_ops,
> - .parent_data = (const struct clk_parent_data []) {
> - { .fw_name = "xtal", },
> - { .hw = &a1_sys_clk.hw, },
> - },
> - .num_parents = 2,
> + .parent_data = pwm_abcd_parents,
> + .num_parents = ARRAY_SIZE(pwm_abcd_parents),
> },
> };
>
> @@ -918,11 +931,8 @@ static struct clk_regmap a1_pwm_b_sel = {
> .hw.init = &(struct clk_init_data){
> .name = "pwm_b_sel",
> .ops = &clk_regmap_mux_ops,
> - .parent_data = (const struct clk_parent_data []) {
> - { .fw_name = "xtal", },
> - { .hw = &a1_sys_clk.hw, },
> - },
> - .num_parents = 2,
> + .parent_data = pwm_abcd_parents,
> + .num_parents = ARRAY_SIZE(pwm_abcd_parents),
> },
> };
>
> @@ -968,11 +978,8 @@ static struct clk_regmap a1_pwm_c_sel = {
> .hw.init = &(struct clk_init_data){
> .name = "pwm_c_sel",
> .ops = &clk_regmap_mux_ops,
> - .parent_data = (const struct clk_parent_data []) {
> - { .fw_name = "xtal", },
> - { .hw = &a1_sys_clk.hw, },
> - },
> - .num_parents = 2,
> + .parent_data = pwm_abcd_parents,
> + .num_parents = ARRAY_SIZE(pwm_abcd_parents),
> },
> };
>
> @@ -1018,11 +1025,8 @@ static struct clk_regmap a1_pwm_d_sel = {
> .hw.init = &(struct clk_init_data){
> .name = "pwm_d_sel",
> .ops = &clk_regmap_mux_ops,
> - .parent_data = (const struct clk_parent_data []) {
> - { .fw_name = "xtal", },
> - { .hw = &a1_sys_clk.hw, },
> - },
> - .num_parents = 2,
> + .parent_data = pwm_abcd_parents,
> + .num_parents = ARRAY_SIZE(pwm_abcd_parents),
> },
> };
>
> @@ -1059,7 +1063,7 @@ static struct clk_regmap a1_pwm_d = {
> },
> };
>
> -static const struct clk_parent_data pwm_ef_parent_data[] = {
> +static const struct clk_parent_data pwm_ef_parents[] = {
> { .fw_name = "xtal", },
> { .hw = &a1_sys_clk.hw },
> { .fw_name = "fclk_div5", },
> @@ -1075,8 +1079,8 @@ static struct clk_regmap a1_pwm_e_sel = {
> .hw.init = &(struct clk_init_data){
> .name = "pwm_e_sel",
> .ops = &clk_regmap_mux_ops,
> - .parent_data = pwm_ef_parent_data,
> - .num_parents = ARRAY_SIZE(pwm_ef_parent_data),
> + .parent_data = pwm_ef_parents,
> + .num_parents = ARRAY_SIZE(pwm_ef_parents),
> },
> };
>
> @@ -1122,8 +1126,8 @@ static struct clk_regmap a1_pwm_f_sel = {
> .hw.init = &(struct clk_init_data){
> .name = "pwm_f_sel",
> .ops = &clk_regmap_mux_ops,
> - .parent_data = pwm_ef_parent_data,
> - .num_parents = ARRAY_SIZE(pwm_ef_parent_data),
> + .parent_data = pwm_ef_parents,
> + .num_parents = ARRAY_SIZE(pwm_ef_parents),
> },
> };
>
> @@ -1169,7 +1173,7 @@ static struct clk_regmap a1_pwm_f = {
> * --------------------|/
> * 24M
> */
> -static const struct clk_parent_data spicc_parents[] = {
> +static const struct clk_parent_data spicc_spifc_parents[] = {
> { .fw_name = "fclk_div2"},
> { .fw_name = "fclk_div3"},
> { .fw_name = "fclk_div5"},
> @@ -1185,8 +1189,8 @@ static struct clk_regmap a1_spicc_sel = {
> .hw.init = &(struct clk_init_data){
> .name = "spicc_sel",
> .ops = &clk_regmap_mux_ops,
> - .parent_data = spicc_parents,
> - .num_parents = 4,
> + .parent_data = spicc_spifc_parents,
> + .num_parents = ARRAY_SIZE(spicc_spifc_parents),
> },
> };
>
> @@ -1282,9 +1286,8 @@ static struct clk_regmap a1_spifc_sel = {
> .hw.init = &(struct clk_init_data){
> .name = "spifc_sel",
> .ops = &clk_regmap_mux_ops,
> - /* the same parent with spicc */
> - .parent_data = spicc_parents,
> - .num_parents = 4,
> + .parent_data = spicc_spifc_parents,
> + .num_parents = ARRAY_SIZE(spicc_spifc_parents),
> },
> };
>
> @@ -1339,7 +1342,7 @@ static struct clk_regmap a1_spifc = {
> },
> };
>
> -static const struct clk_parent_data usb_bus_parent_data[] = {
> +static const struct clk_parent_data usb_bus_parents[] = {
> { .fw_name = "xtal", },
> { .hw = &a1_sys_clk.hw },
> { .fw_name = "fclk_div3", },
> @@ -1355,8 +1358,8 @@ static struct clk_regmap a1_usb_bus_sel = {
> .hw.init = &(struct clk_init_data){
> .name = "usb_bus_sel",
> .ops = &clk_regmap_mux_ops,
> - .parent_data = usb_bus_parent_data,
> - .num_parents = ARRAY_SIZE(usb_bus_parent_data),
> + .parent_data = usb_bus_parents,
> + .num_parents = ARRAY_SIZE(usb_bus_parents),
> .flags = CLK_SET_RATE_PARENT,
> },
> };
> @@ -1394,7 +1397,7 @@ static struct clk_regmap a1_usb_bus = {
> },
> };
>
> -static const struct clk_parent_data sd_emmc_parents[] = {
> +static const struct clk_parent_data sd_emmc_psram_dmc_parents[] = {
> { .fw_name = "fclk_div2", },
> { .fw_name = "fclk_div3", },
> { .fw_name = "fclk_div5", },
> @@ -1410,8 +1413,8 @@ static struct clk_regmap a1_sd_emmc_sel = {
> .hw.init = &(struct clk_init_data){
> .name = "sd_emmc_sel",
> .ops = &clk_regmap_mux_ops,
> - .parent_data = sd_emmc_parents,
> - .num_parents = 4,
> + .parent_data = sd_emmc_psram_dmc_parents,
> + .num_parents = ARRAY_SIZE(sd_emmc_psram_dmc_parents),
> },
> };
>
> @@ -1475,9 +1478,8 @@ static struct clk_regmap a1_psram_sel = {
> .hw.init = &(struct clk_init_data){
> .name = "psram_sel",
> .ops = &clk_regmap_mux_ops,
> - /* the same parent with sd_emmc */
> - .parent_data = sd_emmc_parents,
> - .num_parents = 4,
> + .parent_data = sd_emmc_psram_dmc_parents,
> + .num_parents = ARRAY_SIZE(sd_emmc_psram_dmc_parents),
> },
> };
>
> @@ -1541,8 +1543,8 @@ static struct clk_regmap a1_dmc_sel = {
> .hw.init = &(struct clk_init_data){
> .name = "dmc_sel",
> .ops = &clk_regmap_mux_ops,
> - .parent_data = sd_emmc_parents,
> - .num_parents = 4,
> + .parent_data = sd_emmc_psram_dmc_parents,
> + .num_parents = ARRAY_SIZE(sd_emmc_psram_dmc_parents),
> },
> };
>
> @@ -1873,13 +1875,6 @@ static MESON_GATE(a1_prod_i2c, AXI_CLK_EN, 12);
> /* Array of all clocks provided by this provider */
> static struct clk_hw_onecell_data a1_periphs_hw_onecell_data = {
> .hws = {
> - [CLKID_SYS_B_SEL] = &a1_sys_b_sel.hw,
> - [CLKID_SYS_B_DIV] = &a1_sys_b_div.hw,
> - [CLKID_SYS_B] = &a1_sys_b.hw,
> - [CLKID_SYS_A_SEL] = &a1_sys_a_sel.hw,
> - [CLKID_SYS_A_DIV] = &a1_sys_a_div.hw,
> - [CLKID_SYS_A] = &a1_sys_a.hw,
> - [CLKID_SYS_CLK] = &a1_sys_clk.hw,
> [CLKID_XTAL_CLKTREE] = &a1_xtal_clktree.hw,
> [CLKID_XTAL_FIXPLL] = &a1_xtal_fixpll.hw,
> [CLKID_XTAL_USB_PHY] = &a1_xtal_usb_phy.hw,
> @@ -1887,6 +1882,7 @@ static struct clk_hw_onecell_data a1_periphs_hw_onecell_data = {
> [CLKID_XTAL_HIFIPLL] = &a1_xtal_hifipll.hw,
> [CLKID_XTAL_SYSPLL] = &a1_xtal_syspll.hw,
> [CLKID_XTAL_DDS] = &a1_xtal_dds.hw,
> + [CLKID_SYS_CLK] = &a1_sys_clk.hw,
> [CLKID_CLKTREE] = &a1_clk_tree.hw,
> [CLKID_RESET_CTRL] = &a1_reset_ctrl.hw,
> [CLKID_ANALOG_CTRL] = &a1_analog_ctrl.hw,
> @@ -1940,93 +1936,99 @@ static struct clk_hw_onecell_data a1_periphs_hw_onecell_data = {
> [CLKID_CPU_CTRL] = &a1_cpu_ctrl.hw,
> [CLKID_ROM] = &a1_rom.hw,
> [CLKID_PROC_I2C] = &a1_prod_i2c.hw,
> + [CLKID_DSPA_SEL] = &a1_dspa_sel.hw,
> + [CLKID_DSPB_SEL] = &a1_dspb_sel.hw,
> + [CLKID_DSPA_EN] = &a1_dspa_en.hw,
> + [CLKID_DSPA_EN_NIC] = &a1_dspa_en_nic.hw,
> + [CLKID_DSPB_EN] = &a1_dspb_en.hw,
> + [CLKID_DSPB_EN_NIC] = &a1_dspb_en_nic.hw,
> + [CLKID_RTC_CLK] = &a1_rtc_clk.hw,
> + [CLKID_CECA_32K] = &a1_ceca_32k_clkout.hw,
> + [CLKID_CECB_32K] = &a1_cecb_32k_clkout.hw,
> + [CLKID_24M] = &a1_24m.hw,
> + [CLKID_12M] = &a1_12m.hw,
> + [CLKID_FCLK_DIV2_DIVN] = &a1_fclk_div2_divn.hw,
> + [CLKID_GEN] = &a1_gen.hw,
> + [CLKID_SARADC_SEL] = &a1_saradc_sel.hw,
> + [CLKID_SARADC_CLK] = &a1_saradc_clk.hw,
> + [CLKID_PWM_A] = &a1_pwm_a.hw,
> + [CLKID_PWM_B] = &a1_pwm_b.hw,
> + [CLKID_PWM_C] = &a1_pwm_c.hw,
> + [CLKID_PWM_D] = &a1_pwm_d.hw,
> + [CLKID_PWM_E] = &a1_pwm_e.hw,
> + [CLKID_PWM_F] = &a1_pwm_f.hw,
> + [CLKID_SPICC] = &a1_spicc.hw,
> + [CLKID_TS] = &a1_ts.hw,
> + [CLKID_SPIFC] = &a1_spifc.hw,
> + [CLKID_USB_BUS] = &a1_usb_bus.hw,
> + [CLKID_SD_EMMC] = &a1_sd_emmc.hw,
> + [CLKID_PSRAM] = &a1_psram.hw,
> + [CLKID_DMC] = &a1_dmc.hw,
> + [CLKID_SYS_A_SEL] = &a1_sys_a_sel.hw,
> + [CLKID_SYS_A_DIV] = &a1_sys_a_div.hw,
> + [CLKID_SYS_A] = &a1_sys_a.hw,
> + [CLKID_SYS_B_SEL] = &a1_sys_b_sel.hw,
> + [CLKID_SYS_B_DIV] = &a1_sys_b_div.hw,
> + [CLKID_SYS_B] = &a1_sys_b.hw,
> [CLKID_DSPA_A_SEL] = &a1_dspa_a_sel.hw,
> [CLKID_DSPA_A_DIV] = &a1_dspa_a_div.hw,
> [CLKID_DSPA_A] = &a1_dspa_a.hw,
> [CLKID_DSPA_B_SEL] = &a1_dspa_b_sel.hw,
> [CLKID_DSPA_B_DIV] = &a1_dspa_b_div.hw,
> [CLKID_DSPA_B] = &a1_dspa_b.hw,
> - [CLKID_DSPA_SEL] = &a1_dspa_sel.hw,
> [CLKID_DSPB_A_SEL] = &a1_dspb_a_sel.hw,
> [CLKID_DSPB_A_DIV] = &a1_dspb_a_div.hw,
> [CLKID_DSPB_A] = &a1_dspb_a.hw,
> [CLKID_DSPB_B_SEL] = &a1_dspb_b_sel.hw,
> [CLKID_DSPB_B_DIV] = &a1_dspb_b_div.hw,
> [CLKID_DSPB_B] = &a1_dspb_b.hw,
> - [CLKID_DSPB_SEL] = &a1_dspb_sel.hw,
> - [CLKID_DSPA_EN] = &a1_dspa_en.hw,
> - [CLKID_DSPA_EN_NIC] = &a1_dspa_en_nic.hw,
> - [CLKID_DSPB_EN] = &a1_dspb_en.hw,
> - [CLKID_DSPB_EN_NIC] = &a1_dspb_en_nic.hw,
> - [CLKID_24M] = &a1_24m.hw,
> - [CLKID_24M_DIV2] = &a1_24m_div2.hw,
> - [CLKID_12M] = &a1_12m.hw,
> + [CLKID_RTC_32K_CLKIN] = &a1_rtc_32k_clkin.hw,
> + [CLKID_RTC_32K_DIV] = &a1_rtc_32k_div.hw,
> + [CLKID_RTC_32K_XTAL] = &a1_rtc_32k_xtal.hw,
> + [CLKID_RTC_32K_SEL] = &a1_rtc_32k_sel.hw,
> + [CLKID_CECB_32K_CLKIN] = &a1_cecb_32k_clkin.hw,
> + [CLKID_CECB_32K_DIV] = &a1_cecb_32k_div.hw,
> + [CLKID_CECB_32K_SEL_PRE] = &a1_cecb_32k_sel_pre.hw,
> + [CLKID_CECB_32K_SEL] = &a1_cecb_32k_sel.hw,
> + [CLKID_CECA_32K_CLKIN] = &a1_ceca_32k_clkin.hw,
> + [CLKID_CECA_32K_DIV] = &a1_ceca_32k_div.hw,
> + [CLKID_CECA_32K_SEL_PRE] = &a1_ceca_32k_sel_pre.hw,
> + [CLKID_CECA_32K_SEL] = &a1_ceca_32k_sel.hw,
> [CLKID_DIV2_PRE] = &a1_fclk_div2_divn_pre.hw,
> - [CLKID_FCLK_DIV2_DIVN] = &a1_fclk_div2_divn.hw,
> + [CLKID_24M_DIV2] = &a1_24m_div2.hw,
> [CLKID_GEN_SEL] = &a1_gen_sel.hw,
> [CLKID_GEN_DIV] = &a1_gen_div.hw,
> - [CLKID_GEN] = &a1_gen.hw,
> - [CLKID_SARADC_SEL] = &a1_saradc_sel.hw,
> [CLKID_SARADC_DIV] = &a1_saradc_div.hw,
> - [CLKID_SARADC_CLK] = &a1_saradc_clk.hw,
> [CLKID_PWM_A_SEL] = &a1_pwm_a_sel.hw,
> [CLKID_PWM_A_DIV] = &a1_pwm_a_div.hw,
> - [CLKID_PWM_A] = &a1_pwm_a.hw,
> [CLKID_PWM_B_SEL] = &a1_pwm_b_sel.hw,
> [CLKID_PWM_B_DIV] = &a1_pwm_b_div.hw,
> - [CLKID_PWM_B] = &a1_pwm_b.hw,
> [CLKID_PWM_C_SEL] = &a1_pwm_c_sel.hw,
> [CLKID_PWM_C_DIV] = &a1_pwm_c_div.hw,
> - [CLKID_PWM_C] = &a1_pwm_c.hw,
> [CLKID_PWM_D_SEL] = &a1_pwm_d_sel.hw,
> [CLKID_PWM_D_DIV] = &a1_pwm_d_div.hw,
> - [CLKID_PWM_D] = &a1_pwm_d.hw,
> [CLKID_PWM_E_SEL] = &a1_pwm_e_sel.hw,
> [CLKID_PWM_E_DIV] = &a1_pwm_e_div.hw,
> - [CLKID_PWM_E] = &a1_pwm_e.hw,
> [CLKID_PWM_F_SEL] = &a1_pwm_f_sel.hw,
> [CLKID_PWM_F_DIV] = &a1_pwm_f_div.hw,
> - [CLKID_PWM_F] = &a1_pwm_f.hw,
> [CLKID_SPICC_SEL] = &a1_spicc_sel.hw,
> [CLKID_SPICC_DIV] = &a1_spicc_div.hw,
> [CLKID_SPICC_SEL2] = &a1_spicc_sel2.hw,
> - [CLKID_SPICC] = &a1_spicc.hw,
> [CLKID_TS_DIV] = &a1_ts_div.hw,
> - [CLKID_TS] = &a1_ts.hw,
> [CLKID_SPIFC_SEL] = &a1_spifc_sel.hw,
> [CLKID_SPIFC_DIV] = &a1_spifc_div.hw,
> [CLKID_SPIFC_SEL2] = &a1_spifc_sel2.hw,
> - [CLKID_SPIFC] = &a1_spifc.hw,
> [CLKID_USB_BUS_SEL] = &a1_usb_bus_sel.hw,
> [CLKID_USB_BUS_DIV] = &a1_usb_bus_div.hw,
> - [CLKID_USB_BUS] = &a1_usb_bus.hw,
> [CLKID_SD_EMMC_SEL] = &a1_sd_emmc_sel.hw,
> [CLKID_SD_EMMC_DIV] = &a1_sd_emmc_div.hw,
> [CLKID_SD_EMMC_SEL2] = &a1_sd_emmc_sel2.hw,
> - [CLKID_SD_EMMC] = &a1_sd_emmc.hw,
> [CLKID_PSRAM_SEL] = &a1_psram_sel.hw,
> [CLKID_PSRAM_DIV] = &a1_psram_div.hw,
> [CLKID_PSRAM_SEL2] = &a1_psram_sel2.hw,
> - [CLKID_PSRAM] = &a1_psram.hw,
> [CLKID_DMC_SEL] = &a1_dmc_sel.hw,
> [CLKID_DMC_DIV] = &a1_dmc_div.hw,
> [CLKID_DMC_SEL2] = &a1_dmc_sel2.hw,
> - [CLKID_DMC] = &a1_dmc.hw,
> - [CLKID_RTC_32K_CLKIN] = &a1_rtc_32k_clkin.hw,
> - [CLKID_RTC_32K_DIV] = &a1_rtc_32k_div.hw,
> - [CLKID_RTC_32K_XTAL] = &a1_rtc_32k_xtal.hw,
> - [CLKID_RTC_32K_SEL] = &a1_rtc_32k_sel.hw,
> - [CLKID_RTC_CLK] = &a1_rtc_clk.hw,
> - [CLKID_CECA_32K_CLKIN] = &a1_ceca_32k_clkin.hw,
> - [CLKID_CECA_32K_DIV] = &a1_ceca_32k_div.hw,
> - [CLKID_CECA_32K_SEL_PRE] = &a1_ceca_32k_sel_pre.hw,
> - [CLKID_CECA_32K_SEL] = &a1_ceca_32k_sel.hw,
> - [CLKID_CECA_32K] = &a1_ceca_32k_clkout.hw,
> - [CLKID_CECB_32K_CLKIN] = &a1_cecb_32k_clkin.hw,
> - [CLKID_CECB_32K_DIV] = &a1_cecb_32k_div.hw,
> - [CLKID_CECB_32K_SEL_PRE] = &a1_cecb_32k_sel_pre.hw,
> - [CLKID_CECB_32K_SEL] = &a1_cecb_32k_sel.hw,
> - [CLKID_CECB_32K] = &a1_cecb_32k_clkout.hw,
> [NR_CLKS] = NULL,
> },
Please avoid this ordering change - It is borderline impossible to
review.
Keep the ID Order
> .num = NR_CLKS,
> @@ -2041,10 +2043,12 @@ static struct clk_regmap *const a1_periphs_regmaps[] = {
> &a1_xtal_hifipll,
> &a1_xtal_syspll,
> &a1_xtal_dds,
> + &a1_sys_clk,
> &a1_clk_tree,
> &a1_reset_ctrl,
> &a1_analog_ctrl,
> &a1_pwr_ctrl,
> + &a1_pad_ctrl,
> &a1_sys_ctrl,
> &a1_temp_sensor,
> &a1_am2axi_dev,
> @@ -2093,157 +2097,126 @@ static struct clk_regmap *const a1_periphs_regmaps[] = {
> &a1_cpu_ctrl,
> &a1_rom,
> &a1_prod_i2c,
> + &a1_dspa_sel,
> + &a1_dspb_sel,
> + &a1_dspa_en,
> + &a1_dspa_en_nic,
> + &a1_dspb_en,
> + &a1_dspb_en_nic,
> + &a1_rtc_clk,
> + &a1_ceca_32k_clkout,
> + &a1_cecb_32k_clkout,
> + &a1_24m,
> + &a1_12m,
> + &a1_fclk_div2_divn,
> + &a1_gen,
> + &a1_saradc_sel,
> + &a1_saradc_clk,
> + &a1_pwm_a,
> + &a1_pwm_b,
> + &a1_pwm_c,
> + &a1_pwm_d,
> + &a1_pwm_e,
> + &a1_pwm_f,
> + &a1_spicc,
> + &a1_ts,
> + &a1_spifc,
> + &a1_usb_bus,
> + &a1_sd_emmc,
> + &a1_psram,
> + &a1_dmc,
> + &a1_sys_a_sel,
> + &a1_sys_a_div,
> + &a1_sys_a,
> + &a1_sys_b_sel,
> + &a1_sys_b_div,
> + &a1_sys_b,
> &a1_dspa_a_sel,
> &a1_dspa_a_div,
> &a1_dspa_a,
> &a1_dspa_b_sel,
> &a1_dspa_b_div,
> &a1_dspa_b,
> - &a1_dspa_sel,
> &a1_dspb_a_sel,
> &a1_dspb_a_div,
> &a1_dspb_a,
> &a1_dspb_b_sel,
> &a1_dspb_b_div,
> &a1_dspb_b,
> - &a1_dspb_sel,
> - &a1_dspa_en,
> - &a1_dspa_en_nic,
> - &a1_dspb_en,
> - &a1_dspb_en_nic,
> - &a1_24m,
> - &a1_12m,
> + &a1_rtc_32k_clkin,
> + &a1_rtc_32k_div,
> + &a1_rtc_32k_xtal,
> + &a1_rtc_32k_sel,
> + &a1_cecb_32k_clkin,
> + &a1_cecb_32k_div,
> + &a1_cecb_32k_sel_pre,
> + &a1_cecb_32k_sel,
> + &a1_ceca_32k_clkin,
> + &a1_ceca_32k_div,
> + &a1_ceca_32k_sel_pre,
> + &a1_ceca_32k_sel,
> &a1_fclk_div2_divn_pre,
> - &a1_fclk_div2_divn,
> &a1_gen_sel,
> &a1_gen_div,
> - &a1_gen,
> - &a1_saradc_sel,
> &a1_saradc_div,
> - &a1_saradc_clk,
> &a1_pwm_a_sel,
> &a1_pwm_a_div,
> - &a1_pwm_a,
> &a1_pwm_b_sel,
> &a1_pwm_b_div,
> - &a1_pwm_b,
> &a1_pwm_c_sel,
> &a1_pwm_c_div,
> - &a1_pwm_c,
> &a1_pwm_d_sel,
> &a1_pwm_d_div,
> - &a1_pwm_d,
> &a1_pwm_e_sel,
> &a1_pwm_e_div,
> - &a1_pwm_e,
> &a1_pwm_f_sel,
> &a1_pwm_f_div,
> - &a1_pwm_f,
> &a1_spicc_sel,
> &a1_spicc_div,
> &a1_spicc_sel2,
> - &a1_spicc,
> &a1_ts_div,
> - &a1_ts,
> &a1_spifc_sel,
> &a1_spifc_div,
> &a1_spifc_sel2,
> - &a1_spifc,
> &a1_usb_bus_sel,
> &a1_usb_bus_div,
> - &a1_usb_bus,
> &a1_sd_emmc_sel,
> &a1_sd_emmc_div,
> &a1_sd_emmc_sel2,
> - &a1_sd_emmc,
> &a1_psram_sel,
> &a1_psram_div,
> &a1_psram_sel2,
> - &a1_psram,
> &a1_dmc_sel,
> &a1_dmc_div,
> &a1_dmc_sel2,
> - &a1_dmc,
> - &a1_sys_b_sel,
> - &a1_sys_b_div,
> - &a1_sys_b,
> - &a1_sys_a_sel,
> - &a1_sys_a_div,
> - &a1_sys_a,
> - &a1_sys_clk,
> - &a1_rtc_32k_clkin,
> - &a1_rtc_32k_div,
> - &a1_rtc_32k_xtal,
> - &a1_rtc_32k_sel,
> - &a1_rtc_clk,
> - &a1_ceca_32k_clkin,
> - &a1_ceca_32k_div,
> - &a1_ceca_32k_sel_pre,
> - &a1_ceca_32k_sel,
> - &a1_ceca_32k_clkout,
> - &a1_cecb_32k_clkin,
> - &a1_cecb_32k_div,
> - &a1_cecb_32k_sel_pre,
> - &a1_cecb_32k_sel,
> - &a1_cecb_32k_clkout,
> };
>
> -static struct regmap_config clkc_regmap_config = {
> - .reg_bits = 32,
> - .val_bits = 32,
> - .reg_stride = 4,
> +static const struct meson_a1_clkc_data a1_periphs_clkc __maybe_unused = {
> + .hw = &a1_periphs_hw_onecell_data,
> + .regs = a1_periphs_regmaps,
> + .num_regs = ARRAY_SIZE(a1_periphs_regmaps),
> };
>
> -static int meson_a1_periphs_probe(struct platform_device *pdev)
> -{
> - struct device *dev = &pdev->dev;
> - struct resource *res;
> - void __iomem *base;
> - struct regmap *map;
> - int ret, i;
> -
> - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -
> - base = devm_ioremap_resource(dev, res);
> - if (IS_ERR(base))
> - return PTR_ERR(base);
> -
> - map = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
> - if (IS_ERR(map))
> - return PTR_ERR(map);
> -
> - /* Populate regmap for the regmap backed clocks */
> - for (i = 0; i < ARRAY_SIZE(a1_periphs_regmaps); i++)
> - a1_periphs_regmaps[i]->map = map;
> -
> - for (i = 0; i < a1_periphs_hw_onecell_data.num; i++) {
> - /* array might be sparse */
> - if (!a1_periphs_hw_onecell_data.hws[i])
> - continue;
> -
> - ret = devm_clk_hw_register(dev,
> - a1_periphs_hw_onecell_data.hws[i]);
> - if (ret) {
> - dev_err(dev, "Clock registration failed\n");
> - return ret;
> - }
> - }
> -
> - return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> - &a1_periphs_hw_onecell_data);
> -}
> -
> -static const struct of_device_id clkc_match_table[] = {
> - { .compatible = "amlogic,a1-periphs-clkc", },
> - {}
> +#ifdef CONFIG_OF
> +static const struct of_device_id a1_periphs_clkc_match_table[] = {
> + {
> + .compatible = "amlogic,a1-periphs-clkc",
> + .data = &a1_periphs_clkc,
> + },
> + {},
> };
> +MODULE_DEVICE_TABLE(of, a1_periphs_clkc_match_table);
> +#endif /* CONFIG_OF */
>
> -static struct platform_driver a1_periphs_driver = {
> - .probe = meson_a1_periphs_probe,
> - .driver = {
> - .name = "a1-periphs-clkc",
> - .of_match_table = clkc_match_table,
> +static struct platform_driver a1_periphs_clkc_driver = {
> + .probe = meson_a1_clkc_probe,
> + .driver = {
> + .name = "a1-periphs-clkc",
> + .of_match_table = of_match_ptr(a1_periphs_clkc_match_table),
> },
> };
>
> -builtin_platform_driver(a1_periphs_driver);
> +module_platform_driver(a1_periphs_clkc_driver);
> +MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>");
> +MODULE_AUTHOR("Dmitry Rokosov <ddrokosov@sberdevices.ru>");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/clk/meson/a1.h b/drivers/clk/meson/a1.h
> index 1ae5e04848d6..94b155e33568 100644
> --- a/drivers/clk/meson/a1.h
> +++ b/drivers/clk/meson/a1.h
> @@ -1,6 +1,12 @@
> /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> /*
> + * Amlogic Meson-A1 Peripheral Clock Controller internals
> + *
> * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
> + * Author: Jian Hu <jian.hu@amlogic.com>
> + *
> + * Copyright (c) 2022, SberDevices. All Rights Reserved.
> + * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> */
>
> #ifndef __A1_H
> @@ -12,7 +18,6 @@
> #define RTC_BY_OSCIN_CTRL1 0x8
> #define RTC_CTRL 0xc
> #define SYS_CLK_CTRL0 0x10
> -#define AXI_CLK_CTRL0 0x14
> #define SYS_CLK_EN0 0x1c
> #define SYS_CLK_EN1 0x20
> #define AXI_CLK_EN 0x24
> @@ -22,13 +27,6 @@
> #define DSPB_CLK_CTRL0 0x34
> #define CLK12_24_CTRL 0x38
> #define GEN_CLK_CTRL 0x3c
> -#define TIMESTAMP_CTRL0 0x40
> -#define TIMESTAMP_CTRL1 0x44
> -#define TIMESTAMP_CTRL2 0x48
> -#define TIMESTAMP_VAL0 0x4c
> -#define TIMESTAMP_VAL1 0x50
> -#define TIMEBASE_CTRL0 0x54
> -#define TIMEBASE_CTRL1 0x58
> #define SAR_ADC_CLK_CTRL 0xc0
> #define PWM_CLK_AB_CTRL 0xc4
> #define PWM_CLK_CD_CTRL 0xc8
> @@ -44,8 +42,6 @@
> #define CECB_CLK_CTRL1 0xf0
> #define PSRAM_CLK_CTRL 0xf4
> #define DMC_CLK_CTRL 0xf8
> -#define FCLK_DIV1_SEL 0xfc
> -#define TST_CTRL 0x100
>
> #define CLKID_XTAL_CLKTREE 0
> #define CLKID_SYS_A_SEL 89
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^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 11/11] arm64: dts: meson: a1: introduce PLL and Peripherals clk controllers
2022-12-01 22:57 ` [PATCH v8 11/11] arm64: dts: meson: a1: introduce PLL and Peripherals clk controllers Dmitry Rokosov
2022-12-02 10:43 ` Krzysztof Kozlowski
@ 2022-12-02 12:03 ` Jerome Brunet
2022-12-02 13:37 ` neil.armstrong
1 sibling, 1 reply; 45+ messages in thread
From: Jerome Brunet @ 2022-12-02 12:03 UTC (permalink / raw)
To: Dmitry Rokosov, neil.armstrong, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
On Fri 02 Dec 2022 at 01:57, Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
> This patch adds clkc_periphs and clkc_pll dts nodes to A1 SoC main dtsi.
> The first one clk controller is responsible for all SoC peripherals
> clocks excluding audio clocks. The second one clk controller is used by
> A1 SoC PLLs. Actually, there are two different APB heads, so we have two
> different drivers.
Please send this change through a separate patcheset.
One patcheset/series for clk (and bindings)
Another one for the DTS (usually sent after the first one is accepted)
>
> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> ---
> arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 27 ++++++++++++++++++++++-
> 1 file changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> index b4000cf65a9a..38e6517c603c 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> @@ -6,6 +6,8 @@
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/gpio/meson-a1-gpio.h>
> +#include <dt-bindings/clock/a1-pll-clkc.h>
> +#include <dt-bindings/clock/a1-clkc.h>
>
> / {
> compatible = "amlogic,a1";
> @@ -81,7 +83,6 @@ apb: bus@fe000000 {
> #size-cells = <2>;
> ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
>
> -
> reset: reset-controller@0 {
> compatible = "amlogic,meson-a1-reset";
> reg = <0x0 0x0 0x0 0x8c>;
> @@ -124,6 +125,30 @@ uart_AO_B: serial@2000 {
> clock-names = "xtal", "pclk", "baud";
> status = "disabled";
> };
> +
> + clkc_periphs: periphs-clock-controller@800 {
device name should be generic so
clkc_periphs: clock-controller@800 would be better
> + compatible = "amlogic,a1-periphs-clkc";
> + reg = <0 0x800 0 0x104>;
> + #clock-cells = <1>;
> + clocks = <&clkc_pll CLKID_FCLK_DIV2>,
> + <&clkc_pll CLKID_FCLK_DIV3>,
> + <&clkc_pll CLKID_FCLK_DIV5>,
> + <&clkc_pll CLKID_FCLK_DIV7>,
> + <&clkc_pll CLKID_HIFI_PLL>,
> + <&xtal>;
> + clock-names = "fclk_div2", "fclk_div3",
> + "fclk_div5", "fclk_div7",
> + "hifi_pll", "xtal";
> + };
> +
> + clkc_pll: pll-clock-controller@7c80 {
Same here
> + compatible = "amlogic,a1-pll-clkc";
> + reg = <0 0x7c80 0 0x18c>;
> + #clock-cells = <1>;
> + clocks = <&clkc_periphs CLKID_XTAL_FIXPLL>,
> + <&clkc_periphs CLKID_XTAL_HIFIPLL>;
> + clock-names = "xtal_fixpll", "xtal_hifipll";
> + };
> };
>
> gic: interrupt-controller@ff901000 {
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^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 09/11] clk: meson: redesign A1 Peripherals CLK controller
2022-12-02 12:01 ` Jerome Brunet
@ 2022-12-02 12:10 ` Dmitry Rokosov
0 siblings, 0 replies; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-02 12:10 UTC (permalink / raw)
To: Jerome Brunet
Cc: neil.armstrong, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl, jian.hu,
kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
...
> > @@ -1873,13 +1875,6 @@ static MESON_GATE(a1_prod_i2c, AXI_CLK_EN, 12);
> > /* Array of all clocks provided by this provider */
> > static struct clk_hw_onecell_data a1_periphs_hw_onecell_data = {
> > .hws = {
> > - [CLKID_SYS_B_SEL] = &a1_sys_b_sel.hw,
> > - [CLKID_SYS_B_DIV] = &a1_sys_b_div.hw,
> > - [CLKID_SYS_B] = &a1_sys_b.hw,
> > - [CLKID_SYS_A_SEL] = &a1_sys_a_sel.hw,
> > - [CLKID_SYS_A_DIV] = &a1_sys_a_div.hw,
> > - [CLKID_SYS_A] = &a1_sys_a.hw,
> > - [CLKID_SYS_CLK] = &a1_sys_clk.hw,
> > [CLKID_XTAL_CLKTREE] = &a1_xtal_clktree.hw,
> > [CLKID_XTAL_FIXPLL] = &a1_xtal_fixpll.hw,
> > [CLKID_XTAL_USB_PHY] = &a1_xtal_usb_phy.hw,
> > @@ -1887,6 +1882,7 @@ static struct clk_hw_onecell_data a1_periphs_hw_onecell_data = {
> > [CLKID_XTAL_HIFIPLL] = &a1_xtal_hifipll.hw,
> > [CLKID_XTAL_SYSPLL] = &a1_xtal_syspll.hw,
> > [CLKID_XTAL_DDS] = &a1_xtal_dds.hw,
> > + [CLKID_SYS_CLK] = &a1_sys_clk.hw,
> > [CLKID_CLKTREE] = &a1_clk_tree.hw,
> > [CLKID_RESET_CTRL] = &a1_reset_ctrl.hw,
> > [CLKID_ANALOG_CTRL] = &a1_analog_ctrl.hw,
> > @@ -1940,93 +1936,99 @@ static struct clk_hw_onecell_data a1_periphs_hw_onecell_data = {
> > [CLKID_CPU_CTRL] = &a1_cpu_ctrl.hw,
> > [CLKID_ROM] = &a1_rom.hw,
> > [CLKID_PROC_I2C] = &a1_prod_i2c.hw,
> > + [CLKID_DSPA_SEL] = &a1_dspa_sel.hw,
> > + [CLKID_DSPB_SEL] = &a1_dspb_sel.hw,
> > + [CLKID_DSPA_EN] = &a1_dspa_en.hw,
> > + [CLKID_DSPA_EN_NIC] = &a1_dspa_en_nic.hw,
> > + [CLKID_DSPB_EN] = &a1_dspb_en.hw,
> > + [CLKID_DSPB_EN_NIC] = &a1_dspb_en_nic.hw,
> > + [CLKID_RTC_CLK] = &a1_rtc_clk.hw,
> > + [CLKID_CECA_32K] = &a1_ceca_32k_clkout.hw,
> > + [CLKID_CECB_32K] = &a1_cecb_32k_clkout.hw,
> > + [CLKID_24M] = &a1_24m.hw,
> > + [CLKID_12M] = &a1_12m.hw,
> > + [CLKID_FCLK_DIV2_DIVN] = &a1_fclk_div2_divn.hw,
> > + [CLKID_GEN] = &a1_gen.hw,
> > + [CLKID_SARADC_SEL] = &a1_saradc_sel.hw,
> > + [CLKID_SARADC_CLK] = &a1_saradc_clk.hw,
> > + [CLKID_PWM_A] = &a1_pwm_a.hw,
> > + [CLKID_PWM_B] = &a1_pwm_b.hw,
> > + [CLKID_PWM_C] = &a1_pwm_c.hw,
> > + [CLKID_PWM_D] = &a1_pwm_d.hw,
> > + [CLKID_PWM_E] = &a1_pwm_e.hw,
> > + [CLKID_PWM_F] = &a1_pwm_f.hw,
> > + [CLKID_SPICC] = &a1_spicc.hw,
> > + [CLKID_TS] = &a1_ts.hw,
> > + [CLKID_SPIFC] = &a1_spifc.hw,
> > + [CLKID_USB_BUS] = &a1_usb_bus.hw,
> > + [CLKID_SD_EMMC] = &a1_sd_emmc.hw,
> > + [CLKID_PSRAM] = &a1_psram.hw,
> > + [CLKID_DMC] = &a1_dmc.hw,
> > + [CLKID_SYS_A_SEL] = &a1_sys_a_sel.hw,
> > + [CLKID_SYS_A_DIV] = &a1_sys_a_div.hw,
> > + [CLKID_SYS_A] = &a1_sys_a.hw,
> > + [CLKID_SYS_B_SEL] = &a1_sys_b_sel.hw,
> > + [CLKID_SYS_B_DIV] = &a1_sys_b_div.hw,
> > + [CLKID_SYS_B] = &a1_sys_b.hw,
> > [CLKID_DSPA_A_SEL] = &a1_dspa_a_sel.hw,
> > [CLKID_DSPA_A_DIV] = &a1_dspa_a_div.hw,
> > [CLKID_DSPA_A] = &a1_dspa_a.hw,
> > [CLKID_DSPA_B_SEL] = &a1_dspa_b_sel.hw,
> > [CLKID_DSPA_B_DIV] = &a1_dspa_b_div.hw,
> > [CLKID_DSPA_B] = &a1_dspa_b.hw,
> > - [CLKID_DSPA_SEL] = &a1_dspa_sel.hw,
> > [CLKID_DSPB_A_SEL] = &a1_dspb_a_sel.hw,
> > [CLKID_DSPB_A_DIV] = &a1_dspb_a_div.hw,
> > [CLKID_DSPB_A] = &a1_dspb_a.hw,
> > [CLKID_DSPB_B_SEL] = &a1_dspb_b_sel.hw,
> > [CLKID_DSPB_B_DIV] = &a1_dspb_b_div.hw,
> > [CLKID_DSPB_B] = &a1_dspb_b.hw,
> > - [CLKID_DSPB_SEL] = &a1_dspb_sel.hw,
> > - [CLKID_DSPA_EN] = &a1_dspa_en.hw,
> > - [CLKID_DSPA_EN_NIC] = &a1_dspa_en_nic.hw,
> > - [CLKID_DSPB_EN] = &a1_dspb_en.hw,
> > - [CLKID_DSPB_EN_NIC] = &a1_dspb_en_nic.hw,
> > - [CLKID_24M] = &a1_24m.hw,
> > - [CLKID_24M_DIV2] = &a1_24m_div2.hw,
> > - [CLKID_12M] = &a1_12m.hw,
> > + [CLKID_RTC_32K_CLKIN] = &a1_rtc_32k_clkin.hw,
> > + [CLKID_RTC_32K_DIV] = &a1_rtc_32k_div.hw,
> > + [CLKID_RTC_32K_XTAL] = &a1_rtc_32k_xtal.hw,
> > + [CLKID_RTC_32K_SEL] = &a1_rtc_32k_sel.hw,
> > + [CLKID_CECB_32K_CLKIN] = &a1_cecb_32k_clkin.hw,
> > + [CLKID_CECB_32K_DIV] = &a1_cecb_32k_div.hw,
> > + [CLKID_CECB_32K_SEL_PRE] = &a1_cecb_32k_sel_pre.hw,
> > + [CLKID_CECB_32K_SEL] = &a1_cecb_32k_sel.hw,
> > + [CLKID_CECA_32K_CLKIN] = &a1_ceca_32k_clkin.hw,
> > + [CLKID_CECA_32K_DIV] = &a1_ceca_32k_div.hw,
> > + [CLKID_CECA_32K_SEL_PRE] = &a1_ceca_32k_sel_pre.hw,
> > + [CLKID_CECA_32K_SEL] = &a1_ceca_32k_sel.hw,
> > [CLKID_DIV2_PRE] = &a1_fclk_div2_divn_pre.hw,
> > - [CLKID_FCLK_DIV2_DIVN] = &a1_fclk_div2_divn.hw,
> > + [CLKID_24M_DIV2] = &a1_24m_div2.hw,
> > [CLKID_GEN_SEL] = &a1_gen_sel.hw,
> > [CLKID_GEN_DIV] = &a1_gen_div.hw,
> > - [CLKID_GEN] = &a1_gen.hw,
> > - [CLKID_SARADC_SEL] = &a1_saradc_sel.hw,
> > [CLKID_SARADC_DIV] = &a1_saradc_div.hw,
> > - [CLKID_SARADC_CLK] = &a1_saradc_clk.hw,
> > [CLKID_PWM_A_SEL] = &a1_pwm_a_sel.hw,
> > [CLKID_PWM_A_DIV] = &a1_pwm_a_div.hw,
> > - [CLKID_PWM_A] = &a1_pwm_a.hw,
> > [CLKID_PWM_B_SEL] = &a1_pwm_b_sel.hw,
> > [CLKID_PWM_B_DIV] = &a1_pwm_b_div.hw,
> > - [CLKID_PWM_B] = &a1_pwm_b.hw,
> > [CLKID_PWM_C_SEL] = &a1_pwm_c_sel.hw,
> > [CLKID_PWM_C_DIV] = &a1_pwm_c_div.hw,
> > - [CLKID_PWM_C] = &a1_pwm_c.hw,
> > [CLKID_PWM_D_SEL] = &a1_pwm_d_sel.hw,
> > [CLKID_PWM_D_DIV] = &a1_pwm_d_div.hw,
> > - [CLKID_PWM_D] = &a1_pwm_d.hw,
> > [CLKID_PWM_E_SEL] = &a1_pwm_e_sel.hw,
> > [CLKID_PWM_E_DIV] = &a1_pwm_e_div.hw,
> > - [CLKID_PWM_E] = &a1_pwm_e.hw,
> > [CLKID_PWM_F_SEL] = &a1_pwm_f_sel.hw,
> > [CLKID_PWM_F_DIV] = &a1_pwm_f_div.hw,
> > - [CLKID_PWM_F] = &a1_pwm_f.hw,
> > [CLKID_SPICC_SEL] = &a1_spicc_sel.hw,
> > [CLKID_SPICC_DIV] = &a1_spicc_div.hw,
> > [CLKID_SPICC_SEL2] = &a1_spicc_sel2.hw,
> > - [CLKID_SPICC] = &a1_spicc.hw,
> > [CLKID_TS_DIV] = &a1_ts_div.hw,
> > - [CLKID_TS] = &a1_ts.hw,
> > [CLKID_SPIFC_SEL] = &a1_spifc_sel.hw,
> > [CLKID_SPIFC_DIV] = &a1_spifc_div.hw,
> > [CLKID_SPIFC_SEL2] = &a1_spifc_sel2.hw,
> > - [CLKID_SPIFC] = &a1_spifc.hw,
> > [CLKID_USB_BUS_SEL] = &a1_usb_bus_sel.hw,
> > [CLKID_USB_BUS_DIV] = &a1_usb_bus_div.hw,
> > - [CLKID_USB_BUS] = &a1_usb_bus.hw,
> > [CLKID_SD_EMMC_SEL] = &a1_sd_emmc_sel.hw,
> > [CLKID_SD_EMMC_DIV] = &a1_sd_emmc_div.hw,
> > [CLKID_SD_EMMC_SEL2] = &a1_sd_emmc_sel2.hw,
> > - [CLKID_SD_EMMC] = &a1_sd_emmc.hw,
> > [CLKID_PSRAM_SEL] = &a1_psram_sel.hw,
> > [CLKID_PSRAM_DIV] = &a1_psram_div.hw,
> > [CLKID_PSRAM_SEL2] = &a1_psram_sel2.hw,
> > - [CLKID_PSRAM] = &a1_psram.hw,
> > [CLKID_DMC_SEL] = &a1_dmc_sel.hw,
> > [CLKID_DMC_DIV] = &a1_dmc_div.hw,
> > [CLKID_DMC_SEL2] = &a1_dmc_sel2.hw,
> > - [CLKID_DMC] = &a1_dmc.hw,
> > - [CLKID_RTC_32K_CLKIN] = &a1_rtc_32k_clkin.hw,
> > - [CLKID_RTC_32K_DIV] = &a1_rtc_32k_div.hw,
> > - [CLKID_RTC_32K_XTAL] = &a1_rtc_32k_xtal.hw,
> > - [CLKID_RTC_32K_SEL] = &a1_rtc_32k_sel.hw,
> > - [CLKID_RTC_CLK] = &a1_rtc_clk.hw,
> > - [CLKID_CECA_32K_CLKIN] = &a1_ceca_32k_clkin.hw,
> > - [CLKID_CECA_32K_DIV] = &a1_ceca_32k_div.hw,
> > - [CLKID_CECA_32K_SEL_PRE] = &a1_ceca_32k_sel_pre.hw,
> > - [CLKID_CECA_32K_SEL] = &a1_ceca_32k_sel.hw,
> > - [CLKID_CECA_32K] = &a1_ceca_32k_clkout.hw,
> > - [CLKID_CECB_32K_CLKIN] = &a1_cecb_32k_clkin.hw,
> > - [CLKID_CECB_32K_DIV] = &a1_cecb_32k_div.hw,
> > - [CLKID_CECB_32K_SEL_PRE] = &a1_cecb_32k_sel_pre.hw,
> > - [CLKID_CECB_32K_SEL] = &a1_cecb_32k_sel.hw,
> > - [CLKID_CECB_32K] = &a1_cecb_32k_clkout.hw,
> > [NR_CLKS] = NULL,
> > },
>
> Please avoid this ordering change - It is borderline impossible to
> review.
>
> Keep the ID Order
Yes, it's what I'm trying to achieve here - keeping the ID order. Jian
Hu's version mixed up CLKDID definitions. This patch resolves such
problem. Anyway, next version will not have such diff, because patches
will be squashed.
...
--
Thank you,
Dmitry
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 01/11] dt-bindings: clock: meson: add A1 PLL clock controller bindings
2022-12-02 11:11 ` Jerome Brunet
@ 2022-12-02 12:26 ` Dmitry Rokosov
0 siblings, 0 replies; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-02 12:26 UTC (permalink / raw)
To: Jerome Brunet
Cc: neil.armstrong, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl, jian.hu,
kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
On Fri, Dec 02, 2022 at 12:11:53PM +0100, Jerome Brunet wrote:
>
> On Fri 02 Dec 2022 at 01:56, Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
>
> > From: Jian Hu <jian.hu@amlogic.com>
> >
> > Add the documentation to support Amlogic A1 PLL clock driver,
> > and add A1 PLL clock controller bindings.
> >
> > Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> > Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> > ---
> > .../bindings/clock/amlogic,a1-pll-clkc.yaml | 52 +++++++++++++++++++
> > include/dt-bindings/clock/a1-pll-clkc.h | 16 ++++++
> > 2 files changed, 68 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
> > create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h
> >
> > diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
> > new file mode 100644
> > index 000000000000..d67250fbeece
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
> > @@ -0,0 +1,52 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: "http://devicetree.org/schemas/amlogic,a1-pll-clkc.yaml#"
> > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> > +
> > +title: Amlogic Meson A/C serials PLL Clock Control Unit Device Tree Bindings
> > +
> > +maintainers:
> > + - Neil Armstrong <narmstrong@baylibre.com>
> > + - Jerome Brunet <jbrunet@baylibre.com>
> > + - Jian Hu <jian.hu@jian.hu.com>
> > +
> > +properties:
> > + compatible:
> > + const: amlogic,a1-pll-clkc
> > +
> > + "#clock-cells":
> > + const: 1
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: input xtal_fixpll
> > + - description: input xtal_hifipll
> > +
> > + clock-names:
> > + items:
> > + - const: xtal_fixpll
> > + - const: xtal_hifipll
>
> Do we really need the "xtal_" prefix ?
>
> Seems like the clock is the PLL, not the xtal
>
This name was formed from specification registers description. Register
CLKTREE_SYS_OSCIN_CTRL has "gate en" field which calls "xtal ->
HIFIPLL", therefore if was transformed to xtal_hifipll name.
But I agree with you, that "hifipll" is better name choice.
--
Thank you,
Dmitry
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^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 04/11] clk: meson: a1: add support for Amlogic A1 Peripheral clock driver
2022-12-02 11:19 ` Jerome Brunet
@ 2022-12-02 12:33 ` Dmitry Rokosov
0 siblings, 0 replies; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-02 12:33 UTC (permalink / raw)
To: Jerome Brunet
Cc: neil.armstrong, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl, jian.hu,
kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
...
> > + .ops = &clk_regmap_gate_ro_ops,
> > + .parent_data = &(const struct clk_parent_data) {
> > + .fw_name = "xtal",
> > + },
> > + .num_parents = 1,
> > + },
> > +};
> > +
> > +static struct clk_regmap a1_xtal_fixpll = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = SYS_OSCIN_CTRL,
> > + .bit_idx = 1,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "xtal_fixpll",
>
> same here, this is not a crystal.
> It is the fixpll input gate, what about "fixpll_in"
>
> Same bellow - you get the idea ...
>
Yep, got it. Will fix in the v9.
...
> > +static struct clk_regmap a1_rtc_32k_sel = {
> > + .data = &(struct clk_regmap_mux_data) {
> > + .offset = RTC_CTRL,
> > + .mask = 0x3,
> > + .shift = 0,
> > + .flags = CLK_MUX_ROUND_CLOSEST,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "rtc_32k_sel",
> > + .ops = &clk_regmap_mux_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &a1_rtc_32k_xtal.hw,
> > + &a1_rtc_32k_div.hw,
> > + },
> > + .num_parents = 2,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +struct clk_regmap a1_rtc_clk = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = RTC_BY_OSCIN_CTRL0,
> > + .bit_idx = 30,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "rtc_clk",
>
> Everytime there is an "_clk" suffix, you can remove it.
> In this driver, we know we are going to get clocks ;)
>
Exactly! :-)
...
> > +static struct clk_regmap a1_dspa_en = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = DSPA_CLK_EN,
> > + .bit_idx = 1,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "dspa_en",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &a1_dspa_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
>
> Maybe as a 2nd step, but I suspect a "CLK_SET_RATE_NOREPARENT" is going to
> be needed here at some point.
>
I will think about it, and try to mark all needed points with that in
the next version.
...
> > +static struct clk_regmap a1_dspb_a = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = DSPB_CLK_CTRL0,
> > + .bit_idx = 13,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "dspb_a",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &a1_dspb_a_div.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>
> Any chance we can remove this CLK_IGNORE_UNUSED, or comment why it is
> needed ?
>
This is needed for DSP accelerator in the SoC. I'm afraid it can't be
disabled by kernel logic run on Core IP.
...
--
Thank you,
Dmitry
_______________________________________________
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linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 07/11] clk: meson: a1: redesign Amlogic A1 PLL clock controller
2022-12-02 11:42 ` Jerome Brunet
@ 2022-12-02 12:47 ` Dmitry Rokosov
2022-12-02 12:49 ` Jerome Brunet
0 siblings, 1 reply; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-02 12:47 UTC (permalink / raw)
To: Jerome Brunet
Cc: neil.armstrong, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl, jian.hu,
kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
On Fri, Dec 02, 2022 at 12:42:17PM +0100, Jerome Brunet wrote:
>
> On Fri 02 Dec 2022 at 01:56, Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
>
> > Summary changes:
> > - supported meson-a1-clkc common driver
> > - inherited from the base clk-pll driver, implemented own version of
> > init/enable/disable/enabled routines; rate calculating logic is
> > fully the same
> > - aligned CLKID-related definitions with CLKID list from order
> > perspective to remove holes and permutations
> > - corrected Kconfig dependencies and types
> > - provided correct MODULE_AUTHORs() and MODULE_LICENSE()
> > - optimized and fix up some clock relationships
> > - removed unused register offset definitions (ANACTRL_* group)
>
> This patch mix PLL stuff, factorization change, etc ...
> In general, when your commit description is a list, it is a hint that
> you are doing more than one thing in it. It is unlikely to be OK then
It will be fixed by itself, when I'll squash patches.
> > +static int meson_a1_pll_init(struct clk_hw *hw)
> > +{
> > + struct clk_regmap *clk = to_clk_regmap(hw);
> > + struct meson_a1_pll_data *pll = meson_a1_pll_data(clk);
> > +
> > + regmap_multi_reg_write(clk->map, pll->base.init_regs,
> > + pll->base.init_count);
> > +
> > + return 0;
>
> Looks the the default init mostly
>
> Looks like you are trying the handle the absence of the rst bit.
> I'm pretty sure the hifi PLL of the SoC as one but you really don't want
> to poke, this can be in the generic driver, with MESON_PARM_APPLICABLE()
> test.
>
> No need to redefine this
>
I've redefined it, because in the previous v7 you mentioned that's
not acceptable to mix init/enable/disable sequences between a1 pll and clk
common pll driver:
https://lore.kernel.org/linux-amlogic/1jd0ac5kpk.fsf@starbuckisacylon.baylibre.com/
Hmmm, looks like I've made a mistake. You meant only enable/disable
callbacks...
Anyway, it doesn't matter to me. I think both approaches are okay:
* clk-pll customization using MESON_PARM_APPLICABLE()
* custom callbacks implementation for some clk_ops like implemented in
this patchset.
Please advise what's the best from you point of view?
> > +}
> > +
> > +static int meson_a1_pll_is_enabled(struct clk_hw *hw)
> > +{
> > + struct clk_regmap *clk = to_clk_regmap(hw);
> > + struct meson_a1_pll_data *pll = meson_a1_pll_data(clk);
> > +
> > + if (MESON_PARM_APPLICABLE(&pll->base.rst) &&
> > + meson_parm_read(clk->map, &pll->base.rst))
> > + return 0;
> > +
> > + if (!meson_parm_read(clk->map, &pll->base.en) ||
> > + !meson_parm_read(clk->map, &pll->base.l))
> > + return 0;
> > +
>
> Same here, pretty sure rst is there and the generic function works but
> if this update is required, it seems safe to do in the generic driver.
The same thing... in the v7 version you suggested to not touch clk-pll
driver.
https://lore.kernel.org/linux-amlogic/1jd0ac5kpk.fsf@starbuckisacylon.baylibre.com/
...
--
Thank you,
Dmitry
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 07/11] clk: meson: a1: redesign Amlogic A1 PLL clock controller
2022-12-02 12:47 ` Dmitry Rokosov
@ 2022-12-02 12:49 ` Jerome Brunet
2022-12-02 18:20 ` Dmitry Rokosov
0 siblings, 1 reply; 45+ messages in thread
From: Jerome Brunet @ 2022-12-02 12:49 UTC (permalink / raw)
To: Dmitry Rokosov
Cc: neil.armstrong, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl, jian.hu,
kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
On Fri 02 Dec 2022 at 15:47, Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
> On Fri, Dec 02, 2022 at 12:42:17PM +0100, Jerome Brunet wrote:
>>
>> On Fri 02 Dec 2022 at 01:56, Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
>>
>> > Summary changes:
>> > - supported meson-a1-clkc common driver
>> > - inherited from the base clk-pll driver, implemented own version of
>> > init/enable/disable/enabled routines; rate calculating logic is
>> > fully the same
>> > - aligned CLKID-related definitions with CLKID list from order
>> > perspective to remove holes and permutations
>> > - corrected Kconfig dependencies and types
>> > - provided correct MODULE_AUTHORs() and MODULE_LICENSE()
>> > - optimized and fix up some clock relationships
>> > - removed unused register offset definitions (ANACTRL_* group)
>>
>> This patch mix PLL stuff, factorization change, etc ...
>> In general, when your commit description is a list, it is a hint that
>> you are doing more than one thing in it. It is unlikely to be OK then
>
> It will be fixed by itself, when I'll squash patches.
>
>> > +static int meson_a1_pll_init(struct clk_hw *hw)
>> > +{
>> > + struct clk_regmap *clk = to_clk_regmap(hw);
>> > + struct meson_a1_pll_data *pll = meson_a1_pll_data(clk);
>> > +
>> > + regmap_multi_reg_write(clk->map, pll->base.init_regs,
>> > + pll->base.init_count);
>> > +
>> > + return 0;
>>
>> Looks the the default init mostly
>>
>> Looks like you are trying the handle the absence of the rst bit.
>> I'm pretty sure the hifi PLL of the SoC as one but you really don't want
>> to poke, this can be in the generic driver, with MESON_PARM_APPLICABLE()
>> test.
>>
>> No need to redefine this
>>
>
> I've redefined it, because in the previous v7 you mentioned that's
> not acceptable to mix init/enable/disable sequences between a1 pll and clk
> common pll driver:
>
> https://lore.kernel.org/linux-amlogic/1jd0ac5kpk.fsf@starbuckisacylon.baylibre.com/
>
> Hmmm, looks like I've made a mistake. You meant only enable/disable
> callbacks...
>
> Anyway, it doesn't matter to me. I think both approaches are okay:
> * clk-pll customization using MESON_PARM_APPLICABLE()
> * custom callbacks implementation for some clk_ops like implemented in
> this patchset.
>
> Please advise what's the best from you point of view?
It is a balance.
Everytime a new PLL comes up, it tends to treaded as a new ip block but,
most of the time after some digging and rework, we learn new things and
it ends up being compatible with the previous ones.
From what I see here
* You are trying to make rst optional, that's fine. Do it with
MESON_PARM_APPLICABLE() in the main driver. Still I would recommend to
thorougly for this bit. I'm pretty sure the hifi pll has one.
* You add a new feature called current self-adaptation.
This can be made optional too in the enable sequence.
I would not be surprised to find out more PLL have that, even on
earlier SoC.
>
>> > +}
>> > +
>> > +static int meson_a1_pll_is_enabled(struct clk_hw *hw)
>> > +{
>> > + struct clk_regmap *clk = to_clk_regmap(hw);
>> > + struct meson_a1_pll_data *pll = meson_a1_pll_data(clk);
>> > +
>> > + if (MESON_PARM_APPLICABLE(&pll->base.rst) &&
>> > + meson_parm_read(clk->map, &pll->base.rst))
>> > + return 0;
>> > +
>> > + if (!meson_parm_read(clk->map, &pll->base.en) ||
>> > + !meson_parm_read(clk->map, &pll->base.l))
>> > + return 0;
>> > +
>>
>> Same here, pretty sure rst is there and the generic function works but
>> if this update is required, it seems safe to do in the generic driver.
>
> The same thing... in the v7 version you suggested to not touch clk-pll
> driver.
>
> https://lore.kernel.org/linux-amlogic/1jd0ac5kpk.fsf@starbuckisacylon.baylibre.com/
>
> ...
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^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 01/11] dt-bindings: clock: meson: add A1 PLL clock controller bindings
2022-12-02 11:28 ` Dmitry Rokosov
@ 2022-12-02 13:36 ` neil.armstrong
0 siblings, 0 replies; 45+ messages in thread
From: neil.armstrong @ 2022-12-02 13:36 UTC (permalink / raw)
To: Dmitry Rokosov, Krzysztof Kozlowski
Cc: Jerome Brunet, Rob Herring, devicetree, sboyd, khilman, kernel,
robh+dt, martin.blumenstingl, linux-arm-kernel, jian.hu,
linux-kernel, krzysztof.kozlowski+dt, linux-amlogic, rockosov,
mturquette, linux-clk
On 02/12/2022 12:28, Dmitry Rokosov wrote:
>>>>>> On Fri, 02 Dec 2022 01:56:53 +0300, Dmitry Rokosov wrote:
>>>>>>> From: Jian Hu <jian.hu@amlogic.com>
>>>>>>>
>>>>>>> Add the documentation to support Amlogic A1 PLL clock driver,
>>>>>>> and add A1 PLL clock controller bindings.
>>>>>>>
>>>>>>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>>>>>>> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
>>>>>>> ---
>>>>>>> .../bindings/clock/amlogic,a1-pll-clkc.yaml | 52 +++++++++++++++++++
>>>>>>> include/dt-bindings/clock/a1-pll-clkc.h | 16 ++++++
>>>>>>> 2 files changed, 68 insertions(+)
>>>>>>> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
>>>>>>> create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h
>>>>>>>
>>>>>>
>>>>>> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
>>>>>> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>>>>>>
>>>>>> yamllint warnings/errors:
>>>>>> ./Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml:26:6: [warning] wrong indentation: expected 6 but found 5 (indentation)
>>>>>>
>>>>>> dtschema/dtc warnings/errors:
>>>>>> ./Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml: $id: relative path/filename doesn't match actual path or filename
>
> ...
>
>>>>>
>>>>> Please find all fixes of above warnings and errors in the my patch
>>>>> located at the link:
>>>>>
>>>>> https://lore.kernel.org/linux-amlogic/20221201225703.6507-9-ddrokosov@sberdevices.ru/
>>>>
>>>> Why? This patch here is broken and it should be fixed. Don't apply
>>>> broken patches...
>>>
>>> Dmitry is ressurecting a series that is several years old and not his to
>>> begin with.
>>>
>>> He was unsure about take the code of somebody else.
>>> To be fair, he even asked for advice on IRC about to proceed.
>>>
>>> Dmitry, as you may have guessed, for next revision, please fix Jian Hu
>>> original patches in place, not with fixup patches.
>>>
>>> If your fixes are minor (not complete rewrite), please keep the original
>>> author and add your SoB
>>
>> We never take intentionally wrong patches, e.g. code which does not even
>> compile, and immediately fix it in next patch.
>>
>> Can you imagine adding such drivers? Which are broken in the commit they
>> are added?
>>
>> So the patchset is old or abandoned, take ownership, add co-developed
>> etc. Just don't add known broken code.
>
> Okay, I've got your point. It's reasonable.
> I will fix Jian Hu's patches (squash with mine) and mark all of them
> with co-developed and SoB Jian Hu tags. Thank you for explanation.
It was clearly explained in the cover-letter, nobody expected these patches
to be applied as-is.
Using RFC would have been the best solution, but this situation is rather
specific and he made the right decisions to trigger this current discussion
toward an acceptable solution for everybody.
Neil
>
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^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 11/11] arm64: dts: meson: a1: introduce PLL and Peripherals clk controllers
2022-12-02 12:03 ` Jerome Brunet
@ 2022-12-02 13:37 ` neil.armstrong
0 siblings, 0 replies; 45+ messages in thread
From: neil.armstrong @ 2022-12-02 13:37 UTC (permalink / raw)
To: Jerome Brunet, Dmitry Rokosov, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl
Cc: jian.hu, kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
On 02/12/2022 13:03, Jerome Brunet wrote:
>
> On Fri 02 Dec 2022 at 01:57, Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
>
>> This patch adds clkc_periphs and clkc_pll dts nodes to A1 SoC main dtsi.
>> The first one clk controller is responsible for all SoC peripherals
>> clocks excluding audio clocks. The second one clk controller is used by
>> A1 SoC PLLs. Actually, there are two different APB heads, so we have two
>> different drivers.
>
> Please send this change through a separate patcheset.
>
> One patcheset/series for clk (and bindings)
> Another one for the DTS (usually sent after the first one is accepted)
Yes please split out the DT in a separate patchset, but only send then once
the bindings are fully reviewed and accepted.
Start from v1 for the DT patchset, no need to continue the current numbering.
Thanks,
Neil
>
>>
>> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
>> ---
>> arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 27 ++++++++++++++++++++++-
>> 1 file changed, 26 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> index b4000cf65a9a..38e6517c603c 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> @@ -6,6 +6,8 @@
>> #include <dt-bindings/interrupt-controller/irq.h>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/gpio/meson-a1-gpio.h>
>> +#include <dt-bindings/clock/a1-pll-clkc.h>
>> +#include <dt-bindings/clock/a1-clkc.h>
>>
>> / {
>> compatible = "amlogic,a1";
>> @@ -81,7 +83,6 @@ apb: bus@fe000000 {
>> #size-cells = <2>;
>> ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
>>
>> -
>> reset: reset-controller@0 {
>> compatible = "amlogic,meson-a1-reset";
>> reg = <0x0 0x0 0x0 0x8c>;
>> @@ -124,6 +125,30 @@ uart_AO_B: serial@2000 {
>> clock-names = "xtal", "pclk", "baud";
>> status = "disabled";
>> };
>> +
>> + clkc_periphs: periphs-clock-controller@800 {
>
> device name should be generic so
>
> clkc_periphs: clock-controller@800 would be better
>
>> + compatible = "amlogic,a1-periphs-clkc";
>> + reg = <0 0x800 0 0x104>;
>> + #clock-cells = <1>;
>> + clocks = <&clkc_pll CLKID_FCLK_DIV2>,
>> + <&clkc_pll CLKID_FCLK_DIV3>,
>> + <&clkc_pll CLKID_FCLK_DIV5>,
>> + <&clkc_pll CLKID_FCLK_DIV7>,
>> + <&clkc_pll CLKID_HIFI_PLL>,
>> + <&xtal>;
>> + clock-names = "fclk_div2", "fclk_div3",
>> + "fclk_div5", "fclk_div7",
>> + "hifi_pll", "xtal";
>> + };
>> +
>> + clkc_pll: pll-clock-controller@7c80 {
>
> Same here
>
>> + compatible = "amlogic,a1-pll-clkc";
>> + reg = <0 0x7c80 0 0x18c>;
>> + #clock-cells = <1>;
>> + clocks = <&clkc_periphs CLKID_XTAL_FIXPLL>,
>> + <&clkc_periphs CLKID_XTAL_HIFIPLL>;
>> + clock-names = "xtal_fixpll", "xtal_hifipll";
>> + };
>> };
>>
>> gic: interrupt-controller@ff901000 {
>
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^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v8 07/11] clk: meson: a1: redesign Amlogic A1 PLL clock controller
2022-12-02 12:49 ` Jerome Brunet
@ 2022-12-02 18:20 ` Dmitry Rokosov
0 siblings, 0 replies; 45+ messages in thread
From: Dmitry Rokosov @ 2022-12-02 18:20 UTC (permalink / raw)
To: Jerome Brunet
Cc: neil.armstrong, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl, jian.hu,
kernel, rockosov, linux-amlogic, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
...
> >> > +static int meson_a1_pll_init(struct clk_hw *hw)
> >> > +{
> >> > + struct clk_regmap *clk = to_clk_regmap(hw);
> >> > + struct meson_a1_pll_data *pll = meson_a1_pll_data(clk);
> >> > +
> >> > + regmap_multi_reg_write(clk->map, pll->base.init_regs,
> >> > + pll->base.init_count);
> >> > +
> >> > + return 0;
> >>
> >> Looks the the default init mostly
> >>
> >> Looks like you are trying the handle the absence of the rst bit.
> >> I'm pretty sure the hifi PLL of the SoC as one but you really don't want
> >> to poke, this can be in the generic driver, with MESON_PARM_APPLICABLE()
> >> test.
> >>
> >> No need to redefine this
> >>
> >
> > I've redefined it, because in the previous v7 you mentioned that's
> > not acceptable to mix init/enable/disable sequences between a1 pll and clk
> > common pll driver:
> >
> > https://lore.kernel.org/linux-amlogic/1jd0ac5kpk.fsf@starbuckisacylon.baylibre.com/
> >
> > Hmmm, looks like I've made a mistake. You meant only enable/disable
> > callbacks...
> >
> > Anyway, it doesn't matter to me. I think both approaches are okay:
> > * clk-pll customization using MESON_PARM_APPLICABLE()
> > * custom callbacks implementation for some clk_ops like implemented in
> > this patchset.
> >
> > Please advise what's the best from you point of view?
>
> It is a balance.
>
> Everytime a new PLL comes up, it tends to treaded as a new ip block but,
> most of the time after some digging and rework, we learn new things and
> it ends up being compatible with the previous ones.
>
> From what I see here
> * You are trying to make rst optional, that's fine. Do it with
> MESON_PARM_APPLICABLE() in the main driver. Still I would recommend to
> thorougly for this bit. I'm pretty sure the hifi pll has one.
>
> * You add a new feature called current self-adaptation.
> This can be made optional too in the enable sequence.
> I would not be surprised to find out more PLL have that, even on
> earlier SoC.
Okay, I see.
I will try to modify clk-pll driver in accurate way to support rst
optional bit and current self-adaptation optional IP.
...
--
Thank you,
Dmitry
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linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 45+ messages in thread
end of thread, other threads:[~2022-12-02 18:21 UTC | newest]
Thread overview: 45+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-01 22:56 [PATCH v8 00/11] add Amlogic A1 clock controller drivers Dmitry Rokosov
2022-12-01 22:56 ` [PATCH v8 01/11] dt-bindings: clock: meson: add A1 PLL clock controller bindings Dmitry Rokosov
2022-12-02 4:10 ` Rob Herring
2022-12-02 9:51 ` Dmitry Rokosov
2022-12-02 10:39 ` Krzysztof Kozlowski
2022-12-02 11:04 ` Jerome Brunet
2022-12-02 11:16 ` Krzysztof Kozlowski
2022-12-02 11:28 ` Dmitry Rokosov
2022-12-02 13:36 ` neil.armstrong
2022-12-02 10:42 ` Krzysztof Kozlowski
2022-12-02 11:18 ` Dmitry Rokosov
2022-12-02 11:11 ` Jerome Brunet
2022-12-02 12:26 ` Dmitry Rokosov
2022-12-01 22:56 ` [PATCH v8 02/11] clk: meson: a1: add support for Amlogic A1 PLL clock driver Dmitry Rokosov
2022-12-02 11:16 ` Jerome Brunet
2022-12-02 11:31 ` Dmitry Rokosov
2022-12-01 22:56 ` [PATCH v8 03/11] dt-bindings: clock: meson: add A1 peripheral clock controller bindings Dmitry Rokosov
2022-12-02 4:10 ` Rob Herring
2022-12-02 9:49 ` Dmitry Rokosov
2022-12-02 10:39 ` Krzysztof Kozlowski
2022-12-02 10:58 ` Dmitry Rokosov
2022-12-02 10:43 ` Krzysztof Kozlowski
2022-12-01 22:56 ` [PATCH v8 04/11] clk: meson: a1: add support for Amlogic A1 Peripheral clock driver Dmitry Rokosov
2022-12-02 11:19 ` Jerome Brunet
2022-12-02 12:33 ` Dmitry Rokosov
2022-12-01 22:56 ` [PATCH v8 05/11] clk: meson: pll: export meson_clk_pll_wait_lock symbol Dmitry Rokosov
2022-12-01 22:56 ` [PATCH v8 06/11] clk: meson: introduce a1-clkc common driver for all A1 clock controllers Dmitry Rokosov
2022-12-02 11:36 ` Jerome Brunet
2022-12-02 11:58 ` Dmitry Rokosov
2022-12-01 22:56 ` [PATCH v8 07/11] clk: meson: a1: redesign Amlogic A1 PLL clock controller Dmitry Rokosov
2022-12-02 11:42 ` Jerome Brunet
2022-12-02 12:47 ` Dmitry Rokosov
2022-12-02 12:49 ` Jerome Brunet
2022-12-02 18:20 ` Dmitry Rokosov
2022-12-01 22:57 ` [PATCH v8 08/11] dt-bindings: clock: meson: fixup A1 PLL clkc dtb_check errors Dmitry Rokosov
2022-12-02 10:40 ` Krzysztof Kozlowski
2022-12-01 22:57 ` [PATCH v8 09/11] clk: meson: redesign A1 Peripherals CLK controller Dmitry Rokosov
2022-12-02 12:01 ` Jerome Brunet
2022-12-02 12:10 ` Dmitry Rokosov
2022-12-01 22:57 ` [PATCH v8 10/11] dt-bindings: clock: meson: fixup A1 peripherals clkc dtb_check errors Dmitry Rokosov
2022-12-02 10:40 ` Krzysztof Kozlowski
2022-12-01 22:57 ` [PATCH v8 11/11] arm64: dts: meson: a1: introduce PLL and Peripherals clk controllers Dmitry Rokosov
2022-12-02 10:43 ` Krzysztof Kozlowski
2022-12-02 12:03 ` Jerome Brunet
2022-12-02 13:37 ` neil.armstrong
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