From: Dmitry Rokosov <ddrokosov@sberdevices.ru>
To: <neil.armstrong@linaro.org>, <jbrunet@baylibre.com>,
<mturquette@baylibre.com>, <sboyd@kernel.org>,
<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<khilman@baylibre.com>, <martin.blumenstingl@googlemail.com>
Cc: <jian.hu@amlogic.com>, <kernel@sberdevices.ru>,
<rockosov@gmail.com>, <linux-amlogic@lists.infradead.org>,
<linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Dmitry Rokosov <ddrokosov@sberdevices.ru>
Subject: [PATCH v11 1/5] clk: meson: make pll rst bit as optional
Date: Tue, 21 Mar 2023 22:30:10 +0300 [thread overview]
Message-ID: <20230321193014.26349-2-ddrokosov@sberdevices.ru> (raw)
In-Reply-To: <20230321193014.26349-1-ddrokosov@sberdevices.ru>
Compared with the previous SoCs, self-adaption current module
is newly added for A1, and there is no reset parameter except the
fixed pll. Since we use clk-pll generic driver for A1 pll
implementation, rst bit should be optional to support new behavior.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
---
drivers/clk/meson/clk-pll.c | 24 +++++++++++++++++-------
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index afefeba6e458..314ca945a4d0 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -295,10 +295,14 @@ static int meson_clk_pll_init(struct clk_hw *hw)
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
if (pll->init_count) {
- meson_parm_write(clk->map, &pll->rst, 1);
+ if (MESON_PARM_APPLICABLE(&pll->rst))
+ meson_parm_write(clk->map, &pll->rst, 1);
+
regmap_multi_reg_write(clk->map, pll->init_regs,
pll->init_count);
- meson_parm_write(clk->map, &pll->rst, 0);
+
+ if (MESON_PARM_APPLICABLE(&pll->rst))
+ meson_parm_write(clk->map, &pll->rst, 0);
}
return 0;
@@ -309,8 +313,11 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw)
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
- if (meson_parm_read(clk->map, &pll->rst) ||
- !meson_parm_read(clk->map, &pll->en) ||
+ if (MESON_PARM_APPLICABLE(&pll->rst) &&
+ meson_parm_read(clk->map, &pll->rst))
+ return 0;
+
+ if (!meson_parm_read(clk->map, &pll->en) ||
!meson_parm_read(clk->map, &pll->l))
return 0;
@@ -341,13 +348,15 @@ static int meson_clk_pll_enable(struct clk_hw *hw)
return 0;
/* Make sure the pll is in reset */
- meson_parm_write(clk->map, &pll->rst, 1);
+ if (MESON_PARM_APPLICABLE(&pll->rst))
+ meson_parm_write(clk->map, &pll->rst, 1);
/* Enable the pll */
meson_parm_write(clk->map, &pll->en, 1);
/* Take the pll out reset */
- meson_parm_write(clk->map, &pll->rst, 0);
+ if (MESON_PARM_APPLICABLE(&pll->rst))
+ meson_parm_write(clk->map, &pll->rst, 0);
if (meson_clk_pll_wait_lock(hw))
return -EIO;
@@ -361,7 +370,8 @@ static void meson_clk_pll_disable(struct clk_hw *hw)
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
/* Put the pll is in reset */
- meson_parm_write(clk->map, &pll->rst, 1);
+ if (MESON_PARM_APPLICABLE(&pll->rst))
+ meson_parm_write(clk->map, &pll->rst, 1);
/* Disable the pll */
meson_parm_write(clk->map, &pll->en, 0);
--
2.36.0
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next prev parent reply other threads:[~2023-03-21 19:31 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-21 19:30 [PATCH v11 0/5] add Amlogic A1 clock controller drivers Dmitry Rokosov
2023-03-21 19:30 ` Dmitry Rokosov [this message]
2023-03-21 19:30 ` [PATCH v11 2/5] clk: meson: introduce new pll power-on sequence for A1 SoC family Dmitry Rokosov
2023-03-21 19:30 ` [PATCH v11 3/5] dt-bindings: clock: meson: add A1 PLL and Peripherals clkcs bindings Dmitry Rokosov
2023-03-27 9:51 ` Jerome Brunet
2023-03-27 10:51 ` Dmitry Rokosov
2023-03-27 11:39 ` Jerome Brunet
2023-03-27 12:03 ` neil.armstrong
2023-03-27 13:19 ` Dmitry Rokosov
2023-03-27 13:22 ` Dmitry Rokosov
2023-03-27 13:55 ` neil.armstrong
2023-03-27 14:02 ` Dmitry Rokosov
2023-03-27 13:41 ` Krzysztof Kozlowski
2023-03-27 13:46 ` Dmitry Rokosov
2023-03-27 13:59 ` Jerome Brunet
2023-03-27 15:28 ` Rob Herring
2023-03-21 19:30 ` [PATCH v11 4/5] clk: meson: a1: add Amlogic A1 PLL clock controller driver Dmitry Rokosov
2023-03-21 19:30 ` [PATCH v11 5/5] clk: meson: a1: add Amlogic A1 Peripherals " Dmitry Rokosov
2023-03-27 9:58 ` Jerome Brunet
2023-03-27 13:27 ` Dmitry Rokosov
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