From: Sohil Mehta <sohil.mehta@intel.com>
To: Thomas Gleixner <tglx@linutronix.de>, <x86@kernel.org>
Cc: Tony Luck <tony.luck@intel.com>,
Dave Hansen <dave.hansen@intel.com>,
"Ingo Molnar" <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
"H . Peter Anvin" <hpa@zytor.com>,
Andy Lutomirski <luto@kernel.org>, Jens Axboe <axboe@kernel.dk>,
Christian Brauner <christian@brauner.io>,
Peter Zijlstra <peterz@infradead.org>,
Shuah Khan <shuah@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
Jonathan Corbet <corbet@lwn.net>, Ashok Raj <ashok.raj@intel.com>,
Jacob Pan <jacob.jun.pan@linux.intel.com>,
"Gayatri Kammela" <gayatri.kammela@intel.com>,
Zeng Guang <guang.zeng@intel.com>,
"Dan Williams" <dan.j.williams@intel.com>,
Randy E Witt <randy.e.witt@intel.com>,
Ravi V Shankar <ravi.v.shankar@intel.com>,
Ramesh Thomas <ramesh.thomas@intel.com>,
<linux-api@vger.kernel.org>, <linux-arch@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-kselftest@vger.kernel.org>
Subject: Re: [RFC PATCH 07/13] x86/process/64: Add uintr task context switch support
Date: Mon, 27 Sep 2021 17:30:41 -0700 [thread overview]
Message-ID: <10d23bbd-bc11-d5f4-4032-a814a8bd8dc1@intel.com> (raw)
In-Reply-To: <877df6g603.ffs@tglx>
On 9/23/2021 5:41 PM, Thomas Gleixner wrote:
> On Mon, Sep 13 2021 at 13:01, Sohil Mehta wrote:
>
>> User interrupt state is saved and restored using xstate supervisor
>> feature support. This includes the MSR state and the User Interrupt Flag
>> (UIF) value.
>>
>> During context switch update the UPID for a uintr task to reflect the
>> current state of the task; namely whether the task should receive
>> interrupt notifications and which cpu the task is currently running on.
>>
>> XSAVES clears the notification vector (UINV) in the MISC MSR to prevent
>> interrupts from being recognized in the UIRR MSR while the task is being
>> context switched. The UINV is restored back when the kernel does an
>> XRSTORS.
>>
>> However, this conflicts with the kernel's lazy restore optimization
>> which skips an XRSTORS if the kernel is scheduling the same user task
>> back and the underlying MSR state hasn't been modified. Special handling
>> is needed for a uintr task in the context switch path to keep using this
>> optimization.
> And this special handling is?
By special handling I meant programming the MSR when XRSTORS doesn't
happen on return to userspace. The pseudo code you provided in patch 5
comments handles this well.
>> + * cleared.
>> */
>> void save_fpregs_to_fpstate(struct fpu *fpu)
>> {
>> diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
>> index ec0d836a13b1..62b82137db9c 100644
>> --- a/arch/x86/kernel/process_64.c
>> +++ b/arch/x86/kernel/process_64.c
>> @@ -53,6 +53,7 @@
>> #include <asm/xen/hypervisor.h>
>> #include <asm/vdso.h>
>> #include <asm/resctrl.h>
>> +#include <asm/uintr.h>
>> #include <asm/unistd.h>
>> #include <asm/fsgsbase.h>
>> #ifdef CONFIG_IA32_EMULATION
>> @@ -565,6 +566,9 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
>> WARN_ON_ONCE(IS_ENABLED(CONFIG_DEBUG_ENTRY) &&
>> this_cpu_read(hardirq_stack_inuse));
>>
>> + if (static_cpu_has(X86_FEATURE_UINTR))
> cpu_feature_enabled() please.
I'll fix this and the other issues that you mentioned.
>> + switch_uintr_prepare(prev_p);
>> +
>> if (!test_thread_flag(TIF_NEED_FPU_LOAD))
>> switch_fpu_prepare(prev_fpu, cpu);
>>
>> diff --git a/arch/x86/kernel/uintr_core.c b/arch/x86/kernel/uintr_core.c
>> index 2c6042a6840a..7a29888050ad 100644
>> --- a/arch/x86/kernel/uintr_core.c
>> +++ b/arch/x86/kernel/uintr_core.c
>> @@ -238,3 +238,78 @@ int do_uintr_register_handler(u64 handler)
>>
>> return 0;
>> }
>> +
>> +/* Suppress notifications since this task is being context switched out */
>> +void switch_uintr_prepare(struct task_struct *prev)
>> +{
>> + struct uintr_upid *upid;
>> +
>> + if (is_uintr_receiver(prev)) {
>> + upid = prev->thread.ui_recv->upid_ctx->upid;
>> + set_bit(UPID_SN, (unsigned long *)&upid->nc.status);
> Please add a comment why this needs to be a locked instruction.
>
>
Ok, will do. The SN bit could be read concurrently on another CPU
executing SENDUIPI.
> Of course this is invoked unconditionally when the CPU has
> X86_FEATURE_UINTR:
>
>> + if (static_cpu_has(X86_FEATURE_UINTR))
>> + switch_uintr_return();
> Why?
>
> If the sequence is:
>
> syscall()
> do_stuff()
> return_to_user()
>
> then what on earth has modified that MSR state? Nothing at all, but you
> still run this code. What for?
>
>
The pseudo code in patch 5 covers this. I'll fix the code based on that.
Thanks,
Sohil
next prev parent reply other threads:[~2021-09-28 0:30 UTC|newest]
Thread overview: 87+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-13 20:01 [RFC PATCH 00/13] x86 User Interrupts support Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 01/13] x86/uintr/man-page: Include man pages draft for reference Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 02/13] Documentation/x86: Add documentation for User Interrupts Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 03/13] x86/cpu: Enumerate User Interrupts support Sohil Mehta
2021-09-23 22:24 ` Thomas Gleixner
2021-09-24 19:59 ` Sohil Mehta
2021-09-27 20:42 ` Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 04/13] x86/fpu/xstate: Enumerate User Interrupts supervisor state Sohil Mehta
2021-09-23 22:34 ` Thomas Gleixner
2021-09-27 22:25 ` Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 05/13] x86/irq: Reserve a user IPI notification vector Sohil Mehta
2021-09-23 23:07 ` Thomas Gleixner
2021-09-25 13:30 ` Thomas Gleixner
2021-09-26 12:39 ` Thomas Gleixner
2021-09-27 19:07 ` Sohil Mehta
2021-09-28 8:11 ` Thomas Gleixner
2021-09-27 19:26 ` Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 06/13] x86/uintr: Introduce uintr receiver syscalls Sohil Mehta
2021-09-23 12:26 ` Greg KH
2021-09-24 0:05 ` Thomas Gleixner
2021-09-27 23:20 ` Sohil Mehta
2021-09-28 4:39 ` Greg KH
2021-09-28 16:47 ` Sohil Mehta
2021-09-23 23:52 ` Thomas Gleixner
2021-09-27 23:57 ` Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 07/13] x86/process/64: Add uintr task context switch support Sohil Mehta
2021-09-24 0:41 ` Thomas Gleixner
2021-09-28 0:30 ` Sohil Mehta [this message]
2021-09-13 20:01 ` [RFC PATCH 08/13] x86/process/64: Clean up uintr task fork and exit paths Sohil Mehta
2021-09-24 1:02 ` Thomas Gleixner
2021-09-28 1:23 ` Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 09/13] x86/uintr: Introduce vector registration and uintr_fd syscall Sohil Mehta
2021-09-24 10:33 ` Thomas Gleixner
2021-09-28 20:40 ` Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 10/13] x86/uintr: Introduce user IPI sender syscalls Sohil Mehta
2021-09-23 12:28 ` Greg KH
2021-09-28 18:01 ` Sohil Mehta
2021-09-29 7:04 ` Greg KH
2021-09-29 14:27 ` Sohil Mehta
2021-09-24 10:54 ` Thomas Gleixner
2021-09-13 20:01 ` [RFC PATCH 11/13] x86/uintr: Introduce uintr_wait() syscall Sohil Mehta
2021-09-24 11:04 ` Thomas Gleixner
2021-09-25 12:08 ` Thomas Gleixner
2021-09-28 23:13 ` Sohil Mehta
2021-09-28 23:08 ` Sohil Mehta
2021-09-26 14:41 ` Thomas Gleixner
2021-09-29 1:09 ` Sohil Mehta
2021-09-29 3:30 ` Andy Lutomirski
2021-09-29 4:56 ` Sohil Mehta
2021-09-30 18:08 ` Andy Lutomirski
2021-09-30 19:29 ` Thomas Gleixner
2021-09-30 22:01 ` Andy Lutomirski
2021-10-01 0:01 ` Thomas Gleixner
2021-10-01 4:41 ` Andy Lutomirski
2021-10-01 9:56 ` Thomas Gleixner
2021-10-01 15:13 ` Andy Lutomirski
2021-10-01 18:04 ` Sohil Mehta
2021-10-01 21:29 ` Thomas Gleixner
2021-10-01 23:00 ` Sohil Mehta
2021-10-01 23:04 ` Andy Lutomirski
2021-09-13 20:01 ` [RFC PATCH 12/13] x86/uintr: Wire up the user interrupt syscalls Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 13/13] selftests/x86: Add basic tests for User IPI Sohil Mehta
2021-09-13 20:27 ` [RFC PATCH 00/13] x86 User Interrupts support Dave Hansen
2021-09-14 19:03 ` Mehta, Sohil
2021-09-23 12:19 ` Greg KH
2021-09-23 14:09 ` Greg KH
2021-09-23 14:46 ` Dave Hansen
2021-09-23 15:07 ` Greg KH
2021-09-23 23:24 ` Sohil Mehta
2021-09-23 23:09 ` Sohil Mehta
2021-09-24 0:17 ` Sohil Mehta
2021-09-23 14:39 ` Jens Axboe
2021-09-29 4:31 ` Andy Lutomirski
2021-09-30 16:30 ` Stefan Hajnoczi
2021-09-30 17:24 ` Sohil Mehta
2021-09-30 17:26 ` Andy Lutomirski
2021-10-01 16:35 ` Stefan Hajnoczi
2021-10-01 16:41 ` Richard Henderson
2021-09-30 16:26 ` Stefan Hajnoczi
2021-10-01 0:40 ` Sohil Mehta
2021-10-01 8:19 ` Pavel Machek
2021-11-18 22:19 ` Sohil Mehta
2021-11-16 3:49 ` Prakash Sangappa
2021-11-18 21:44 ` Sohil Mehta
2021-12-22 16:17 ` Chrisma Pakha
2022-01-07 2:08 ` Sohil Mehta
2022-01-17 1:14 ` Chrisma Pakha
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