From: Guo Ren <ren_guo@c-sky.com>
To: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org,
tglx@linutronix.de, daniel.lezcano@linaro.org,
jason@lakedaemon.net, arnd@arndb.de, devicetree@vger.kernel.org,
andrea.parri@amarulasolutions.com, peterz@infradead.org
Cc: c-sky_gcc_upstream@c-sky.com, gnu-csky@mentor.com,
thomas.petazzoni@bootlin.com, wbx@uclibc-ng.org,
ren_guo@c-sky.com, green.hu@gmail.com
Subject: [PATCH V3 23/27] clocksource: add gx6605s SOC system timer
Date: Wed, 12 Sep 2018 21:24:57 +0800 [thread overview]
Message-ID: <0a7e182c46e1bbe2802d4bf11a04012ba3e589b0.1536757532.git.ren_guo@c-sky.com> (raw)
Message-ID: <20180912132457.8bfZ3tHfqZk7pzbmPClU1xNwHa5G0Wxljk0QH6UIlmc@z> (raw)
In-Reply-To: <cover.1536757532.git.ren_guo@c-sky.com>
In-Reply-To: <cover.1536757532.git.ren_guo@c-sky.com>
Changelog:
- Add License and Copyright
- Use timer-of framework
- Change name with upstream feedback
- Use clksource_mmio framework
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
---
drivers/clocksource/timer-gx6605s.c | 150 ++++++++++++++++++++++++++++++++++++
1 file changed, 150 insertions(+)
create mode 100644 drivers/clocksource/timer-gx6605s.c
diff --git a/drivers/clocksource/timer-gx6605s.c b/drivers/clocksource/timer-gx6605s.c
new file mode 100644
index 0000000..10194c9
--- /dev/null
+++ b/drivers/clocksource/timer-gx6605s.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/sched_clock.h>
+
+#include "timer-of.h"
+
+#define CLKSRC_OFFSET 0x40
+
+#define TIMER_STATUS 0x00
+#define TIMER_VALUE 0x04
+#define TIMER_CONTRL 0x10
+#define TIMER_CONFIG 0x20
+#define TIMER_DIV 0x24
+#define TIMER_INI 0x28
+
+#define GX6605S_STATUS_CLR BIT(0)
+#define GX6605S_CONTRL_RST BIT(0)
+#define GX6605S_CONTRL_START BIT(1)
+#define GX6605S_CONFIG_EN BIT(0)
+#define GX6605S_CONFIG_IRQ_EN BIT(1)
+
+static irqreturn_t gx6605s_timer_interrupt(int irq, void *dev)
+{
+ struct clock_event_device *ce = (struct clock_event_device *) dev;
+ void __iomem *base = timer_of_base(to_timer_of(ce));
+
+ writel_relaxed(GX6605S_STATUS_CLR, base + TIMER_STATUS);
+
+ ce->event_handler(ce);
+
+ return IRQ_HANDLED;
+}
+
+static int gx6605s_timer_set_oneshot(struct clock_event_device *ce)
+{
+ void __iomem *base = timer_of_base(to_timer_of(ce));
+
+ /* reset and stop counter */
+ writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
+
+ /* enable with irq and start */
+ writel_relaxed(GX6605S_CONFIG_EN | GX6605S_CONFIG_IRQ_EN, base + TIMER_CONFIG);
+
+ return 0;
+}
+
+static int gx6605s_timer_set_next_event(unsigned long delta, struct clock_event_device *ce)
+{
+ void __iomem *base = timer_of_base(to_timer_of(ce));
+
+ /* use reset to pause timer */
+ writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
+
+ /* config next timeout value */
+ writel_relaxed(ULONG_MAX - delta, base + TIMER_INI);
+ writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL);
+
+ return 0;
+}
+
+static int gx6605s_timer_shutdown(struct clock_event_device *ce)
+{
+ void __iomem *base = timer_of_base(to_timer_of(ce));
+
+ writel_relaxed(0, base + TIMER_CONTRL);
+ writel_relaxed(0, base + TIMER_CONFIG);
+
+ return 0;
+}
+
+static struct timer_of to = {
+ .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
+ .clkevt = {
+ .rating = 300,
+ .features = CLOCK_EVT_FEAT_DYNIRQ |
+ CLOCK_EVT_FEAT_ONESHOT,
+ .set_state_shutdown = gx6605s_timer_shutdown,
+ .set_state_oneshot = gx6605s_timer_set_oneshot,
+ .set_next_event = gx6605s_timer_set_next_event,
+ .cpumask = cpu_possible_mask,
+ },
+ .of_irq = {
+ .handler = gx6605s_timer_interrupt,
+ .flags = IRQF_TIMER | IRQF_IRQPOLL,
+ },
+};
+
+static u64 notrace gx6605s_sched_clock_read(void)
+{
+ void __iomem *base;
+
+ base = timer_of_base(&to) + CLKSRC_OFFSET;
+
+ return (u64) readl_relaxed(base + TIMER_VALUE);
+}
+
+static void gx6605s_clkevt_init(void __iomem *base)
+{
+ writel_relaxed(0, base + TIMER_DIV);
+ writel_relaxed(0, base + TIMER_CONFIG);
+
+ clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), 2, ULONG_MAX);
+}
+
+static int gx6605s_clksrc_init(void __iomem *base)
+{
+ writel_relaxed(0, base + TIMER_DIV);
+ writel_relaxed(0, base + TIMER_INI);
+
+ writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
+
+ writel_relaxed(GX6605S_CONFIG_EN, base + TIMER_CONFIG);
+
+ writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL);
+
+ sched_clock_register(gx6605s_sched_clock_read, 32, timer_of_rate(&to));
+
+ return clocksource_mmio_init(base + TIMER_VALUE, "gx6605s", timer_of_rate(&to),
+ 200, 32, clocksource_mmio_readl_up);
+}
+
+static int __init gx6605s_timer_init(struct device_node *np)
+{
+ int ret;
+
+ /*
+ * The timer driver is for nationalchip gx6605s SOC and there are two same timer
+ * in gx6605s. We use one for clkevt and another for clksrc.
+ *
+ * The timer is mmio map to access, so we need give mmio addres in dts.
+ *
+ * It provides a 32bit countup timer and interrupt will be caused by count-overflow.
+ * So we need set-next-event by ULONG_MAX - delta in TIMER_INI reg.
+ *
+ * The counter at 0x0 offset is clock event.
+ * The counter at 0x40 offset is clock source.
+ * They are the same in hardware, just different used by driver.
+ */
+ ret = timer_of_init(np, &to);
+ if (ret)
+ return ret;
+
+ gx6605s_clkevt_init(timer_of_base(&to));
+
+ return gx6605s_clksrc_init(timer_of_base(&to) + CLKSRC_OFFSET);
+}
+TIMER_OF_DECLARE(csky_gx6605s_timer, "csky,gx6605s-timer", gx6605s_timer_init);
--
2.7.4
next prev parent reply other threads:[~2018-09-12 18:30 UTC|newest]
Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-12 13:24 [PATCH V4 00/27] C-SKY(csky) Linux Kernel Port Guo Ren
2018-09-12 13:24 ` Guo Ren
2018-09-12 13:24 ` [PATCH V3 01/27] csky: Build infrastructure Guo Ren
2018-09-12 13:24 ` Guo Ren
2018-09-12 13:24 ` [PATCH V3 02/27] csky: defconfig Guo Ren
2018-09-12 13:24 ` Guo Ren
2018-09-12 13:24 ` [PATCH V3 03/27] csky: Kernel booting Guo Ren
2018-09-12 13:24 ` Guo Ren
2018-09-12 13:24 ` [PATCH V3 04/27] csky: Exception handling Guo Ren
2018-09-12 13:24 ` Guo Ren
2018-09-12 13:24 ` [PATCH V3 05/27] csky: System Call Guo Ren
2018-09-12 13:24 ` Guo Ren
2018-09-12 13:24 ` [PATCH V3 06/27] csky: Cache and TLB routines Guo Ren
2018-09-12 13:24 ` Guo Ren
2018-09-12 13:24 ` [PATCH V3 07/27] csky: MMU and page table management Guo Ren
2018-09-12 13:24 ` Guo Ren
2018-09-12 13:24 ` [PATCH V3 08/27] csky: Process management and Signal Guo Ren
2018-09-12 13:24 ` Guo Ren
2018-09-12 13:24 ` [PATCH V3 09/27] csky: VDSO and rt_sigreturn Guo Ren
2018-09-12 13:24 ` Guo Ren
2018-09-12 13:24 ` [PATCH V3 10/27] csky: IRQ handling Guo Ren
2018-09-12 13:24 ` Guo Ren
2018-09-12 13:24 ` [PATCH V3 12/27] csky: ELF and module probe Guo Ren
2018-09-12 13:24 ` Guo Ren
2018-09-12 13:24 ` [PATCH V3 13/27] csky: Library functions Guo Ren
2018-09-12 13:24 ` Guo Ren
2018-09-12 13:24 ` [PATCH V3 14/27] csky: User access Guo Ren
2018-09-12 13:24 ` Guo Ren
2018-09-12 13:24 ` [PATCH V3 15/27] csky: Debug and Ptrace GDB Guo Ren
2018-09-12 13:24 ` Guo Ren
2018-09-12 13:24 ` [PATCH V3 16/27] csky: SMP support Guo Ren
2018-09-12 13:24 ` Guo Ren
2018-09-12 13:24 ` [PATCH V3 18/27] dt-bindings: csky CPU Bindings Guo Ren
2018-09-12 13:24 ` Guo Ren
2018-09-12 13:24 ` [PATCH V3 19/27] dt-bindings: timer: gx6605s SOC timer Guo Ren
2018-09-12 13:24 ` Guo Ren
2018-09-12 13:24 ` [PATCH V3 20/27] dt-bindings: timer: C-SKY Multi-processor timer Guo Ren
2018-09-12 13:24 ` Guo Ren
2018-09-12 13:24 ` [PATCH V3 22/27] dt-bindings: interrupt-controller: C-SKY SMP intc Guo Ren
2018-09-12 13:24 ` Guo Ren
2018-09-12 13:24 ` Guo Ren [this message]
2018-09-12 13:24 ` [PATCH V3 23/27] clocksource: add gx6605s SOC system timer Guo Ren
[not found] ` <abb46d366b513b814f7af234d560306a818b7324.1536757532.git.ren_guo@c-sky.com>
2018-09-12 14:22 ` [PATCH V3 17/27] csky: Misc headers Arnd Bergmann
2018-09-12 14:22 ` Arnd Bergmann
2018-09-12 14:30 ` [PATCH V4 00/27] C-SKY(csky) Linux Kernel Port Arnd Bergmann
2018-09-12 14:30 ` Arnd Bergmann
2018-09-14 14:37 ` Guo Ren
2018-09-14 14:37 ` Guo Ren
2018-09-14 14:46 ` Arnd Bergmann
2018-09-14 14:46 ` Arnd Bergmann
2018-09-14 16:02 ` Guo Ren
2018-09-14 16:02 ` Guo Ren
2018-09-14 16:09 ` Arnd Bergmann
2018-09-14 16:09 ` Arnd Bergmann
2018-09-14 23:28 ` Guo Ren
2018-09-14 23:28 ` Guo Ren
2018-09-20 17:52 ` Palmer Dabbelt
2018-09-20 17:52 ` Palmer Dabbelt
2018-09-21 5:18 ` Arnd Bergmann
2018-09-21 5:18 ` Arnd Bergmann
2018-09-21 23:48 ` Guo Ren
2018-09-21 23:48 ` Guo Ren
2018-09-24 7:21 ` Geert Uytterhoeven
2018-09-24 7:21 ` Geert Uytterhoeven
2018-09-24 8:47 ` Arnd Bergmann
2018-09-24 8:47 ` Arnd Bergmann
2018-09-16 1:07 ` Guo Ren
2018-09-16 1:07 ` Guo Ren
2018-09-16 4:53 ` Guo Ren
2018-09-16 4:53 ` Guo Ren
2018-09-17 11:54 ` Stephen Rothwell
2018-09-17 11:54 ` Stephen Rothwell
2018-09-17 12:03 ` Stephen Rothwell
2018-09-17 12:03 ` Stephen Rothwell
2018-09-17 14:50 ` Guo Ren
2018-09-17 14:50 ` Guo Ren
2018-09-17 14:37 ` Guo Ren
2018-09-17 14:37 ` Guo Ren
[not found] ` <93e8b592e429c156ad4d4ca5d85ef48fd0ab8b70.1536757532.git.ren_guo@c-sky.com>
2018-09-12 15:55 ` [PATCH V3 11/27] csky: Atomic operations Peter Zijlstra
2018-09-12 15:55 ` Peter Zijlstra
2018-09-15 14:55 ` Guo Ren
2018-09-15 14:55 ` Guo Ren
2018-09-17 8:17 ` Peter Zijlstra
2018-09-17 8:17 ` Peter Zijlstra
2018-09-17 15:05 ` Guo Ren
2018-09-17 15:05 ` Guo Ren
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