From: Yu-cheng Yu <yu-cheng.yu@intel.com> To: x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>, Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann <arnd@arndb.de>, Andy Lutomirski <luto@amacapital.net>, Balbir Singh <bsingharora@gmail.com>, Cyrill Gorcunov <gorcunov@gmail.com>, Dave Hansen <dave.hansen@linux.intel.com>, Eugene Syromiatnikov <esyr@redhat.com>, Florian Weimer <fweimer@redhat.com>, "H.J. Lu" <hjl.tools@gmail.com>, Jann Horn <jannh@google.com>, Jonathan Corbet <corbet@lwn.net>, Kees Cook <keescook@chromium.org>, Mike Kravetz <mike.kravetz@oracle.com>, Nadav Amit <nadav.amit@gmail.com>, Oleg Nesterov <oleg@redhat.com>, Pa Cc: Yu-cheng Yu <yu-cheng.yu@intel.com> Subject: [PATCH v5 03/11] x86/cet/ibt: Add IBT legacy code bitmap allocation function Date: Thu, 11 Oct 2018 08:16:46 -0700 [thread overview] Message-ID: <20181011151654.27221-4-yu-cheng.yu@intel.com> (raw) In-Reply-To: <20181011151654.27221-1-yu-cheng.yu@intel.com> Indirect branch tracking provides an optional legacy code bitmap that indicates locations of non-IBT compatible code. When set, each bit in the bitmap represents a page in the linear address is legacy code. We allocate the bitmap only when the application requests it. Most applications do not need the bitmap. Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com> --- arch/x86/kernel/cet.c | 47 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/x86/kernel/cet.c b/arch/x86/kernel/cet.c index 40c4c08e5e31..77ae4eaa9dea 100644 --- a/arch/x86/kernel/cet.c +++ b/arch/x86/kernel/cet.c @@ -21,6 +21,7 @@ #include <asm/compat.h> #include <asm/cet.h> #include <asm/special_insns.h> +#include <asm/elf.h> static int set_shstk_ptr(unsigned long addr) { @@ -327,3 +328,49 @@ void cet_disable_ibt(void) wrmsrl(MSR_IA32_U_CET, r); current->thread.cet.ibt_enabled = 0; } + +int cet_setup_ibt_bitmap(void) +{ + u64 r; + unsigned long bitmap; + unsigned long size; + + if (!cpu_feature_enabled(X86_FEATURE_IBT)) + return -EOPNOTSUPP; + + if (!current->thread.cet.ibt_bitmap_addr) { + /* + * Calculate size and put in thread header. + * may_expand_vm() needs this information. + */ + size = in_compat_syscall() ? task_size_32bit() : task_size_64bit(1); + size = size / PAGE_SIZE / BITS_PER_BYTE; + current->thread.cet.ibt_bitmap_size = size; + bitmap = do_mmap_locked(0, size, PROT_READ | PROT_WRITE, + MAP_ANONYMOUS | MAP_PRIVATE, + VM_DONTDUMP); + + if ((bitmap >= TASK_SIZE) || (bitmap < size)) { + current->thread.cet.ibt_bitmap_size = 0; + return -ENOMEM; + } + + current->thread.cet.ibt_bitmap_addr = bitmap; + + /* + * Lower bits of MSR_IA32_CET_LEG_IW_EN are for IBT + * settings. Clear lower bits even bitmap is already + * page-aligned. + */ + bitmap &= PAGE_MASK; + + /* + * Turn on IBT legacy bitmap. + */ + rdmsrl(MSR_IA32_U_CET, r); + r |= (MSR_IA32_CET_LEG_IW_EN | bitmap); + wrmsrl(MSR_IA32_U_CET, r); + } + + return 0; +} -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Yu-cheng Yu <yu-cheng.yu@intel.com> To: x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>, Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann <arnd@arndb.de>, Andy Lutomirski <luto@amacapital.net>, Balbir Singh <bsingharora@gmail.com>, Cyrill Gorcunov <gorcunov@gmail.com>, Dave Hansen <dave.hansen@linux.intel.com>, Eugene Syromiatnikov <esyr@redhat.com>, Florian Weimer <fweimer@redhat.com>, "H.J. Lu" <hjl.tools@gmail.com>, Jann Horn <jannh@google.com>, Jonathan Corbet <corbet@lwn.net>, Kees Cook <keescook@chromium.org>, Mike Kravetz <mike.kravetz@oracle.com>, Nadav Amit <nadav.amit@gmail.com>, Oleg Nesterov <oleg@redhat.com>, Pavel Machek <pavel@ucw.cz>, Peter Zijlstra <peterz@infradead.org>, Randy Dunlap <rdunlap@infradead.org>, "Ravi V. Shankar" <ravi.v.shankar@intel.com>, Vedvyas Shanbhogue <vedvyas.shanbhogue@intel.com> Cc: Yu-cheng Yu <yu-cheng.yu@intel.com> Subject: [PATCH v5 03/11] x86/cet/ibt: Add IBT legacy code bitmap allocation function Date: Thu, 11 Oct 2018 08:16:46 -0700 [thread overview] Message-ID: <20181011151654.27221-4-yu-cheng.yu@intel.com> (raw) Message-ID: <20181011151646.MMpoEl_koKqRed27j48Fum3BcHPVj4HV-QXRkkJwVus@z> (raw) In-Reply-To: <20181011151654.27221-1-yu-cheng.yu@intel.com> Indirect branch tracking provides an optional legacy code bitmap that indicates locations of non-IBT compatible code. When set, each bit in the bitmap represents a page in the linear address is legacy code. We allocate the bitmap only when the application requests it. Most applications do not need the bitmap. Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com> --- arch/x86/kernel/cet.c | 47 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/x86/kernel/cet.c b/arch/x86/kernel/cet.c index 40c4c08e5e31..77ae4eaa9dea 100644 --- a/arch/x86/kernel/cet.c +++ b/arch/x86/kernel/cet.c @@ -21,6 +21,7 @@ #include <asm/compat.h> #include <asm/cet.h> #include <asm/special_insns.h> +#include <asm/elf.h> static int set_shstk_ptr(unsigned long addr) { @@ -327,3 +328,49 @@ void cet_disable_ibt(void) wrmsrl(MSR_IA32_U_CET, r); current->thread.cet.ibt_enabled = 0; } + +int cet_setup_ibt_bitmap(void) +{ + u64 r; + unsigned long bitmap; + unsigned long size; + + if (!cpu_feature_enabled(X86_FEATURE_IBT)) + return -EOPNOTSUPP; + + if (!current->thread.cet.ibt_bitmap_addr) { + /* + * Calculate size and put in thread header. + * may_expand_vm() needs this information. + */ + size = in_compat_syscall() ? task_size_32bit() : task_size_64bit(1); + size = size / PAGE_SIZE / BITS_PER_BYTE; + current->thread.cet.ibt_bitmap_size = size; + bitmap = do_mmap_locked(0, size, PROT_READ | PROT_WRITE, + MAP_ANONYMOUS | MAP_PRIVATE, + VM_DONTDUMP); + + if ((bitmap >= TASK_SIZE) || (bitmap < size)) { + current->thread.cet.ibt_bitmap_size = 0; + return -ENOMEM; + } + + current->thread.cet.ibt_bitmap_addr = bitmap; + + /* + * Lower bits of MSR_IA32_CET_LEG_IW_EN are for IBT + * settings. Clear lower bits even bitmap is already + * page-aligned. + */ + bitmap &= PAGE_MASK; + + /* + * Turn on IBT legacy bitmap. + */ + rdmsrl(MSR_IA32_U_CET, r); + r |= (MSR_IA32_CET_LEG_IW_EN | bitmap); + wrmsrl(MSR_IA32_U_CET, r); + } + + return 0; +} -- 2.17.1
next prev parent reply other threads:[~2018-10-11 15:16 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-10-11 15:16 [PATCH v5 00/11] Control Flow Enforcement: Branch Tracking, PTRACE Yu-cheng Yu 2018-10-11 15:16 ` Yu-cheng Yu 2018-10-11 15:16 ` [PATCH v5 01/11] x86/cet/ibt: Add Kconfig option for user-mode Indirect Branch Tracking Yu-cheng Yu 2018-10-11 15:16 ` Yu-cheng Yu 2018-10-11 15:16 ` [PATCH v5 02/11] x86/cet/ibt: User-mode indirect branch tracking support Yu-cheng Yu 2018-10-11 15:16 ` Yu-cheng Yu 2018-10-11 15:16 ` Yu-cheng Yu [this message] 2018-10-11 15:16 ` [PATCH v5 03/11] x86/cet/ibt: Add IBT legacy code bitmap allocation function Yu-cheng Yu 2018-10-11 15:16 ` [PATCH v5 04/11] mm/mmap: Add IBT bitmap size to address space limit check Yu-cheng Yu 2018-10-11 15:16 ` Yu-cheng Yu 2018-10-11 15:16 ` [PATCH v5 05/11] x86/cet/ibt: ELF header parsing for IBT Yu-cheng Yu 2018-10-11 15:16 ` Yu-cheng Yu 2018-10-11 15:16 ` [PATCH v5 06/11] x86/cet/ibt: Add arch_prctl functions " Yu-cheng Yu 2018-10-11 15:16 ` Yu-cheng Yu 2018-10-11 15:16 ` [PATCH v5 07/11] x86/cet/ibt: Add ENDBR to op-code-map Yu-cheng Yu 2018-10-11 15:16 ` Yu-cheng Yu 2018-10-11 15:16 ` [PATCH v5 08/11] x86: Insert endbr32/endbr64 to vDSO Yu-cheng Yu 2018-10-11 15:16 ` Yu-cheng Yu 2018-10-11 15:16 ` [PATCH v5 09/11] x86/vsyscall/32: Add ENDBR32 to vsyscall entry point Yu-cheng Yu 2018-10-11 15:16 ` Yu-cheng Yu 2018-10-11 15:16 ` [PATCH v5 10/11] x86/vsyscall/64: Add ENDBR64 to vsyscall entry points Yu-cheng Yu 2018-10-11 15:16 ` Yu-cheng Yu 2018-10-11 15:16 ` [PATCH v5 11/11] x86/cet: Add PTRACE interface for CET Yu-cheng Yu 2018-10-11 15:16 ` Yu-cheng Yu
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20181011151654.27221-4-yu-cheng.yu@intel.com \ --to=yu-cheng.yu@intel.com \ --cc=arnd@arndb.de \ --cc=bsingharora@gmail.com \ --cc=corbet@lwn.net \ --cc=dave.hansen@linux.intel.com \ --cc=esyr@redhat.com \ --cc=fweimer@redhat.com \ --cc=gorcunov@gmail.com \ --cc=hjl.tools@gmail.com \ --cc=hpa@zytor.com \ --cc=jannh@google.com \ --cc=keescook@chromium.org \ --cc=linux-api@vger.kernel.org \ --cc=linux-arch@vger.kernel.org \ --cc=linux-doc@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-mm@kvack.org \ --cc=luto@amacapital.net \ --cc=mike.kravetz@oracle.com \ --cc=mingo@redhat.com \ --cc=nadav.amit@gmail.com \ --cc=oleg@redhat.com \ --cc=tglx@linutronix.de \ --cc=x86@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).