From: Qais Yousef <qais.yousef@arm.com>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
"Peter Zijlstra (Intel)" <peterz@infradead.org>,
Morten Rasmussen <morten.rasmussen@arm.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Linus Torvalds <torvalds@linux-foundation.org>,
James Morse <james.morse@arm.com>,
linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org
Subject: Re: [RFC PATCH v2 4/4] arm64: Export id_aar64fpr0 via sysfs
Date: Thu, 22 Oct 2020 10:58:01 +0100 [thread overview]
Message-ID: <20201022095801.4xb4xrvxm35cmz5b@e107158-lin> (raw)
In-Reply-To: <20201022081624.GA1229@gaia>
On 10/22/20 09:16, Catalin Marinas wrote:
> On Wed, Oct 21, 2020 at 09:26:27PM +0100, Will Deacon wrote:
> > On Wed, Oct 21, 2020 at 08:57:36PM +0100, Qais Yousef wrote:
> > > On 10/21/20 18:23, Will Deacon wrote:
> > > > On Wed, Oct 21, 2020 at 05:07:30PM +0100, Qais Yousef wrote:
> > > > > > > For example, the new sysctl_enable_asym_32bit could be a cpumask instead of
> > > > > > > a bool as it currently is. Or we can make it a cmdline parameter too.
> > > > > > > In both cases some admin (bootloader or init process) has to ensure to fill it
> > > > > > > correctly for the target platform. The bootloader should be able to read the
> > > > > > > registers to figure out the mask. So more weight to make it a cmdline param.
> > > > > >
> > > > > > I think this is adding complexity for the sake of it. I'm much more in
> > > > >
> > > > > I actually think it reduces complexity. No special ABI to generate the mask
> > > > > from the kernel. The same opt-in flag is the cpumask too.
> > > >
> > > > Maybe I'm misunderstanding your proposal but having a cpumask instead of
> > >
> > > What I meant is that if we change the requirement to opt-in from a boolean
> > > switch
> > >
> > > sysctl.enable_32bit_asym=1
> > >
> > > to require the bootloader/init scripts provide the mask of aarch32 capable cpus
> > >
> > > sysctl.asym_32bit_cpus=0xf0
> [...]
> > > * We don't need a separate API to export which cpus are 32bit capable.
> > > They can read it directly from /proc/sys/kernel/asym_32bit_cpus.
> > > When it's 0 it means the system is not asymmetric.
> >
> > I don't see how this is better than a separate cpumask for this purpose.
> > It feels like you're trying to overload the control and the identification,
> > but that just makes things confusing and hard to use as I now need to know
> > which logical CPUs correspond to which physical CPUs in order to set the
> > command-line.
I tend to disagree with some of the statements. But I'll leave it at that.
Whatever makes the ship move :)
> I agree. Let's leave the identification to the kernel as it has access
> to the CPUID registers and can provide the cpumask. The control in this
> case doesn't need to be more than a boolean and its meaning is that the
> user knows what it is doing.
Thanks
--
Qais Yousef
next prev parent reply other threads:[~2020-10-22 9:58 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-21 10:46 [RFC PATCH v2 0/4] Add support for Asymmetric AArch32 systems Qais Yousef
2020-10-21 10:46 ` [RFC PATCH v2 1/4] arm64: kvm: Handle " Qais Yousef
2020-10-21 12:02 ` Marc Zyngier
2020-10-21 13:35 ` Qais Yousef
2020-10-21 13:51 ` Marc Zyngier
2020-10-21 14:38 ` Qais Yousef
2020-11-02 17:58 ` Qais Yousef
2020-10-21 10:46 ` [RFC PATCH v2 2/4] arm64: Add support for asymmetric AArch32 EL0 configurations Qais Yousef
2020-10-21 15:39 ` Will Deacon
2020-10-21 16:21 ` Qais Yousef
2020-10-21 16:52 ` Catalin Marinas
2020-10-21 17:39 ` Will Deacon
2020-10-22 9:53 ` Catalin Marinas
2020-10-21 10:46 ` [RFC PATCH v2 3/4] arm64: export emulate_sys_reg() Qais Yousef
2020-10-21 10:46 ` [RFC PATCH v2 4/4] arm64: Export id_aar64fpr0 via sysfs Qais Yousef
2020-10-21 11:09 ` Marc Zyngier
2020-10-21 11:25 ` Greg Kroah-Hartman
2020-10-21 11:46 ` Marc Zyngier
2020-10-21 12:11 ` Greg Kroah-Hartman
2020-10-21 13:18 ` Qais Yousef
2020-10-21 12:15 ` Catalin Marinas
2020-10-21 13:20 ` Qais Yousef
2020-10-21 13:33 ` Morten Rasmussen
2020-10-21 14:09 ` Catalin Marinas
2020-10-21 14:41 ` Morten Rasmussen
2020-10-21 14:45 ` Will Deacon
2020-10-21 15:10 ` Catalin Marinas
2020-10-21 15:37 ` Will Deacon
2020-10-21 16:18 ` Catalin Marinas
2020-10-21 17:19 ` Will Deacon
2020-10-22 9:55 ` Morten Rasmussen
2020-10-21 14:31 ` Qais Yousef
2020-10-22 10:16 ` Morten Rasmussen
2020-10-22 10:48 ` Qais Yousef
2020-10-21 14:41 ` Will Deacon
2020-10-21 15:03 ` Qais Yousef
2020-10-21 15:23 ` Will Deacon
2020-10-21 16:07 ` Qais Yousef
2020-10-21 17:23 ` Will Deacon
2020-10-21 19:57 ` Qais Yousef
2020-10-21 20:26 ` Will Deacon
2020-10-22 8:16 ` Catalin Marinas
2020-10-22 9:58 ` Qais Yousef [this message]
2020-10-22 13:47 ` Qais Yousef
2020-10-22 13:55 ` Greg Kroah-Hartman
2020-10-22 14:31 ` Catalin Marinas
2020-10-22 14:34 ` Qais Yousef
2020-10-26 19:02 ` Qais Yousef
2020-10-26 19:08 ` Greg Kroah-Hartman
2020-10-26 19:18 ` Qais Yousef
2020-10-21 11:28 ` Greg Kroah-Hartman
2020-10-21 13:22 ` Qais Yousef
2020-10-21 11:26 ` [RFC PATCH v2 0/4] Add support for Asymmetric AArch32 systems Greg Kroah-Hartman
2020-10-21 13:15 ` Qais Yousef
2020-10-21 13:31 ` Greg Kroah-Hartman
2020-10-21 13:55 ` Qais Yousef
2020-10-21 14:35 ` Catalin Marinas
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