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From: Marc Zyngier <maz@kernel.org>
To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Qais Yousef <qais.yousef@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	"Peter Zijlstra (Intel)" <peterz@infradead.org>,
	Morten Rasmussen <morten.rasmussen@arm.com>,
	Linus Torvalds <torvalds@linux-foundation.org>,
	James Morse <james.morse@arm.com>,
	linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org
Subject: Re: [RFC PATCH v2 4/4] arm64: Export id_aar64fpr0 via sysfs
Date: Wed, 21 Oct 2020 12:46:46 +0100	[thread overview]
Message-ID: <a534ade95315a55c4ab3048727d846a1@kernel.org> (raw)
In-Reply-To: <20201021112519.GA1141598@kroah.com>

On 2020-10-21 12:25, Greg Kroah-Hartman wrote:
> On Wed, Oct 21, 2020 at 12:09:58PM +0100, Marc Zyngier wrote:
>> On 2020-10-21 11:46, Qais Yousef wrote:
>> > So that userspace can detect if the cpu has aarch32 support at EL0.
>> >
>> > CPUREGS_ATTR_RO() was renamed to CPUREGS_RAW_ATTR_RO() to better reflect
>> > what it does. And fixed to accept both u64 and u32 without causing the
>> > printf to print out a warning about mismatched type. This was caught
>> > while testing to check the new CPUREGS_USER_ATTR_RO().
>> >
>> > The new CPUREGS_USER_ATTR_RO() exports a Sanitised or RAW sys_reg based
>> > on a @cond to user space. The exported fields match the definition in
>> > arm64_ftr_reg so that the content of a register exported via MRS and
>> > sysfs are kept cohesive.
>> >
>> > The @cond in our case is that the system is asymmetric aarch32 and the
>> > controlling sysctl.enable_asym_32bit is enabled.
>> >
>> > Update Documentation/arm64/cpu-feature-registers.rst to reflect the
>> > newly visible EL0 field in ID_AA64FPR0_EL1.
>> >
>> > Note that the MRS interface will still return the sanitized content
>> > _only_.
>> >
>> > Signed-off-by: Qais Yousef <qais.yousef@arm.com>
>> > ---
>> >
>> > Example output. I was surprised that the 2nd field (bits[7:4]) is
>> > printed out
>> > although it's set as FTR_HIDDEN.
>> >
>> > # cat /sys/devices/system/cpu/cpu*/regs/identification/id_aa64pfr0
>> > 0x0000000000000011
>> > 0x0000000000000011
>> > 0x0000000000000011
>> > 0x0000000000000011
>> > 0x0000000000000011
>> > 0x0000000000000011
>> >
>> > # echo 1 > /proc/sys/kernel/enable_asym_32bit
>> >
>> > # cat /sys/devices/system/cpu/cpu*/regs/identification/id_aa64pfr0
>> > 0x0000000000000011
>> > 0x0000000000000011
>> > 0x0000000000000012
>> > 0x0000000000000012
>> > 0x0000000000000011
>> > 0x0000000000000011
>> 
>> This looks like a terrible userspace interface.
> 
> It's also not allowed, sorry.  sysfs is "one value per file", which is
> NOT what is happening at all.

I *think* Qais got that part right, though it is hard to tell without
knowing how many CPUs this system has (cpu/cpu* is ambiguous).

         M.
-- 
Jazz is not dead. It just smells funny...

  reply	other threads:[~2020-10-21 11:46 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-21 10:46 [RFC PATCH v2 0/4] Add support for Asymmetric AArch32 systems Qais Yousef
2020-10-21 10:46 ` [RFC PATCH v2 1/4] arm64: kvm: Handle " Qais Yousef
2020-10-21 12:02   ` Marc Zyngier
2020-10-21 13:35     ` Qais Yousef
2020-10-21 13:51       ` Marc Zyngier
2020-10-21 14:38         ` Qais Yousef
2020-11-02 17:58         ` Qais Yousef
2020-10-21 10:46 ` [RFC PATCH v2 2/4] arm64: Add support for asymmetric AArch32 EL0 configurations Qais Yousef
2020-10-21 15:39   ` Will Deacon
2020-10-21 16:21     ` Qais Yousef
2020-10-21 16:52       ` Catalin Marinas
2020-10-21 17:39         ` Will Deacon
2020-10-22  9:53           ` Catalin Marinas
2020-10-21 10:46 ` [RFC PATCH v2 3/4] arm64: export emulate_sys_reg() Qais Yousef
2020-10-21 10:46 ` [RFC PATCH v2 4/4] arm64: Export id_aar64fpr0 via sysfs Qais Yousef
2020-10-21 11:09   ` Marc Zyngier
2020-10-21 11:25     ` Greg Kroah-Hartman
2020-10-21 11:46       ` Marc Zyngier [this message]
2020-10-21 12:11         ` Greg Kroah-Hartman
2020-10-21 13:18         ` Qais Yousef
2020-10-21 12:15     ` Catalin Marinas
2020-10-21 13:20       ` Qais Yousef
2020-10-21 13:33       ` Morten Rasmussen
2020-10-21 14:09         ` Catalin Marinas
2020-10-21 14:41           ` Morten Rasmussen
2020-10-21 14:45           ` Will Deacon
2020-10-21 15:10             ` Catalin Marinas
2020-10-21 15:37               ` Will Deacon
2020-10-21 16:18                 ` Catalin Marinas
2020-10-21 17:19                   ` Will Deacon
2020-10-22  9:55                     ` Morten Rasmussen
2020-10-21 14:31         ` Qais Yousef
2020-10-22 10:16           ` Morten Rasmussen
2020-10-22 10:48             ` Qais Yousef
2020-10-21 14:41       ` Will Deacon
2020-10-21 15:03         ` Qais Yousef
2020-10-21 15:23           ` Will Deacon
2020-10-21 16:07             ` Qais Yousef
2020-10-21 17:23               ` Will Deacon
2020-10-21 19:57                 ` Qais Yousef
2020-10-21 20:26                   ` Will Deacon
2020-10-22  8:16                     ` Catalin Marinas
2020-10-22  9:58                       ` Qais Yousef
2020-10-22 13:47         ` Qais Yousef
2020-10-22 13:55           ` Greg Kroah-Hartman
2020-10-22 14:31             ` Catalin Marinas
2020-10-22 14:34               ` Qais Yousef
2020-10-26 19:02             ` Qais Yousef
2020-10-26 19:08               ` Greg Kroah-Hartman
2020-10-26 19:18                 ` Qais Yousef
2020-10-21 11:28   ` Greg Kroah-Hartman
2020-10-21 13:22     ` Qais Yousef
2020-10-21 11:26 ` [RFC PATCH v2 0/4] Add support for Asymmetric AArch32 systems Greg Kroah-Hartman
2020-10-21 13:15   ` Qais Yousef
2020-10-21 13:31     ` Greg Kroah-Hartman
2020-10-21 13:55       ` Qais Yousef
2020-10-21 14:35       ` Catalin Marinas

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