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From: Huang Pei <huangpei@loongson.cn>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>, ambrosehua@gmail.com
Cc: Bibo Mao <maobibo@loongson.cn>,
	Andrew Morton <akpm@linux-foundation.org>,
	linux-mips@vger.kernel.org, linux-arch@vger.kernel.org,
	linux-mm@kvack.org, Jiaxun Yang <jiaxun.yang@flygoat.com>,
	Paul Burton <paulburton@kernel.org>,
	Li Xuefeng <lixuefeng@loongson.cn>,
	Yang Tiezhu <yangtiezhu@loongson.cn>,
	Gao Juxin <gaojuxin@loongson.cn>,
	Huacai Chen <chenhuacai@loongson.cn>,
	Jinyang He <hejinyang@loongson.cn>
Subject: [PATCH 1/3] MIPS: sync arrangement of pt_regs with user_pt_regs and regoffset_table
Date: Fri,  5 Mar 2021 18:03:08 +0800	[thread overview]
Message-ID: <20210305100310.26627-2-huangpei@loongson.cn> (raw)
In-Reply-To: <20210305100310.26627-1-huangpei@loongson.cn>

Signed-off-by: Huang Pei <huangpei@loongson.cn>
---
 arch/mips/include/asm/ptrace.h | 10 +++++-----
 arch/mips/kernel/asm-offsets.c |  6 +++---
 arch/mips/kernel/ptrace.c      | 10 +++++-----
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index 1e76774b36dd..e51691f2b7af 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -34,16 +34,16 @@ struct pt_regs {
 	/* Saved main processor registers. */
 	unsigned long regs[32];
 
+	unsigned long lo;
+	unsigned long hi;
 	/* Saved special registers. */
+	unsigned long cp0_epc;
+	unsigned long cp0_badvaddr;
 	unsigned long cp0_status;
-	unsigned long hi;
-	unsigned long lo;
+	unsigned long cp0_cause;
 #ifdef CONFIG_CPU_HAS_SMARTMIPS
 	unsigned long acx;
 #endif
-	unsigned long cp0_badvaddr;
-	unsigned long cp0_cause;
-	unsigned long cp0_epc;
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 	unsigned long long mpl[6];        /* MTM{0-5} */
 	unsigned long long mtp[6];        /* MTP{0-5} */
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index aebfda81120a..8a9ab78bcc63 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -60,13 +60,13 @@ void output_ptreg_defines(void)
 	OFFSET(PT_R31, pt_regs, regs[31]);
 	OFFSET(PT_LO, pt_regs, lo);
 	OFFSET(PT_HI, pt_regs, hi);
-#ifdef CONFIG_CPU_HAS_SMARTMIPS
-	OFFSET(PT_ACX, pt_regs, acx);
-#endif
 	OFFSET(PT_EPC, pt_regs, cp0_epc);
 	OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr);
 	OFFSET(PT_STATUS, pt_regs, cp0_status);
 	OFFSET(PT_CAUSE, pt_regs, cp0_cause);
+#ifdef CONFIG_CPU_HAS_SMARTMIPS
+	OFFSET(PT_ACX, pt_regs, acx);
+#endif
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 	OFFSET(PT_MPL, pt_regs, mpl);
 	OFFSET(PT_MTP, pt_regs, mtp);
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index db7c5be1d4a3..06ee1184fad3 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -886,15 +886,15 @@ static const struct pt_regs_offset regoffset_table[] = {
 	REG_OFFSET_NAME(r29, regs[29]),
 	REG_OFFSET_NAME(r30, regs[30]),
 	REG_OFFSET_NAME(r31, regs[31]),
-	REG_OFFSET_NAME(c0_status, cp0_status),
-	REG_OFFSET_NAME(hi, hi),
 	REG_OFFSET_NAME(lo, lo),
+	REG_OFFSET_NAME(hi, hi),
+	REG_OFFSET_NAME(c0_epc, cp0_epc),
+	REG_OFFSET_NAME(c0_badvaddr, cp0_badvaddr),
+	REG_OFFSET_NAME(c0_status, cp0_status),
+	REG_OFFSET_NAME(c0_cause, cp0_cause),
 #ifdef CONFIG_CPU_HAS_SMARTMIPS
 	REG_OFFSET_NAME(acx, acx),
 #endif
-	REG_OFFSET_NAME(c0_badvaddr, cp0_badvaddr),
-	REG_OFFSET_NAME(c0_cause, cp0_cause),
-	REG_OFFSET_NAME(c0_epc, cp0_epc),
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 	REG_OFFSET_NAME(mpl0, mpl[0]),
 	REG_OFFSET_NAME(mpl1, mpl[1]),
-- 
2.17.1


  reply	other threads:[~2021-03-05 10:04 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-05 10:03 [PATCH V2]: MIPS work Huang Pei
2021-03-05 10:03 ` Huang Pei [this message]
2021-03-06  7:47   ` [PATCH 1/3] MIPS: sync arrangement of pt_regs with user_pt_regs and regoffset_table Thomas Bogendoerfer
2021-03-07  1:36     ` 黄沛
2021-03-05 10:03 ` [PATCH 2/3] MIPS: clean up CONFIG_MIPS_PGD_C0_CONTEXT handling Huang Pei
2021-03-05 10:03 ` [PATCH 3/3] MIPS: loongson64: alloc pglist_data at run time Huang Pei

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