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From: ebiederm@xmission.com (Eric W. Biederman)
To: Arnd Bergmann <arnd@arndb.de>
Cc: linux-arch <linux-arch@vger.kernel.org>,
	Richard Earnshaw <Richard.Earnshaw@arm.com>,
	Szabolcs Nagy <szabolcs.nagy@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Kevin Brodsky <kevin.brodsky@arm.com>,
	Andrey Konovalov <andreyknvl@google.com>,
	Linux-MM <linux-mm@kvack.org>, Al Viro <viro@zeniv.linux.org.uk>,
	Marc Zyngier <maz@kernel.org>,
	Vincenzo Frascino <vincenzo.frascino@arm.com>,
	Will Deacon <will@kernel.org>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 12/22] arm64: mte: Add specific SIGSEGV codes
Date: Thu, 12 Dec 2019 12:26:41 -0600	[thread overview]
Message-ID: <87zhfxqu1q.fsf@x220.int.ebiederm.org> (raw)
In-Reply-To: <CAK8P3a1-eaR7NddhDce65vXKCGeZD3xUMrTTAWN4U3oW0ecN=g@mail.gmail.com> (Arnd Bergmann's message of "Wed, 11 Dec 2019 20:31:28 +0100")

Arnd Bergmann <arnd@arndb.de> writes:

> On Wed, Dec 11, 2019 at 7:40 PM Catalin Marinas <catalin.marinas@arm.com> wrote:
>>
>> From: Vincenzo Frascino <vincenzo.frascino@arm.com>
>>
>> Add MTE-specific SIGSEGV codes to siginfo.h.
>>
>> Note that the for MTE we are reusing the same SPARC ADI codes because
>> the two functionalities are similar and they cannot coexist on the same
>> system.

Please Please Please don't do that.

It is actively harmful to have architecture specific si_code values.
As it makes maintenance much more difficult.

Especially as the si_codes are part of union descrimanator.

If your functionality is identical reuse the numbers otherwise please
just select the next numbers not yet used.

We have at least 256 si_codes per signal 2**32 if we really need them so
there is no need to be reuse numbers.

The practical problem is that architecture specific si_codes start
turning kernel/signal.c into #ifdef soup, and we loose a lot of
basic compile coverage because of that.  In turn not compiling the code
leads to bit-rot in all kinds of weird places.



Now as far as the observation that this is almost the same as other
functionality why can't this fit the existing interface exposed to
userspace?   Sometimes there are good reasons, but technology gets
a lot more uptake and testing when the same interfaces are more widely
available.

Eric

p.s. As for coexistence there is always the possibility that one chip
in a cpu family does supports one thing and another chip in a cpu
family supports another.  So userspace may have to cope with the
situation even if an individual chip doesn't.

I remember a similar case where sparc had several distinct page table
formats and we had a single kernel that had to cope with them all.


>> Cc: Arnd Bergmann <arnd@arndb.de>
>> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
>> [catalin.marinas@arm.com: renamed precise/imprecise to sync/async]
>> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
>> ---
>>  include/uapi/asm-generic/siginfo.h | 9 +++++++--
>>  1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/include/uapi/asm-generic/siginfo.h b/include/uapi/asm-generic/siginfo.h
>> index cb3d6c267181..a5184a5438c6 100644
>> --- a/include/uapi/asm-generic/siginfo.h
>> +++ b/include/uapi/asm-generic/siginfo.h
>> @@ -227,8 +227,13 @@ typedef struct siginfo {
>>  # define SEGV_PKUERR   4       /* failed protection key checks */
>>  #endif
>>  #define SEGV_ACCADI    5       /* ADI not enabled for mapped object */
>> -#define SEGV_ADIDERR   6       /* Disrupting MCD error */
>> -#define SEGV_ADIPERR   7       /* Precise MCD exception */
>> +#ifdef __aarch64__
>> +# define SEGV_MTEAERR  6       /* Asynchronous MTE error */
>> +# define SEGV_MTESERR  7       /* Synchronous MTE exception */
>> +#else
>> +# define SEGV_ADIDERR  6       /* Disrupting MCD error */
>> +# define SEGV_ADIPERR  7       /* Precise MCD exception */
>> +#endif
>
> SEGV_ADIPERR/SEGV_ADIDERR were added together with SEGV_ACCADI,
> it seems a bit odd to make only two of them conditional but not the others.
>
> I think we are generally working towards having the same constants
> across architectures even for features that only exist on one of them.
>
> Adding Al and Eric to Cc, maybe they have another suggestion on what
> constants should be used.
>
>      Arnd

WARNING: multiple messages have this Message-ID (diff)
From: ebiederm@xmission.com (Eric W. Biederman)
To: Arnd Bergmann <arnd@arndb.de>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
	Vincenzo Frascino <vincenzo.frascino@arm.com>,
	Szabolcs Nagy <szabolcs.nagy@arm.com>,
	Richard Earnshaw <Richard.Earnshaw@arm.com>,
	Kevin Brodsky <kevin.brodsky@arm.com>,
	Andrey Konovalov <andreyknvl@google.com>,
	Linux-MM <linux-mm@kvack.org>,
	linux-arch <linux-arch@vger.kernel.org>,
	Al Viro <viro@zeniv.linux.org.uk>
Subject: Re: [PATCH 12/22] arm64: mte: Add specific SIGSEGV codes
Date: Thu, 12 Dec 2019 12:26:41 -0600	[thread overview]
Message-ID: <87zhfxqu1q.fsf@x220.int.ebiederm.org> (raw)
Message-ID: <20191212182641.Sv8dv56azP0gmdOwu1HMLKKCl1A5yEuMAXs9fMtJt2w@z> (raw)
In-Reply-To: <CAK8P3a1-eaR7NddhDce65vXKCGeZD3xUMrTTAWN4U3oW0ecN=g@mail.gmail.com> (Arnd Bergmann's message of "Wed, 11 Dec 2019 20:31:28 +0100")

Arnd Bergmann <arnd@arndb.de> writes:

> On Wed, Dec 11, 2019 at 7:40 PM Catalin Marinas <catalin.marinas@arm.com> wrote:
>>
>> From: Vincenzo Frascino <vincenzo.frascino@arm.com>
>>
>> Add MTE-specific SIGSEGV codes to siginfo.h.
>>
>> Note that the for MTE we are reusing the same SPARC ADI codes because
>> the two functionalities are similar and they cannot coexist on the same
>> system.

Please Please Please don't do that.

It is actively harmful to have architecture specific si_code values.
As it makes maintenance much more difficult.

Especially as the si_codes are part of union descrimanator.

If your functionality is identical reuse the numbers otherwise please
just select the next numbers not yet used.

We have at least 256 si_codes per signal 2**32 if we really need them so
there is no need to be reuse numbers.

The practical problem is that architecture specific si_codes start
turning kernel/signal.c into #ifdef soup, and we loose a lot of
basic compile coverage because of that.  In turn not compiling the code
leads to bit-rot in all kinds of weird places.



Now as far as the observation that this is almost the same as other
functionality why can't this fit the existing interface exposed to
userspace?   Sometimes there are good reasons, but technology gets
a lot more uptake and testing when the same interfaces are more widely
available.

Eric

p.s. As for coexistence there is always the possibility that one chip
in a cpu family does supports one thing and another chip in a cpu
family supports another.  So userspace may have to cope with the
situation even if an individual chip doesn't.

I remember a similar case where sparc had several distinct page table
formats and we had a single kernel that had to cope with them all.


>> Cc: Arnd Bergmann <arnd@arndb.de>
>> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
>> [catalin.marinas@arm.com: renamed precise/imprecise to sync/async]
>> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
>> ---
>>  include/uapi/asm-generic/siginfo.h | 9 +++++++--
>>  1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/include/uapi/asm-generic/siginfo.h b/include/uapi/asm-generic/siginfo.h
>> index cb3d6c267181..a5184a5438c6 100644
>> --- a/include/uapi/asm-generic/siginfo.h
>> +++ b/include/uapi/asm-generic/siginfo.h
>> @@ -227,8 +227,13 @@ typedef struct siginfo {
>>  # define SEGV_PKUERR   4       /* failed protection key checks */
>>  #endif
>>  #define SEGV_ACCADI    5       /* ADI not enabled for mapped object */
>> -#define SEGV_ADIDERR   6       /* Disrupting MCD error */
>> -#define SEGV_ADIPERR   7       /* Precise MCD exception */
>> +#ifdef __aarch64__
>> +# define SEGV_MTEAERR  6       /* Asynchronous MTE error */
>> +# define SEGV_MTESERR  7       /* Synchronous MTE exception */
>> +#else
>> +# define SEGV_ADIDERR  6       /* Disrupting MCD error */
>> +# define SEGV_ADIPERR  7       /* Precise MCD exception */
>> +#endif
>
> SEGV_ADIPERR/SEGV_ADIDERR were added together with SEGV_ACCADI,
> it seems a bit odd to make only two of them conditional but not the others.
>
> I think we are generally working towards having the same constants
> across architectures even for features that only exist on one of them.
>
> Adding Al and Eric to Cc, maybe they have another suggestion on what
> constants should be used.
>
>      Arnd

  parent reply	other threads:[~2019-12-12 18:26 UTC|newest]

Thread overview: 92+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-11 18:40 [PATCH 00/22] arm64: Memory Tagging Extension user-space support Catalin Marinas
2019-12-11 18:40 ` Catalin Marinas
2019-12-11 18:40 ` [PATCH 01/22] mm: Reserve asm-generic prot flags 0x10 and 0x20 for arch use Catalin Marinas
2019-12-11 18:40   ` Catalin Marinas
2019-12-11 19:26   ` Arnd Bergmann
2019-12-11 19:26     ` Arnd Bergmann
2019-12-11 18:40 ` [PATCH 02/22] kbuild: Add support for 'as-instr' to be used in Kconfig files Catalin Marinas
2019-12-11 18:40   ` Catalin Marinas
2019-12-12  5:03   ` Masahiro Yamada
2019-12-12  5:03     ` Masahiro Yamada
2019-12-11 18:40 ` [PATCH 03/22] arm64: alternative: Allow alternative_insn to always issue the first instruction Catalin Marinas
2019-12-11 18:40   ` Catalin Marinas
2019-12-11 18:40 ` [PATCH 04/22] arm64: Use macros instead of hard-coded constants for MAIR_EL1 Catalin Marinas
2019-12-11 18:40   ` Catalin Marinas
2019-12-11 18:40 ` [PATCH 05/22] arm64: mte: system register definitions Catalin Marinas
2019-12-11 18:40   ` Catalin Marinas
2019-12-11 18:40 ` [PATCH 06/22] arm64: mte: CPU feature detection and initial sysreg configuration Catalin Marinas
2019-12-11 18:40   ` Catalin Marinas
2019-12-11 18:40 ` [PATCH 07/22] arm64: mte: Use Normal Tagged attributes for the linear map Catalin Marinas
2019-12-11 18:40   ` Catalin Marinas
2019-12-11 18:40 ` [PATCH 08/22] arm64: mte: Assembler macros and default architecture for .S files Catalin Marinas
2019-12-11 18:40   ` Catalin Marinas
2019-12-11 18:40 ` [PATCH 09/22] arm64: mte: Tags-aware clear_page() implementation Catalin Marinas
2019-12-11 18:40   ` Catalin Marinas
2019-12-11 18:40 ` [PATCH 10/22] arm64: mte: Tags-aware copy_page() implementation Catalin Marinas
2019-12-11 18:40   ` Catalin Marinas
2019-12-11 18:40 ` [PATCH 11/22] arm64: Tags-aware memcmp_pages() implementation Catalin Marinas
2019-12-11 18:40   ` Catalin Marinas
2019-12-11 18:40 ` [PATCH 12/22] arm64: mte: Add specific SIGSEGV codes Catalin Marinas
2019-12-11 18:40   ` Catalin Marinas
2019-12-11 19:31   ` Arnd Bergmann
2019-12-11 19:31     ` Arnd Bergmann
2019-12-12  9:34     ` Catalin Marinas
2019-12-12  9:34       ` Catalin Marinas
2019-12-12 18:26     ` Eric W. Biederman [this message]
2019-12-12 18:26       ` Eric W. Biederman
2019-12-17 17:48       ` Catalin Marinas
2019-12-17 17:48         ` Catalin Marinas
2019-12-17 20:06         ` Eric W. Biederman
2019-12-17 20:06           ` Eric W. Biederman
2019-12-11 18:40 ` [PATCH 13/22] arm64: mte: Handle synchronous and asynchronous tag check faults Catalin Marinas
2019-12-11 18:40   ` Catalin Marinas
2019-12-14  1:43   ` Peter Collingbourne
2019-12-14  1:43     ` Peter Collingbourne
2019-12-17 18:01     ` Catalin Marinas
2019-12-17 18:01       ` Catalin Marinas
2019-12-20  1:36       ` [PATCH] arm64: mte: Do not service syscalls after async tag fault Peter Collingbourne
2019-12-20  1:36         ` Peter Collingbourne
2020-02-12 11:09         ` Catalin Marinas
2020-02-18 21:59           ` Peter Collingbourne
2020-02-19 16:16             ` Catalin Marinas
2019-12-11 18:40 ` [PATCH 14/22] mm: Introduce arch_calc_vm_flag_bits() Catalin Marinas
2019-12-11 18:40   ` Catalin Marinas
2019-12-11 18:40 ` [PATCH 15/22] arm64: mte: Add PROT_MTE support to mmap() and mprotect() Catalin Marinas
2019-12-11 18:40   ` Catalin Marinas
2020-01-21 22:06   ` Peter Collingbourne
2019-12-11 18:40 ` [PATCH 16/22] mm: Introduce arch_validate_flags() Catalin Marinas
2019-12-11 18:40   ` Catalin Marinas
2019-12-11 18:40 ` [PATCH 17/22] arm64: mte: Validate the PROT_MTE request via arch_validate_flags() Catalin Marinas
2019-12-11 18:40   ` Catalin Marinas
2019-12-11 18:40 ` [PATCH 18/22] mm: Allow arm64 mmap(PROT_MTE) on RAM-based files Catalin Marinas
2019-12-11 18:40   ` Catalin Marinas
2019-12-11 18:40 ` [PATCH 19/22] arm64: mte: Allow user control of the tag check mode via prctl() Catalin Marinas
2019-12-11 18:40   ` Catalin Marinas
2019-12-19 20:32   ` Peter Collingbourne
2019-12-19 20:32     ` Peter Collingbourne
2019-12-20  1:48     ` [PATCH] arm64: mte: Clear SCTLR_EL1.TCF0 on exec Peter Collingbourne
2019-12-20  1:48       ` Peter Collingbourne
2020-02-12 17:03       ` Catalin Marinas
2019-12-27 14:34   ` [PATCH 19/22] arm64: mte: Allow user control of the tag check mode via prctl() Kevin Brodsky
2019-12-27 14:34     ` Kevin Brodsky
2020-02-12 11:45     ` Catalin Marinas
2019-12-11 18:40 ` [PATCH 20/22] arm64: mte: Allow user control of the excluded tags " Catalin Marinas
2019-12-11 18:40   ` Catalin Marinas
2019-12-16 14:20   ` Kevin Brodsky
2019-12-16 14:20     ` Kevin Brodsky
2019-12-16 17:30     ` Peter Collingbourne
2019-12-16 17:30       ` Peter Collingbourne
2019-12-17 17:56       ` Catalin Marinas
2019-12-17 17:56         ` Catalin Marinas
2020-06-22 17:17       ` Catalin Marinas
2020-06-22 19:00         ` Peter Collingbourne
2020-06-23 16:42           ` Catalin Marinas
2019-12-11 18:40 ` [PATCH 21/22] arm64: mte: Kconfig entry Catalin Marinas
2019-12-11 18:40   ` Catalin Marinas
2019-12-11 18:40 ` [PATCH 22/22] arm64: mte: Add Memory Tagging Extension documentation Catalin Marinas
2019-12-11 18:40   ` Catalin Marinas
2019-12-24 15:03   ` Kevin Brodsky
2019-12-24 15:03     ` Kevin Brodsky
2019-12-13 18:05 ` [PATCH 00/22] arm64: Memory Tagging Extension user-space support Peter Collingbourne
2019-12-13 18:05   ` Peter Collingbourne
2020-02-13 11:23   ` Catalin Marinas

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