* [PATCH v2 2/3] dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF
2021-11-12 5:38 [PATCH v2 1/3] ARM: dts: stm32: Enable LVDS panel on i.Core STM32MP1 EDIMM2.2 Jagan Teki
@ 2021-11-12 5:38 ` Jagan Teki
2021-11-29 1:42 ` Rob Herring
2021-11-12 5:38 ` [PATCH v2 3/3] ARM: dts: " Jagan Teki
2021-11-29 13:38 ` [PATCH v2 1/3] ARM: dts: stm32: Enable LVDS panel on i.Core STM32MP1 EDIMM2.2 Alexandre TORGUE
2 siblings, 1 reply; 5+ messages in thread
From: Jagan Teki @ 2021-11-12 5:38 UTC (permalink / raw)
To: Rob Herring, Maxime Coquelin, Alexandre Torgue
Cc: devicetree, linux-stm32, linux-arm-kernel, linux-amarula,
Matteo Lisi, Jagan Teki
i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.
C.TOUCH 2.0 is a general purpose carrier board with capacitive
touch interface support.
10.1" OF is a capacitive touch 10.1" Open Frame panel solutions.
i.Core STM32MP1 needs to mount on top of C.TOUCH 2.0 carrier with
pluged 10.1" OF for creating complete i.Core STM32MP1 C.TOUCH 2.0
10.1" Open Frame board.
Add bindings for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- Fix line-length warning
Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
index bcaf7be3ab37..b07720ea9611 100644
--- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
@@ -77,6 +77,7 @@ properties:
items:
- enum:
- engicam,icore-stm32mp1-ctouch2 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0
+ - engicam,icore-stm32mp1-ctouch2-of10 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF
- engicam,icore-stm32mp1-edimm2.2 # STM32MP1 Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit
- const: engicam,icore-stm32mp1 # STM32MP1 Engicam i.Core STM32MP1 SoM
- const: st,stm32mp157
--
2.25.1
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* Re: [PATCH v2 2/3] dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF
2021-11-12 5:38 ` [PATCH v2 2/3] dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF Jagan Teki
@ 2021-11-29 1:42 ` Rob Herring
0 siblings, 0 replies; 5+ messages in thread
From: Rob Herring @ 2021-11-29 1:42 UTC (permalink / raw)
To: Jagan Teki
Cc: Maxime Coquelin, linux-stm32, Matteo Lisi, devicetree,
Alexandre Torgue, linux-amarula, Rob Herring, linux-arm-kernel
On Fri, 12 Nov 2021 11:08:55 +0530, Jagan Teki wrote:
> i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.
>
> C.TOUCH 2.0 is a general purpose carrier board with capacitive
> touch interface support.
>
> 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions.
>
> i.Core STM32MP1 needs to mount on top of C.TOUCH 2.0 carrier with
> pluged 10.1" OF for creating complete i.Core STM32MP1 C.TOUCH 2.0
> 10.1" Open Frame board.
>
> Add bindings for it.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> Changes for v2:
> - Fix line-length warning
>
> Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
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* [PATCH v2 3/3] ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF
2021-11-12 5:38 [PATCH v2 1/3] ARM: dts: stm32: Enable LVDS panel on i.Core STM32MP1 EDIMM2.2 Jagan Teki
2021-11-12 5:38 ` [PATCH v2 2/3] dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF Jagan Teki
@ 2021-11-12 5:38 ` Jagan Teki
2021-11-29 13:38 ` [PATCH v2 1/3] ARM: dts: stm32: Enable LVDS panel on i.Core STM32MP1 EDIMM2.2 Alexandre TORGUE
2 siblings, 0 replies; 5+ messages in thread
From: Jagan Teki @ 2021-11-12 5:38 UTC (permalink / raw)
To: Rob Herring, Maxime Coquelin, Alexandre Torgue
Cc: devicetree, linux-stm32, linux-arm-kernel, linux-amarula,
Matteo Lisi, Jagan Teki
ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0
Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
board.
Genaral features:
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- 10" LVDS Panel (SN65DSI84 DSI-LVDS bridge on SoM)
i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.
10.1" OF is a capacitive touch 10.1" Open Frame panel solutions.
i.Core STM32MP1 needs to mount on top of C.TOUCH 2.0 carrier with
pluged 10.1" OF for creating complete i.Core STM32MP1 C.TOUCH 2.0
10.1" Open Frame board.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- none
arch/arm/boot/dts/Makefile | 1 +
...tm32mp157a-icore-stm32mp1-ctouch2-of10.dts | 132 ++++++++++++++++++
2 files changed, 133 insertions(+)
create mode 100644 arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0de64f237cd8..641220e970e8 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1140,6 +1140,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
stm32mp157a-icore-stm32mp1-ctouch2.dtb \
+ stm32mp157a-icore-stm32mp1-ctouch2-of10.dtb \
stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
stm32mp157a-stinger96.dtb \
stm32mp157c-dhcom-pdk2.dtb \
diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts
new file mode 100644
index 000000000000..351be43b3d39
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/dts-v1/;
+#include "stm32mp157.dtsi"
+#include "stm32mp157a-icore-stm32mp1.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1\" Open Frame";
+ compatible = "engicam,icore-stm32mp1-ctouch2-of10",
+ "engicam,icore-stm32mp1", "st,stm32mp157";
+
+ aliases {
+ serial0 = &uart4;
+ };
+
+ backlight: backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>;
+ default-on;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ panel {
+ compatible = "ampire,am-1280800n3tzqw-t00h";
+ backlight = <&backlight>;
+ power-supply = <&v3v3>;
+
+ port {
+ panel_in_lvds: endpoint {
+ remote-endpoint = <&bridge_out>;
+ };
+ };
+ };
+};
+
+&dsi {
+ status = "okay";
+ phy-dsi-supply = <®18>;
+
+ ports {
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <<dc_ep0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&bridge_in>;
+ };
+ };
+ };
+};
+
+&i2c6 {
+ i2c-scl-falling-time-ns = <20>;
+ i2c-scl-rising-time-ns = <185>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c6_pins_a>;
+ pinctrl-1 = <&i2c6_sleep_pins_a>;
+ status = "okay";
+
+ bridge@2c {
+ compatible = "ti,sn65dsi84";
+ reg = <0x2c>;
+ enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ bridge_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ data-lanes = <0 1>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ bridge_out: endpoint {
+ remote-endpoint = <&panel_in_lvds>;
+ };
+ };
+ };
+ };
+};
+
+<dc {
+ status = "okay";
+
+ port {
+ ltdc_ep0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+};
+
+&sdmmc1 {
+ bus-width = <4>;
+ disable-wp;
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+ st,neg-edge;
+ vmmc-supply = <&v3v3>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart4_pins_a>;
+ pinctrl-1 = <&uart4_sleep_pins_a>;
+ pinctrl-2 = <&uart4_idle_pins_a>;
+ status = "okay";
+};
--
2.25.1
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* Re: [PATCH v2 1/3] ARM: dts: stm32: Enable LVDS panel on i.Core STM32MP1 EDIMM2.2
2021-11-12 5:38 [PATCH v2 1/3] ARM: dts: stm32: Enable LVDS panel on i.Core STM32MP1 EDIMM2.2 Jagan Teki
2021-11-12 5:38 ` [PATCH v2 2/3] dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF Jagan Teki
2021-11-12 5:38 ` [PATCH v2 3/3] ARM: dts: " Jagan Teki
@ 2021-11-29 13:38 ` Alexandre TORGUE
2 siblings, 0 replies; 5+ messages in thread
From: Alexandre TORGUE @ 2021-11-29 13:38 UTC (permalink / raw)
To: Jagan Teki, Rob Herring, Maxime Coquelin
Cc: devicetree, linux-stm32, linux-arm-kernel, linux-amarula, Matteo Lisi
Hi Jagan
On 11/12/21 6:38 AM, Jagan Teki wrote:
> Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit has plugged with
> 7" LVDS panel.
>
> Engicam i.Core STM32MP1 SoM has SN65DSI84 DSI to LVDS bridge.
>
> This patch adds a display pipeline to connect DSI to SN65DSI84
> to 7" LVDS panel.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> Changes for v2:
> - none
>
> .../stm32mp157a-icore-stm32mp1-edimm2.2.dts | 85 +++++++++++++++++++
> 1 file changed, 85 insertions(+)
>
> diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
> index ec9f1d1cd50f..d80b4415e761 100644
> --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
> +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
> @@ -24,6 +24,91 @@ aliases {
> chosen {
> stdout-path = "serial0:115200n8";
> };
> +
> + backlight: backlight {
> + compatible = "gpio-backlight";
> + gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>;
> + default-on;
> + };
> +
> + panel {
> + compatible = "yes-optoelectronics,ytc700tlag-05-201c";
> + backlight = <&backlight>;
> + power-supply = <&v3v3>;
> +
> + port {
> + panel_out_bridge: endpoint {
> + remote-endpoint = <&bridge_out_panel>;
> + };
> + };
> + };
> +};
> +
> +&dsi {
> + status = "okay";
> + phy-dsi-supply = <®18>;
> +
> + ports {
> + port@0 {
> + reg = <0>;
> + dsi_in_ltdc: endpoint {
> + remote-endpoint = <<dc_out_dsi>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi_out_bridge: endpoint {
> + remote-endpoint = <&bridge_in_dsi>;
> + };
> + };
> + };
> +};
> +
> +&i2c6 {
> + i2c-scl-falling-time-ns = <20>;
> + i2c-scl-rising-time-ns = <185>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&i2c6_pins_a>;
> + pinctrl-1 = <&i2c6_sleep_pins_a>;
> + status = "okay";
> +
> + bridge@2c {
> + compatible = "ti,sn65dsi84";
Running dtb_check I observe following issue:
bridge@2c: ports:port@0:endpoint:data-lanes:0:0: 1 was expected
From schema:
/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml
Note, the same issue is observed in patch[3] of the series.
regards
Alex
> + reg = <0x2c>;
> + enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + bridge_in_dsi: endpoint {
> + remote-endpoint = <&dsi_out_bridge>;
> + data-lanes = <0 1>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + bridge_out_panel: endpoint {
> + remote-endpoint = <&panel_out_bridge>;
> + };
> + };
> + };
> + };
> +};
> +
> +<dc {
> + status = "okay";
> +
> + port {
> + ltdc_out_dsi: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&dsi_in_ltdc>;
> + };
> + };
> };
>
> &sdmmc1 {
>
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