* [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework
@ 2013-02-18 8:21 Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 01/16] clk: samsung: add common clock framework helper functions for Samsung platforms Thomas Abraham
` (15 more replies)
0 siblings, 16 replies; 37+ messages in thread
From: Thomas Abraham @ 2013-02-18 8:21 UTC (permalink / raw)
To: linux-arm-kernel
Changes since v5:
- Squashed several Exynos4 fixes patch from Tomasz Figa
- Included support for Exynos5250 and Exynos5440, thus converting all
Exynos4 and Exynos5 platforms to common clock framework.
- Depends on the following patch series.
- http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg15849.html
- http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg15852.html
Changes since v4:
- Rebased to linux-3.8-rc1.
Changes since v3:
- Includes changes suggested by Tomasz Figa <tomasz.figa@gmail.com>
This patch series migrates the Samsung Exynos4/5 SoC clock code to adopt the
common clock framework. The use of Samsung specific clock structures has
been removed and all board support code has been updated. imx-style of
clock registration and lookup has been adopted for device tree based
exynos4/5 platforms.
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v6 01/16] clk: samsung: add common clock framework helper functions for Samsung platforms
2013-02-18 8:21 [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework Thomas Abraham
@ 2013-02-18 8:21 ` Thomas Abraham
2013-03-03 1:08 ` Heiko Stübner
2013-02-18 8:21 ` [PATCH v6 02/16] clk: samsung: add pll clock registration helper functions Thomas Abraham
` (14 subsequent siblings)
15 siblings, 1 reply; 37+ messages in thread
From: Thomas Abraham @ 2013-02-18 8:21 UTC (permalink / raw)
To: linux-arm-kernel
All Samsung platforms include different types of clock including fixed-rate,
mux, divider and gate clock types. There are typically hundreds of such clocks
on each of the Samsung platforms. To enable Samsung platforms to register these
clocks using the common clock framework, a bunch of utility functions are
introduced here which simplify the clock registration process. The clocks are
usually statically instantiated and registered with common clock framework.
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
drivers/clk/Makefile | 1 +
drivers/clk/samsung/Makefile | 5 +
drivers/clk/samsung/clk.c | 273 ++++++++++++++++++++++++++++++++++++++++++
drivers/clk/samsung/clk.h | 262 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 541 insertions(+), 0 deletions(-)
create mode 100644 drivers/clk/samsung/Makefile
create mode 100644 drivers/clk/samsung/clk.c
create mode 100644 drivers/clk/samsung/clk.h
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 0ad642f..1467a48 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
obj-$(CONFIG_ARCH_U8500) += ux500/
obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o
+obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
# Chip specific
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
new file mode 100644
index 0000000..bd920b4
--- /dev/null
+++ b/drivers/clk/samsung/Makefile
@@ -0,0 +1,5 @@
+#
+# Samsung Clock specific Makefile
+#
+
+obj-$(CONFIG_COMMON_CLK) += clk.o
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
new file mode 100644
index 0000000..aea1fb9
--- /dev/null
+++ b/drivers/clk/samsung/clk.c
@@ -0,0 +1,273 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ * Author: Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file includes utility functions to register clocks to common
+ * clock framework for Samsung platforms.
+*/
+
+#include <linux/syscore_ops.h>
+#include "clk.h"
+
+static DEFINE_SPINLOCK(lock);
+static struct clk **clk_table;
+static void __iomem *reg_base;
+#ifdef CONFIG_OF
+static struct clk_onecell_data clk_data;
+#endif
+
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *reg_dump;
+static unsigned long nr_reg_dump;
+
+static int samsung_clk_suspend(void)
+{
+ struct samsung_clk_reg_dump *rd = reg_dump;
+ unsigned long i;
+
+ for (i = 0; i < nr_reg_dump; i++, rd++)
+ rd->value = __raw_readl(reg_base + rd->offset);
+
+ return 0;
+}
+
+static void samsung_clk_resume(void)
+{
+ struct samsung_clk_reg_dump *rd = reg_dump;
+ unsigned long i;
+
+ for (i = 0; i < nr_reg_dump; i++, rd++)
+ __raw_writel(rd->value, reg_base + rd->offset);
+}
+
+static struct syscore_ops samsung_clk_syscore_ops = {
+ .suspend = samsung_clk_suspend,
+ .resume = samsung_clk_resume,
+};
+#endif /* CONFIG_PM_SLEEP */
+
+/* setup the essentials required to support clock lookup using ccf */
+void __init samsung_clk_init(struct device_node *np, void __iomem *base,
+ unsigned long nr_clks, unsigned long *rdump,
+ unsigned long nr_rdump)
+{
+ reg_base = base;
+ if (!np)
+ return;
+
+#ifdef CONFIG_OF
+ clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
+ if (!clk_table)
+ panic("could not allocate clock lookup table\n");
+
+ clk_data.clks = clk_table;
+ clk_data.clk_num = nr_clks;
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+#endif
+
+#ifdef CONFIG_PM_SLEEP
+ if (rdump && nr_rdump) {
+ unsigned int idx;
+ reg_dump = kzalloc(sizeof(struct samsung_clk_reg_dump)
+ * nr_rdump, GFP_KERNEL);
+ if (!reg_dump) {
+ pr_err("%s: memory alloc for register dump failed\n",
+ __func__);
+ return;
+ }
+
+ for (idx = 0; idx < nr_rdump; idx++)
+ reg_dump[idx].offset = rdump[idx];
+ nr_reg_dump = nr_rdump;
+ register_syscore_ops(&samsung_clk_syscore_ops);
+ }
+#endif
+}
+
+/* add a clock instance to the clock lookup table used for dt based lookup */
+void samsung_clk_add_lookup(struct clk *clk, unsigned int id)
+{
+ if (clk_table && id)
+ clk_table[id] = clk;
+}
+
+/* register a list of fixed clocks */
+void __init samsung_clk_register_fixed_rate(
+ struct samsung_fixed_rate_clock *list, unsigned int nr_clk)
+{
+ struct clk *clk;
+ unsigned int idx, ret;
+
+ for (idx = 0; idx < nr_clk; idx++, list++) {
+ clk = clk_register_fixed_rate(NULL, list->name,
+ list->parent_name, list->flags, list->fixed_rate);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ list->name);
+ continue;
+ }
+
+ samsung_clk_add_lookup(clk, list->id);
+
+ /*
+ * Unconditionally add a clock lookup for the fixed rate clocks.
+ * There are not many of these on any of Samsung platforms.
+ */
+ ret = clk_register_clkdev(clk, list->name, NULL);
+ if (ret)
+ pr_err("%s: failed to register clock lookup for %s",
+ __func__, list->name);
+ }
+}
+
+/* register a list of fixed factor clocks */
+void __init samsung_clk_register_fixed_factor(
+ struct samsung_fixed_factor_clock *list, unsigned int nr_clk)
+{
+ struct clk *clk;
+ unsigned int idx;
+
+ for (idx = 0; idx < nr_clk; idx++, list++) {
+ clk = clk_register_fixed_factor(NULL, list->name,
+ list->parent_name, list->flags, list->mult, list->div);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ list->name);
+ continue;
+ }
+
+ samsung_clk_add_lookup(clk, list->id);
+ }
+}
+
+/* register a list of mux clocks */
+void __init samsung_clk_register_mux(struct samsung_mux_clock *list,
+ unsigned int nr_clk)
+{
+ struct clk *clk;
+ unsigned int idx, ret;
+
+ for (idx = 0; idx < nr_clk; idx++, list++) {
+ clk = clk_register_mux(NULL, list->name, list->parent_names,
+ list->num_parents, list->flags, reg_base + list->offset,
+ list->shift, list->width, list->mux_flags, &lock);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ list->name);
+ continue;
+ }
+
+ samsung_clk_add_lookup(clk, list->id);
+
+ /* register a clock lookup only if a clock alias is specified */
+ if (list->alias) {
+ ret = clk_register_clkdev(clk, list->alias,
+ list->dev_name);
+ if (ret)
+ pr_err("%s: failed to register lookup %s\n",
+ __func__, list->alias);
+ }
+ }
+}
+
+/* register a list of div clocks */
+void __init samsung_clk_register_div(struct samsung_div_clock *list,
+ unsigned int nr_clk)
+{
+ struct clk *clk;
+ unsigned int idx, ret;
+
+ for (idx = 0; idx < nr_clk; idx++, list++) {
+ clk = clk_register_divider(NULL, list->name, list->parent_name,
+ list->flags, reg_base + list->offset, list->shift,
+ list->width, list->div_flags, &lock);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ list->name);
+ continue;
+ }
+
+ samsung_clk_add_lookup(clk, list->id);
+
+ /* register a clock lookup only if a clock alias is specified */
+ if (list->alias) {
+ ret = clk_register_clkdev(clk, list->alias,
+ list->dev_name);
+ if (ret)
+ pr_err("%s: failed to register lookup %s\n",
+ __func__, list->alias);
+ }
+ }
+}
+
+/* register a list of gate clocks */
+void __init samsung_clk_register_gate(struct samsung_gate_clock *list,
+ unsigned int nr_clk)
+{
+ struct clk *clk;
+ unsigned int idx, ret;
+
+ for (idx = 0; idx < nr_clk; idx++, list++) {
+ clk = clk_register_gate(NULL, list->name, list->parent_name,
+ list->flags, reg_base + list->offset,
+ list->bit_idx, list->gate_flags, &lock);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ list->name);
+ continue;
+ }
+
+ /* register a clock lookup only if a clock alias is specified */
+ if (list->alias) {
+ ret = clk_register_clkdev(clk, list->alias,
+ list->dev_name);
+ if (ret)
+ pr_err("%s: failed to register lookup %s\n",
+ __func__, list->alias);
+ }
+
+ samsung_clk_add_lookup(clk, list->id);
+ }
+}
+
+/*
+ * obtain the clock speed of all external fixed clock sources from device
+ * tree and register it
+ */
+void __init samsung_clk_of_register_fixed_ext(
+ struct samsung_fixed_rate_clock *fixed_rate_clk,
+ unsigned int nr_fixed_rate_clk,
+ struct of_device_id *clk_matches)
+{
+ const struct of_device_id *match;
+ struct device_node *np;
+ u32 freq;
+
+ for_each_matching_node_and_match(np, clk_matches, &match) {
+ if (of_property_read_u32(np, "clock-frequency", &freq))
+ continue;
+ fixed_rate_clk[(u32)match->data].fixed_rate = freq;
+ }
+ samsung_clk_register_fixed_rate(fixed_rate_clk, nr_fixed_rate_clk);
+}
+
+/* utility function to get the rate of a specified clock */
+unsigned long _get_rate(const char *clk_name)
+{
+ struct clk *clk;
+ unsigned long rate;
+
+ clk = clk_get(NULL, clk_name);
+ if (IS_ERR(clk)) {
+ pr_err("%s: could not find clock %s\n", __func__, clk_name);
+ return 0;
+ }
+ rate = clk_get_rate(clk);
+ clk_put(clk);
+ return rate;
+}
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
new file mode 100644
index 0000000..961192f
--- /dev/null
+++ b/drivers/clk/samsung/clk.h
@@ -0,0 +1,262 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ * Author: Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for all Samsung platforms
+*/
+
+#ifndef __SAMSUNG_CLK_H
+#define __SAMSUNG_CLK_H
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <mach/map.h>
+
+/**
+ * struct samsung_fixed_rate_clock: information about fixed-rate clock
+ * @id: platform specific id of the clock.
+ * @name: name of this fixed-rate clock.
+ * @parent_name: optional parent clock name.
+ * @flags: optional fixed-rate clock flags.
+ * @fixed-rate: fixed clock rate of this clock.
+ */
+struct samsung_fixed_rate_clock {
+ unsigned int id;
+ char *name;
+ const char *parent_name;
+ unsigned long flags;
+ unsigned long fixed_rate;
+};
+
+#define FRATE(_id, cname, pname, f, frate) \
+ { \
+ .id = _id, \
+ .name = cname, \
+ .parent_name = pname, \
+ .flags = f, \
+ .fixed_rate = frate, \
+ }
+
+/*
+ * struct samsung_fixed_factor_clock: information about fixed-factor clock
+ * @id: platform specific id of the clock.
+ * @name: name of this fixed-factor clock.
+ * @parent_name: parent clock name.
+ * @mult: fixed multiplication factor.
+ * @div: fixed division factor.
+ * @flags: optional fixed-factor clock flags.
+ */
+struct samsung_fixed_factor_clock {
+ unsigned int id;
+ char *name;
+ const char *parent_name;
+ unsigned long mult;
+ unsigned long div;
+ unsigned long flags;
+};
+
+#define FFACTOR(_id, cname, pname, m, d, f) \
+ { \
+ .id = _id, \
+ .name = cname, \
+ .parent_name = pname, \
+ .mult = m, \
+ .div = d, \
+ .flags = f, \
+ }
+
+/**
+ * struct samsung_mux_clock: information about mux clock
+ * @id: platform specific id of the clock.
+ * @dev_name: name of the device to which this clock belongs.
+ * @name: name of this mux clock.
+ * @parent_names: array of pointer to parent clock names.
+ * @num_parents: number of parents listed in @parent_names.
+ * @flags: optional flags for basic clock.
+ * @offset: offset of the register for configuring the mux.
+ * @shift: starting bit location of the mux control bit-field in @reg.
+ * @width: width of the mux control bit-field in @reg.
+ * @mux_flags: flags for mux-type clock.
+ * @alias: optional clock alias name to be assigned to this clock.
+ */
+struct samsung_mux_clock {
+ unsigned int id;
+ const char *dev_name;
+ const char *name;
+ const char **parent_names;
+ u8 num_parents;
+ unsigned long flags;
+ unsigned long offset;
+ u8 shift;
+ u8 width;
+ u8 mux_flags;
+ const char *alias;
+};
+
+#define __MUX(_id, dname, cname, pnames, o, s, w, f, mf, a) \
+ { \
+ .id = _id, \
+ .dev_name = dname, \
+ .name = cname, \
+ .parent_names = pnames, \
+ .num_parents = ARRAY_SIZE(pnames), \
+ .flags = f, \
+ .offset = o, \
+ .shift = s, \
+ .width = w, \
+ .mux_flags = mf, \
+ .alias = a, \
+ }
+
+#define MUX(_id, cname, pnames, o, s, w) \
+ __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, NULL)
+
+#define MUX_A(_id, cname, pnames, o, s, w, a) \
+ __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, a)
+
+#define MUX_F(_id, cname, pnames, o, s, w, f, mf) \
+ __MUX(_id, NULL, cname, pnames, o, s, w, f, mf, NULL)
+
+/**
+ * @id: platform specific id of the clock.
+ * struct samsung_div_clock: information about div clock
+ * @dev_name: name of the device to which this clock belongs.
+ * @name: name of this div clock.
+ * @parent_name: name of the parent clock.
+ * @flags: optional flags for basic clock.
+ * @offset: offset of the register for configuring the div.
+ * @shift: starting bit location of the div control bit-field in @reg.
+ * @div_flags: flags for div-type clock.
+ * @alias: optional clock alias name to be assigned to this clock.
+ */
+struct samsung_div_clock {
+ unsigned int id;
+ const char *dev_name;
+ const char *name;
+ const char *parent_name;
+ unsigned long flags;
+ unsigned long offset;
+ u8 shift;
+ u8 width;
+ u8 div_flags;
+ const char *alias;
+};
+
+#define __DIV(_id, dname, cname, pname, o, s, w, f, df, a) \
+ { \
+ .id = _id, \
+ .dev_name = dname, \
+ .name = cname, \
+ .parent_name = pname, \
+ .flags = f, \
+ .offset = o, \
+ .shift = s, \
+ .width = w, \
+ .div_flags = df, \
+ .alias = a, \
+ }
+
+#define DIV(_id, cname, pname, o, s, w) \
+ __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL)
+
+#define DIV_A(_id, cname, pname, o, s, w, a) \
+ __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, a)
+
+#define DIV_F(_id, cname, pname, o, s, w, f, df) \
+ __DIV(_id, NULL, cname, pname, o, s, w, f, df, NULL)
+
+/**
+ * struct samsung_gate_clock: information about gate clock
+ * @id: platform specific id of the clock.
+ * @dev_name: name of the device to which this clock belongs.
+ * @name: name of this gate clock.
+ * @parent_name: name of the parent clock.
+ * @flags: optional flags for basic clock.
+ * @offset: offset of the register for configuring the gate.
+ * @bit_idx: bit index of the gate control bit-field in @reg.
+ * @gate_flags: flags for gate-type clock.
+ * @alias: optional clock alias name to be assigned to this clock.
+ */
+struct samsung_gate_clock {
+ unsigned int id;
+ const char *dev_name;
+ const char *name;
+ const char *parent_name;
+ unsigned long flags;
+ unsigned long offset;
+ u8 bit_idx;
+ u8 gate_flags;
+ const char *alias;
+};
+
+#define __GATE(_id, dname, cname, pname, o, b, f, gf, a) \
+ { \
+ .id = _id, \
+ .dev_name = dname, \
+ .name = cname, \
+ .parent_name = pname, \
+ .flags = f, \
+ .offset = o, \
+ .bit_idx = b, \
+ .gate_flags = gf, \
+ .alias = a, \
+ }
+
+#define GATE(_id, cname, pname, o, b, f, gf) \
+ __GATE(_id, NULL, cname, pname, o, b, f, gf, NULL)
+
+#define GATE_A(_id, cname, pname, o, b, f, gf, a) \
+ __GATE(_id, NULL, cname, pname, o, b, f, gf, a)
+
+#define GATE_D(_id, dname, cname, pname, o, b, f, gf) \
+ __GATE(_id, dname, cname, pname, o, b, f, gf, NULL)
+
+#define GATE_DA(_id, dname, cname, pname, o, b, f, gf, a) \
+ __GATE(_id, dname, cname, pname, o, b, f, gf, a)
+
+#define PNAME(x) static const char *x[] __initdata
+
+/**
+ * struct samsung_clk_reg_dump: register dump of clock controller registers.
+ * @offset: clock register offset from the controller base address.
+ * @value: the value to be register at offset.
+ */
+struct samsung_clk_reg_dump {
+ u32 offset;
+ u32 value;
+};
+
+extern void __init samsung_clk_init(struct device_node *np, void __iomem *base,
+ unsigned long nr_clks, unsigned long *rdump,
+ unsigned long nr_rdump);
+extern void __init samsung_clk_of_register_fixed_ext(
+ struct samsung_fixed_rate_clock *fixed_rate_clk,
+ unsigned int nr_fixed_rate_clk,
+ struct of_device_id *clk_matches);
+
+extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id);
+
+extern void __init samsung_clk_register_fixed_rate(
+ struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk);
+extern void __init samsung_clk_register_fixed_factor(
+ struct samsung_fixed_factor_clock *list, unsigned int nr_clk);
+extern void __init samsung_clk_register_mux(struct samsung_mux_clock *clk_list,
+ unsigned int nr_clk);
+extern void __init samsung_clk_register_div(struct samsung_div_clock *clk_list,
+ unsigned int nr_clk);
+extern void __init samsung_clk_register_gate(
+ struct samsung_gate_clock *clk_list, unsigned int nr_clk);
+
+extern unsigned long _get_rate(const char *clk_name);
+
+#endif /* __SAMSUNG_CLK_H */
--
1.7.5.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v6 02/16] clk: samsung: add pll clock registration helper functions
2013-02-18 8:21 [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 01/16] clk: samsung: add common clock framework helper functions for Samsung platforms Thomas Abraham
@ 2013-02-18 8:21 ` Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 03/16] clk: exynos4: register clocks using common clock framework Thomas Abraham
` (13 subsequent siblings)
15 siblings, 0 replies; 37+ messages in thread
From: Thomas Abraham @ 2013-02-18 8:21 UTC (permalink / raw)
To: linux-arm-kernel
There are several types of pll clocks used in Samsung SoC's and these pll
clocks can be represented as Samsung specific pll clock types and registered
with the common clock framework. Add support for pll35xx, pll36xx, pll45xx,
pll46xx and pll2550x clock types and helper functions to register them.
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
drivers/clk/samsung/Makefile | 2 +-
drivers/clk/samsung/clk-pll.c | 499 +++++++++++++++++++++++++++++++++++++++++
drivers/clk/samsung/clk-pll.h | 41 ++++
3 files changed, 541 insertions(+), 1 deletions(-)
create mode 100644 drivers/clk/samsung/clk-pll.c
create mode 100644 drivers/clk/samsung/clk-pll.h
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index bd920b4..78e5aaa 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -2,4 +2,4 @@
# Samsung Clock specific Makefile
#
-obj-$(CONFIG_COMMON_CLK) += clk.o
+obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
new file mode 100644
index 0000000..4b24511
--- /dev/null
+++ b/drivers/clk/samsung/clk-pll.c
@@ -0,0 +1,499 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility functions to register the pll clocks.
+*/
+
+#include <linux/errno.h>
+#include "clk.h"
+#include "clk-pll.h"
+
+/*
+ * PLL35xx Clock Type
+ */
+
+#define PLL35XX_MDIV_MASK (0x3FF)
+#define PLL35XX_PDIV_MASK (0x3F)
+#define PLL35XX_SDIV_MASK (0x7)
+#define PLL35XX_MDIV_SHIFT (16)
+#define PLL35XX_PDIV_SHIFT (8)
+#define PLL35XX_SDIV_SHIFT (0)
+
+struct samsung_clk_pll35xx {
+ struct clk_hw hw;
+ const void __iomem *con_reg;
+};
+
+#define to_clk_pll35xx(_hw) container_of(_hw, struct samsung_clk_pll35xx, hw)
+
+static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll35xx *pll = to_clk_pll35xx(hw);
+ u32 mdiv, pdiv, sdiv, pll_con;
+ u64 fvco = parent_rate;
+
+ pll_con = __raw_readl(pll->con_reg);
+ mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
+ pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
+ sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+
+ return (unsigned long)fvco;
+}
+
+/* todo: implement pl35xx clock round rate operation */
+static long samsung_pll35xx_round_rate(struct clk_hw *hw,
+ unsigned long drate, unsigned long *prate)
+{
+ return -ENOTSUPP;
+}
+
+/* todo: implement pl35xx clock set rate */
+static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ return -ENOTSUPP;
+}
+
+static const struct clk_ops samsung_pll35xx_clk_ops = {
+ .recalc_rate = samsung_pll35xx_recalc_rate,
+ .round_rate = samsung_pll35xx_round_rate,
+ .set_rate = samsung_pll35xx_set_rate,
+};
+
+struct clk * __init samsung_clk_register_pll35xx(const char *name,
+ const char *pname, const void __iomem *con_reg)
+{
+ struct samsung_clk_pll35xx *pll;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll) {
+ pr_err("%s: could not allocate pll clk %s\n", __func__, name);
+ return NULL;
+ }
+
+ init.name = name;
+ init.ops = &samsung_pll35xx_clk_ops;
+ init.flags = CLK_GET_RATE_NOCACHE;
+ init.parent_names = &pname;
+ init.num_parents = 1;
+
+ pll->hw.init = &init;
+ pll->con_reg = con_reg;
+
+ clk = clk_register(NULL, &pll->hw);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register pll clock %s\n", __func__,
+ name);
+ kfree(pll);
+ }
+
+ if (clk_register_clkdev(clk, name, NULL))
+ pr_err("%s: failed to register lookup for %s", __func__, name);
+
+ return clk;
+}
+
+/*
+ * PLL36xx Clock Type
+ */
+
+#define PLL36XX_KDIV_MASK (0xFFFF)
+#define PLL36XX_MDIV_MASK (0x1FF)
+#define PLL36XX_PDIV_MASK (0x3F)
+#define PLL36XX_SDIV_MASK (0x7)
+#define PLL36XX_MDIV_SHIFT (16)
+#define PLL36XX_PDIV_SHIFT (8)
+#define PLL36XX_SDIV_SHIFT (0)
+
+struct samsung_clk_pll36xx {
+ struct clk_hw hw;
+ const void __iomem *con_reg;
+};
+
+#define to_clk_pll36xx(_hw) container_of(_hw, struct samsung_clk_pll36xx, hw)
+
+static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll36xx *pll = to_clk_pll36xx(hw);
+ u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
+ u64 fvco = parent_rate;
+
+ pll_con0 = __raw_readl(pll->con_reg);
+ pll_con1 = __raw_readl(pll->con_reg + 4);
+ mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
+ pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
+ sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
+ kdiv = pll_con1 & PLL36XX_KDIV_MASK;
+
+ fvco *= (mdiv << 16) + kdiv;
+ do_div(fvco, (pdiv << sdiv));
+ fvco >>= 16;
+
+ return (unsigned long)fvco;
+}
+
+/* todo: implement pl36xx clock round rate operation */
+static long samsung_pll36xx_round_rate(struct clk_hw *hw,
+ unsigned long drate, unsigned long *prate)
+{
+ return -ENOTSUPP;
+}
+
+/* todo: implement pl36xx clock set rate */
+static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ return -ENOTSUPP;
+}
+
+static const struct clk_ops samsung_pll36xx_clk_ops = {
+ .recalc_rate = samsung_pll36xx_recalc_rate,
+ .round_rate = samsung_pll36xx_round_rate,
+ .set_rate = samsung_pll36xx_set_rate,
+};
+
+struct clk * __init samsung_clk_register_pll36xx(const char *name,
+ const char *pname, const void __iomem *con_reg)
+{
+ struct samsung_clk_pll36xx *pll;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll) {
+ pr_err("%s: could not allocate pll clk %s\n", __func__, name);
+ return NULL;
+ }
+
+ init.name = name;
+ init.ops = &samsung_pll36xx_clk_ops;
+ init.flags = CLK_GET_RATE_NOCACHE;
+ init.parent_names = &pname;
+ init.num_parents = 1;
+
+ pll->hw.init = &init;
+ pll->con_reg = con_reg;
+
+ clk = clk_register(NULL, &pll->hw);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register pll clock %s\n", __func__,
+ name);
+ kfree(pll);
+ }
+
+ if (clk_register_clkdev(clk, name, NULL))
+ pr_err("%s: failed to register lookup for %s", __func__, name);
+
+ return clk;
+}
+
+/*
+ * PLL45xx Clock Type
+ */
+
+#define PLL45XX_MDIV_MASK (0x3FF)
+#define PLL45XX_PDIV_MASK (0x3F)
+#define PLL45XX_SDIV_MASK (0x7)
+#define PLL45XX_MDIV_SHIFT (16)
+#define PLL45XX_PDIV_SHIFT (8)
+#define PLL45XX_SDIV_SHIFT (0)
+
+struct samsung_clk_pll45xx {
+ struct clk_hw hw;
+ enum pll45xx_type type;
+ const void __iomem *con_reg;
+};
+
+#define to_clk_pll45xx(_hw) container_of(_hw, struct samsung_clk_pll45xx, hw)
+
+static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll45xx *pll = to_clk_pll45xx(hw);
+ u32 mdiv, pdiv, sdiv, pll_con;
+ u64 fvco = parent_rate;
+
+ pll_con = __raw_readl(pll->con_reg);
+ mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
+ pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
+ sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
+
+ if (pll->type == pll_4508)
+ sdiv = sdiv - 1;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+
+ return (unsigned long)fvco;
+}
+
+/* todo: implement pl45xx clock round rate operation */
+static long samsung_pll45xx_round_rate(struct clk_hw *hw,
+ unsigned long drate, unsigned long *prate)
+{
+ return -ENOTSUPP;
+}
+
+/* todo: implement pl45xx clock set rate */
+static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ return -ENOTSUPP;
+}
+
+static const struct clk_ops samsung_pll45xx_clk_ops = {
+ .recalc_rate = samsung_pll45xx_recalc_rate,
+ .round_rate = samsung_pll45xx_round_rate,
+ .set_rate = samsung_pll45xx_set_rate,
+};
+
+struct clk * __init samsung_clk_register_pll45xx(const char *name,
+ const char *pname, const void __iomem *con_reg,
+ enum pll45xx_type type)
+{
+ struct samsung_clk_pll45xx *pll;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll) {
+ pr_err("%s: could not allocate pll clk %s\n", __func__, name);
+ return NULL;
+ }
+
+ init.name = name;
+ init.ops = &samsung_pll45xx_clk_ops;
+ init.flags = CLK_GET_RATE_NOCACHE;
+ init.parent_names = &pname;
+ init.num_parents = 1;
+
+ pll->hw.init = &init;
+ pll->con_reg = con_reg;
+ pll->type = type;
+
+ clk = clk_register(NULL, &pll->hw);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register pll clock %s\n", __func__,
+ name);
+ kfree(pll);
+ }
+
+ if (clk_register_clkdev(clk, name, NULL))
+ pr_err("%s: failed to register lookup for %s", __func__, name);
+
+ return clk;
+}
+
+/*
+ * PLL46xx Clock Type
+ */
+
+#define PLL46XX_MDIV_MASK (0x1FF)
+#define PLL46XX_PDIV_MASK (0x3F)
+#define PLL46XX_SDIV_MASK (0x7)
+#define PLL46XX_MDIV_SHIFT (16)
+#define PLL46XX_PDIV_SHIFT (8)
+#define PLL46XX_SDIV_SHIFT (0)
+
+#define PLL46XX_KDIV_MASK (0xFFFF)
+#define PLL4650C_KDIV_MASK (0xFFF)
+#define PLL46XX_KDIV_SHIFT (0)
+
+struct samsung_clk_pll46xx {
+ struct clk_hw hw;
+ enum pll46xx_type type;
+ const void __iomem *con_reg;
+};
+
+#define to_clk_pll46xx(_hw) container_of(_hw, struct samsung_clk_pll46xx, hw)
+
+static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll46xx *pll = to_clk_pll46xx(hw);
+ u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift;
+ u64 fvco = parent_rate;
+
+ pll_con0 = __raw_readl(pll->con_reg);
+ pll_con1 = __raw_readl(pll->con_reg + 4);
+ mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
+ pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
+ sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
+ kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
+ pll_con1 & PLL46XX_KDIV_MASK;
+
+ shift = pll->type == pll_4600 ? 16 : 10;
+ fvco *= (mdiv << shift) + kdiv;
+ do_div(fvco, (pdiv << sdiv));
+ fvco >>= shift;
+
+ return (unsigned long)fvco;
+}
+
+/* todo: implement pl46xx clock round rate operation */
+static long samsung_pll46xx_round_rate(struct clk_hw *hw,
+ unsigned long drate, unsigned long *prate)
+{
+ return -ENOTSUPP;
+}
+
+/* todo: implement pl46xx clock set rate */
+static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ return -ENOTSUPP;
+}
+
+static const struct clk_ops samsung_pll46xx_clk_ops = {
+ .recalc_rate = samsung_pll46xx_recalc_rate,
+ .round_rate = samsung_pll46xx_round_rate,
+ .set_rate = samsung_pll46xx_set_rate,
+};
+
+struct clk * __init samsung_clk_register_pll46xx(const char *name,
+ const char *pname, const void __iomem *con_reg,
+ enum pll46xx_type type)
+{
+ struct samsung_clk_pll46xx *pll;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll) {
+ pr_err("%s: could not allocate pll clk %s\n", __func__, name);
+ return NULL;
+ }
+
+ init.name = name;
+ init.ops = &samsung_pll46xx_clk_ops;
+ init.flags = CLK_GET_RATE_NOCACHE;
+ init.parent_names = &pname;
+ init.num_parents = 1;
+
+ pll->hw.init = &init;
+ pll->con_reg = con_reg;
+ pll->type = type;
+
+ clk = clk_register(NULL, &pll->hw);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register pll clock %s\n", __func__,
+ name);
+ kfree(pll);
+ }
+
+ if (clk_register_clkdev(clk, name, NULL))
+ pr_err("%s: failed to register lookup for %s", __func__, name);
+
+ return clk;
+}
+
+/*
+ * PLL2550x Clock Type
+ */
+
+#define PLL2550X_R_MASK (0x1)
+#define PLL2550X_P_MASK (0x3F)
+#define PLL2550X_M_MASK (0x3FF)
+#define PLL2550X_S_MASK (0x7)
+#define PLL2550X_R_SHIFT (20)
+#define PLL2550X_P_SHIFT (14)
+#define PLL2550X_M_SHIFT (4)
+#define PLL2550X_S_SHIFT (0)
+
+struct samsung_clk_pll2550x {
+ struct clk_hw hw;
+ const void __iomem *reg_base;
+ unsigned long offset;
+};
+
+#define to_clk_pll2550x(_hw) container_of(_hw, struct samsung_clk_pll2550x, hw)
+
+static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll2550x *pll = to_clk_pll2550x(hw);
+ u32 r, p, m, s, pll_stat;
+ u64 fvco = parent_rate;
+
+ pll_stat = __raw_readl(pll->reg_base + pll->offset * 3);
+ r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK;
+ if (!r)
+ return 0;
+ p = (pll_stat >> PLL2550X_P_SHIFT) & PLL2550X_P_MASK;
+ m = (pll_stat >> PLL2550X_M_SHIFT) & PLL2550X_M_MASK;
+ s = (pll_stat >> PLL2550X_S_SHIFT) & PLL2550X_S_MASK;
+
+ fvco *= m;
+ do_div(fvco, (p << s));
+
+ return (unsigned long)fvco;
+}
+
+/* todo: implement pl2550x clock round rate operation */
+static long samsung_pll2550x_round_rate(struct clk_hw *hw,
+ unsigned long drate, unsigned long *prate)
+{
+ return -ENOTSUPP;
+}
+
+/* todo: implement pl2550x clock set rate */
+static int samsung_pll2550x_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ return -ENOTSUPP;
+}
+
+static const struct clk_ops samsung_pll2550x_clk_ops = {
+ .recalc_rate = samsung_pll2550x_recalc_rate,
+ .round_rate = samsung_pll2550x_round_rate,
+ .set_rate = samsung_pll2550x_set_rate,
+};
+
+struct clk * __init samsung_clk_register_pll2550x(const char *name,
+ const char *pname, const void __iomem *reg_base,
+ const unsigned long offset)
+{
+ struct samsung_clk_pll2550x *pll;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll) {
+ pr_err("%s: could not allocate pll clk %s\n", __func__, name);
+ return NULL;
+ }
+
+ init.name = name;
+ init.ops = &samsung_pll2550x_clk_ops;
+ init.flags = CLK_GET_RATE_NOCACHE;
+ init.parent_names = &pname;
+ init.num_parents = 1;
+
+ pll->hw.init = &init;
+ pll->reg_base = reg_base;
+ pll->offset = offset;
+
+ clk = clk_register(NULL, &pll->hw);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register pll clock %s\n", __func__,
+ name);
+ kfree(pll);
+ }
+
+ if (clk_register_clkdev(clk, name, NULL))
+ pr_err("%s: failed to register lookup for %s", __func__, name);
+
+ return clk;
+}
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
new file mode 100644
index 0000000..f33786e
--- /dev/null
+++ b/drivers/clk/samsung/clk-pll.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for all PLL's in Samsung platforms
+*/
+
+#ifndef __SAMSUNG_CLK_PLL_H
+#define __SAMSUNG_CLK_PLL_H
+
+enum pll45xx_type {
+ pll_4500,
+ pll_4502,
+ pll_4508
+};
+
+enum pll46xx_type {
+ pll_4600,
+ pll_4650,
+ pll_4650c,
+};
+
+extern struct clk * __init samsung_clk_register_pll35xx(const char *name,
+ const char *pname, const void __iomem *con_reg);
+extern struct clk * __init samsung_clk_register_pll36xx(const char *name,
+ const char *pname, const void __iomem *con_reg);
+extern struct clk * __init samsung_clk_register_pll45xx(const char *name,
+ const char *pname, const void __iomem *con_reg,
+ enum pll45xx_type type);
+extern struct clk * __init samsung_clk_register_pll46xx(const char *name,
+ const char *pname, const void __iomem *con_reg,
+ enum pll46xx_type type);
+extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
+ const char *pname, const void __iomem *reg_base,
+ const unsigned long offset);
+
+#endif /* __SAMSUNG_CLK_PLL_H */
--
1.7.5.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v6 03/16] clk: exynos4: register clocks using common clock framework
2013-02-18 8:21 [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 01/16] clk: samsung: add common clock framework helper functions for Samsung platforms Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 02/16] clk: samsung: add pll clock registration helper functions Thomas Abraham
@ 2013-02-18 8:21 ` Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 04/16] clk: exynos5250: " Thomas Abraham
` (12 subsequent siblings)
15 siblings, 0 replies; 37+ messages in thread
From: Thomas Abraham @ 2013-02-18 8:21 UTC (permalink / raw)
To: linux-arm-kernel
The Exynos4 clocks are statically listed and registered using the Samsung
specific common clock helper functions. Both device tree based clock lookup
and clkdev based clock lookups are supported.
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
.../devicetree/bindings/clock/exynos4-clock.txt | 215 +++++
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos4.c | 843 ++++++++++++++++++++
3 files changed, 1059 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/exynos4-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos4.c
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
new file mode 100644
index 0000000..e874add
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -0,0 +1,215 @@
+* Samsung Exynos4 Clock Controller
+
+The Exynos4 clock controller generates and supplies clock to various controllers
+within the Exynos4 SoC. The clock binding described here is applicable to all
+SoC's in the Exynos4 family.
+
+Required Properties:
+
+- comptible: should be one of the following.
+ - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
+ - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume. Some of the clocks are available only on a particular
+Exynos4 SoC and this is specified where applicable.
+
+
+ [Core Clocks]
+
+ Clock ID SoC (if specific)
+ -----------------------------------------------
+
+ xxti 1
+ xusbxti 2
+ fin_pll 3
+ fout_apll 4
+ fout_mpll 5
+ fout_epll 6
+ fout_vpll 7
+ sclk_apll 8
+ sclk_mpll 9
+ sclk_epll 10
+ sclk_vpll 11
+ arm_clk 12
+ aclk200 13
+ aclk100 14
+ aclk160 15
+ aclk133 16
+
+
+ [Clock Gate for Special Clocks]
+
+ Clock ID SoC (if specific)
+ -----------------------------------------------
+
+ sclk_fimc0 128
+ sclk_fimc1 129
+ sclk_fimc2 130
+ sclk_fimc3 131
+ sclk_cam0 132
+ sclk_cam1 133
+ sclk_csis0 134
+ sclk_csis1 135
+ sclk_hdmi 136
+ sclk_mixer 137
+ sclk_dac 138
+ sclk_pixel 139
+ sclk_fimd0 140
+ sclk_mdnie0 141 Exynos4412
+ sclk_mdnie_pwm0 12 142 Exynos4412
+ sclk_mipi0 143
+ sclk_audio0 144
+ sclk_mmc0 145
+ sclk_mmc1 146
+ sclk_mmc2 147
+ sclk_mmc3 148
+ sclk_mmc4 149
+ sclk_sata 150 Exynos4210
+ sclk_uart0 151
+ sclk_uart1 152
+ sclk_uart2 153
+ sclk_uart3 154
+ sclk_uart4 155
+ sclk_audio1 156
+ sclk_audio2 157
+ sclk_spdif 158
+ sclk_spi0 159
+ sclk_spi1 160
+ sclk_spi2 161
+ sclk_slimbus 162
+ sclk_fimd1 163 Exynos4210
+ sclk_mipi1 164 Exynos4210
+ sclk_pcm1 165
+ sclk_pcm2 166
+ sclk_i2s1 167
+ sclk_i2s2 168
+ sclk_mipihsi 169 Exynos4412
+
+
+ [Peripheral Clock Gates]
+
+ Clock ID SoC (if specific)
+ -----------------------------------------------
+
+ fimc0 256
+ fimc1 257
+ fimc2 258
+ fimc3 259
+ csis0 260
+ csis1 261
+ jpeg 262
+ smmu_fimc0 263
+ smmu_fimc1 264
+ smmu_fimc2 265
+ smmu_fimc3 266
+ smmu_jpeg 267
+ vp 268
+ mixer 269
+ tvenc 270 Exynos4210
+ hdmi 271
+ smmu_tv 272
+ mfc 273
+ smmu_mfcl 274
+ smmu_mfcr 275
+ g3d 276
+ g2d 277 Exynos4210
+ rotator 278 Exynos4210
+ mdma 279 Exynos4210
+ smmu_g2d 280 Exynos4210
+ smmu_rotator 281 Exynos4210
+ smmu_mdma 282 Exynos4210
+ fimd0 283
+ mie0 284
+ mdnie0 285 Exynos4412
+ dsim0 286
+ smmu_fimd0 287
+ fimd1 288 Exynos4210
+ mie1 289 Exynos4210
+ dsim1 290 Exynos4210
+ smmu_fimd1 291 Exynos4210
+ pdma0 292
+ pdma1 293
+ pcie_phy 294
+ sata_phy 295 Exynos4210
+ tsi 296
+ sdmmc0 297
+ sdmmc1 298
+ sdmmc2 299
+ sdmmc3 300
+ sdmmc4 301
+ sata 302 Exynos4210
+ sromc 303
+ usb_host 304
+ usb_device 305
+ pcie 306
+ onenand 307
+ nfcon 308
+ smmu_pcie 309
+ gps 310
+ smmu_gps 311
+ uart0 312
+ uart1 313
+ uart2 314
+ uart3 315
+ uart4 316
+ i2c0 317
+ i2c1 318
+ i2c2 319
+ i2c3 320
+ i2c4 321
+ i2c5 322
+ i2c6 323
+ i2c7 324
+ i2c_hdmi 325
+ tsadc 326
+ spi0 327
+ spi1 328
+ spi2 329
+ i2s1 330
+ i2s2 331
+ pcm0 332
+ i2s0 333
+ pcm1 334
+ pcm2 335
+ pwm 336
+ slimbus 337
+ spdif 338
+ ac97 339
+ modemif 340
+ chipid 341
+ sysreg 342
+ hdmi_cec 343
+ mct 344
+ wdt 345
+ rtc 346
+ keyif 347
+ audss 348
+ mipi_hsi 349 Exynos4210
+ mdma2 350 Exynos4210
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller at 0x10030000 {
+ compatible = "samsung,exynos4210-clock";
+ reg = <0x10030000 0x20000>;
+ #clock-cells = <1>;
+ };
+
+Example 2: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial at 13820000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13820000 0x100>;
+ interrupts = <0 54 0>;
+ clocks = <&clock 314>, <&clock 153>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 78e5aaa..8862f0d 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -3,3 +3,4 @@
#
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
+obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
new file mode 100644
index 0000000..e1bb81a
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -0,0 +1,843 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ * Author: Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for all Exynos4 SoCs.
+*/
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <plat/cpu.h>
+#include "clk.h"
+#include "clk-pll.h"
+
+/* Exynos4 clock controller register offsets */
+#define SRC_LEFTBUS 0x4200
+#define E4X12_GATE_IP_IMAGE 0x4930
+#define GATE_IP_RIGHTBUS 0x8800
+#define E4X12_GATE_IP_PERIR 0x8960
+#define SRC_TOP0 0xc210
+#define SRC_TOP1 0xc214
+#define SRC_CAM 0xc220
+#define SRC_TV 0xc224
+#define SRC_MFC 0xcc28
+#define SRC_G3D 0xc22c
+#define E4210_SRC_IMAGE 0xc230
+#define SRC_LCD0 0xc234
+#define SRC_LCD1 0xc238
+#define SRC_MAUDIO 0xc23c
+#define SRC_FSYS 0xc240
+#define SRC_PERIL0 0xc250
+#define SRC_PERIL1 0xc254
+#define E4X12_SRC_CAM1 0xc258
+#define SRC_MASK_CAM 0xc320
+#define SRC_MASK_TV 0xc324
+#define SRC_MASK_LCD0 0xc334
+#define SRC_MASK_LCD1 0xc338
+#define SRC_MASK_MAUDIO 0xc33c
+#define SRC_MASK_FSYS 0xc340
+#define SRC_MASK_PERIL0 0xc350
+#define SRC_MASK_PERIL1 0xc354
+#define DIV_TOP 0xc510
+#define DIV_CAM 0xc520
+#define DIV_TV 0xc524
+#define DIV_MFC 0xc528
+#define DIV_G3D 0xc52c
+#define DIV_IMAGE 0xc530
+#define DIV_LCD0 0xc534
+#define E4210_DIV_LCD1 0xc538
+#define E4X12_DIV_ISP 0xc538
+#define DIV_MAUDIO 0xc53c
+#define DIV_FSYS0 0xc540
+#define DIV_FSYS1 0xc544
+#define DIV_FSYS2 0xc548
+#define DIV_FSYS3 0xc54c
+#define DIV_PERIL0 0xc550
+#define DIV_PERIL1 0xc554
+#define DIV_PERIL2 0xc558
+#define DIV_PERIL3 0xc55c
+#define DIV_PERIL4 0xc560
+#define DIV_PERIL5 0xc564
+#define E4X12_DIV_CAM1 0xc568
+#define GATE_SCLK_CAM 0xc820
+#define GATE_IP_CAM 0xc920
+#define GATE_IP_TV 0xc924
+#define GATE_IP_MFC 0xc928
+#define GATE_IP_G3D 0xc92c
+#define E4210_GATE_IP_IMAGE 0xc930
+#define GATE_IP_LCD0 0xc934
+#define GATE_IP_LCD1 0xc938
+#define E4X12_GATE_IP_MAUDIO 0xc93c
+#define GATE_IP_FSYS 0xc940
+#define GATE_IP_GPS 0xc94c
+#define GATE_IP_PERIL 0xc950
+#define GATE_IP_PERIR 0xc960
+#define E4X12_MPLL_CON0 0x10108
+#define E4X12_SRC_DMC 0x10200
+#define APLL_CON0 0x14100
+#define E4210_MPLL_CON0 0x14108
+#define SRC_CPU 0x14200
+#define DIV_CPU0 0x14500
+
+/* the exynos4 soc type */
+enum exynos4_soc {
+ EXYNOS4210,
+ EXYNOS4X12,
+};
+
+/*
+ * Let each supported clock get a unique id. This id is used to lookup the clock
+ * for device tree based platforms. The clocks are categorized into three
+ * sections: core, sclk gate and bus interface gate clocks.
+ *
+ * When adding a new clock to this list, it is advised to choose a clock
+ * category and add it to the end of that category. That is because the the
+ * device tree source file is referring to these ids and any change in the
+ * sequence number of existing clocks will require corresponding change in the
+ * device tree files. This limitation would go away when pre-processor support
+ * for dtc would be available.
+ */
+enum exynos4_clks {
+ none,
+
+ /* core clocks */
+ xxti, xusbxti, fin_pll, fout_apll, fout_mpll, fout_epll, fout_vpll,
+ sclk_apll, sclk_mpll, sclk_epll, sclk_vpll, arm_clk, aclk200, aclk100,
+ aclk160, aclk133,
+
+ /* gate for special clocks (sclk) */
+ sclk_fimc0 = 128, sclk_fimc1, sclk_fimc2, sclk_fimc3, sclk_cam0,
+ sclk_cam1, sclk_csis0, sclk_csis1, sclk_hdmi, sclk_mixer, sclk_dac,
+ sclk_pixel, sclk_fimd0, sclk_mdnie0, sclk_mdnie_pwm0, sclk_mipi0,
+ sclk_audio0, sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_mmc4,
+ sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4,
+ sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
+ sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
+ sclk_i2s2, sclk_mipihsi,
+
+ /* gate clocks */
+ fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
+ smmu_fimc1, smmu_fimc2, smmu_fimc3, smmu_jpeg, vp, mixer, tvenc, hdmi,
+ smmu_tv, mfc, smmu_mfcl, smmu_mfcr, g3d, g2d, rotator, mdma, smmu_g2d,
+ smmu_rotator, smmu_mdma, fimd0, mie0, mdnie0, dsim0, smmu_fimd0, fimd1,
+ mie1, dsim1, smmu_fimd1, pdma0, pdma1, pcie_phy, sata_phy, tsi, sdmmc0,
+ sdmmc1, sdmmc2, sdmmc3, sdmmc4, sata, sromc, usb_host, usb_device, pcie,
+ onenand, nfcon, smmu_pcie, gps, smmu_gps, uart0, uart1, uart2, uart3,
+ uart4, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc,
+ spi0, spi1, spi2, i2s1, i2s2, pcm0, i2s0, pcm1, pcm2, pwm, slimbus,
+ spdif, ac97, modemif, chipid, sysreg, hdmi_cec, mct, wdt, rtc, keyif,
+ audss, mipi_hsi, mdma2,
+
+ nr_clks,
+};
+
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+static __initdata unsigned long exynos4_clk_regs[] = {
+ SRC_LEFTBUS,
+ E4X12_GATE_IP_IMAGE,
+ GATE_IP_RIGHTBUS,
+ E4X12_GATE_IP_PERIR,
+ SRC_TOP0,
+ SRC_TOP1,
+ SRC_CAM,
+ SRC_TV,
+ SRC_MFC,
+ SRC_G3D,
+ E4210_SRC_IMAGE,
+ SRC_LCD0,
+ SRC_LCD1,
+ SRC_MAUDIO,
+ SRC_FSYS,
+ SRC_PERIL0,
+ SRC_PERIL1,
+ E4X12_SRC_CAM1,
+ SRC_MASK_CAM,
+ SRC_MASK_TV,
+ SRC_MASK_LCD0,
+ SRC_MASK_LCD1,
+ SRC_MASK_MAUDIO,
+ SRC_MASK_FSYS,
+ SRC_MASK_PERIL0,
+ SRC_MASK_PERIL1,
+ DIV_TOP,
+ DIV_CAM,
+ DIV_TV,
+ DIV_MFC,
+ DIV_G3D,
+ DIV_IMAGE,
+ DIV_LCD0,
+ E4210_DIV_LCD1,
+ E4X12_DIV_ISP,
+ DIV_MAUDIO,
+ DIV_FSYS0,
+ DIV_FSYS1,
+ DIV_FSYS2,
+ DIV_FSYS3,
+ DIV_PERIL0,
+ DIV_PERIL1,
+ DIV_PERIL2,
+ DIV_PERIL3,
+ DIV_PERIL4,
+ DIV_PERIL5,
+ E4X12_DIV_CAM1,
+ GATE_SCLK_CAM,
+ GATE_IP_CAM,
+ GATE_IP_TV,
+ GATE_IP_MFC,
+ GATE_IP_G3D,
+ E4210_GATE_IP_IMAGE,
+ GATE_IP_LCD0,
+ GATE_IP_LCD1,
+ E4X12_GATE_IP_MAUDIO,
+ GATE_IP_FSYS,
+ GATE_IP_GPS,
+ GATE_IP_PERIL,
+ GATE_IP_PERIR,
+ E4X12_MPLL_CON0,
+ E4X12_SRC_DMC,
+ APLL_CON0,
+ E4210_MPLL_CON0,
+ SRC_CPU,
+ DIV_CPU0,
+};
+
+/* list of all parent clock list */
+PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
+PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
+PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
+PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", };
+PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", };
+PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
+PNAME(mout_core_p) = { "mout_apll", "sclk_mpll", };
+PNAME(sclk_ampll_p) = { "sclk_mpll", "sclk_apll", };
+PNAME(mout_mpll_user_p) = { "fin_pll", "sclk_mpll", };
+PNAME(aclk_p4412) = { "mout_mpll_user", "sclk_apll", };
+PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", };
+PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", };
+PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", };
+PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", };
+PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", };
+PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", };
+PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", };
+PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", };
+PNAME(group1_p) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
+ "none", "sclk_hdmiphy", "sclk_mpll",
+ "sclk_epll", "sclk_vpll", };
+PNAME(mout_audio0_p) = { "cdclk0", "none", "sclk_hdmi24m", "sclk_usbphy0",
+ "xxti", "xusbxti", "sclk_mpll", "sclk_epll",
+ "sclk_vpll" };
+PNAME(mout_audio1_p) = { "cdclk1", "none", "sclk_hdmi24m", "sclk_usbphy0",
+ "xxti", "xusbxti", "sclk_mpll", "sclk_epll",
+ "sclk_vpll", };
+PNAME(mout_audio2_p) = { "cdclk2", "none", "sclk_hdmi24m", "sclk_usbphy0",
+ "xxti", "xusbxti", "sclk_mpll", "sclk_epll",
+ "sclk_vpll", };
+PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
+ "spdif_extclk", };
+
+/* fixed rate clocks generated outside the soc */
+struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
+ FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0),
+ FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0),
+};
+
+/* fixed rate clocks generated inside the soc */
+struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
+ FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
+ FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
+ FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
+};
+
+struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
+ FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
+};
+
+/* list of mux clocks supported in all exynos4 soc's */
+struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
+ MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
+ MUX(none, "mout_core", mout_core_p, SRC_CPU, 16, 1),
+ MUX(none, "mout_fimc0", group1_p, SRC_CAM, 0, 4),
+ MUX(none, "mout_fimc1", group1_p, SRC_CAM, 4, 4),
+ MUX(none, "mout_fimc2", group1_p, SRC_CAM, 8, 4),
+ MUX(none, "mout_fimc3", group1_p, SRC_CAM, 12, 4),
+ MUX(none, "mout_cam0", group1_p, SRC_CAM, 16, 4),
+ MUX(none, "mout_cam1", group1_p, SRC_CAM, 20, 4),
+ MUX(none, "mout_csis0", group1_p, SRC_CAM, 24, 4),
+ MUX(none, "mout_csis1", group1_p, SRC_CAM, 28, 4),
+ MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
+ MUX(none, "mout_mfc0", sclk_ampll_p, SRC_MFC, 0, 1),
+ MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
+ MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
+ MUX(none, "mout_g3d0", sclk_ampll_p, SRC_G3D, 0, 1),
+ MUX(none, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1),
+ MUX(none, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
+ MUX(none, "mout_fimd0", group1_p, SRC_LCD0, 0, 4),
+ MUX(none, "mout_mipi0", group1_p, SRC_LCD0, 12, 4),
+ MUX(none, "mout_audio0", mout_audio0_p, SRC_MAUDIO, 0, 4),
+ MUX(none, "mout_mmc0", group1_p, SRC_FSYS, 0, 4),
+ MUX(none, "mout_mmc1", group1_p, SRC_FSYS, 4, 4),
+ MUX(none, "mout_mmc2", group1_p, SRC_FSYS, 8, 4),
+ MUX(none, "mout_mmc3", group1_p, SRC_FSYS, 12, 4),
+ MUX(none, "mout_mmc4", group1_p, SRC_FSYS, 16, 4),
+ MUX(none, "mout_uart0", group1_p, SRC_PERIL0, 0, 4),
+ MUX(none, "mout_uart1", group1_p, SRC_PERIL0, 4, 4),
+ MUX(none, "mout_uart2", group1_p, SRC_PERIL0, 8, 4),
+ MUX(none, "mout_uart3", group1_p, SRC_PERIL0, 12, 4),
+ MUX(none, "mout_uart4", group1_p, SRC_PERIL0, 16, 4),
+ MUX(none, "mout_audio1", mout_audio1_p, SRC_PERIL1, 0, 4),
+ MUX(none, "mout_audio2", mout_audio2_p, SRC_PERIL1, 4, 4),
+ MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
+ MUX(none, "mout_spi0", group1_p, SRC_PERIL1, 16, 4),
+ MUX(none, "mout_spi1", group1_p, SRC_PERIL1, 20, 4),
+ MUX(none, "mout_spi2", group1_p, SRC_PERIL1, 24, 4),
+ MUX_A(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, "sclk_epll"),
+};
+
+/* list of mux clocks supported in exynos4210 soc */
+struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
+ MUX(none, "mout_aclk200", sclk_ampll_p, SRC_TOP0, 12, 1),
+ MUX(none, "mout_aclk100", sclk_ampll_p, SRC_TOP0, 16, 1),
+ MUX(none, "mout_aclk160", sclk_ampll_p, SRC_TOP0, 20, 1),
+ MUX(none, "mout_aclk133", sclk_ampll_p, SRC_TOP0, 24, 1),
+ MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
+ MUX(none, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
+ MUX(none, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
+ MUX(none, "mout_g2d0", sclk_ampll_p, E4210_SRC_IMAGE, 0, 1),
+ MUX(none, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
+ MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
+ MUX(none, "mout_fimd1", group1_p, SRC_LCD1, 0, 4),
+ MUX(none, "mout_mipi1", group1_p, SRC_LCD1, 12, 4),
+ MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "sclk_mpll"),
+ MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210,
+ SRC_TOP0, 8, 1, "sclk_vpll"),
+};
+
+/* list of mux clocks supported in exynos4x12 soc */
+struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
+ MUX(none, "mout_mpll_user", mout_mpll_user_p, SRC_LEFTBUS, 4, 1),
+ MUX(none, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
+ MUX(none, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
+ MUX(none, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
+ MUX(none, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1),
+ MUX(none, "mout_mdnie0", group1_p, SRC_LCD0, 4, 4),
+ MUX(none, "mout_mdnie_pwm0", group1_p, SRC_LCD0, 8, 4),
+ MUX(none, "mout_sata", sclk_ampll_p, SRC_FSYS, 24, 1),
+ MUX(none, "mout_jpeg0", sclk_ampll_p, E4X12_SRC_CAM1, 0, 1),
+ MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
+ MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
+ MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p,
+ E4X12_SRC_DMC, 12, 1, "sclk_mpll"),
+ MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p,
+ SRC_TOP0, 8, 1, "sclk_vpll"),
+};
+
+/* list of divider clocks supported in all exynos4 soc's */
+struct samsung_div_clock exynos4_div_clks[] __initdata = {
+ DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3),
+ DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3),
+ DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
+ DIV(none, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
+ DIV(none, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
+ DIV(none, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
+ DIV(none, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
+ DIV(none, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
+ DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
+ DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
+ DIV(none, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
+ DIV(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
+ DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
+ DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
+ DIV(none, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
+ DIV(none, "div_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
+ DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+ DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
+ DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
+ DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
+ DIV(sclk_pixel, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
+ DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
+ DIV(aclk100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
+ DIV(aclk160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
+ DIV(aclk133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
+ DIV(sclk_slimbus, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
+ DIV(sclk_pcm1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
+ DIV(sclk_pcm2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
+ DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
+ DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
+ DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
+ DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8),
+ DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
+ DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
+ DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
+ DIV(none, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
+ DIV(none, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
+ DIV(none, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
+ DIV(none, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
+ DIV(none, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
+ DIV(none, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
+ DIV(none, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
+ DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
+ DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
+ DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
+ DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "arm_clk"),
+ DIV_A(sclk_apll, "sclk_apll", "mout_apll",
+ DIV_CPU0, 24, 3, "sclk_apll"),
+ DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
+ CLK_SET_RATE_PARENT, 0),
+ DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV_F(none, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV_F(none, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV_F(none, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
+ CLK_SET_RATE_PARENT, 0),
+};
+
+/* list of divider clocks supported in exynos4210 soc */
+struct samsung_div_clock exynos4210_div_clks[] __initdata = {
+ DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4),
+ DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
+ DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
+ DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
+ DIV_F(none, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4,
+ CLK_SET_RATE_PARENT, 0),
+};
+
+/* list of divider clocks supported in exynos4x12 soc */
+struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
+ DIV(none, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
+ DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
+ DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
+ DIV(none, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
+ DIV(none, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
+};
+
+/* list of gate clocks supported in all exynos4 soc's */
+struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
+ /*
+ * After all Exynos4 based platforms are migrated to use device tree,
+ * the device name and clock alias names specified below for some
+ * of the clocks can be removed.
+ */
+ GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
+ GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
+ GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
+ GATE(sclk_spdif, "sclk_spdif", "mout_spdif", 0xc354, 8, 0, 0),
+ GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
+ GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
+ GATE(dsim0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
+ GATE(fimd1, "fimd1", "aclk160", GATE_IP_LCD1, 0, 0, 0),
+ GATE(mie1, "mie1", "aclk160", GATE_IP_LCD1, 1, 0, 0),
+ GATE(dsim1, "dsim1", "aclk160", GATE_IP_LCD1, 3, 0, 0),
+ GATE(smmu_fimd1, "smmu_fimd1", "aclk160", GATE_IP_LCD1, 4, 0, 0),
+ GATE(tsi, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
+ GATE(sromc, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
+ GATE(g3d, "g3d", "aclk200", GATE_IP_G3D, 0, 0, 0),
+ GATE(usb_device, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
+ GATE(onenand, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
+ GATE(nfcon, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
+ GATE(gps, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
+ GATE(smmu_gps, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
+ GATE(slimbus, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
+ GATE(sclk_cam0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_cam1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5,
+ CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_mipi0, "sclk_mipi0", "div_mipi_pre0",
+ SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_audio1, "sclk_audio1", "div_audio1", 0xc354, 0,
+ CLK_SET_RATE_PARENT, 0),
+ GATE_D(vp, "s5p-mixer", "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
+ GATE_D(mixer, "s5p-mixer", "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
+ GATE_D(hdmi, "exynos4-hdmi", "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
+ GATE_A(pwm, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0, "timers"),
+ GATE_A(sdmmc4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0, "biu"),
+ GATE_A(usb_host, "usb_host", "aclk133",
+ GATE_IP_FSYS, 12, 0, 0, "usbhost"),
+ GATE_DA(sclk_fimc0, "exynos4-fimc.0", "sclk_fimc0", "div_fimc0",
+ SRC_MASK_CAM, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
+ GATE_DA(sclk_fimc1, "exynos4-fimc.1", "sclk_fimc1", "div_fimc1",
+ SRC_MASK_CAM, 4, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
+ GATE_DA(sclk_fimc2, "exynos4-fimc.2", "sclk_fimc2", "div_fimc2",
+ SRC_MASK_CAM, 8, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
+ GATE_DA(sclk_fimc3, "exynos4-fimc.3", "sclk_fimc3", "div_fimc3",
+ SRC_MASK_CAM, 12, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
+ GATE_DA(sclk_csis0, "s5p-mipi-csis.0", "sclk_csis0", "div_csis0",
+ SRC_MASK_CAM, 24, CLK_SET_RATE_PARENT, 0, "sclk_csis"),
+ GATE_DA(sclk_csis1, "s5p-mipi-csis.1", "sclk_csis1", "div_csis1",
+ SRC_MASK_CAM, 28, CLK_SET_RATE_PARENT, 0, "sclk_csis"),
+ GATE_DA(sclk_fimd0, "exynos4-fb.0", "sclk_fimd0", "div_fimd0",
+ SRC_MASK_LCD0, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),
+ GATE_DA(sclk_mmc0, "exynos4-sdhci.0", "sclk_mmc0", "div_mmc_pre0",
+ SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0,
+ "mmc_busclk.2"),
+ GATE_DA(sclk_mmc1, "exynos4-sdhci.1", "sclk_mmc1", "div_mmc_pre1",
+ SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0,
+ "mmc_busclk.2"),
+ GATE_DA(sclk_mmc2, "exynos4-sdhci.2", "sclk_mmc2", "div_mmc_pre2",
+ SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0,
+ "mmc_busclk.2"),
+ GATE_DA(sclk_mmc3, "exynos4-sdhci.3", "sclk_mmc3", "div_mmc_pre3",
+ SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0,
+ "mmc_busclk.2"),
+ GATE_DA(sclk_mmc4, NULL, "sclk_mmc4", "div_mmc_pre4",
+ SRC_MASK_FSYS, 16, CLK_SET_RATE_PARENT, 0, "ciu"),
+ GATE_DA(sclk_uart0, "exynos4210-uart.0", "uclk0", "div_uart0",
+ 0xc350, 0, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"),
+ GATE_DA(sclk_uart1, "exynos4210-uart.1", "uclk1", "div_uart1",
+ 0xc350, 4, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"),
+ GATE_DA(sclk_uart2, "exynos4210-uart.2", "uclk2", "div_uart2",
+ 0xc350, 8, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"),
+ GATE_DA(sclk_uart3, "exynos4210-uart.3", "uclk3", "div_uart3",
+ 0xc350, 12, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"),
+ GATE_DA(sclk_uart4, "exynos4210-uart.4", "uclk4", "div_uart4",
+ 0xc350, 16, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"),
+ GATE(sclk_audio2, "sclk_audio2", "div_audio2", 0xc354, 4,
+ CLK_SET_RATE_PARENT, 0),
+ GATE_DA(sclk_spi0, "exynos4210-spi.0", "sclk_spi0", "div_spi_pre0",
+ 0xc354, 16, CLK_SET_RATE_PARENT, 0, "spi_busclk0"),
+ GATE_DA(sclk_spi1, "exynos4210-spi.1", "sclk_spi1", "div_spi_pre1",
+ 0xc354, 20, CLK_SET_RATE_PARENT, 0, "spi_busclk0"),
+ GATE_DA(sclk_spi2, "exynos4210-spi.2", "sclk_spi2", "div_spi_pre2",
+ 0xc354, 24, CLK_SET_RATE_PARENT, 0, "spi_busclk0"),
+ GATE_DA(fimc0, "exynos4-fimc.0", "fimc0", "aclk160",
+ GATE_IP_CAM, 0, 0, 0, "fimc"),
+ GATE_DA(fimc1, "exynos4-fimc.1", "fimc1", "aclk160",
+ GATE_IP_CAM, 1, 0, 0, "fimc"),
+ GATE_DA(fimc2, "exynos4-fimc.2", "fimc2", "aclk160",
+ GATE_IP_CAM, 2, 0, 0, "fimc"),
+ GATE_DA(fimc3, "exynos4-fimc.3", "fimc3", "aclk160",
+ GATE_IP_CAM, 3, 0, 0, "fimc"),
+ GATE_DA(csis0, "s5p-mipi-csis.0", "csis0", "aclk160",
+ GATE_IP_CAM, 4, 0, 0, "fimc"),
+ GATE_DA(csis1, "s5p-mipi-csis.1", "csis1", "aclk160",
+ GATE_IP_CAM, 5, 0, 0, "fimc"),
+ GATE_DA(smmu_fimc0, "exynos-sysmmu.5", "smmu_fimc0", "aclk160",
+ GATE_IP_CAM, 7, 0, 0, "sysmmu"),
+ GATE_DA(smmu_fimc1, "exynos-sysmmu.6", "smmu_fimc1", "aclk160",
+ GATE_IP_CAM, 8, 0, 0, "sysmmu"),
+ GATE_DA(smmu_fimc2, "exynos-sysmmu.7", "smmu_fimc2", "aclk160",
+ GATE_IP_CAM, 9, 0, 0, "sysmmu"),
+ GATE_DA(smmu_fimc3, "exynos-sysmmu.8", "smmu_fimc3", "aclk160",
+ GATE_IP_CAM, 10, 0, 0, "sysmmu"),
+ GATE_DA(smmu_jpeg, "exynos-sysmmu.3", "smmu_jpeg", "aclk160",
+ GATE_IP_CAM, 11, 0, 0, "sysmmu"),
+ GATE_DA(smmu_tv, "exynos-sysmmu.2", "smmu_tv", "aclk160",
+ GATE_IP_TV, 4, 0, 0, "sysmmu"),
+ GATE_DA(mfc, "s5p-mfc", "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0, "mfc"),
+ GATE_DA(smmu_mfcl, "exynos-sysmmu.0", "smmu_mfcl", "aclk100",
+ GATE_IP_MFC, 1, 0, 0, "sysmmu"),
+ GATE_DA(smmu_mfcr, "exynos-sysmmu.1", "smmu_mfcr", "aclk100",
+ GATE_IP_MFC, 2, 0, 0, "sysmmu"),
+ GATE_DA(fimd0, "exynos4-fb.0", "fimd0", "aclk160",
+ GATE_IP_LCD0, 0, 0, 0, "fimd"),
+ GATE_DA(smmu_fimd0, "exynos-sysmmu.10", "smmu_fimd0", "aclk160",
+ GATE_IP_LCD0, 4, 0, 0, "sysmmu"),
+ GATE_DA(pdma0, "dma-pl330.0", "pdma0", "aclk133",
+ GATE_IP_FSYS, 0, 0, 0, "dma"),
+ GATE_DA(pdma1, "dma-pl330.1", "pdma1", "aclk133",
+ GATE_IP_FSYS, 1, 0, 0, "dma"),
+ GATE_DA(sdmmc0, "exynos4-sdhci.0", "sdmmc0", "aclk133",
+ GATE_IP_FSYS, 5, 0, 0, "hsmmc"),
+ GATE_DA(sdmmc1, "exynos4-sdhci.1", "sdmmc1", "aclk133",
+ GATE_IP_FSYS, 6, 0, 0, "hsmmc"),
+ GATE_DA(sdmmc2, "exynos4-sdhci.2", "sdmmc2", "aclk133",
+ GATE_IP_FSYS, 7, 0, 0, "hsmmc"),
+ GATE_DA(sdmmc3, "exynos4-sdhci.3", "sdmmc3", "aclk133",
+ GATE_IP_FSYS, 8, 0, 0, "hsmmc"),
+ GATE_DA(uart0, "exynos4210-uart.0", "uart0", "aclk100",
+ GATE_IP_PERIL, 0, 0, 0, "uart"),
+ GATE_DA(uart1, "exynos4210-uart.1", "uart1", "aclk100",
+ GATE_IP_PERIL, 1, 0, 0, "uart"),
+ GATE_DA(uart2, "exynos4210-uart.2", "uart2", "aclk100",
+ GATE_IP_PERIL, 2, 0, 0, "uart"),
+ GATE_DA(uart3, "exynos4210-uart.3", "uart3", "aclk100",
+ GATE_IP_PERIL, 3, 0, 0, "uart"),
+ GATE_DA(uart4, "exynos4210-uart.4", "uart4", "aclk100",
+ GATE_IP_PERIL, 4, 0, 0, "uart"),
+ GATE_DA(i2c0, "s3c2440-i2c.0", "i2c0", "aclk100",
+ GATE_IP_PERIL, 6, 0, 0, "i2c"),
+ GATE_DA(i2c1, "s3c2440-i2c.1", "i2c1", "aclk100",
+ GATE_IP_PERIL, 7, 0, 0, "i2c"),
+ GATE_DA(i2c2, "s3c2440-i2c.2", "i2c2", "aclk100",
+ GATE_IP_PERIL, 8, 0, 0, "i2c"),
+ GATE_DA(i2c3, "s3c2440-i2c.3", "i2c3", "aclk100",
+ GATE_IP_PERIL, 9, 0, 0, "i2c"),
+ GATE_DA(i2c4, "s3c2440-i2c.4", "i2c4", "aclk100",
+ GATE_IP_PERIL, 10, 0, 0, "i2c"),
+ GATE_DA(i2c5, "s3c2440-i2c.5", "i2c5", "aclk100",
+ GATE_IP_PERIL, 11, 0, 0, "i2c"),
+ GATE_DA(i2c6, "s3c2440-i2c.6", "i2c6", "aclk100",
+ GATE_IP_PERIL, 12, 0, 0, "i2c"),
+ GATE_DA(i2c7, "s3c2440-i2c.7", "i2c7", "aclk100",
+ GATE_IP_PERIL, 13, 0, 0, "i2c"),
+ GATE_DA(i2c_hdmi, "s3c2440-hdmiphy-i2c", "i2c-hdmi", "aclk100",
+ GATE_IP_PERIL, 14, 0, 0, "i2c"),
+ GATE_DA(spi0, "exynos4210-spi.0", "spi0", "aclk100",
+ GATE_IP_PERIL, 16, 0, 0, "spi"),
+ GATE_DA(spi1, "exynos4210-spi.1", "spi1", "aclk100",
+ GATE_IP_PERIL, 17, 0, 0, "spi"),
+ GATE_DA(spi2, "exynos4210-spi.2", "spi2", "aclk100",
+ GATE_IP_PERIL, 18, 0, 0, "spi"),
+ GATE_DA(i2s1, "samsung-i2s.1", "i2s1", "aclk100",
+ GATE_IP_PERIL, 20, 0, 0, "iis"),
+ GATE_DA(i2s2, "samsung-i2s.2", "i2s2", "aclk100",
+ GATE_IP_PERIL, 21, 0, 0, "iis"),
+ GATE_DA(pcm1, "samsung-pcm.1", "pcm1", "aclk100",
+ GATE_IP_PERIL, 22, 0, 0, "pcm"),
+ GATE_DA(pcm2, "samsung-pcm.2", "pcm2", "aclk100",
+ GATE_IP_PERIL, 23, 0, 0, "pcm"),
+ GATE_DA(spdif, "samsung-spdif", "spdif", "aclk100",
+ GATE_IP_PERIL, 26, 0, 0, "spdif"),
+ GATE_DA(ac97, "samsung-ac97", "ac97", "aclk100",
+ GATE_IP_PERIL, 27, 0, 0, "ac97"),
+};
+
+/* list of gate clocks supported in exynos4210 soc */
+struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
+ GATE(tvenc, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
+ GATE(g2d, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
+ GATE(rotator, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
+ GATE(mdma, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0),
+ GATE(smmu_g2d, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
+ GATE(smmu_mdma, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, 0),
+ GATE(pcie_phy, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
+ GATE(sata_phy, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
+ GATE(sata, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
+ GATE(pcie, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
+ GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
+ GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
+ GATE(chipid, "chipid", "aclk100", GATE_IP_PERIR, 0, 0, 0),
+ GATE(sysreg, "sysreg", "aclk100", GATE_IP_PERIR, 0, 0, 0),
+ GATE(hdmi_cec, "hdmi_cec", "aclk100", GATE_IP_PERIR, 11, 0, 0),
+ GATE(smmu_rotator, "smmu_rotator", "aclk200",
+ E4210_GATE_IP_IMAGE, 4, 0, 0),
+ GATE(sclk_mipi1, "sclk_mipi1", "div_mipi_pre1",
+ SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_sata, "sclk_sata", "div_sata",
+ SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
+ GATE_A(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 0, 0, "adc"),
+ GATE_A(mct, "mct", "aclk100", GATE_IP_PERIR, 13, 0, 0, "mct"),
+ GATE_A(wdt, "watchdog", "aclk100", GATE_IP_PERIR, 14, 0, 0, "watchdog"),
+ GATE_A(rtc, "rtc", "aclk100", GATE_IP_PERIR, 15, 0, 0, "rtc"),
+ GATE_A(keyif, "keyif", "aclk100", GATE_IP_PERIR, 16, 0, 0, "keypad"),
+ GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1",
+ SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),
+};
+
+/* list of gate clocks supported in exynos4x12 soc */
+struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
+ GATE(audss, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
+ GATE(mdnie0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
+ GATE(rotator, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
+ GATE(mdma2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
+ GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0),
+ GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
+ GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
+ GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 0, 0),
+ GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0),
+ GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0",
+ SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_mdnie_pwm0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0",
+ SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_mipihsi, "sclk_mipihsi", "div_mipihsi",
+ SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
+ GATE(smmu_rotator, "smmu_rotator", "aclk200",
+ E4X12_GATE_IP_IMAGE, 4, 0, 0),
+ GATE_A(mct, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, 0, 0, "mct"),
+ GATE_A(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 0, 0, "rtc"),
+ GATE_A(keyif, "keyif", "aclk100",
+ E4X12_GATE_IP_PERIR, 16, 0, 0, "keypad"),
+ GATE_A(wdt, "watchdog", "aclk100",
+ E4X12_GATE_IP_PERIR, 14, 0, 0, "watchdog"),
+ GATE_DA(pcm0, "samsung-pcm.0", "pcm0", "aclk100",
+ E4X12_GATE_IP_MAUDIO, 2, 0, 0, "pcm"),
+ GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100",
+ E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"),
+};
+
+#ifdef CONFIG_OF
+static struct of_device_id exynos4_clk_ids[] __initdata = {
+ { .compatible = "samsung,exynos4210-clock",
+ .data = (void *)EXYNOS4210, },
+ { .compatible = "samsung,exynos4412-clock",
+ .data = (void *)EXYNOS4X12, },
+ { },
+};
+#endif
+
+/*
+ * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
+ * resides in chipid register space, outside of the clock controller memory
+ * mapped space. So to determine the parent of fin_pll clock, the chipid
+ * controller is first remapped and the value of XOM[0] bit is read to
+ * determine the parent clock.
+ */
+static void __init exynos4_clk_register_finpll(void)
+{
+ struct samsung_fixed_rate_clock fclk;
+ struct device_node *np;
+ struct clk *clk;
+ void __iomem *chipid_base = S5P_VA_CHIPID;
+ unsigned long xom, finpll_f = 24000000;
+ char *parent_name;
+
+ np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
+ if (np)
+ chipid_base = of_iomap(np, 0);
+
+ if (chipid_base) {
+ xom = readl(chipid_base + 8);
+ parent_name = xom & 1 ? "xusbxti" : "xxti";
+ clk = clk_get(NULL, parent_name);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to lookup parent clock %s, assuming "
+ "fin_pll clock frequency is 24MHz\n", __func__,
+ parent_name);
+ } else {
+ finpll_f = clk_get_rate(clk);
+ }
+ } else {
+ pr_err("%s: failed to map chipid registers, assuming "
+ "fin_pll clock frequency is 24MHz\n", __func__);
+ }
+
+ fclk.id = fin_pll;
+ fclk.name = "fin_pll";
+ fclk.parent_name = NULL;
+ fclk.flags = CLK_IS_ROOT;
+ fclk.fixed_rate = finpll_f;
+ samsung_clk_register_fixed_rate(&fclk, 1);
+
+ if (np)
+ iounmap(chipid_base);
+}
+
+/*
+ * This function allows non-dt platforms to specify the clock speed of the
+ * xxti and xusbxti clocks. These clocks are then registered with the specified
+ * clock speed.
+ */
+void __init exynos4_clk_register_fixed_ext(unsigned long xxti_f,
+ unsigned long xusbxti_f)
+{
+ exynos4_fixed_rate_ext_clks[0].fixed_rate = xxti_f;
+ exynos4_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f;
+ samsung_clk_register_fixed_rate(exynos4_fixed_rate_ext_clks,
+ ARRAY_SIZE(exynos4_fixed_rate_ext_clks));
+}
+
+static __initdata struct of_device_id ext_clk_match[] = {
+ { .compatible = "samsung,clock-xxti", .data = (void *)0, },
+ { .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
+ {},
+};
+
+/* register exynos4 clocks */
+void __init exynos4_clk_init(struct device_node *np)
+{
+ void __iomem *reg_base;
+ struct clk *apll, *mpll, *epll, *vpll;
+ u32 exynos4_soc;
+
+ if (np) {
+ const struct of_device_id *match;
+ match = of_match_node(exynos4_clk_ids, np);
+ exynos4_soc = (u32)match->data;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+ } else {
+ reg_base = S5P_VA_CMU;
+ if (soc_is_exynos4210())
+ exynos4_soc = EXYNOS4210;
+ else if (soc_is_exynos4212() || soc_is_exynos4412())
+ exynos4_soc = EXYNOS4X12;
+ else
+ panic("%s: unable to determine soc\n", __func__);
+ }
+
+ samsung_clk_init(np, reg_base, nr_clks,
+ exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs));
+
+ if (np)
+ samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
+ ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
+ ext_clk_match);
+
+ exynos4_clk_register_finpll();
+
+ if (exynos4_soc == EXYNOS4210) {
+ apll = samsung_clk_register_pll45xx("fout_apll", "fin_pll",
+ reg_base + APLL_CON0, pll_4508);
+ mpll = samsung_clk_register_pll45xx("fout_mpll", "fin_pll",
+ reg_base + E4210_MPLL_CON0, pll_4508);
+ epll = samsung_clk_register_pll46xx("fout_epll", "fin_pll",
+ reg_base + 0xc110, pll_4600);
+ vpll = samsung_clk_register_pll46xx("fout_vpll", "mout_vpllsrc",
+ reg_base + 0xc120, pll_4650c);
+ } else {
+ apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
+ reg_base + APLL_CON0);
+ mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
+ reg_base + E4X12_MPLL_CON0);
+ epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
+ reg_base + 0xc110);
+ vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll",
+ reg_base + 0xc120);
+ }
+
+ samsung_clk_add_lookup(apll, fout_apll);
+ samsung_clk_add_lookup(mpll, fout_mpll);
+ samsung_clk_add_lookup(epll, fout_epll);
+ samsung_clk_add_lookup(vpll, fout_vpll);
+
+ samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks,
+ ARRAY_SIZE(exynos4_fixed_rate_clks));
+ samsung_clk_register_mux(exynos4_mux_clks,
+ ARRAY_SIZE(exynos4_mux_clks));
+ samsung_clk_register_div(exynos4_div_clks,
+ ARRAY_SIZE(exynos4_div_clks));
+ samsung_clk_register_gate(exynos4_gate_clks,
+ ARRAY_SIZE(exynos4_gate_clks));
+
+ if (exynos4_soc == EXYNOS4210) {
+ samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks,
+ ARRAY_SIZE(exynos4210_fixed_rate_clks));
+ samsung_clk_register_mux(exynos4210_mux_clks,
+ ARRAY_SIZE(exynos4210_mux_clks));
+ samsung_clk_register_div(exynos4210_div_clks,
+ ARRAY_SIZE(exynos4210_div_clks));
+ samsung_clk_register_gate(exynos4210_gate_clks,
+ ARRAY_SIZE(exynos4210_gate_clks));
+ } else {
+ samsung_clk_register_mux(exynos4x12_mux_clks,
+ ARRAY_SIZE(exynos4x12_mux_clks));
+ samsung_clk_register_div(exynos4x12_div_clks,
+ ARRAY_SIZE(exynos4x12_div_clks));
+ samsung_clk_register_gate(exynos4x12_gate_clks,
+ ARRAY_SIZE(exynos4x12_gate_clks));
+ }
+
+ pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
+ "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
+ exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
+ _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
+ _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
+ _get_rate("arm_clk"));
+}
+CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4_clk_init);
+CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4_clk_init);
--
1.7.5.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v6 04/16] clk: exynos5250: register clocks using common clock framework
2013-02-18 8:21 [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework Thomas Abraham
` (2 preceding siblings ...)
2013-02-18 8:21 ` [PATCH v6 03/16] clk: exynos4: register clocks using common clock framework Thomas Abraham
@ 2013-02-18 8:21 ` Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 05/16] clk: exynos5440: " Thomas Abraham
` (11 subsequent siblings)
15 siblings, 0 replies; 37+ messages in thread
From: Thomas Abraham @ 2013-02-18 8:21 UTC (permalink / raw)
To: linux-arm-kernel
The Exynos5250 clocks are statically listed and registered using the Samsung
specific common clock helper functions. Both device tree based clock lookup
and clkdev based clock lookups are supported.
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
.../devicetree/bindings/clock/exynos5250-clock.txt | 171 +++++++
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5250.c | 514 ++++++++++++++++++++
3 files changed, 686 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5250-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5250.c
diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
new file mode 100644
index 0000000..7104f02
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -0,0 +1,171 @@
+* Samsung Exynos5250 Clock Controller
+
+The Exynos5250 clock controller generates and supplies clock to various
+controllers within the Exynos5250 SoC.
+
+Required Properties:
+
+- comptible: should be one of the following.
+ - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume.
+
+
+ [Core Clocks]
+
+ Clock ID
+ ----------------------------
+
+ fin_pll 1
+
+ [Clock Gate for Special Clocks]
+
+ Clock ID
+ ----------------------------
+
+ sclk_cam_bayer 128
+ sclk_cam0 129
+ sclk_cam1 130
+ sclk_gscl_wa 131
+ sclk_gscl_wb 132
+ sclk_fimd1 133
+ sclk_mipi1 134
+ sclk_dp 135
+ sclk_hdmi 136
+ sclk_pixel 137
+ sclk_audio0 138
+ sclk_mmc0 139
+ sclk_mmc1 140
+ sclk_mmc2 141
+ sclk_mmc3 142
+ sclk_sata 143
+ sclk_usb3 144
+ sclk_jpeg 145
+ sclk_uart0 146
+ sclk_uart1 147
+ sclk_uart2 148
+ sclk_uart3 149
+ sclk_pwm 150
+ sclk_audio1 151
+ sclk_audio2 152
+ sclk_spdif 153
+ sclk_spi0 154
+ sclk_spi1 155
+ sclk_spi2 156
+
+
+ [Peripheral Clock Gates]
+
+ Clock ID
+ ----------------------------
+
+ gscl0 256
+ gscl1 257
+ gscl2 258
+ gscl3 259
+ gscl_wa 260
+ gscl_wb 261
+ smmu_gscl0 262
+ smmu_gscl1 263
+ smmu_gscl2 264
+ smmu_gscl3 265
+ mfc 266
+ smmu_mfcl 267
+ smmu_mfcr 268
+ rotator 269
+ jpeg 270
+ mdma1 271
+ smmu_rotator 272
+ smmu_jpeg 273
+ smmu_mdma1 274
+ pdma0 275
+ pdma1 276
+ sata 277
+ usbotg 278
+ mipi_hsi 279
+ sdmmc0 280
+ sdmmc1 281
+ sdmmc2 282
+ sdmmc3 283
+ sromc 284
+ usb2 285
+ usb3 286
+ sata_phyctrl 287
+ sata_phyi2c 288
+ uart0 289
+ uart1 290
+ uart2 291
+ uart3 292
+ uart4 293
+ i2c0 294
+ i2c1 295
+ i2c2 296
+ i2c3 297
+ i2c4 298
+ i2c5 299
+ i2c6 300
+ i2c7 301
+ i2c_hdmi 302
+ adc 303
+ spi0 304
+ spi1 305
+ spi2 306
+ i2s1 307
+ i2s2 308
+ pcm1 309
+ pcm2 310
+ pwm 311
+ spdif 312
+ ac97 313
+ hsi2c0 314
+ hsi2c1 315
+ hs12c2 316
+ hs12c3 317
+ chipid 318
+ sysreg 319
+ pmu 320
+ cmu_top 321
+ cmu_core 322
+ cmu_mem 323
+ tzpc0 324
+ tzpc1 325
+ tzpc2 326
+ tzpc3 327
+ tzpc4 328
+ tzpc5 329
+ tzpc6 330
+ tzpc7 331
+ tzpc8 332
+ tzpc9 333
+ hdmi_cec 334
+ mct 335
+ wdt 336
+ rtc 337
+ tmu 338
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller at 0x10010000 {
+ compatible = "samsung,exynos5250-clock";
+ reg = <0x10010000 0x30000>;
+ #clock-cells = <1>;
+ };
+
+Example 2: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial at 13820000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13820000 0x100>;
+ interrupts = <0 54 0>;
+ clocks = <&clock 314>, <&clock 153>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 8862f0d..f18fb07 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -4,3 +4,4 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
+obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
new file mode 100644
index 0000000..1152125
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -0,0 +1,514 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ * Author: Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5250 SoC.
+*/
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <plat/cpu.h>
+#include "clk.h"
+#include "clk-pll.h"
+
+#define SRC_CPU 0x200
+#define DIV_CPU0 0x500
+#define SRC_CORE1 0x4204
+#define SRC_TOP0 0x10210
+#define SRC_TOP2 0x10218
+#define SRC_GSCL 0x10220
+#define SRC_DISP1_0 0x1022c
+#define SRC_MAU 0x10240
+#define SRC_FSYS 0x10244
+#define SRC_GEN 0x10248
+#define SRC_PERIC0 0x10250
+#define SRC_PERIC1 0x10254
+#define SRC_MASK_GSCL 0x10320
+#define SRC_MASK_DISP1_0 0x1032c
+#define SRC_MASK_MAU 0x10334
+#define SRC_MASK_FSYS 0x10340
+#define SRC_MASK_GEN 0x10344
+#define SRC_MASK_PERIC0 0x10350
+#define SRC_MASK_PERIC1 0x10354
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_GSCL 0x10520
+#define DIV_DISP1_0 0x1052c
+#define DIV_GEN 0x1053c
+#define DIV_MAU 0x10544
+#define DIV_FSYS0 0x10548
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define DIV_PERIC1 0x1055c
+#define DIV_PERIC2 0x10560
+#define DIV_PERIC3 0x10564
+#define DIV_PERIC4 0x10568
+#define DIV_PERIC5 0x1056c
+#define GATE_IP_GSCL 0x10920
+#define GATE_IP_MFC 0x1092c
+#define GATE_IP_GEN 0x10934
+#define GATE_IP_FSYS 0x10944
+#define GATE_IP_PERIC 0x10950
+#define GATE_IP_PERIS 0x10960
+#define SRC_CDREX 0x20200
+#define PLL_DIV2_SEL 0x20a24
+
+/*
+ * Let each supported clock get a unique id. This id is used to lookup the clock
+ * for device tree based platforms. The clocks are categorized into three
+ * sections: core, sclk gate and bus interface gate clocks.
+ *
+ * When adding a new clock to this list, it is advised to choose a clock
+ * category and add it to the end of that category. That is because the the
+ * device tree source file is referring to these ids and any change in the
+ * sequence number of existing clocks will require corresponding change in the
+ * device tree files. This limitation would go away when pre-processor support
+ * for dtc would be available.
+ */
+enum exynos5250_clks {
+ none,
+
+ /* core clocks */
+ fin_pll,
+
+ /* gate for special clocks (sclk) */
+ sclk_cam_bayer = 128, sclk_cam0, sclk_cam1, sclk_gscl_wa, sclk_gscl_wb,
+ sclk_fimd1, sclk_mipi1, sclk_dp, sclk_hdmi, sclk_pixel, sclk_audio0,
+ sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
+ sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
+ sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
+
+ /* gate clocks */
+ gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
+ smmu_gscl1, smmu_gscl2, smmu_gscl3, mfc, smmu_mfcl, smmu_mfcr, rotator,
+ jpeg, mdma1, smmu_rotator, smmu_jpeg, smmu_mdma1, pdma0, pdma1, sata,
+ usbotg, mipi_hsi, sdmmc0, sdmmc1, sdmmc2, sdmmc3, sromc, usb2, usb3,
+ sata_phyctrl, sata_phyi2c, uart0, uart1, uart2, uart3, uart4, i2c0,
+ i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, adc, spi0, spi1,
+ spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
+ hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
+ tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
+ wdt, rtc, tmu,
+
+ nr_clks,
+};
+
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+static __initdata unsigned long exynos5250_clk_regs[] = {
+ SRC_CPU,
+ DIV_CPU0,
+ SRC_CORE1,
+ SRC_TOP0,
+ SRC_TOP2,
+ SRC_GSCL,
+ SRC_DISP1_0,
+ SRC_MAU,
+ SRC_FSYS,
+ SRC_GEN,
+ SRC_PERIC0,
+ SRC_PERIC1,
+ SRC_MASK_GSCL,
+ SRC_MASK_DISP1_0,
+ SRC_MASK_MAU,
+ SRC_MASK_FSYS,
+ SRC_MASK_GEN,
+ SRC_MASK_PERIC0,
+ SRC_MASK_PERIC1,
+ DIV_TOP0,
+ DIV_TOP1,
+ DIV_GSCL,
+ DIV_DISP1_0,
+ DIV_GEN,
+ DIV_MAU,
+ DIV_FSYS0,
+ DIV_FSYS1,
+ DIV_FSYS2,
+ DIV_PERIC0,
+ DIV_PERIC1,
+ DIV_PERIC2,
+ DIV_PERIC3,
+ DIV_PERIC4,
+ DIV_PERIC5,
+ GATE_IP_GSCL,
+ GATE_IP_MFC,
+ GATE_IP_GEN,
+ GATE_IP_FSYS,
+ GATE_IP_PERIC,
+ GATE_IP_PERIS,
+ SRC_CDREX,
+ PLL_DIV2_SEL,
+};
+
+/* list of all parent clock list */
+PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
+PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", };
+PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
+PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" };
+PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
+PNAME(mout_bpll_p) = { "fin_pll", "mout_bpll_fout" };
+PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
+PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" };
+PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
+PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
+PNAME(mout_mpll_user_p) = { "fin_pll", "sclk_mpll" };
+PNAME(mout_bpll_user_p) = { "fin_pll", "sclk_bpll" };
+PNAME(mout_aclk166_p) = { "sclk_cpll", "sclk_mpll_user" };
+PNAME(mout_aclk200_p) = { "sclk_mpll_user", "sclk_bpll_user" };
+PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" };
+PNAME(mout_usb3_p) = { "sclk_mpll_user", "sclk_cpll" };
+PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m",
+ "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
+ "sclk_mpll_user", "sclk_epll", "sclk_vpll",
+ "sclk_cpll" };
+PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
+ "sclk_uhostphy", "sclk_hdmiphy",
+ "sclk_mpll_user", "sclk_epll", "sclk_vpll",
+ "sclk_cpll" };
+PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
+ "sclk_uhostphy", "sclk_hdmiphy",
+ "sclk_mpll_user", "sclk_epll", "sclk_vpll",
+ "sclk_cpll" };
+PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
+ "sclk_uhostphy", "sclk_hdmiphy",
+ "sclk_mpll_user", "sclk_epll", "sclk_vpll",
+ "sclk_cpll" };
+PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
+ "spdif_extclk" };
+
+/* fixed rate clocks generated outside the soc */
+struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
+ FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
+};
+
+/* fixed rate clocks generated inside the soc */
+struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
+ FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
+ FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
+ FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),
+ FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),
+};
+
+struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
+ FFACTOR(none, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
+ FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
+};
+
+struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
+ MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
+ MUX(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
+ MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
+ MUX(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
+ MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
+ MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
+ MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
+ MUX(none, "sclk_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
+ MUX(none, "sclk_epll", mout_epll_p, SRC_TOP2, 12, 1),
+ MUX(none, "sclk_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
+ MUX(none, "sclk_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
+ MUX(none, "sclk_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
+ MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
+ MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
+ MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
+ MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
+ MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
+ MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
+ MUX(none, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
+ MUX(none, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
+ MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
+ MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
+ MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
+ MUX(none, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
+ MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
+ MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
+ MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
+ MUX(none, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
+ MUX(none, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
+ MUX(none, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
+ MUX(none, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
+ MUX(none, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
+ MUX(none, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
+ MUX(none, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
+ MUX(none, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
+ MUX(none, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
+ MUX(none, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
+ MUX(none, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
+ MUX(none, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
+ MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
+ MUX(none, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
+ MUX(none, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
+ MUX(none, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
+};
+
+struct samsung_div_clock exynos5250_div_clks[] __initdata = {
+ DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
+ DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
+ DIV(none, "aclk66_pre", "sclk_mpll_user", DIV_TOP1, 24, 3),
+ DIV(none, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
+ DIV(none, "aclk266", "sclk_mpll_user", DIV_TOP0, 16, 3),
+ DIV(none, "aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
+ DIV(none, "aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
+ DIV(none, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
+ DIV(none, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
+ DIV(none, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
+ DIV(none, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
+ DIV(none, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
+ DIV(none, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
+ DIV(none, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
+ DIV(none, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
+ DIV(none, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
+ DIV(none, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
+ DIV(none, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
+ DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
+ DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
+ DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
+ DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+ DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
+ DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
+ DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
+ DIV(none, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
+ DIV(none, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
+ DIV(none, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
+ DIV(none, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
+ DIV(none, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
+ DIV(none, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
+ DIV(none, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
+ DIV(none, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
+ DIV(none, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
+ DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
+ DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
+ DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
+ DIV(none, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
+ DIV(none, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
+ DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4),
+ DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"),
+ DIV_F(none, "div_mipi1_pre", "div_mipi1",
+ DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
+ DIV_F(none, "div_mmc_pre0", "div_mmc0",
+ DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
+ DIV_F(none, "div_mmc_pre1", "div_mmc1",
+ DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
+ DIV_F(none, "div_mmc_pre2", "div_mmc2",
+ DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
+ DIV_F(none, "div_mmc_pre3", "div_mmc3",
+ DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
+ DIV_F(none, "div_spi_pre0", "div_spi0",
+ DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
+ DIV_F(none, "div_spi_pre1", "div_spi1",
+ DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
+ DIV_F(none, "div_spi_pre2", "div_spi2",
+ DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
+};
+
+struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
+ GATE(gscl0, "gscl0", "none", GATE_IP_GSCL, 0, 0, 0),
+ GATE(gscl1, "gscl1", "none", GATE_IP_GSCL, 1, 0, 0),
+ GATE(gscl2, "gscl2", "aclk266", GATE_IP_GSCL, 2, 0, 0),
+ GATE(gscl3, "gscl3", "aclk266", GATE_IP_GSCL, 3, 0, 0),
+ GATE(gscl_wa, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
+ GATE(gscl_wb, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
+ GATE(smmu_gscl0, "smmu_gscl0", "aclk266", GATE_IP_GSCL, 7, 0, 0),
+ GATE(smmu_gscl1, "smmu_gscl1", "aclk266", GATE_IP_GSCL, 8, 0, 0),
+ GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0),
+ GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0),
+ GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
+ GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
+ GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
+ GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
+ GATE(jpeg, "jpeg", "aclk166", GATE_IP_GEN, 2, 0, 0),
+ GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
+ GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
+ GATE(smmu_jpeg, "smmu_jpeg", "aclk166", GATE_IP_GEN, 7, 0, 0),
+ GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
+ GATE(pdma0, "pdma0", "aclk200", GATE_IP_FSYS, 1, 0, 0),
+ GATE(pdma1, "pdma1", "aclk200", GATE_IP_FSYS, 2, 0, 0),
+ GATE(sata, "sata", "aclk200", GATE_IP_FSYS, 6, 0, 0),
+ GATE(usbotg, "usbotg", "aclk200", GATE_IP_FSYS, 7, 0, 0),
+ GATE(mipi_hsi, "mipi_hsi", "aclk200", GATE_IP_FSYS, 8, 0, 0),
+ GATE(sdmmc0, "sdmmc0", "aclk200", GATE_IP_FSYS, 12, 0, 0),
+ GATE(sdmmc1, "sdmmc1", "aclk200", GATE_IP_FSYS, 13, 0, 0),
+ GATE(sdmmc2, "sdmmc2", "aclk200", GATE_IP_FSYS, 14, 0, 0),
+ GATE(sdmmc3, "sdmmc3", "aclk200", GATE_IP_FSYS, 15, 0, 0),
+ GATE(sromc, "sromc", "aclk200", GATE_IP_FSYS, 17, 0, 0),
+ GATE(usb2, "usb2", "aclk200", GATE_IP_FSYS, 18, 0, 0),
+ GATE(usb3, "usb3", "aclk200", GATE_IP_FSYS, 19, 0, 0),
+ GATE(sata_phyctrl, "sata_phyctrl", "aclk200", GATE_IP_FSYS, 24, 0, 0),
+ GATE(sata_phyi2c, "sata_phyi2c", "aclk200", GATE_IP_FSYS, 25, 0, 0),
+ GATE(uart0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
+ GATE(uart1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
+ GATE(uart2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
+ GATE(uart3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0),
+ GATE(uart4, "uart4", "aclk66", GATE_IP_PERIC, 4, 0, 0),
+ GATE(i2c0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0),
+ GATE(i2c1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0),
+ GATE(i2c2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0),
+ GATE(i2c3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0),
+ GATE(i2c4, "i2c4", "aclk66", GATE_IP_PERIC, 10, 0, 0),
+ GATE(i2c5, "i2c5", "aclk66", GATE_IP_PERIC, 11, 0, 0),
+ GATE(i2c6, "i2c6", "aclk66", GATE_IP_PERIC, 12, 0, 0),
+ GATE(i2c7, "i2c7", "aclk66", GATE_IP_PERIC, 13, 0, 0),
+ GATE(i2c_hdmi, "i2c_hdmi", "aclk66", GATE_IP_PERIC, 14, 0, 0),
+ GATE(adc, "adc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
+ GATE(spi0, "spi0", "aclk66", GATE_IP_PERIC, 16, 0, 0),
+ GATE(spi1, "spi1", "aclk66", GATE_IP_PERIC, 17, 0, 0),
+ GATE(spi2, "spi2", "aclk66", GATE_IP_PERIC, 18, 0, 0),
+ GATE(i2s1, "i2s1", "aclk66", GATE_IP_PERIC, 20, 0, 0),
+ GATE(i2s2, "i2s2", "aclk66", GATE_IP_PERIC, 21, 0, 0),
+ GATE(pcm1, "pcm1", "aclk66", GATE_IP_PERIC, 22, 0, 0),
+ GATE(pcm2, "pcm2", "aclk66", GATE_IP_PERIC, 23, 0, 0),
+ GATE(pwm, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
+ GATE(spdif, "spdif", "aclk66", GATE_IP_PERIC, 26, 0, 0),
+ GATE(ac97, "ac97", "aclk66", GATE_IP_PERIC, 27, 0, 0),
+ GATE(hsi2c0, "hsi2c0", "aclk66", GATE_IP_PERIC, 28, 0, 0),
+ GATE(hsi2c1, "hsi2c1", "aclk66", GATE_IP_PERIC, 29, 0, 0),
+ GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
+ GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
+ GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
+ GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0),
+ GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, 0, 0),
+ GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
+ GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
+ GATE(tzpc2, "tzpc2", "aclk66", GATE_IP_PERIS, 8, 0, 0),
+ GATE(tzpc3, "tzpc3", "aclk66", GATE_IP_PERIS, 9, 0, 0),
+ GATE(tzpc4, "tzpc4", "aclk66", GATE_IP_PERIS, 10, 0, 0),
+ GATE(tzpc5, "tzpc5", "aclk66", GATE_IP_PERIS, 11, 0, 0),
+ GATE(tzpc6, "tzpc6", "aclk66", GATE_IP_PERIS, 12, 0, 0),
+ GATE(tzpc7, "tzpc7", "aclk66", GATE_IP_PERIS, 13, 0, 0),
+ GATE(tzpc8, "tzpc8", "aclk66", GATE_IP_PERIS, 14, 0, 0),
+ GATE(tzpc9, "tzpc9", "aclk66", GATE_IP_PERIS, 15, 0, 0),
+ GATE(hdmi_cec, "hdmi_cec", "aclk66", GATE_IP_PERIS, 16, 0, 0),
+ GATE(mct, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
+ GATE(wdt, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
+ GATE(rtc, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
+ GATE(tmu, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),
+ GATE(cmu_top, "cmu_top", "aclk66",
+ GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(cmu_core, "cmu_core", "aclk66",
+ GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(cmu_mem, "cmu_mem", "aclk66",
+ GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
+ GATE(sclk_cam_bayer, "sclk_cam_bayer", "div_cam_bayer",
+ SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_cam0, "sclk_cam0", "div_cam0",
+ SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_cam1, "sclk_cam1", "div_cam1",
+ SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_gscl_wa, "sclk_gscl_wa", "div_gscl_wa",
+ SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_gscl_wb, "sclk_gscl_wb", "div_gscl_wb",
+ SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_fimd1, "sclk_fimd1", "div_fimd1",
+ SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_mipi1, "sclk_mipi1", "div_mipi1",
+ SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_dp, "sclk_dp", "div_dp",
+ SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi",
+ SRC_MASK_DISP1_0, 20, 0, 0),
+ GATE(sclk_audio0, "sclk_audio0", "div_audio0",
+ SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_mmc0, "sclk_mmc0", "div_mmc0",
+ SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_mmc1, "sclk_mmc1", "div_mmc1",
+ SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_mmc2, "sclk_mmc2", "div_mmc2",
+ SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_mmc3, "sclk_mmc3", "div_mmc3",
+ SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_sata, "sclk_sata", "div_sata",
+ SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_usb3, "sclk_usb3", "div_usb3",
+ SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_jpeg, "sclk_jpeg", "div_jpeg",
+ SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_uart0, "sclk_uart0", "div_uart0",
+ SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_uart1, "sclk_uart1", "div_uart1",
+ SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_uart2, "sclk_uart2", "div_uart2",
+ SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_uart3, "sclk_uart3", "div_uart3",
+ SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_pwm, "sclk_pwm", "div_pwm",
+ SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_audio1, "sclk_audio1", "div_audio1",
+ SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_audio2, "sclk_audio2", "div_audio2",
+ SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_spdif, "sclk_spdif", "mout_spdif",
+ SRC_MASK_PERIC1, 4, 0, 0),
+ GATE(sclk_spi0, "sclk_spi0", "div_spi_pre0",
+ SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_spi1, "sclk_spi1", "div_spi_pre1",
+ SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
+ GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2",
+ SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
+};
+
+static __initdata struct of_device_id ext_clk_match[] = {
+ { .compatible = "samsung,clock-xxti", .data = (void *)0, },
+ { },
+};
+
+/* register exynox5250 clocks */
+void __init exynos5250_clk_init(struct device_node *np)
+{
+ void __iomem *reg_base;
+ struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
+
+ if (np) {
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+ } else {
+ panic("%s: unable to determine soc\n", __func__);
+ }
+
+ samsung_clk_init(np, reg_base, nr_clks,
+ exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs));
+ samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
+ ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
+ ext_clk_match);
+
+ apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
+ reg_base + 0x100);
+ mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
+ reg_base + 0x4100);
+ bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
+ reg_base + 0x20110);
+ gpll = samsung_clk_register_pll35xx("fout_gpll", "fin_pll",
+ reg_base + 0x10150);
+ cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
+ reg_base + 0x10120);
+ epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
+ reg_base + 0x10130);
+ vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
+ reg_base + 0x10140);
+
+ samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
+ ARRAY_SIZE(exynos5250_fixed_rate_clks));
+ samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks,
+ ARRAY_SIZE(exynos5250_fixed_factor_clks));
+ samsung_clk_register_mux(exynos5250_mux_clks,
+ ARRAY_SIZE(exynos5250_mux_clks));
+ samsung_clk_register_div(exynos5250_div_clks,
+ ARRAY_SIZE(exynos5250_div_clks));
+ samsung_clk_register_gate(exynos5250_gate_clks,
+ ARRAY_SIZE(exynos5250_gate_clks));
+
+ pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
+ _get_rate("armclk"));
+}
+CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
--
1.7.5.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v6 05/16] clk: exynos5440: register clocks using common clock framework
2013-02-18 8:21 [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework Thomas Abraham
` (3 preceding siblings ...)
2013-02-18 8:21 ` [PATCH v6 04/16] clk: exynos5250: " Thomas Abraham
@ 2013-02-18 8:21 ` Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 07/16] ARM: Exynos: Initialize the clocks prior to timer initialization Thomas Abraham
` (10 subsequent siblings)
15 siblings, 0 replies; 37+ messages in thread
From: Thomas Abraham @ 2013-02-18 8:21 UTC (permalink / raw)
To: linux-arm-kernel
The Exynos5440 clocks are statically listed and registered using the Samsung
specific common clock helper functions.
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
.../devicetree/bindings/clock/exynos5440-clock.txt | 61 +++++++++
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5440.c | 139 ++++++++++++++++++++
3 files changed, 201 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5440-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5440.c
diff --git a/Documentation/devicetree/bindings/clock/exynos5440-clock.txt b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
new file mode 100644
index 0000000..9dbf0a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
@@ -0,0 +1,61 @@
+* Samsung Exynos5440 Clock Controller
+
+The Exynos5440 clock controller generates and supplies clock to various
+controllers within the Exynos5440 SoC.
+
+Required Properties:
+
+- comptible: should be "samsung,exynos5440-clock".
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume.
+
+
+ [Core Clocks]
+
+ Clock ID
+ ----------------------------
+
+ xtal 1
+ arm_clk 2
+
+ [Peripheral Clock Gates]
+
+ Clock ID
+ ----------------------------
+
+ spi_baud 16
+ pb0_250 17
+ pr0_250 18
+ pr1_250 19
+ b_250 20
+ b_125 21
+ b_200 22
+ sata 23
+ usb 24
+ gmac0 25
+ cs250 26
+ pb0_250_o 27
+ pr0_250_o 28
+ pr1_250_o 29
+ b_250_o 30
+ b_125_o 31
+ b_200_o 32
+ sata_o 33
+ usb_o 34
+ gmac0_o 35
+ cs250_o 36
+
+Example: An example of a clock controller node is listed below.
+
+ clock: clock-controller at 0x10010000 {
+ compatible = "samsung,exynos5440-clock";
+ reg = <0x160000 0x10000>;
+ #clock-cells = <1>;
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index f18fb07..b7c232e 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,3 +5,4 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
new file mode 100644
index 0000000..d588e93
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5440 SoC.
+*/
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <plat/cpu.h>
+#include "clk.h"
+#include "clk-pll.h"
+
+#define CLKEN_OV_VAL 0xf8
+#define CPU_CLK_STATUS 0xfc
+#define MISC_DOUT1 0x558
+
+/*
+ * Let each supported clock get a unique id. This id is used to lookup the clock
+ * for device tree based platforms.
+ */
+enum exynos5440_clks {
+ none, xtal, arm_clk,
+
+ spi_baud = 16, pb0_250, pr0_250, pr1_250, b_250, b_125, b_200, sata,
+ usb, gmac0, cs250, pb0_250_o, pr0_250_o, pr1_250_o, b_250_o, b_125_o,
+ b_200_o, sata_o, usb_o, gmac0_o, cs250_o,
+
+ nr_clks,
+};
+
+/* parent clock name list */
+PNAME(mout_armclk_p) = { "cplla", "cpllb" };
+PNAME(mout_spi_p) = { "div125", "div200" };
+
+/* fixed rate clocks generated outside the soc */
+struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
+ FRATE(none, "xtal", NULL, CLK_IS_ROOT, 0),
+};
+
+/* fixed rate clocks */
+struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = {
+ FRATE(none, "ppll", NULL, CLK_IS_ROOT, 1000000000),
+ FRATE(none, "usb_phy0", NULL, CLK_IS_ROOT, 60000000),
+ FRATE(none, "usb_phy1", NULL, CLK_IS_ROOT, 60000000),
+ FRATE(none, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000),
+ FRATE(none, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000),
+};
+
+/* fixed factor clocks */
+struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = {
+ FFACTOR(none, "div250", "ppll", 1, 4, 0),
+ FFACTOR(none, "div200", "ppll", 1, 5, 0),
+ FFACTOR(none, "div125", "div250", 1, 2, 0),
+};
+
+/* mux clocks */
+struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
+ MUX(none, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
+ MUX_A(arm_clk, "arm_clk", mout_armclk_p,
+ CPU_CLK_STATUS, 0, 1, "armclk"),
+};
+
+/* divider clocks */
+struct samsung_div_clock exynos5440_div_clks[] __initdata = {
+ DIV(spi_baud, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
+};
+
+/* gate clocks */
+struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
+ GATE(pb0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
+ GATE(pr0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
+ GATE(pr1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
+ GATE(b_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0),
+ GATE(b_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0),
+ GATE(b_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0),
+ GATE(sata, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0),
+ GATE(usb, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0),
+ GATE(gmac0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0),
+ GATE(cs250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0),
+ GATE(pb0_250_o, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0),
+ GATE(pr0_250_o, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0),
+ GATE(pr1_250_o, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0),
+ GATE(b_250_o, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0),
+ GATE(b_125_o, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0),
+ GATE(b_200_o, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0),
+ GATE(sata_o, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0),
+ GATE(usb_o, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0),
+ GATE(gmac0_o, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0),
+ GATE(cs250_o, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
+};
+
+static __initdata struct of_device_id ext_clk_match[] = {
+ { .compatible = "samsung,clock-xtal", .data = (void *)0, },
+ {},
+};
+
+/* register exynos5440 clocks */
+void __init exynos5440_clk_init(struct device_node *np)
+{
+ void __iomem *reg_base;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ pr_err("%s: failed to map clock controller registers,"
+ " aborting clock initialization\n", __func__);
+ return;
+ }
+
+ samsung_clk_init(np, reg_base, nr_clks, NULL, 0);
+ samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks,
+ ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
+
+ samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10);
+ samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10);
+
+ samsung_clk_register_fixed_rate(exynos5440_fixed_rate_clks,
+ ARRAY_SIZE(exynos5440_fixed_rate_clks));
+ samsung_clk_register_fixed_factor(exynos5440_fixed_factor_clks,
+ ARRAY_SIZE(exynos5440_fixed_factor_clks));
+ samsung_clk_register_mux(exynos5440_mux_clks,
+ ARRAY_SIZE(exynos5440_mux_clks));
+ samsung_clk_register_div(exynos5440_div_clks,
+ ARRAY_SIZE(exynos5440_div_clks));
+ samsung_clk_register_gate(exynos5440_gate_clks,
+ ARRAY_SIZE(exynos5440_gate_clks));
+
+ pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("armclk"));
+ pr_info("exynos5440 clock initialization complete\n");
+}
+CLK_OF_DECLARE(exynos5440_clk, "samsung,exynos5440-clock", exynos5440_clk_init);
--
1.7.5.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v6 07/16] ARM: Exynos: Initialize the clocks prior to timer initialization
2013-02-18 8:21 [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework Thomas Abraham
` (4 preceding siblings ...)
2013-02-18 8:21 ` [PATCH v6 05/16] clk: exynos5440: " Thomas Abraham
@ 2013-02-18 8:21 ` Thomas Abraham
2013-02-18 8:32 ` Kyungmin Park
2013-02-18 8:21 ` [PATCH v6 08/16] ARM: Exynos4: allow legacy board support to specify xxti and xusbxti clock speed Thomas Abraham
` (9 subsequent siblings)
15 siblings, 1 reply; 37+ messages in thread
From: Thomas Abraham @ 2013-02-18 8:21 UTC (permalink / raw)
To: linux-arm-kernel
Since the clock initialization should be completed prior to the mct timer
initialization, create a new function 'exynos_init_time' that first sets up
the clock and then invokes the timer initialization function. The 'init_time'
callback in the board files are updated to invoke this new wrapper function.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos/common.c | 16 ++++++++++++++++
arch/arm/mach-exynos/mach-armlex4210.c | 2 +-
arch/arm/mach-exynos/mach-exynos4-dt.c | 2 +-
arch/arm/mach-exynos/mach-exynos5-dt.c | 2 +-
arch/arm/mach-exynos/mach-nuri.c | 2 +-
arch/arm/mach-exynos/mach-origen.c | 2 +-
arch/arm/mach-exynos/mach-smdk4x12.c | 4 ++--
arch/arm/mach-exynos/mach-smdkv310.c | 4 ++--
arch/arm/mach-exynos/mach-universal_c210.c | 8 +++++++-
9 files changed, 32 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 8e4a25c..64585af 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -23,6 +23,8 @@
#include <linux/export.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
+#include <linux/clocksource.h>
+#include <linux/clk-provider.h>
#include <asm/proc-fns.h>
#include <asm/exception.h>
@@ -436,6 +438,20 @@ static void __init exynos5440_map_io(void)
iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
}
+void __init exynos_init_time(void)
+{
+ if (of_have_populated_dt()) {
+#ifdef CONFIG_OF
+ of_clk_init(NULL);
+ clocksource_of_init();
+#endif
+ } else {
+ /* todo: remove after migrating legacy E4 platforms to dt */
+ exynos4_clk_init(NULL);
+ mct_init();
+ }
+}
+
#define COMBINER_ENABLE_SET 0x0
#define COMBINER_ENABLE_CLEAR 0x4
#define COMBINER_INT_STATUS 0xC
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index e45b4b4..3518ac8 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -203,6 +203,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
.handle_irq = gic_handle_irq,
.init_machine = armlex4210_machine_init,
.init_late = exynos_init_late,
- .init_time = mct_init,
+ .init_time = exynos_init_time,
.restart = exynos4_restart,
MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 2c25f2c..6c5e068 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -127,7 +127,7 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
.init_early = exynos_firmware_init,
.init_machine = exynos4_dt_machine_init,
.init_late = exynos_init_late,
- .init_time = clocksource_of_init,
+ .init_time = exynos_init_time,
.dt_compat = exynos4_dt_compat,
.restart = exynos4_restart,
.reserve = exynos4_reserve,
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index b5f9549..dfe51ee 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -179,7 +179,7 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
.handle_irq = gic_handle_irq,
.init_machine = exynos5_dt_machine_init,
.init_late = exynos_init_late,
- .init_time = clocksource_of_init,
+ .init_time = exynos_init_time,
.dt_compat = exynos5_dt_compat,
.restart = exynos5_restart,
.reserve = exynos5_reserve,
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index c49ec9d..cdae74b 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -1381,7 +1381,7 @@ MACHINE_START(NURI, "NURI")
.handle_irq = gic_handle_irq,
.init_machine = nuri_machine_init,
.init_late = exynos_init_late,
- .init_time = mct_init,
+ .init_time = exynos_init_time,
.reserve = &nuri_reserve,
.restart = exynos4_restart,
MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 656967d..e9ab921 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -816,7 +816,7 @@ MACHINE_START(ORIGEN, "ORIGEN")
.handle_irq = gic_handle_irq,
.init_machine = origen_machine_init,
.init_late = exynos_init_late,
- .init_time = mct_init,
+ .init_time = exynos_init_time,
.reserve = &origen_reserve,
.restart = exynos4_restart,
MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index c56cc21..71422ad 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -377,7 +377,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
.map_io = smdk4x12_map_io,
.handle_irq = gic_handle_irq,
.init_machine = smdk4x12_machine_init,
- .init_time = mct_init,
+ .init_time = exynos_init_time,
.restart = exynos4_restart,
.reserve = &smdk4x12_reserve,
MACHINE_END
@@ -392,7 +392,7 @@ MACHINE_START(SMDK4412, "SMDK4412")
.handle_irq = gic_handle_irq,
.init_machine = smdk4x12_machine_init,
.init_late = exynos_init_late,
- .init_time = mct_init,
+ .init_time = exynos_init_time,
.restart = exynos4_restart,
.reserve = &smdk4x12_reserve,
MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 9d511f5..eb51c06 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -424,7 +424,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
.map_io = smdkv310_map_io,
.handle_irq = gic_handle_irq,
.init_machine = smdkv310_machine_init,
- .init_time = mct_init,
+ .init_time = exynos_init_time,
.reserve = &smdkv310_reserve,
.restart = exynos4_restart,
MACHINE_END
@@ -438,7 +438,7 @@ MACHINE_START(SMDKC210, "SMDKC210")
.handle_irq = gic_handle_irq,
.init_machine = smdkv310_machine_init,
.init_late = exynos_init_late,
- .init_time = mct_init,
+ .init_time = exynos_init_time,
.reserve = &smdkv310_reserve,
.restart = exynos4_restart,
MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 3998c81..53de074 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -1144,6 +1144,12 @@ static void __init universal_machine_init(void)
platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
}
+static void __init universal_init_time(void)
+{
+ exynos4_clk_init(NULL);
+ mct_init();
+}
+
MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
/* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
.atag_offset = 0x100,
@@ -1153,7 +1159,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
.handle_irq = gic_handle_irq,
.init_machine = universal_machine_init,
.init_late = exynos_init_late,
- .init_time = samsung_timer_init,
+ .init_time = universal_init_time,
.reserve = &universal_reserve,
.restart = exynos4_restart,
MACHINE_END
--
1.7.5.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v6 08/16] ARM: Exynos4: allow legacy board support to specify xxti and xusbxti clock speed
2013-02-18 8:21 [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework Thomas Abraham
` (5 preceding siblings ...)
2013-02-18 8:21 ` [PATCH v6 07/16] ARM: Exynos: Initialize the clocks prior to timer initialization Thomas Abraham
@ 2013-02-18 8:21 ` Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 09/16] ARM: Exynos: remove auxdata table from exynos4/5 dt machine file Thomas Abraham
` (8 subsequent siblings)
15 siblings, 0 replies; 37+ messages in thread
From: Thomas Abraham @ 2013-02-18 8:21 UTC (permalink / raw)
To: linux-arm-kernel
The clock speed of xxti and xusbxti clocks depends on the oscillator used on the
board to generate these clocks. For non-dt platforms, allow the board support
for those platforms to set the clock frequency of xxti and xusbxti clocks.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos/common.c | 3 +++
arch/arm/mach-exynos/common.h | 1 +
arch/arm/mach-exynos/mach-nuri.c | 2 ++
arch/arm/mach-exynos/mach-origen.c | 2 ++
arch/arm/mach-exynos/mach-smdkv310.c | 2 ++
arch/arm/mach-exynos/mach-universal_c210.c | 2 ++
6 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 64585af..974978b 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -68,6 +68,8 @@ static void exynos5440_map_io(void);
static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
static int exynos_init(void);
+unsigned long xxti_f = 0, xusbxti_f = 0;
+
static struct cpu_table cpu_ids[] __initdata = {
{
.idcode = EXYNOS4210_CPU_ID,
@@ -448,6 +450,7 @@ void __init exynos_init_time(void)
} else {
/* todo: remove after migrating legacy E4 platforms to dt */
exynos4_clk_init(NULL);
+ exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
mct_init();
}
}
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 2c3cdae..8d9ae73 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -16,6 +16,7 @@
extern void mct_init(void);
void exynos_init_time(void);
+extern unsigned long xxti_f, xusbxti_f;
struct map_desc;
void exynos_init_io(struct map_desc *mach_desc, int size);
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index cdae74b..abe36ec 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -1332,6 +1332,8 @@ static void __init nuri_map_io(void)
{
exynos_init_io(NULL, 0);
s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
+ xxti_f = 0;
+ xusbxti_f = 24000000;
}
static void __init nuri_reserve(void)
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index e9ab921..e7b36ca 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -756,6 +756,8 @@ static void __init origen_map_io(void)
{
exynos_init_io(NULL, 0);
s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
+ xxti_f = 0;
+ xusbxti_f = 24000000;
}
static void __init origen_power_init(void)
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index eb51c06..d146393 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -373,6 +373,8 @@ static void __init smdkv310_map_io(void)
{
exynos_init_io(NULL, 0);
s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
+ xxti_f = 12000000;
+ xusbxti_f = 24000000;
}
static void __init smdkv310_reserve(void)
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 53de074..8cc315e 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -1095,6 +1095,8 @@ static void __init universal_map_io(void)
exynos_init_io(NULL, 0);
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
+ xxti_f = 0;
+ xusbxti_f = 24000000;
}
static void s5p_tv_setup(void)
--
1.7.5.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v6 09/16] ARM: Exynos: remove auxdata table from exynos4/5 dt machine file
2013-02-18 8:21 [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework Thomas Abraham
` (6 preceding siblings ...)
2013-02-18 8:21 ` [PATCH v6 08/16] ARM: Exynos4: allow legacy board support to specify xxti and xusbxti clock speed Thomas Abraham
@ 2013-02-18 8:21 ` Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 10/16] clocksource: mct: use fin_pll clock as the tick clock source for mct Thomas Abraham
` (7 subsequent siblings)
15 siblings, 0 replies; 37+ messages in thread
From: Thomas Abraham @ 2013-02-18 8:21 UTC (permalink / raw)
To: linux-arm-kernel
With support for device tree based clock lookup now available, remove the
auxdata table from exynos4/5 dt-enabled machine file.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos/mach-exynos4-dt.c | 69 +----------------------
arch/arm/mach-exynos/mach-exynos5-dt.c | 98 +-------------------------------
2 files changed, 3 insertions(+), 164 deletions(-)
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 6c5e068..809c274 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -11,6 +11,7 @@
* published by the Free Software Foundation.
*/
+#include <linux/kernel.h>
#include <linux/of_platform.h>
#include <linux/of_fdt.h>
#include <linux/serial_core.h>
@@ -19,75 +20,10 @@
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
-#include <mach/map.h>
-
-#include <plat/cpu.h>
-#include <plat/regs-serial.h>
#include <plat/mfc.h>
#include "common.h"
-/*
- * The following lookup table is used to override device names when devices
- * are registered from device tree. This is temporarily added to enable
- * device tree support addition for the Exynos4 architecture.
- *
- * For drivers that require platform data to be provided from the machine
- * file, a platform data pointer can also be supplied along with the
- * devices names. Usually, the platform data elements that cannot be parsed
- * from the device tree by the drivers (example: function pointers) are
- * supplied. But it should be noted that this is a temporary mechanism and
- * at some point, the drivers should be capable of parsing all the platform
- * data from the device tree.
- */
-static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
- OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
- "exynos4210-uart.0", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
- "exynos4210-uart.1", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART2,
- "exynos4210-uart.2", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART3,
- "exynos4210-uart.3", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
- "exynos4-sdhci.0", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(1),
- "exynos4-sdhci.1", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(2),
- "exynos4-sdhci.2", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(3),
- "exynos4-sdhci.3", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
- "s3c2440-i2c.0", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(1),
- "s3c2440-i2c.1", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(2),
- "s3c2440-i2c.2", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(3),
- "s3c2440-i2c.3", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(4),
- "s3c2440-i2c.4", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(5),
- "s3c2440-i2c.5", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(6),
- "s3c2440-i2c.6", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(7),
- "s3c2440-i2c.7", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0,
- "exynos4210-spi.0", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1,
- "exynos4210-spi.1", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2,
- "exynos4210-spi.2", NULL),
- OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
- OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
- OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
- "exynos-tmu", NULL),
- OF_DEV_AUXDATA("samsung,mfc-v5", 0x13400000, "s5p-mfc", NULL),
- {},
-};
-
static void __init exynos4_dt_map_io(void)
{
exynos_init_io(NULL, 0);
@@ -95,8 +31,7 @@ static void __init exynos4_dt_map_io(void)
static void __init exynos4_dt_machine_init(void)
{
- of_platform_populate(NULL, of_default_bus_match_table,
- exynos4_auxdata_lookup, NULL);
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static char const *exynos4_dt_compat[] __initdata = {
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index dfe51ee..7027bb9 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -11,110 +11,19 @@
#include <linux/of_platform.h>
#include <linux/of_fdt.h>
-#include <linux/serial_core.h>
#include <linux/memblock.h>
#include <linux/io.h>
#include <linux/clocksource.h>
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
-#include <mach/map.h>
#include <mach/regs-pmu.h>
#include <plat/cpu.h>
-#include <plat/regs-serial.h>
#include <plat/mfc.h>
#include "common.h"
-/*
- * The following lookup table is used to override device names when devices
- * are registered from device tree. This is temporarily added to enable
- * device tree support addition for the EXYNOS5 architecture.
- *
- * For drivers that require platform data to be provided from the machine
- * file, a platform data pointer can also be supplied along with the
- * devices names. Usually, the platform data elements that cannot be parsed
- * from the device tree by the drivers (example: function pointers) are
- * supplied. But it should be noted that this is a temporary mechanism and
- * at some point, the drivers should be capable of parsing all the platform
- * data from the device tree.
- */
-static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
- OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
- "exynos4210-uart.0", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
- "exynos4210-uart.1", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
- "exynos4210-uart.2", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
- "exynos4210-uart.3", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
- "s3c2440-i2c.0", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
- "s3c2440-i2c.1", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
- "s3c2440-i2c.2", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
- "s3c2440-i2c.3", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
- "s3c2440-i2c.4", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
- "s3c2440-i2c.5", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
- "s3c2440-i2c.6", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
- "s3c2440-i2c.7", NULL),
- OF_DEV_AUXDATA("samsung,s3c2440-hdmiphy-i2c", EXYNOS5_PA_IIC(8),
- "s3c2440-hdmiphy-i2c", NULL),
- OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0,
- "dw_mmc.0", NULL),
- OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1,
- "dw_mmc.1", NULL),
- OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI2,
- "dw_mmc.2", NULL),
- OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI3,
- "dw_mmc.3", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
- "exynos4210-spi.0", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
- "exynos4210-spi.1", NULL),
- OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
- "exynos4210-spi.2", NULL),
- OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000,
- "exynos5-sata", NULL),
- OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x12170000,
- "exynos5-sata-phy", NULL),
- OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000,
- "exynos5-sata-phy-i2c", NULL),
- OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
- OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
- OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
- OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC0,
- "exynos-gsc.0", NULL),
- OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC1,
- "exynos-gsc.1", NULL),
- OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC2,
- "exynos-gsc.2", NULL),
- OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
- "exynos-gsc.3", NULL),
- OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
- "exynos5-hdmi", NULL),
- OF_DEV_AUXDATA("samsung,exynos5-mixer", 0x14450000,
- "exynos5-mixer", NULL),
- OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
- OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000,
- "exynos-tmu", NULL),
- OF_DEV_AUXDATA("samsung,exynos5-dp", 0x145B0000, "exynos-dp", NULL),
- {},
-};
-
-static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = {
- OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5440_PA_UART0,
- "exynos4210-uart.0", NULL),
- {},
-};
-
static void __init exynos5_dt_map_io(void)
{
exynos_init_io(NULL, 0);
@@ -144,12 +53,7 @@ static void __init exynos5_dt_machine_init(void)
}
}
- if (of_machine_is_compatible("samsung,exynos5250"))
- of_platform_populate(NULL, of_default_bus_match_table,
- exynos5250_auxdata_lookup, NULL);
- else if (of_machine_is_compatible("samsung,exynos5440"))
- of_platform_populate(NULL, of_default_bus_match_table,
- exynos5440_auxdata_lookup, NULL);
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static char const *exynos5_dt_compat[] __initdata = {
--
1.7.5.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v6 10/16] clocksource: mct: use fin_pll clock as the tick clock source for mct
2013-02-18 8:21 [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework Thomas Abraham
` (7 preceding siblings ...)
2013-02-18 8:21 ` [PATCH v6 09/16] ARM: Exynos: remove auxdata table from exynos4/5 dt machine file Thomas Abraham
@ 2013-02-18 8:21 ` Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 11/16] clocksource: mct: add support for mct clock setup Thomas Abraham
` (6 subsequent siblings)
15 siblings, 0 replies; 37+ messages in thread
From: Thomas Abraham @ 2013-02-18 8:21 UTC (permalink / raw)
To: linux-arm-kernel
With the migration of Exynos4 clocks to use common clock framework, the old
styled 'xtal' clock is not used anymore. Instead, the clock 'fin_pll' is used
as the tick clock for mct controller.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
drivers/clocksource/exynos_mct.c | 9 ++++++---
1 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index e067130..8f84c42 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -480,10 +480,13 @@ static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
static void __init exynos4_timer_resources(struct device_node *np)
{
- struct clk *mct_clk;
- mct_clk = clk_get(NULL, "xtal");
+ struct clk *tick_clk;
- clk_rate = clk_get_rate(mct_clk);
+ tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
+ clk_get(NULL, "fin_pll");
+ if (IS_ERR(tick_clk))
+ panic("%s: unable to determine tick clock rate\n", __func__);
+ clk_rate = clk_get_rate(tick_clk);
reg_base = np ? of_iomap(np, 0) : S5P_VA_SYSTIMER;
if (!reg_base)
--
1.7.5.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v6 11/16] clocksource: mct: add support for mct clock setup
2013-02-18 8:21 [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework Thomas Abraham
` (8 preceding siblings ...)
2013-02-18 8:21 ` [PATCH v6 10/16] clocksource: mct: use fin_pll clock as the tick clock source for mct Thomas Abraham
@ 2013-02-18 8:21 ` Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 12/16] ARM: dts: add Exynos4 and Exynos5 clock controller nodes Thomas Abraham
` (5 subsequent siblings)
15 siblings, 0 replies; 37+ messages in thread
From: Thomas Abraham @ 2013-02-18 8:21 UTC (permalink / raw)
To: linux-arm-kernel
Add support for mct clock lookup and setup to ensure that the mct clock
is has been turned on.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
drivers/clocksource/exynos_mct.c | 7 ++++++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 8f84c42..43e39b5 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -480,7 +480,7 @@ static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
static void __init exynos4_timer_resources(struct device_node *np)
{
- struct clk *tick_clk;
+ struct clk *mct_clk, *tick_clk;
tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
clk_get(NULL, "fin_pll");
@@ -488,6 +488,11 @@ static void __init exynos4_timer_resources(struct device_node *np)
panic("%s: unable to determine tick clock rate\n", __func__);
clk_rate = clk_get_rate(tick_clk);
+ mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
+ if (IS_ERR(mct_clk))
+ panic("%s: unable to retrieve mct clock instance\n", __func__);
+ clk_prepare_enable(mct_clk);
+
reg_base = np ? of_iomap(np, 0) : S5P_VA_SYSTIMER;
if (!reg_base)
panic("%s: unable to ioremap mct address space\n", __func__);
--
1.7.5.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v6 12/16] ARM: dts: add Exynos4 and Exynos5 clock controller nodes
2013-02-18 8:21 [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework Thomas Abraham
` (9 preceding siblings ...)
2013-02-18 8:21 ` [PATCH v6 11/16] clocksource: mct: add support for mct clock setup Thomas Abraham
@ 2013-02-18 8:21 ` Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 13/16] ARM: dts: add clock provider information for all controllers in Exynos4 SoCs Thomas Abraham
` (4 subsequent siblings)
15 siblings, 0 replies; 37+ messages in thread
From: Thomas Abraham @ 2013-02-18 8:21 UTC (permalink / raw)
To: linux-arm-kernel
Add clock controller nodes for Exynos4210, Exynos4x12, Exynos5250 and
Exynos5440 SoC.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/boot/dts/exynos4210.dtsi | 6 ++++++
arch/arm/boot/dts/exynos4x12.dtsi | 6 ++++++
arch/arm/boot/dts/exynos5250.dtsi | 6 ++++++
arch/arm/boot/dts/exynos5440.dtsi | 6 ++++++
4 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 0e16a34..6b25095 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -69,6 +69,12 @@
};
};
+ clock: clock-controller at 0x10030000 {
+ compatible = "samsung,exynos4210-clock";
+ reg = <0x10030000 0x20000>;
+ #clock-cells = <1>;
+ };
+
pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <&combiner>;
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 022a839..75be8f5 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -36,6 +36,12 @@
<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
};
+ clock: clock-controller at 0x10030000 {
+ compatible = "samsung,exynos4412-clock";
+ reg = <0x10030000 0x20000>;
+ #clock-cells = <1>;
+ };
+
pinctrl_0: pinctrl at 11400000 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11400000 0x1000>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 2bb558e..d3eae4e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -60,6 +60,12 @@
compatible = "samsung,exynos4210-pd";
reg = <0x10044040 0x20>;
};
+
+ clock: clock-controller at 0x10010000 {
+ compatible = "samsung,exynos5250-clock";
+ reg = <0x10010000 0x30000>;
+ #clock-cells = <1>;
+ };
gic:interrupt-controller at 10481000 {
compatible = "arm,cortex-a9-gic";
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 5c5a699..f5834d0 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -16,6 +16,12 @@
interrupt-parent = <&gic>;
+ clock: clock-controller at 0x160000 {
+ compatible = "samsung,exynos5440-clock";
+ reg = <0x160000 0x1000>;
+ #clock-cells = <1>;
+ };
+
gic:interrupt-controller at 2E0000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
--
1.7.5.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v6 13/16] ARM: dts: add clock provider information for all controllers in Exynos4 SoCs
2013-02-18 8:21 [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework Thomas Abraham
` (10 preceding siblings ...)
2013-02-18 8:21 ` [PATCH v6 12/16] ARM: dts: add Exynos4 and Exynos5 clock controller nodes Thomas Abraham
@ 2013-02-18 8:21 ` Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 14/16] ARM: dts: add clock provider information for all controllers in Exynos5250 SoC Thomas Abraham
` (3 subsequent siblings)
15 siblings, 0 replies; 37+ messages in thread
From: Thomas Abraham @ 2013-02-18 8:21 UTC (permalink / raw)
To: linux-arm-kernel
For all supported peripheral controllers on Exynos4 SoCs, add clock lookup
information.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/boot/dts/exynos4.dtsi | 50 +++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/exynos4210.dtsi | 2 +
arch/arm/boot/dts/exynos4412.dtsi | 2 +
3 files changed, 54 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 1a02189..621f331 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -91,6 +91,8 @@
compatible = "samsung,s3c2410-wdt";
reg = <0x10060000 0x100>;
interrupts = <0 43 0>;
+ clocks = <&clock 345>;
+ clock-names = "watchdog";
status = "disabled";
};
@@ -98,6 +100,8 @@
compatible = "samsung,s3c6410-rtc";
reg = <0x10070000 0x100>;
interrupts = <0 44 0>, <0 45 0>;
+ clocks = <&clock 346>;
+ clock-names = "rtc";
status = "disabled";
};
@@ -105,6 +109,8 @@
compatible = "samsung,s5pv210-keypad";
reg = <0x100A0000 0x100>;
interrupts = <0 109 0>;
+ clocks = <&clock 347>;
+ clock-names = "keypad";
status = "disabled";
};
@@ -112,6 +118,8 @@
compatible = "samsung,exynos4210-sdhci";
reg = <0x12510000 0x100>;
interrupts = <0 73 0>;
+ clocks = <&clock 297>, <&clock 145>;
+ clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
};
@@ -119,6 +127,8 @@
compatible = "samsung,exynos4210-sdhci";
reg = <0x12520000 0x100>;
interrupts = <0 74 0>;
+ clocks = <&clock 298>, <&clock 146>;
+ clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
};
@@ -126,6 +136,8 @@
compatible = "samsung,exynos4210-sdhci";
reg = <0x12530000 0x100>;
interrupts = <0 75 0>;
+ clocks = <&clock 299>, <&clock 147>;
+ clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
};
@@ -133,6 +145,8 @@
compatible = "samsung,exynos4210-sdhci";
reg = <0x12540000 0x100>;
interrupts = <0 76 0>;
+ clocks = <&clock 300>, <&clock 148>;
+ clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
};
@@ -148,6 +162,8 @@
compatible = "samsung,exynos4210-uart";
reg = <0x13800000 0x100>;
interrupts = <0 52 0>;
+ clocks = <&clock 312>, <&clock 151>;
+ clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
@@ -155,6 +171,8 @@
compatible = "samsung,exynos4210-uart";
reg = <0x13810000 0x100>;
interrupts = <0 53 0>;
+ clocks = <&clock 313>, <&clock 152>;
+ clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
@@ -162,6 +180,8 @@
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>;
interrupts = <0 54 0>;
+ clocks = <&clock 314>, <&clock 153>;
+ clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
@@ -169,6 +189,8 @@
compatible = "samsung,exynos4210-uart";
reg = <0x13830000 0x100>;
interrupts = <0 55 0>;
+ clocks = <&clock 315>, <&clock 154>;
+ clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
@@ -178,6 +200,8 @@
compatible = "samsung,s3c2440-i2c";
reg = <0x13860000 0x100>;
interrupts = <0 58 0>;
+ clocks = <&clock 317>;
+ clock-names = "i2c";
status = "disabled";
};
@@ -187,6 +211,8 @@
compatible = "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>;
interrupts = <0 59 0>;
+ clocks = <&clock 318>;
+ clock-names = "i2c";
status = "disabled";
};
@@ -196,6 +222,8 @@
compatible = "samsung,s3c2440-i2c";
reg = <0x13880000 0x100>;
interrupts = <0 60 0>;
+ clocks = <&clock 319>;
+ clock-names = "i2c";
status = "disabled";
};
@@ -205,6 +233,8 @@
compatible = "samsung,s3c2440-i2c";
reg = <0x13890000 0x100>;
interrupts = <0 61 0>;
+ clocks = <&clock 320>;
+ clock-names = "i2c";
status = "disabled";
};
@@ -214,6 +244,8 @@
compatible = "samsung,s3c2440-i2c";
reg = <0x138A0000 0x100>;
interrupts = <0 62 0>;
+ clocks = <&clock 321>;
+ clock-names = "i2c";
status = "disabled";
};
@@ -223,6 +255,8 @@
compatible = "samsung,s3c2440-i2c";
reg = <0x138B0000 0x100>;
interrupts = <0 63 0>;
+ clocks = <&clock 322>;
+ clock-names = "i2c";
status = "disabled";
};
@@ -232,6 +266,8 @@
compatible = "samsung,s3c2440-i2c";
reg = <0x138C0000 0x100>;
interrupts = <0 64 0>;
+ clocks = <&clock 323>;
+ clock-names = "i2c";
status = "disabled";
};
@@ -241,6 +277,8 @@
compatible = "samsung,s3c2440-i2c";
reg = <0x138D0000 0x100>;
interrupts = <0 65 0>;
+ clocks = <&clock 324>;
+ clock-names = "i2c";
status = "disabled";
};
@@ -252,6 +290,8 @@
rx-dma-channel = <&pdma0 6>; /* preliminary */
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 327>, <&clock 159>;
+ clock-names = "spi", "spi_busclk0";
status = "disabled";
};
@@ -263,6 +303,8 @@
rx-dma-channel = <&pdma1 6>; /* preliminary */
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 328>, <&clock 160>;
+ clock-names = "spi", "spi_busclk0";
status = "disabled";
};
@@ -274,6 +316,8 @@
rx-dma-channel = <&pdma0 8>; /* preliminary */
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 329>, <&clock 161>;
+ clock-names = "spi", "spi_busclk0";
status = "disabled";
};
@@ -288,18 +332,24 @@
compatible = "arm,pl330", "arm,primecell";
reg = <0x12680000 0x1000>;
interrupts = <0 35 0>;
+ clocks = <&clock 292>;
+ clock-names = "apb_pclk";
};
pdma1: pdma at 12690000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12690000 0x1000>;
interrupts = <0 36 0>;
+ clocks = <&clock 293>;
+ clock-names = "apb_pclk";
};
mdma1: mdma at 12850000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12850000 0x1000>;
interrupts = <0 34 0>;
+ clocks = <&clock 279>;
+ clock-names = "apb_pclk";
};
};
};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 6b25095..072d3b2 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -55,6 +55,8 @@
interrupt-parent = <&mct_map>;
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
<4 0>, <5 0>;
+ clocks = <&clock 3>, <&clock 344>;
+ clock-names = "fin_pll", "mct";
mct_map: mct-map {
#interrupt-cells = <2>;
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 821c9fd..1ecc28d 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -34,6 +34,8 @@
interrupt-parent = <&mct_map>;
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
<4 0>, <5 0>, <6 0>, <7 0>;
+ clocks = <&clock 3>, <&clock 344>;
+ clock-names = "fin_pll", "mct";
mct_map: mct-map {
#interrupt-cells = <2>;
--
1.7.5.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v6 14/16] ARM: dts: add clock provider information for all controllers in Exynos5250 SoC
2013-02-18 8:21 [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework Thomas Abraham
` (11 preceding siblings ...)
2013-02-18 8:21 ` [PATCH v6 13/16] ARM: dts: add clock provider information for all controllers in Exynos4 SoCs Thomas Abraham
@ 2013-02-18 8:21 ` Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 15/16] ARM: dts: add clock provider information for all controllers in Exynos5440 SoC Thomas Abraham
` (2 subsequent siblings)
15 siblings, 0 replies; 37+ messages in thread
From: Thomas Abraham @ 2013-02-18 8:21 UTC (permalink / raw)
To: linux-arm-kernel
For all supported peripheral controllers on Exynos5250, add clock lookup
information.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/boot/dts/exynos5250.dtsi | 72 +++++++++++++++++++++++++++++++++++++
1 files changed, 72 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index d3eae4e..d7a49a3 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -98,6 +98,8 @@
interrupt-parent = <&mct_map>;
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
<4 0>, <5 0>;
+ clocks = <&clock 1>, <&clock 335>;
+ clock-names = "fin_pll", "mct";
mct_map: mct-map {
#interrupt-cells = <2>;
@@ -122,6 +124,8 @@
compatible = "samsung,s3c2410-wdt";
reg = <0x101D0000 0x100>;
interrupts = <0 42 0>;
+ clocks = <&clock 336>;
+ clock-names = "watchdog";
};
mfc: codec at 11000000 {
@@ -135,42 +139,56 @@
compatible = "samsung,s3c6410-rtc";
reg = <0x101E0000 0x100>;
interrupts = <0 43 0>, <0 44 0>;
+ clocks = <&clock 337>;
+ clock-names = "rtc";
};
tmu at 10060000 {
compatible = "samsung,exynos5250-tmu";
reg = <0x10060000 0x100>;
interrupts = <0 65 0>;
+ clocks = <&clock 338>;
+ clock-names = "tmu_apbif";
};
serial at 12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
interrupts = <0 51 0>;
+ clocks = <&clock 289>, <&clock 146>;
+ clock-names = "uart", "clk_uart_baud0";
};
serial at 12C10000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C10000 0x100>;
interrupts = <0 52 0>;
+ clocks = <&clock 290>, <&clock 147>;
+ clock-names = "uart", "clk_uart_baud0";
};
serial at 12C20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C20000 0x100>;
interrupts = <0 53 0>;
+ clocks = <&clock 291>, <&clock 148>;
+ clock-names = "uart", "clk_uart_baud0";
};
serial at 12C30000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C30000 0x100>;
interrupts = <0 54 0>;
+ clocks = <&clock 292>, <&clock 149>;
+ clock-names = "uart", "clk_uart_baud0";
};
sata at 122F0000 {
compatible = "samsung,exynos5-sata-ahci";
reg = <0x122F0000 0x1ff>;
interrupts = <0 115 0>;
+ clocks = <&clock 277>, <&clock 143>;
+ clock-names = "sata", "sclk_sata";
};
sata-phy at 12170000 {
@@ -184,6 +202,8 @@
interrupts = <0 56 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 294>;
+ clock-names = "i2c";
};
i2c_1: i2c at 12C70000 {
@@ -192,6 +212,8 @@
interrupts = <0 57 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 295>;
+ clock-names = "i2c";
};
i2c_2: i2c at 12C80000 {
@@ -200,6 +222,8 @@
interrupts = <0 58 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 296>;
+ clock-names = "i2c";
};
i2c_3: i2c at 12C90000 {
@@ -208,6 +232,8 @@
interrupts = <0 59 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 297>;
+ clock-names = "i2c";
};
i2c_4: i2c at 12CA0000 {
@@ -216,6 +242,8 @@
interrupts = <0 60 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 298>;
+ clock-names = "i2c";
};
i2c_5: i2c at 12CB0000 {
@@ -224,6 +252,8 @@
interrupts = <0 61 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 299>;
+ clock-names = "i2c";
};
i2c_6: i2c at 12CC0000 {
@@ -232,6 +262,8 @@
interrupts = <0 62 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 300>;
+ clock-names = "i2c";
};
i2c_7: i2c at 12CD0000 {
@@ -240,6 +272,8 @@
interrupts = <0 63 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 301>;
+ clock-names = "i2c";
};
i2c_8: i2c at 12CE0000 {
@@ -248,6 +282,8 @@
interrupts = <0 64 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 302>;
+ clock-names = "i2c";
};
i2c at 121D0000 {
@@ -255,6 +291,8 @@
reg = <0x121D0000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 288>;
+ clock-names = "i2c";
};
spi_0: spi at 12d20000 {
@@ -265,6 +303,8 @@
rx-dma-channel = <&pdma0 4>; /* preliminary */
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 304>, <&clock 154>;
+ clock-names = "spi", "spi_busclk0";
};
spi_1: spi at 12d30000 {
@@ -275,6 +315,8 @@
rx-dma-channel = <&pdma1 4>; /* preliminary */
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 305>, <&clock 155>;
+ clock-names = "spi", "spi_busclk0";
};
spi_2: spi at 12d40000 {
@@ -285,6 +327,8 @@
rx-dma-channel = <&pdma0 6>; /* preliminary */
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 306>, <&clock 156>;
+ clock-names = "spi", "spi_busclk0";
};
dwmmc_0: dwmmc0 at 12200000 {
@@ -293,6 +337,8 @@
interrupts = <0 75 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 280>, <&clock 139>;
+ clock-names = "biu", "ciu";
};
dwmmc_1: dwmmc1 at 12210000 {
@@ -301,6 +347,8 @@
interrupts = <0 76 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 281>, <&clock 140>;
+ clock-names = "biu", "ciu";
};
dwmmc_2: dwmmc2 at 12220000 {
@@ -309,6 +357,8 @@
interrupts = <0 77 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 282>, <&clock 141>;
+ clock-names = "biu", "ciu";
};
dwmmc_3: dwmmc3 at 12230000 {
@@ -317,6 +367,8 @@
interrupts = <0 78 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 283>, <&clock 142>;
+ clock-names = "biu", "ciu";
};
usb at 12110000 {
@@ -342,24 +394,32 @@
compatible = "arm,pl330", "arm,primecell";
reg = <0x121A0000 0x1000>;
interrupts = <0 34 0>;
+ clocks = <&clock 275>;
+ clock-names = "apb_pclk";
};
pdma1: pdma at 121B0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121B0000 0x1000>;
interrupts = <0 35 0>;
+ clocks = <&clock 276>;
+ clock-names = "apb_pclk";
};
mdma0: mdma at 10800000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10800000 0x1000>;
interrupts = <0 33 0>;
+ clocks = <&clock 271>;
+ clock-names = "apb_pclk";
};
mdma1: mdma at 11C10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x11C10000 0x1000>;
interrupts = <0 124 0>;
+ clocks = <&clock 271>;
+ clock-names = "apb_pclk";
};
};
@@ -616,6 +676,8 @@
reg = <0x13e00000 0x1000>;
interrupts = <0 85 0>;
samsung,power-domain = <&pd_gsc>;
+ clocks = <&clock 256>;
+ clock-names = "gscl";
};
gsc_1: gsc at 0x13e10000 {
@@ -623,6 +685,8 @@
reg = <0x13e10000 0x1000>;
interrupts = <0 86 0>;
samsung,power-domain = <&pd_gsc>;
+ clocks = <&clock 257>;
+ clock-names = "gscl";
};
gsc_2: gsc at 0x13e20000 {
@@ -630,6 +694,8 @@
reg = <0x13e20000 0x1000>;
interrupts = <0 87 0>;
samsung,power-domain = <&pd_gsc>;
+ clocks = <&clock 258>;
+ clock-names = "gscl";
};
gsc_3: gsc at 0x13e30000 {
@@ -637,12 +703,18 @@
reg = <0x13e30000 0x1000>;
interrupts = <0 88 0>;
samsung,power-domain = <&pd_gsc>;
+ clocks = <&clock 259>;
+ clock-names = "gscl";
};
hdmi {
compatible = "samsung,exynos5-hdmi";
reg = <0x14530000 0x70000>;
interrupts = <0 95 0>;
+ clocks = <&clock 333>, <&clock 136>, <&clock 137>,
+ <&clock 333>, <&clock 333>;
+ clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
+ "sclk_hdmiphy", "hdmiphy";
};
mixer: mixer {
--
1.7.5.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v6 15/16] ARM: dts: add clock provider information for all controllers in Exynos5440 SoC
2013-02-18 8:21 [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework Thomas Abraham
` (12 preceding siblings ...)
2013-02-18 8:21 ` [PATCH v6 14/16] ARM: dts: add clock provider information for all controllers in Exynos5250 SoC Thomas Abraham
@ 2013-02-18 8:21 ` Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 16/16] ARM: dts: add board specific fixed rate clock nodes for Exynos based platforms Thomas Abraham
2013-03-19 18:49 ` [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework Mike Turquette
15 siblings, 0 replies; 37+ messages in thread
From: Thomas Abraham @ 2013-02-18 8:21 UTC (permalink / raw)
To: linux-arm-kernel
For all supported peripheral controllers on Exynos5440, add clock lookup
information.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/boot/dts/exynos5440.dtsi | 18 ++++++++++++++++++
1 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index f5834d0..a54c4ab 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -65,12 +65,16 @@
compatible = "samsung,exynos4210-uart";
reg = <0xB0000 0x1000>;
interrupts = <0 2 0>;
+ clocks = <&clock 21>, <&clock 21>;
+ clock-names = "uart", "clk_uart_baud0";
};
serial at C0000 {
compatible = "samsung,exynos4210-uart";
reg = <0xC0000 0x1000>;
interrupts = <0 3 0>;
+ clocks = <&clock 21>, <&clock 21>;
+ clock-names = "uart", "clk_uart_baud0";
};
spi {
@@ -81,6 +85,8 @@
rx-dma-channel = <&pdma0 4>; /* preliminary */
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 21>, <&clock 16>;
+ clock-names = "spi", "spi_busclk0";
};
pinctrl {
@@ -113,6 +119,8 @@
interrupts = <0 5 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 21>;
+ clock-names = "i2c";
};
i2c at 100000 {
@@ -121,12 +129,16 @@
interrupts = <0 6 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clock 21>;
+ clock-names = "i2c";
};
watchdog {
compatible = "samsung,s3c2410-wdt";
reg = <0x110000 0x1000>;
interrupts = <0 1 0>;
+ clocks = <&clock 21>;
+ clock-names = "watchdog";
};
amba {
@@ -140,12 +152,16 @@
compatible = "arm,pl330", "arm,primecell";
reg = <0x120000 0x1000>;
interrupts = <0 34 0>;
+ clocks = <&clock 21>;
+ clock-names = "apb_pclk";
};
pdma1: pdma at 121B0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121000 0x1000>;
interrupts = <0 35 0>;
+ clocks = <&clock 21>;
+ clock-names = "apb_pclk";
};
};
@@ -153,5 +169,7 @@
compatible = "samsung,s3c6410-rtc";
reg = <0x130000 0x1000>;
interrupts = <0 17 0>, <0 16 0>;
+ clocks = <&clock 21>;
+ clock-names = "rtc";
};
};
--
1.7.5.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v6 16/16] ARM: dts: add board specific fixed rate clock nodes for Exynos based platforms
2013-02-18 8:21 [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework Thomas Abraham
` (13 preceding siblings ...)
2013-02-18 8:21 ` [PATCH v6 15/16] ARM: dts: add clock provider information for all controllers in Exynos5440 SoC Thomas Abraham
@ 2013-02-18 8:21 ` Thomas Abraham
2013-02-19 5:11 ` Olof Johansson
2013-03-19 18:49 ` [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework Mike Turquette
15 siblings, 1 reply; 37+ messages in thread
From: Thomas Abraham @ 2013-02-18 8:21 UTC (permalink / raw)
To: linux-arm-kernel
The clock frequency of xxti and xusbxti clocks is dependent on the frequency of the
on-board oscillator that is used to generate these clocks. So allow the frequency
of these clocks to be specfied from device tree.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/boot/dts/exynos4210-origen.dts | 12 ++++++++++++
arch/arm/boot/dts/exynos4210-smdkv310.dts | 12 ++++++++++++
arch/arm/boot/dts/exynos4210-trats.dts | 12 ++++++++++++
arch/arm/boot/dts/exynos4412-odroidx.dts | 12 ++++++++++++
arch/arm/boot/dts/exynos4412-origen.dts | 12 ++++++++++++
arch/arm/boot/dts/exynos4412-smdk4412.dts | 12 ++++++++++++
arch/arm/boot/dts/exynos5250-arndale.dts | 7 +++++++
arch/arm/boot/dts/exynos5250-smdk5250.dts | 7 +++++++
arch/arm/boot/dts/exynos5250-snow.dts | 7 +++++++
arch/arm/boot/dts/exynos5440-ssdk5440.dts | 7 +++++++
10 files changed, 100 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 052606b..1b30bc8 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -127,4 +127,16 @@
linux,default-trigger = "heartbeat";
};
};
+
+ fixed-rate-clocks {
+ xxti {
+ compatible = "samsung,clock-xxti";
+ clock-frequency = <0>;
+ };
+
+ xusbxti {
+ compatible = "samsung,clock-xusbxti";
+ clock-frequency = <24000000>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 2b1e03a..f52c86e 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -195,4 +195,16 @@
};
};
};
+
+ fixed-rate-clocks {
+ xxti {
+ compatible = "samsung,clock-xxti";
+ clock-frequency = <12000000>;
+ };
+
+ xusbxti {
+ compatible = "samsung,clock-xusbxti";
+ clock-frequency = <24000000>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index c346b64..9a14484 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -289,4 +289,16 @@
};
};
};
+
+ fixed-rate-clocks {
+ xxti {
+ compatible = "samsung,clock-xxti";
+ clock-frequency = <0>;
+ };
+
+ xusbxti {
+ compatible = "samsung,clock-xusbxti";
+ clock-frequency = <24000000>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 0084d95..15dc0a3 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -94,4 +94,16 @@
serial at 13830000 {
status = "okay";
};
+
+ fixed-rate-clocks {
+ xxti {
+ compatible = "samsung,clock-xxti";
+ clock-frequency = <0>;
+ };
+
+ xusbxti {
+ compatible = "samsung,clock-xusbxti";
+ clock-frequency = <24000000>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index 31e14c4..a944611 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -415,4 +415,16 @@
};
};
};
+
+ fixed-rate-clocks {
+ xxti {
+ compatible = "samsung,clock-xxti";
+ clock-frequency = <0>;
+ };
+
+ xusbxti {
+ compatible = "samsung,clock-xusbxti";
+ clock-frequency = <24000000>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index 6ae4276..874beea 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -55,4 +55,16 @@
serial at 13830000 {
status = "okay";
};
+
+ fixed-rate-clocks {
+ xxti {
+ compatible = "samsung,clock-xxti";
+ clock-frequency = <0>;
+ };
+
+ xusbxti {
+ compatible = "samsung,clock-xusbxti";
+ clock-frequency = <24000000>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 63572f9..5de019c 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -119,4 +119,11 @@
spi_2: spi at 12d40000 {
status = "disabled";
};
+
+ fixed-rate-clocks {
+ xxti {
+ compatible = "samsung,clock-xxti";
+ clock-frequency = <24000000>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 1391c31..f77bf3a 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -217,4 +217,11 @@
samsung,link-rate = <0x0a>;
samsung,lane-count = <4>;
};
+
+ fixed-rate-clocks {
+ xxti {
+ compatible = "samsung,clock-xxti";
+ clock-frequency = <24000000>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 47b6b84..babd9f9 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -44,4 +44,11 @@
usb at 12110000 {
samsung,vbus-gpio = <&gpx1 1 1 3 3>;
};
+
+ fixed-rate-clocks {
+ xxti {
+ compatible = "samsung,clock-xxti";
+ clock-frequency = <24000000>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index ee60c57..a21eb4c 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -27,4 +27,11 @@
spi {
status = "disabled";
};
+
+ fixed-rate-clocks {
+ xtal {
+ compatible = "samsung,clock-xtal";
+ clock-frequency = <50000000>;
+ };
+ };
};
--
1.7.5.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v6 07/16] ARM: Exynos: Initialize the clocks prior to timer initialization
2013-02-18 8:21 ` [PATCH v6 07/16] ARM: Exynos: Initialize the clocks prior to timer initialization Thomas Abraham
@ 2013-02-18 8:32 ` Kyungmin Park
0 siblings, 0 replies; 37+ messages in thread
From: Kyungmin Park @ 2013-02-18 8:32 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Feb 18, 2013 at 5:21 PM, Thomas Abraham
<thomas.abraham@linaro.org> wrote:
> Since the clock initialization should be completed prior to the mct timer
> initialization, create a new function 'exynos_init_time' that first sets up
> the clock and then invokes the timer initialization function. The 'init_time'
> callback in the board files are updated to invoke this new wrapper function.
>
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> ---
> arch/arm/mach-exynos/common.c | 16 ++++++++++++++++
> arch/arm/mach-exynos/mach-armlex4210.c | 2 +-
> arch/arm/mach-exynos/mach-exynos4-dt.c | 2 +-
> arch/arm/mach-exynos/mach-exynos5-dt.c | 2 +-
> arch/arm/mach-exynos/mach-nuri.c | 2 +-
> arch/arm/mach-exynos/mach-origen.c | 2 +-
> arch/arm/mach-exynos/mach-smdk4x12.c | 4 ++--
> arch/arm/mach-exynos/mach-smdkv310.c | 4 ++--
> arch/arm/mach-exynos/mach-universal_c210.c | 8 +++++++-
> 9 files changed, 32 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index 8e4a25c..64585af 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -23,6 +23,8 @@
> #include <linux/export.h>
> #include <linux/irqdomain.h>
> #include <linux/of_address.h>
> +#include <linux/clocksource.h>
> +#include <linux/clk-provider.h>
>
> #include <asm/proc-fns.h>
> #include <asm/exception.h>
> @@ -436,6 +438,20 @@ static void __init exynos5440_map_io(void)
> iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
> }
>
> +void __init exynos_init_time(void)
> +{
> + if (of_have_populated_dt()) {
> +#ifdef CONFIG_OF
> + of_clk_init(NULL);
> + clocksource_of_init();
> +#endif
> + } else {
> + /* todo: remove after migrating legacy E4 platforms to dt */
> + exynos4_clk_init(NULL);
> + mct_init();
> + }
> +}
> +
> #define COMBINER_ENABLE_SET 0x0
> #define COMBINER_ENABLE_CLEAR 0x4
> #define COMBINER_INT_STATUS 0xC
> diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
> index e45b4b4..3518ac8 100644
> --- a/arch/arm/mach-exynos/mach-armlex4210.c
> +++ b/arch/arm/mach-exynos/mach-armlex4210.c
> @@ -203,6 +203,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
> .handle_irq = gic_handle_irq,
> .init_machine = armlex4210_machine_init,
> .init_late = exynos_init_late,
> - .init_time = mct_init,
> + .init_time = exynos_init_time,
> .restart = exynos4_restart,
> MACHINE_END
> diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
> index 2c25f2c..6c5e068 100644
> --- a/arch/arm/mach-exynos/mach-exynos4-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
> @@ -127,7 +127,7 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
> .init_early = exynos_firmware_init,
> .init_machine = exynos4_dt_machine_init,
> .init_late = exynos_init_late,
> - .init_time = clocksource_of_init,
> + .init_time = exynos_init_time,
> .dt_compat = exynos4_dt_compat,
> .restart = exynos4_restart,
> .reserve = exynos4_reserve,
> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
> index b5f9549..dfe51ee 100644
> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> @@ -179,7 +179,7 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
> .handle_irq = gic_handle_irq,
> .init_machine = exynos5_dt_machine_init,
> .init_late = exynos_init_late,
> - .init_time = clocksource_of_init,
> + .init_time = exynos_init_time,
> .dt_compat = exynos5_dt_compat,
> .restart = exynos5_restart,
> .reserve = exynos5_reserve,
> diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
> index c49ec9d..cdae74b 100644
> --- a/arch/arm/mach-exynos/mach-nuri.c
> +++ b/arch/arm/mach-exynos/mach-nuri.c
> @@ -1381,7 +1381,7 @@ MACHINE_START(NURI, "NURI")
> .handle_irq = gic_handle_irq,
> .init_machine = nuri_machine_init,
> .init_late = exynos_init_late,
> - .init_time = mct_init,
> + .init_time = exynos_init_time,
> .reserve = &nuri_reserve,
> .restart = exynos4_restart,
> MACHINE_END
> diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
> index 656967d..e9ab921 100644
> --- a/arch/arm/mach-exynos/mach-origen.c
> +++ b/arch/arm/mach-exynos/mach-origen.c
> @@ -816,7 +816,7 @@ MACHINE_START(ORIGEN, "ORIGEN")
> .handle_irq = gic_handle_irq,
> .init_machine = origen_machine_init,
> .init_late = exynos_init_late,
> - .init_time = mct_init,
> + .init_time = exynos_init_time,
> .reserve = &origen_reserve,
> .restart = exynos4_restart,
> MACHINE_END
> diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
> index c56cc21..71422ad 100644
> --- a/arch/arm/mach-exynos/mach-smdk4x12.c
> +++ b/arch/arm/mach-exynos/mach-smdk4x12.c
> @@ -377,7 +377,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
> .map_io = smdk4x12_map_io,
> .handle_irq = gic_handle_irq,
> .init_machine = smdk4x12_machine_init,
> - .init_time = mct_init,
> + .init_time = exynos_init_time,
> .restart = exynos4_restart,
> .reserve = &smdk4x12_reserve,
> MACHINE_END
> @@ -392,7 +392,7 @@ MACHINE_START(SMDK4412, "SMDK4412")
> .handle_irq = gic_handle_irq,
> .init_machine = smdk4x12_machine_init,
> .init_late = exynos_init_late,
> - .init_time = mct_init,
> + .init_time = exynos_init_time,
> .restart = exynos4_restart,
> .reserve = &smdk4x12_reserve,
> MACHINE_END
> diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
> index 9d511f5..eb51c06 100644
> --- a/arch/arm/mach-exynos/mach-smdkv310.c
> +++ b/arch/arm/mach-exynos/mach-smdkv310.c
> @@ -424,7 +424,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
> .map_io = smdkv310_map_io,
> .handle_irq = gic_handle_irq,
> .init_machine = smdkv310_machine_init,
> - .init_time = mct_init,
> + .init_time = exynos_init_time,
> .reserve = &smdkv310_reserve,
> .restart = exynos4_restart,
> MACHINE_END
> @@ -438,7 +438,7 @@ MACHINE_START(SMDKC210, "SMDKC210")
> .handle_irq = gic_handle_irq,
> .init_machine = smdkv310_machine_init,
> .init_late = exynos_init_late,
> - .init_time = mct_init,
> + .init_time = exynos_init_time,
> .reserve = &smdkv310_reserve,
> .restart = exynos4_restart,
> MACHINE_END
> diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
> index 3998c81..53de074 100644
> --- a/arch/arm/mach-exynos/mach-universal_c210.c
> +++ b/arch/arm/mach-exynos/mach-universal_c210.c
> @@ -1144,6 +1144,12 @@ static void __init universal_machine_init(void)
> platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
> }
>
> +static void __init universal_init_time(void)
> +{
> + exynos4_clk_init(NULL);
> + mct_init();
No, It's not support MCT timer at universal board, please don't modify
universal board at this time.
Others are okay.
Thank you,
Kyungmin Park
> +}
> +
> MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
> /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
> .atag_offset = 0x100,
> @@ -1153,7 +1159,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
> .handle_irq = gic_handle_irq,
> .init_machine = universal_machine_init,
> .init_late = exynos_init_late,
> - .init_time = samsung_timer_init,
> + .init_time = universal_init_time,
> .reserve = &universal_reserve,
> .restart = exynos4_restart,
> MACHINE_END
> --
> 1.7.5.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v6 16/16] ARM: dts: add board specific fixed rate clock nodes for Exynos based platforms
2013-02-18 8:21 ` [PATCH v6 16/16] ARM: dts: add board specific fixed rate clock nodes for Exynos based platforms Thomas Abraham
@ 2013-02-19 5:11 ` Olof Johansson
0 siblings, 0 replies; 37+ messages in thread
From: Olof Johansson @ 2013-02-19 5:11 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Mon, Feb 18, 2013 at 12:21 AM, Thomas Abraham
<thomas.abraham@linaro.org> wrote:
> The clock frequency of xxti and xusbxti clocks is dependent on the frequency of the
> on-board oscillator that is used to generate these clocks. So allow the frequency
> of these clocks to be specfied from device tree.
>
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> ---
> arch/arm/boot/dts/exynos4210-origen.dts | 12 ++++++++++++
> arch/arm/boot/dts/exynos4210-smdkv310.dts | 12 ++++++++++++
> arch/arm/boot/dts/exynos4210-trats.dts | 12 ++++++++++++
> arch/arm/boot/dts/exynos4412-odroidx.dts | 12 ++++++++++++
> arch/arm/boot/dts/exynos4412-origen.dts | 12 ++++++++++++
> arch/arm/boot/dts/exynos4412-smdk4412.dts | 12 ++++++++++++
> arch/arm/boot/dts/exynos5250-arndale.dts | 7 +++++++
> arch/arm/boot/dts/exynos5250-smdk5250.dts | 7 +++++++
> arch/arm/boot/dts/exynos5250-snow.dts | 7 +++++++
> arch/arm/boot/dts/exynos5440-ssdk5440.dts | 7 +++++++
> 10 files changed, 100 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
> index 052606b..1b30bc8 100644
> --- a/arch/arm/boot/dts/exynos4210-origen.dts
> +++ b/arch/arm/boot/dts/exynos4210-origen.dts
> @@ -127,4 +127,16 @@
> linux,default-trigger = "heartbeat";
> };
> };
> +
> + fixed-rate-clocks {
> + xxti {
> + compatible = "samsung,clock-xxti";
> + clock-frequency = <0>;
> + };
> +
> + xusbxti {
> + compatible = "samsung,clock-xusbxti";
> + clock-frequency = <24000000>;
> + };
> + };
Looks like xxti = 0 and xusbxti = 24MHz is the common frequencies on
nearly all boards. It probably makes sense to add that to the defaults
in dtsi, and override on the boards where it isn't the case. Saves
some boilerplate code in the .dts files.
-Olof
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v6 01/16] clk: samsung: add common clock framework helper functions for Samsung platforms
2013-02-18 8:21 ` [PATCH v6 01/16] clk: samsung: add common clock framework helper functions for Samsung platforms Thomas Abraham
@ 2013-03-03 1:08 ` Heiko Stübner
2013-03-03 11:17 ` Sylwester Nawrocki
0 siblings, 1 reply; 37+ messages in thread
From: Heiko Stübner @ 2013-03-03 1:08 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Am Montag, 18. Februar 2013, 09:21:11 schrieb Thomas Abraham:
> All Samsung platforms include different types of clock including
> fixed-rate, mux, divider and gate clock types. There are typically
> hundreds of such clocks on each of the Samsung platforms. To enable
> Samsung platforms to register these clocks using the common clock
> framework, a bunch of utility functions are introduced here which simplify
> the clock registration process. The clocks are usually statically
> instantiated and registered with common clock framework.
>
> Cc: Mike Turquette <mturquette@linaro.org>
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Reviewed-by: Tomasz Figa <t.figa@samsung.com>
> Tested-by: Tomasz Figa <t.figa@samsung.com>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
I'm playing around with this on my s3c2416 platform and it works like a charm
for the most part - and the system already comes sort of up again :-) .
So,
Tested-by: Heiko Stuebner <heiko@sntech.de>
But is there an easy way to define more than one alias? On the s3c2416 for
example the hsmmc hclk is the "hsmmc" io-clock, as well as the source for the
"mmc_busclk.0". Same for the "uart" pclk, that is also a baud clock source.
Thanks
Heiko
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v6 01/16] clk: samsung: add common clock framework helper functions for Samsung platforms
2013-03-03 1:08 ` Heiko Stübner
@ 2013-03-03 11:17 ` Sylwester Nawrocki
2013-03-03 11:45 ` Tomasz Figa
2013-03-03 11:59 ` Sylwester Nawrocki
0 siblings, 2 replies; 37+ messages in thread
From: Sylwester Nawrocki @ 2013-03-03 11:17 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On 03/03/2013 02:08 AM, Heiko St?bner wrote:
> But is there an easy way to define more than one alias? On the s3c2416 for
> example the hsmmc hclk is the "hsmmc" io-clock, as well as the source for the
> "mmc_busclk.0". Same for the "uart" pclk, that is also a baud clock source.
This driver currently provides for only one additional clkdev lookup entry
per a platform clock. I pointed out this desing issue in the early version
of the patch set. It's because a machine clock definition is coupled with
a clock consumer definition. And IMO various samsung_clock_register_*
functions should not have clk_register_clkdev() inside them. I.e. first
step could be registering all machine clocks and in the second one clkdev
lookup entries could be created. This is how most (all?) existing SoC
clock drivers are working.
But those multiple aliases are important only for machines with device
tree support, aren't they ?
I hope this patch series gets merged early to linux-next in the 3.10
cycle so the multiple accumulated fixup patches for this clock driver
can be merged as well and issues like that you pointed out can be
resolved with incremental patches.
Regards,
Sylwester
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v6 01/16] clk: samsung: add common clock framework helper functions for Samsung platforms
2013-03-03 11:17 ` Sylwester Nawrocki
@ 2013-03-03 11:45 ` Tomasz Figa
2013-03-03 12:08 ` Heiko Stübner
` (2 more replies)
2013-03-03 11:59 ` Sylwester Nawrocki
1 sibling, 3 replies; 37+ messages in thread
From: Tomasz Figa @ 2013-03-03 11:45 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Sunday 03 of March 2013 12:17:29 Sylwester Nawrocki wrote:
> Hi,
>
> On 03/03/2013 02:08 AM, Heiko St?bner wrote:
> > But is there an easy way to define more than one alias? On the s3c2416
> > for example the hsmmc hclk is the "hsmmc" io-clock, as well as the
> > source for the "mmc_busclk.0". Same for the "uart" pclk, that is also
> > a baud clock source.
> This driver currently provides for only one additional clkdev lookup
> entry per a platform clock. I pointed out this desing issue in the
> early version of the patch set. It's because a machine clock definition
> is coupled with a clock consumer definition. And IMO various
> samsung_clock_register_* functions should not have
> clk_register_clkdev() inside them. I.e. first step could be registering
> all machine clocks and in the second one clkdev lookup entries could be
> created. This is how most (all?) existing SoC clock drivers are
> working.
>
> But those multiple aliases are important only for machines with device
> tree support, aren't they ?
I suppose you meant _without_ device tree support, right?
> I hope this patch series gets merged early to linux-next in the 3.10
> cycle so the multiple accumulated fixup patches for this clock driver
> can be merged as well and issues like that you pointed out can be
> resolved with incremental patches.
Yes, I hope so too.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v6 01/16] clk: samsung: add common clock framework helper functions for Samsung platforms
2013-03-03 11:17 ` Sylwester Nawrocki
2013-03-03 11:45 ` Tomasz Figa
@ 2013-03-03 11:59 ` Sylwester Nawrocki
2013-03-03 12:34 ` Heiko Stübner
1 sibling, 1 reply; 37+ messages in thread
From: Sylwester Nawrocki @ 2013-03-03 11:59 UTC (permalink / raw)
To: linux-arm-kernel
On 03/03/2013 12:17 PM, Sylwester Nawrocki wrote:
> On 03/03/2013 02:08 AM, Heiko St?bner wrote:
>> But is there an easy way to define more than one alias? On the s3c2416
>> for
>> example the hsmmc hclk is the "hsmmc" io-clock, as well as the source
>> for the
>> "mmc_busclk.0". Same for the "uart" pclk, that is also a baud clock
>> source.
[...]
> But those multiple aliases are important only for machines with device
^^^^^
Sorry, this should have read "without". Also please note that due to
representing original struct clk_clksrc objects (mux + div + gate clock)
with separate primitive clocks device drivers may not work as before
where clk_{set/get}_parent() was called. I.e. a separate consumer clock
id needs to be used to control a clock mux. Hmm, however this issue
doesn't affect anything on s3c24xx, since such composite clocks have
been introduced only starting from s3c64xx.
I guess to create multiple aliases now a new helper function could be
created that takes as an argument a clock index (as in enum exynos4_clks)
and adds a clkdev lookup entry to a matched clk object. Probably it
wouldn't be difficult to rework the driver to be registering all clkdev
entries like this.
Do you have your source tree in any public git available ? ;) Perhaps
I could find a time to adjust and try it with s3c2440 based board.
> tree support, aren't they ?
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v6 01/16] clk: samsung: add common clock framework helper functions for Samsung platforms
2013-03-03 11:45 ` Tomasz Figa
@ 2013-03-03 12:08 ` Heiko Stübner
2013-03-03 12:48 ` Sylwester Nawrocki
2013-03-07 1:44 ` Kukjin Kim
2013-03-09 9:15 ` Kukjin Kim
2 siblings, 1 reply; 37+ messages in thread
From: Heiko Stübner @ 2013-03-03 12:08 UTC (permalink / raw)
To: linux-arm-kernel
Am Sonntag, 3. M?rz 2013, 12:45:01 schrieb Tomasz Figa:
> Hi,
>
> On Sunday 03 of March 2013 12:17:29 Sylwester Nawrocki wrote:
> > Hi,
> >
> > On 03/03/2013 02:08 AM, Heiko St?bner wrote:
> > > But is there an easy way to define more than one alias? On the s3c2416
> > > for example the hsmmc hclk is the "hsmmc" io-clock, as well as the
> > > source for the "mmc_busclk.0". Same for the "uart" pclk, that is also
> > > a baud clock source.
> >
> > This driver currently provides for only one additional clkdev lookup
> > entry per a platform clock. I pointed out this desing issue in the
> > early version of the patch set. It's because a machine clock definition
> > is coupled with a clock consumer definition. And IMO various
> > samsung_clock_register_* functions should not have
> > clk_register_clkdev() inside them. I.e. first step could be registering
> > all machine clocks and in the second one clkdev lookup entries could be
> > created. This is how most (all?) existing SoC clock drivers are
> > working.
> >
> > But those multiple aliases are important only for machines with device
> > tree support, aren't they ?
>
> I suppose you meant _without_ device tree support, right?
The aliases are only needed for the non-dt case. But as I think common clk
support will be a requirement for dt support in the future, similar to
pinctrl, without the correct handling of the aliases it will be hard to
incrementally convert the other platforms (i.e. s3c24xx before s3c2443, etc).
For the time being I've added my own register_alias function to Thomas' core
code, hijacking the clk_table for this - attached for reference below.
> > I hope this patch series gets merged early to linux-next in the 3.10
> > cycle so the multiple accumulated fixup patches for this clock driver
> > can be merged as well and issues like that you pointed out can be
> > resolved with incremental patches.
>
> Yes, I hope so too.
me too. Following all this still out-of-tree stuff makes me dizzy :-)
Heiko
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index d36cdd5..7f1b5bc 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -57,14 +57,15 @@ void __init samsung_clk_init(struct device_node *np, void __iomem *base,
unsigned long nr_rdump)
{
reg_base = base;
- if (!np)
- return;
-#ifdef CONFIG_OF
clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
if (!clk_table)
panic("could not allocate clock lookup table\n");
+ if (!np)
+ return;
+
+#ifdef CONFIG_OF
clk_data.clks = clk_table;
clk_data.clk_num = nr_clks;
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
@@ -96,6 +97,46 @@ void samsung_clk_add_lookup(struct clk *clk, unsigned int id)
clk_table[id] = clk;
}
+/* register a list of aliases */
+void __init samsung_clk_register_alias(struct samsung_clock_alias *list,
+ unsigned int nr_clk)
+{
+ struct clk *clk;
+ unsigned int idx, ret;
+
+ if (!clk_table) {
+ pr_err("%s: clock table missing\n", __func__);
+ return;
+ }
+
+ for (idx = 0; idx < nr_clk; idx++, list++) {
+ if (!list->id) {
+ pr_err("%s: clock id missing for index %d\n", __func__,
+ idx);
+ continue;
+ }
+
+ clk = clk_table[list->id];
+ if (!clk) {
+ pr_err("%s: failed to find clock %d\n", __func__,
+ list->id);
+ continue;
+ }
+
+ /* register a clock lookup only if a clock alias is specified */
+ if (!list->alias) {
+ pr_err("%s: no alias defined for clock %d\n", __func__,
+ list->id);
+ continue;
+ }
+
+ ret = clk_register_clkdev(clk, list->alias, list->dev_name);
+ if (ret)
+ pr_err("%s: failed to register lookup %s\n",
+ __func__, list->alias);
+ }
+}
+
/* register a list of fixed clocks */
void __init samsung_clk_register_fixed_rate(
struct samsung_fixed_rate_clock *list, unsigned int nr_clk)
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index 175a9d0..8be9248 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -23,6 +23,25 @@
#include <mach/map.h>
/**
+ * struct samsung_clock_alias: information about mux clock
+ * @id: platform specific id of the clock.
+ * @dev_name: name of the device to which this clock belongs.
+ * @alias: optional clock alias name to be assigned to this clock.
+ */
+struct samsung_clock_alias {
+ unsigned int id;
+ const char *dev_name;
+ const char *alias;
+};
+
+#define ALIAS(_id, dname, a) \
+ { \
+ .id = _id, \
+ .dev_name = dname, \
+ .alias = a, \
+ }
+
+/**
* struct samsung_fixed_rate_clock: information about fixed-rate clock
* @id: platform specific id of the clock.
* @name: name of this fixed-rate clock.
@@ -260,6 +282,8 @@ extern void __init samsung_clk_of_register_fixed_ext(
extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id);
+extern void samsung_clk_register_alias(struct samsung_clock_alias *list,
+ unsigned int nr_clk);
extern void __init samsung_clk_register_fixed_rate(
struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk);
extern void __init samsung_clk_register_fixed_factor(
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v6 01/16] clk: samsung: add common clock framework helper functions for Samsung platforms
2013-03-03 11:59 ` Sylwester Nawrocki
@ 2013-03-03 12:34 ` Heiko Stübner
0 siblings, 0 replies; 37+ messages in thread
From: Heiko Stübner @ 2013-03-03 12:34 UTC (permalink / raw)
To: linux-arm-kernel
Am Sonntag, 3. M?rz 2013, 12:59:03 schrieb Sylwester Nawrocki:
> On 03/03/2013 12:17 PM, Sylwester Nawrocki wrote:
> > On 03/03/2013 02:08 AM, Heiko St?bner wrote:
> >> But is there an easy way to define more than one alias? On the s3c2416
> >> for
> >> example the hsmmc hclk is the "hsmmc" io-clock, as well as the source
> >> for the
> >> "mmc_busclk.0". Same for the "uart" pclk, that is also a baud clock
> >> source.
>
> [...]
>
> > But those multiple aliases are important only for machines with device
>
> ^^^^^
> Sorry, this should have read "without". Also please note that due to
> representing original struct clk_clksrc objects (mux + div + gate clock)
> with separate primitive clocks device drivers may not work as before
> where clk_{set/get}_parent() was called. I.e. a separate consumer clock
> id needs to be used to control a clock mux. Hmm, however this issue
> doesn't affect anything on s3c24xx, since such composite clocks have
> been introduced only starting from s3c64xx.
>
> I guess to create multiple aliases now a new helper function could be
> created that takes as an argument a clock index (as in enum exynos4_clks)
> and adds a clkdev lookup entry to a matched clk object. Probably it
> wouldn't be difficult to rework the driver to be registering all clkdev
> entries like this.
>
> Do you have your source tree in any public git available ? ;) Perhaps
> I could find a time to adjust and try it with s3c2440 based board.
It's all quite messy still :-) ... I just managed to fix my last boot issues
with adding the baud clock aliases.
As I'm currently working on a linux-next variant with a lot of pending patches
merged in, there is no public git tree of it. But I've attached an archive of
the changes I did. As always I'm doing s3c2416 and s3c2443 as they are quite
similar, but as always there is a big difference to SoCs earlier than s3c2443.
Heiko
-------------- next part --------------
A non-text attachment was scrubbed...
Name: s3c2416-clk.tar.gz
Type: application/x-compressed-tar
Size: 16112 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20130303/e235bf90/attachment.bin>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v6 01/16] clk: samsung: add common clock framework helper functions for Samsung platforms
2013-03-03 12:08 ` Heiko Stübner
@ 2013-03-03 12:48 ` Sylwester Nawrocki
0 siblings, 0 replies; 37+ messages in thread
From: Sylwester Nawrocki @ 2013-03-03 12:48 UTC (permalink / raw)
To: linux-arm-kernel
On 03/03/2013 01:08 PM, Heiko St?bner wrote:
> Am Sonntag, 3. M?rz 2013, 12:45:01 schrieb Tomasz Figa:
>> On Sunday 03 of March 2013 12:17:29 Sylwester Nawrocki wrote:
>>> On 03/03/2013 02:08 AM, Heiko St?bner wrote:
>>>> But is there an easy way to define more than one alias? On the s3c2416
>>>> for example the hsmmc hclk is the "hsmmc" io-clock, as well as the
>>>> source for the "mmc_busclk.0". Same for the "uart" pclk, that is also
>>>> a baud clock source.
>>>
>>> This driver currently provides for only one additional clkdev lookup
>>> entry per a platform clock. I pointed out this desing issue in the
>>> early version of the patch set. It's because a machine clock definition
>>> is coupled with a clock consumer definition. And IMO various
>>> samsung_clock_register_* functions should not have
>>> clk_register_clkdev() inside them. I.e. first step could be registering
>>> all machine clocks and in the second one clkdev lookup entries could be
>>> created. This is how most (all?) existing SoC clock drivers are
>>> working.
>>>
>>> But those multiple aliases are important only for machines with device
>>> tree support, aren't they ?
>>
>> I suppose you meant _without_ device tree support, right?
Yes, my mistake, sorry for the confusion.
> The aliases are only needed for the non-dt case. But as I think common clk
> support will be a requirement for dt support in the future, similar to
> pinctrl, without the correct handling of the aliases it will be hard to
> incrementally convert the other platforms (i.e. s3c24xx before s3c2443, etc).
Yes, indeed. That's a very valid point to have the handling of the aliases
implemented correctly, not assuming it will be needed temporarily only.
> For the time being I've added my own register_alias function to Thomas' core
> code, hijacking the clk_table for this - attached for reference below.
The patch looks good to me. It would make sense to handle all clkdev
entries like this.
>>> I hope this patch series gets merged early to linux-next in the 3.10
>>> cycle so the multiple accumulated fixup patches for this clock driver
>>> can be merged as well and issues like that you pointed out can be
>>> resolved with incremental patches.
>>
>> Yes, I hope so too.
>
> me too. Following all this still out-of-tree stuff makes me dizzy :-)
Yeah, especially that it is not always clear what tag the patch series
are based of off. For a long patch series like these, touching the core
subsystems, it would be nice to have a corresponding git tree so it is
possible to actually use and test the patches without much trouble.
> Heiko
>
>
> diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
> index d36cdd5..7f1b5bc 100644
> --- a/drivers/clk/samsung/clk.c
> +++ b/drivers/clk/samsung/clk.c
> @@ -57,14 +57,15 @@ void __init samsung_clk_init(struct device_node *np, void __iomem *base,
> unsigned long nr_rdump)
> {
> reg_base = base;
> - if (!np)
> - return;
>
> -#ifdef CONFIG_OF
> clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
> if (!clk_table)
> panic("could not allocate clock lookup table\n");
>
> + if (!np)
> + return;
> +
> +#ifdef CONFIG_OF
> clk_data.clks = clk_table;
> clk_data.clk_num = nr_clks;
> of_clk_add_provider(np, of_clk_src_onecell_get,&clk_data);
> @@ -96,6 +97,46 @@ void samsung_clk_add_lookup(struct clk *clk, unsigned int id)
> clk_table[id] = clk;
> }
>
> +/* register a list of aliases */
> +void __init samsung_clk_register_alias(struct samsung_clock_alias *list,
> + unsigned int nr_clk)
> +{
> + struct clk *clk;
> + unsigned int idx, ret;
> +
> + if (!clk_table) {
> + pr_err("%s: clock table missing\n", __func__);
> + return;
> + }
> +
> + for (idx = 0; idx< nr_clk; idx++, list++) {
> + if (!list->id) {
> + pr_err("%s: clock id missing for index %d\n", __func__,
> + idx);
> + continue;
> + }
> +
> + clk = clk_table[list->id];
> + if (!clk) {
> + pr_err("%s: failed to find clock %d\n", __func__,
> + list->id);
> + continue;
> + }
> +
> + /* register a clock lookup only if a clock alias is specified */
> + if (!list->alias) {
> + pr_err("%s: no alias defined for clock %d\n", __func__,
> + list->id);
I wouldn't print that error in general. It might be a clock with NULL
conn_id.
It's not an error condition.
> + continue;
> + }
> +
> + ret = clk_register_clkdev(clk, list->alias, list->dev_name);
> + if (ret)
> + pr_err("%s: failed to register lookup %s\n",
> + __func__, list->alias);
> + }
> +}
> +
> /* register a list of fixed clocks */
> void __init samsung_clk_register_fixed_rate(
> struct samsung_fixed_rate_clock *list, unsigned int nr_clk)
> diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
> index 175a9d0..8be9248 100644
> --- a/drivers/clk/samsung/clk.h
> +++ b/drivers/clk/samsung/clk.h
> @@ -23,6 +23,25 @@
> #include<mach/map.h>
>
> /**
> + * struct samsung_clock_alias: information about mux clock
> + * @id: platform specific id of the clock.
> + * @dev_name: name of the device to which this clock belongs.
> + * @alias: optional clock alias name to be assigned to this clock.
> + */
> +struct samsung_clock_alias {
> + unsigned int id;
> + const char *dev_name;
> + const char *alias;
> +};
> +
> +#define ALIAS(_id, dname, a) \
> + { \
> + .id = _id, \
> + .dev_name = dname, \
> + .alias = a, \
> + }
> +
> +/**
> * struct samsung_fixed_rate_clock: information about fixed-rate clock
> * @id: platform specific id of the clock.
> * @name: name of this fixed-rate clock.
> @@ -260,6 +282,8 @@ extern void __init samsung_clk_of_register_fixed_ext(
>
> extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id);
>
> +extern void samsung_clk_register_alias(struct samsung_clock_alias *list,
> + unsigned int nr_clk);
> extern void __init samsung_clk_register_fixed_rate(
> struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk);
> extern void __init samsung_clk_register_fixed_factor(
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v6 01/16] clk: samsung: add common clock framework helper functions for Samsung platforms
2013-03-03 11:45 ` Tomasz Figa
2013-03-03 12:08 ` Heiko Stübner
@ 2013-03-07 1:44 ` Kukjin Kim
2013-03-09 9:15 ` Kukjin Kim
2 siblings, 0 replies; 37+ messages in thread
From: Kukjin Kim @ 2013-03-07 1:44 UTC (permalink / raw)
To: linux-arm-kernel
Tomasz Figa wrote:
>
> Hi,
>
> On Sunday 03 of March 2013 12:17:29 Sylwester Nawrocki wrote:
> > Hi,
> >
> > On 03/03/2013 02:08 AM, Heiko St?bner wrote:
> > > But is there an easy way to define more than one alias? On the s3c2416
> > > for example the hsmmc hclk is the "hsmmc" io-clock, as well as the
> > > source for the "mmc_busclk.0". Same for the "uart" pclk, that is also
> > > a baud clock source.
> > This driver currently provides for only one additional clkdev lookup
> > entry per a platform clock. I pointed out this desing issue in the
> > early version of the patch set. It's because a machine clock definition
> > is coupled with a clock consumer definition. And IMO various
> > samsung_clock_register_* functions should not have
> > clk_register_clkdev() inside them. I.e. first step could be registering
> > all machine clocks and in the second one clkdev lookup entries could be
> > created. This is how most (all?) existing SoC clock drivers are
> > working.
> >
> > But those multiple aliases are important only for machines with device
> > tree support, aren't they ?
>
> I suppose you meant _without_ device tree support, right?
>
> > I hope this patch series gets merged early to linux-next in the 3.10
> > cycle so the multiple accumulated fixup patches for this clock driver
> > can be merged as well and issues like that you pointed out can be
> > resolved with incremental patches.
>
> Yes, I hope so too.
>
Yes, I will in this weekend.
Note, I will modify [07/16] for universal_c210 as per Kyungmin's request,
I'm not sure about universal_c210 though.
Thanks.
- Kukjin
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v6 01/16] clk: samsung: add common clock framework helper functions for Samsung platforms
2013-03-03 11:45 ` Tomasz Figa
2013-03-03 12:08 ` Heiko Stübner
2013-03-07 1:44 ` Kukjin Kim
@ 2013-03-09 9:15 ` Kukjin Kim
2 siblings, 0 replies; 37+ messages in thread
From: Kukjin Kim @ 2013-03-09 9:15 UTC (permalink / raw)
To: linux-arm-kernel
Kukjin Kim wrote:
[...]
Thomas,
As I said, I applied this whole series into Samsung tree, following error
happens with exynos4_defconfig(non-DT) though.
drivers/clk/samsung/clk.c: In function 'samsung_clk_of_register_fixed_ext':
drivers/clk/samsung/clk.c:251:2: error: implicit declaration of function
'for_each_matching_node_and_match' [-Werror=implicit-function-declaration]
drivers/clk/samsung/clk.c:251:60: error: expected ';' before '{' token
drivers/clk/samsung/clk.c:249:6: warning: unused variable 'freq'
[-Wunused-variable]
cc1: some warnings being treated as errors
make[3]: *** [drivers/clk/samsung/clk.o] Error 1
make[2]: *** [drivers/clk/samsung] Error 2
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [drivers/clk] Error 2
make[1]: *** Waiting for unfinished jobs....
make: *** [drivers] Error 2
make: *** Waiting for unfinished jobs....
I think, it's time to decide to support non-DT exynos continuously, above
compilation error can be fixed though.
Hey guys, how do you think?
- Kukjin
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework
2013-02-18 8:21 [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework Thomas Abraham
` (14 preceding siblings ...)
2013-02-18 8:21 ` [PATCH v6 16/16] ARM: dts: add board specific fixed rate clock nodes for Exynos based platforms Thomas Abraham
@ 2013-03-19 18:49 ` Mike Turquette
2013-03-19 21:12 ` Heiko Stübner
15 siblings, 1 reply; 37+ messages in thread
From: Mike Turquette @ 2013-03-19 18:49 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Thomas Abraham (2013-02-18 00:21:10)
> Changes since v5:
> - Squashed several Exynos4 fixes patch from Tomasz Figa
> - Included support for Exynos5250 and Exynos5440, thus converting all
> Exynos4 and Exynos5 platforms to common clock framework.
> - Depends on the following patch series.
> - http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg15849.html
> - http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg15852.html
>
> Changes since v4:
> - Rebased to linux-3.8-rc1.
>
> Changes since v3:
> - Includes changes suggested by Tomasz Figa <tomasz.figa@gmail.com>
>
> This patch series migrates the Samsung Exynos4/5 SoC clock code to adopt the
> common clock framework. The use of Samsung specific clock structures has
> been removed and all board support code has been updated. imx-style of
> clock registration and lookup has been adopted for device tree based
> exynos4/5 platforms.
Thomas,
Are you planning a V7 series which includes the clock alias bits from
patch #1?
Regards,
Mike
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework
2013-03-19 18:49 ` [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework Mike Turquette
@ 2013-03-19 21:12 ` Heiko Stübner
2013-03-19 21:50 ` Mike Turquette
0 siblings, 1 reply; 37+ messages in thread
From: Heiko Stübner @ 2013-03-19 21:12 UTC (permalink / raw)
To: linux-arm-kernel
Am Dienstag, 19. M?rz 2013, 19:49:38 schrieb Mike Turquette:
> Quoting Thomas Abraham (2013-02-18 00:21:10)
>
> > Changes since v5:
> > - Squashed several Exynos4 fixes patch from Tomasz Figa
> > - Included support for Exynos5250 and Exynos5440, thus converting all
> >
> > Exynos4 and Exynos5 platforms to common clock framework.
> >
> > - Depends on the following patch series.
> >
> > -
> > http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg15849
> > .html -
> > http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg15852
> > .html
> >
> > Changes since v4:
> > - Rebased to linux-3.8-rc1.
> >
> > Changes since v3:
> > - Includes changes suggested by Tomasz Figa <tomasz.figa@gmail.com>
> >
> > This patch series migrates the Samsung Exynos4/5 SoC clock code to adopt
> > the common clock framework. The use of Samsung specific clock structures
> > has been removed and all board support code has been updated. imx-style
> > of clock registration and lookup has been adopted for device tree based
> > exynos4/5 platforms.
>
> Thomas,
>
> Are you planning a V7 series which includes the clock alias bits from
> patch #1?
Kukjin has already applied this series into the linux-samsung tree [0].
The alias changes are available in the series "clk: samsung: pm fixes
and multiple aliases" from last wednesday to on top, which you should
hopefully also have received.
This v2 series implements the changes discussed in the previous v1
"clk: samsung: small fixes and enhancements" from 2013-03-12, but didn't
get any responses yet.
Heiko
[0] https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=next/clk-exynos
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework
2013-03-19 21:12 ` Heiko Stübner
@ 2013-03-19 21:50 ` Mike Turquette
2013-03-20 0:00 ` Kukjin Kim
0 siblings, 1 reply; 37+ messages in thread
From: Mike Turquette @ 2013-03-19 21:50 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Heiko St?bner (2013-03-19 14:12:16)
> Am Dienstag, 19. M?rz 2013, 19:49:38 schrieb Mike Turquette:
> > Quoting Thomas Abraham (2013-02-18 00:21:10)
> >
> > > Changes since v5:
> > > - Squashed several Exynos4 fixes patch from Tomasz Figa
> > > - Included support for Exynos5250 and Exynos5440, thus converting all
> > >
> > > Exynos4 and Exynos5 platforms to common clock framework.
> > >
> > > - Depends on the following patch series.
> > >
> > > -
> > > http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg15849
> > > .html -
> > > http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg15852
> > > .html
> > >
> > > Changes since v4:
> > > - Rebased to linux-3.8-rc1.
> > >
> > > Changes since v3:
> > > - Includes changes suggested by Tomasz Figa <tomasz.figa@gmail.com>
> > >
> > > This patch series migrates the Samsung Exynos4/5 SoC clock code to adopt
> > > the common clock framework. The use of Samsung specific clock structures
> > > has been removed and all board support code has been updated. imx-style
> > > of clock registration and lookup has been adopted for device tree based
> > > exynos4/5 platforms.
> >
> > Thomas,
> >
> > Are you planning a V7 series which includes the clock alias bits from
> > patch #1?
>
> Kukjin has already applied this series into the linux-samsung tree [0].
>
That really is too much code to go into drivers/clk without my ACK. I
have not made much noise about this in the past but there has been more
and more "bonus" code slipping into drivers/clk each merge window.
Let's not do that any more.
Regards,
Mike
> The alias changes are available in the series "clk: samsung: pm fixes
> and multiple aliases" from last wednesday to on top, which you should
> hopefully also have received.
>
> This v2 series implements the changes discussed in the previous v1
> "clk: samsung: small fixes and enhancements" from 2013-03-12, but didn't
> get any responses yet.
>
>
> Heiko
>
>
> [0] https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=next/clk-exynos
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework
2013-03-19 21:50 ` Mike Turquette
@ 2013-03-20 0:00 ` Kukjin Kim
2013-03-20 2:56 ` Mike Turquette
0 siblings, 1 reply; 37+ messages in thread
From: Kukjin Kim @ 2013-03-20 0:00 UTC (permalink / raw)
To: linux-arm-kernel
Mike Turquette wrote:
>
[...]
> > > Thomas,
> > >
> > > Are you planning a V7 series which includes the clock alias bits from
> > > patch #1?
> >
> > Kukjin has already applied this series into the linux-samsung tree [0].
> >
Thanks, Heiko.
Mike, yes I did, as we discussed before. Since I missed in last window for v3.9, so I merged every common clock stuff for exynos into samsung tree in the early 3.9-rc time for v3.10.
>
> That really is too much code to go into drivers/clk without my ACK. I
> have not made much noise about this in the past but there has been more
> and more "bonus" code slipping into drivers/clk each merge window.
> Let's not do that any more.
>
Hmm, I remember you already agreed on previous version, and I thought if any further codes are required, we could do it on top of that.
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-January/143429.html
However, if you don't want current codes to be sent to upstream, let me know, but I don't think it would be better to us though.
Thanks.
- Kukjin
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework
2013-03-20 0:00 ` Kukjin Kim
@ 2013-03-20 2:56 ` Mike Turquette
2013-03-20 4:50 ` Kukjin Kim
0 siblings, 1 reply; 37+ messages in thread
From: Mike Turquette @ 2013-03-20 2:56 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Kukjin Kim (2013-03-19 17:00:09)
> Mike Turquette wrote:
> >
>
> [...]
>
> > > > Thomas,
> > > >
> > > > Are you planning a V7 series which includes the clock alias bits from
> > > > patch #1?
> > >
> > > Kukjin has already applied this series into the linux-samsung tree [0].
> > >
> Thanks, Heiko.
>
> Mike, yes I did, as we discussed before. Since I missed in last window for v3.9, so I merged every common clock stuff for exynos into samsung tree in the early 3.9-rc time for v3.10.
> >
> > That really is too much code to go into drivers/clk without my ACK. I
> > have not made much noise about this in the past but there has been more
> > and more "bonus" code slipping into drivers/clk each merge window.
> > Let's not do that any more.
> >
>
> Hmm, I remember you already agreed on previous version, and I thought if any further codes are required, we could do it on top of that.
> http://lists.infradead.org/pipermail/linux-arm-kernel/2013-January/143429.html
>
In the email you linked to my use of the word "merged" did not imply an
ACK. I was asking about merging the two separate exynos4 and exynos5
ccf development efforts together.
Furthermore if I *had* agreed on the previous version it would still
have been appropriate to put my Acked-by on those patches, which is
clearly missing today.
> However, if you don't want current codes to be sent to upstream, let me know, but I don't think it would be better to us though.
No, I am not asking you to revert/drop the patches, but I am using this
as a public example.
Regards,
Mike
>
> Thanks.
>
> - Kukjin
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework
2013-03-20 2:56 ` Mike Turquette
@ 2013-03-20 4:50 ` Kukjin Kim
2013-03-20 14:40 ` Mike Turquette
0 siblings, 1 reply; 37+ messages in thread
From: Kukjin Kim @ 2013-03-20 4:50 UTC (permalink / raw)
To: linux-arm-kernel
Mike Turquette wrote:
>
> Quoting Kukjin Kim (2013-03-19 17:00:09)
> > Mike Turquette wrote:
> > >
> >
> > [...]
> >
> > > > > Thomas,
> > > > >
> > > > > Are you planning a V7 series which includes the clock alias bits from
> > > > > patch #1?
> > > >
> > > > Kukjin has already applied this series into the linux-samsung tree [0].
> > > >
> > Thanks, Heiko.
> >
> > Mike, yes I did, as we discussed before. Since I missed in last window for
> v3.9, so I merged every common clock stuff for exynos into samsung tree in the
> early 3.9-rc time for v3.10.
> > >
> > > That really is too much code to go into drivers/clk without my ACK. I
> > > have not made much noise about this in the past but there has been more
> > > and more "bonus" code slipping into drivers/clk each merge window.
> > > Let's not do that any more.
> > >
> >
> > Hmm, I remember you already agreed on previous version, and I thought if any
> further codes are required, we could do it on top of that.
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2013-
> January/143429.html
> >
>
> In the email you linked to my use of the word "merged" did not imply an
> ACK. I was asking about merging the two separate exynos4 and exynos5
> ccf development efforts together.
>
OK, I see.
> Furthermore if I *had* agreed on the previous version it would still
> have been appropriate to put my Acked-by on those patches, which is
> clearly missing today.
>
BTW, how about following?
http://www.spinics.net/lists/arm-kernel/msg210266.html
In my understanding, it should be your agreement, it cannot be 'ack' though.
> > However, if you don't want current codes to be sent to upstream, let me know,
> but I don't think it would be better to us though.
>
> No, I am not asking you to revert/drop the patches, but I am using this
> as a public example.
>
What's the 'public example'?
As I linked, you already said 'sounds good to me' on my asking.
- Kukjin
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework
2013-03-20 4:50 ` Kukjin Kim
@ 2013-03-20 14:40 ` Mike Turquette
2013-03-21 23:26 ` Kukjin Kim
0 siblings, 1 reply; 37+ messages in thread
From: Mike Turquette @ 2013-03-20 14:40 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Kukjin Kim (2013-03-19 21:50:05)
> Mike Turquette wrote:
> >
> > Quoting Kukjin Kim (2013-03-19 17:00:09)
> > > Mike Turquette wrote:
> > > >
> > >
> > > [...]
> > >
> > > > > > Thomas,
> > > > > >
> > > > > > Are you planning a V7 series which includes the clock alias bits from
> > > > > > patch #1?
> > > > >
> > > > > Kukjin has already applied this series into the linux-samsung tree [0].
> > > > >
> > > Thanks, Heiko.
> > >
> > > Mike, yes I did, as we discussed before. Since I missed in last window for
> > v3.9, so I merged every common clock stuff for exynos into samsung tree in the
> > early 3.9-rc time for v3.10.
> > > >
> > > > That really is too much code to go into drivers/clk without my ACK. I
> > > > have not made much noise about this in the past but there has been more
> > > > and more "bonus" code slipping into drivers/clk each merge window.
> > > > Let's not do that any more.
> > > >
> > >
> > > Hmm, I remember you already agreed on previous version, and I thought if any
> > further codes are required, we could do it on top of that.
> > > http://lists.infradead.org/pipermail/linux-arm-kernel/2013-
> > January/143429.html
> > >
> >
> > In the email you linked to my use of the word "merged" did not imply an
> > ACK. I was asking about merging the two separate exynos4 and exynos5
> > ccf development efforts together.
> >
> OK, I see.
>
> > Furthermore if I *had* agreed on the previous version it would still
> > have been appropriate to put my Acked-by on those patches, which is
> > clearly missing today.
> >
> BTW, how about following?
>
> http://www.spinics.net/lists/arm-kernel/msg210266.html
>
> In my understanding, it should be your agreement, it cannot be 'ack' though.
>
I had forgotten about that email from November. Still my ack should
have been added. If necessary I'll be painfully explicit in the future
about adding my acked-by. It's a simple and good rule to follow.
Thanks,
Mike
> > > However, if you don't want current codes to be sent to upstream, let me know,
> > but I don't think it would be better to us though.
> >
> > No, I am not asking you to revert/drop the patches, but I am using this
> > as a public example.
> >
> What's the 'public example'?
>
> As I linked, you already said 'sounds good to me' on my asking.
>
> - Kukjin
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework
2013-03-20 14:40 ` Mike Turquette
@ 2013-03-21 23:26 ` Kukjin Kim
2013-03-22 14:27 ` Mike Turquette
0 siblings, 1 reply; 37+ messages in thread
From: Kukjin Kim @ 2013-03-21 23:26 UTC (permalink / raw)
To: linux-arm-kernel
Mike Turquette wrote:
[...]
> >
> > > Furthermore if I *had* agreed on the previous version it would still
> > > have been appropriate to put my Acked-by on those patches, which is
> > > clearly missing today.
> > >
> > BTW, how about following?
> >
> > http://www.spinics.net/lists/arm-kernel/msg210266.html
> >
> > In my understanding, it should be your agreement, it cannot be 'ack' though.
> >
>
> I had forgotten about that email from November. Still my ack should
> have been added. If necessary I'll be painfully explicit in the future
Agreed.
> about adding my acked-by. It's a simple and good rule to follow.
>
Yeah, I know. So if you want to add your ack on drivers/clk stuff for this series in samsung tree, please let me know.
Thanks, Mike.
- Kukjin
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework
2013-03-21 23:26 ` Kukjin Kim
@ 2013-03-22 14:27 ` Mike Turquette
2013-03-25 1:05 ` Kukjin Kim
0 siblings, 1 reply; 37+ messages in thread
From: Mike Turquette @ 2013-03-22 14:27 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Kukjin Kim (2013-03-21 16:26:24)
> Mike Turquette wrote:
>
> [...]
> > >
> > > > Furthermore if I *had* agreed on the previous version it would still
> > > > have been appropriate to put my Acked-by on those patches, which is
> > > > clearly missing today.
> > > >
> > > BTW, how about following?
> > >
> > > http://www.spinics.net/lists/arm-kernel/msg210266.html
> > >
> > > In my understanding, it should be your agreement, it cannot be 'ack' though.
> > >
> >
> > I had forgotten about that email from November. Still my ack should
> > have been added. If necessary I'll be painfully explicit in the future
>
> Agreed.
>
> > about adding my acked-by. It's a simple and good rule to follow.
> >
> Yeah, I know. So if you want to add your ack on drivers/clk stuff for this series in samsung tree, please let me know.
>
The patches are in pretty good shape. Please add my ack if you are able
to rebase comfortably. But if rebasing causes you and your downstream
users a lot of pain then don't do it.
Regards,
Mike
> Thanks, Mike.
>
> - Kukjin
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework
2013-03-22 14:27 ` Mike Turquette
@ 2013-03-25 1:05 ` Kukjin Kim
0 siblings, 0 replies; 37+ messages in thread
From: Kukjin Kim @ 2013-03-25 1:05 UTC (permalink / raw)
To: linux-arm-kernel
Mike Turquette wrote:
[...]
> > Yeah, I know. So if you want to add your ack on drivers/clk stuff for
> this series in samsung tree, please let me know.
> >
>
> The patches are in pretty good shape. Please add my ack if you are able
OK, I will.
> to rebase comfortably. But if rebasing causes you and your downstream
> users a lot of pain then don't do it.
>
Yes it can be, but it can be handled easily because of no-changing codes.
Note, please check Heiko's follow-up clk/samsung patches.
<http://comments.gmane.org/gmane.linux.kernel.samsung-soc/16817>
I'm fine on that and if you're ok, I'd like to take that with this series.
Thanks.
- Kukjin
^ permalink raw reply [flat|nested] 37+ messages in thread
end of thread, other threads:[~2013-03-25 1:05 UTC | newest]
Thread overview: 37+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-02-18 8:21 [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 01/16] clk: samsung: add common clock framework helper functions for Samsung platforms Thomas Abraham
2013-03-03 1:08 ` Heiko Stübner
2013-03-03 11:17 ` Sylwester Nawrocki
2013-03-03 11:45 ` Tomasz Figa
2013-03-03 12:08 ` Heiko Stübner
2013-03-03 12:48 ` Sylwester Nawrocki
2013-03-07 1:44 ` Kukjin Kim
2013-03-09 9:15 ` Kukjin Kim
2013-03-03 11:59 ` Sylwester Nawrocki
2013-03-03 12:34 ` Heiko Stübner
2013-02-18 8:21 ` [PATCH v6 02/16] clk: samsung: add pll clock registration helper functions Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 03/16] clk: exynos4: register clocks using common clock framework Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 04/16] clk: exynos5250: " Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 05/16] clk: exynos5440: " Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 07/16] ARM: Exynos: Initialize the clocks prior to timer initialization Thomas Abraham
2013-02-18 8:32 ` Kyungmin Park
2013-02-18 8:21 ` [PATCH v6 08/16] ARM: Exynos4: allow legacy board support to specify xxti and xusbxti clock speed Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 09/16] ARM: Exynos: remove auxdata table from exynos4/5 dt machine file Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 10/16] clocksource: mct: use fin_pll clock as the tick clock source for mct Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 11/16] clocksource: mct: add support for mct clock setup Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 12/16] ARM: dts: add Exynos4 and Exynos5 clock controller nodes Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 13/16] ARM: dts: add clock provider information for all controllers in Exynos4 SoCs Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 14/16] ARM: dts: add clock provider information for all controllers in Exynos5250 SoC Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 15/16] ARM: dts: add clock provider information for all controllers in Exynos5440 SoC Thomas Abraham
2013-02-18 8:21 ` [PATCH v6 16/16] ARM: dts: add board specific fixed rate clock nodes for Exynos based platforms Thomas Abraham
2013-02-19 5:11 ` Olof Johansson
2013-03-19 18:49 ` [PATCH v6 00/16] clk: exynos4/5: migrate to common clock framework Mike Turquette
2013-03-19 21:12 ` Heiko Stübner
2013-03-19 21:50 ` Mike Turquette
2013-03-20 0:00 ` Kukjin Kim
2013-03-20 2:56 ` Mike Turquette
2013-03-20 4:50 ` Kukjin Kim
2013-03-20 14:40 ` Mike Turquette
2013-03-21 23:26 ` Kukjin Kim
2013-03-22 14:27 ` Mike Turquette
2013-03-25 1:05 ` Kukjin Kim
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).