* [PATCH 0/7] exynos: add basic support for exynos5260 SoC
@ 2013-12-06 15:56 Rahul Sharma
2013-12-06 15:56 ` [PATCH 1/7] ARM: EXYNOS: initial board " Rahul Sharma
` (5 more replies)
0 siblings, 6 replies; 28+ messages in thread
From: Rahul Sharma @ 2013-12-06 15:56 UTC (permalink / raw)
To: linux-arm-kernel
add basic support for exynos5260 SoC.
This series is based on linux-next, Kukjin's for-next and
Mike's clk-for-linus-3.13 branches.
This patch is dependent on the following series from
Tomasz Figa <t.figa@samsung.com>:
http://www.spinics.net/lists/arm-kernel/msg280223.html
Arun Kumar K (1):
ARM: dts: add dts files for exynos5260 SoC
Pankaj Dubey (2):
ARM: EXYNOS: initial board support for exynos5260 SoC
clk/samsung: add support for pll2550xx
Rahul Sharma (3):
clk/samsung: add support for multuple clock providers
clk/samsung: add support for pll2650xx
clk/exynos5260: add clock file for exynos5260
Young-Gun Jang (1):
pinctrl: exynos: add exynos5260 SoC specific data
.../devicetree/bindings/clock/exynos5260-clock.txt | 228 ++
.../bindings/pinctrl/samsung-pinctrl.txt | 1 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 586 +++++
arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts | 85 +
arch/arm/boot/dts/exynos5260.dtsi | 315 +++
arch/arm/mach-exynos/Kconfig | 9 +
arch/arm/mach-exynos/common.c | 19 +-
arch/arm/mach-exynos/cpuidle.c | 2 +-
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/include/mach/regs-pmu.h | 4 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
arch/arm/plat-samsung/include/plat/cpu.h | 8 +
arch/arm/plat-samsung/include/plat/map-s5p.h | 1 +
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos4.c | 47 +-
drivers/clk/samsung/clk-exynos5250.c | 26 +-
drivers/clk/samsung/clk-exynos5260.c | 2661 ++++++++++++++++++++
drivers/clk/samsung/clk-exynos5260.h | 496 ++++
drivers/clk/samsung/clk-exynos5420.c | 24 +-
drivers/clk/samsung/clk-exynos5440.c | 18 +-
drivers/clk/samsung/clk-pll.c | 222 +-
drivers/clk/samsung/clk-pll.h | 3 +-
drivers/clk/samsung/clk-s3c64xx.c | 44 +-
drivers/clk/samsung/clk.c | 110 +-
drivers/clk/samsung/clk.h | 46 +-
drivers/pinctrl/pinctrl-exynos.c | 82 +
drivers/pinctrl/pinctrl-samsung.c | 2 +
drivers/pinctrl/pinctrl-samsung.h | 1 +
include/dt-bindings/clk/exynos5260-clk.h | 169 ++
30 files changed, 5076 insertions(+), 137 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt
create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
create mode 100644 arch/arm/boot/dts/exynos5260.dtsi
create mode 100644 drivers/clk/samsung/clk-exynos5260.c
create mode 100644 drivers/clk/samsung/clk-exynos5260.h
create mode 100644 include/dt-bindings/clk/exynos5260-clk.h
--
1.7.9.5
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 1/7] ARM: EXYNOS: initial board support for exynos5260 SoC
2013-12-06 15:56 [PATCH 0/7] exynos: add basic support for exynos5260 SoC Rahul Sharma
@ 2013-12-06 15:56 ` Rahul Sharma
2013-12-09 6:23 ` Sachin Kamat
2013-12-10 15:57 ` Tomasz Figa
2013-12-06 15:56 ` [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data Rahul Sharma
` (4 subsequent siblings)
5 siblings, 2 replies; 28+ messages in thread
From: Rahul Sharma @ 2013-12-06 15:56 UTC (permalink / raw)
To: linux-arm-kernel
From: Pankaj Dubey <pankaj.dubey@samsung.com>
This patch add basic arch side support for exynos5260 SoC.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
---
arch/arm/mach-exynos/Kconfig | 9 +++++++++
arch/arm/mach-exynos/common.c | 19 ++++++++++++++++++-
arch/arm/mach-exynos/cpuidle.c | 2 +-
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/include/mach/regs-pmu.h | 4 ++++
arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
arch/arm/plat-samsung/include/plat/cpu.h | 8 ++++++++
arch/arm/plat-samsung/include/plat/map-s5p.h | 1 +
8 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index f9d67a0..dcae2ec 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -93,6 +93,15 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5260
+ bool "SAMSUNG EXYNOS5260"
+ default y
+ depends on ARCH_EXYNOS5
+ select AUTO_ZRELADDR
+ select SAMSUNG_DMADEV
+ help
+ Enable EXYNOS5260 SoC support
+
config SOC_EXYNOS5420
bool "SAMSUNG EXYNOS5420"
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 61d2906..5eb77d1 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -52,6 +52,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";
static const char name_exynos5250[] = "EXYNOS5250";
+static const char name_exynos5260[] = "EXYNOS5260";
static const char name_exynos5420[] = "EXYNOS5420";
static const char name_exynos5440[] = "EXYNOS5440";
@@ -85,6 +86,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = exynos_init,
.name = name_exynos5250,
}, {
+ .idcode = EXYNOS5260_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5260,
+ }, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
@@ -263,6 +270,15 @@ static struct map_desc exynos5_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5260_iodesc[] __initdata = {
+ {
+ .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn = __phys_to_pfn(EXYNOS5260_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
void exynos4_restart(enum reboot_mode mode, const char *cmd)
{
__raw_writel(0x1, S5P_SWRESET);
@@ -371,7 +387,8 @@ static void __init exynos4_map_io(void)
static void __init exynos5_map_io(void)
{
iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
-
+ if (soc_is_exynos5260())
+ iotable_init(exynos5260_iodesc, ARRAY_SIZE(exynos5260_iodesc));
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
}
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index ddbfe87..405c11a 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -120,7 +120,7 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
cpu_suspend(0, idle_finisher);
#ifdef CONFIG_SMP
- if (!soc_is_exynos5250())
+ if (!soc_is_exynos5250() || soc_is_exynos5260())
scu_enable(S5P_VA_SCU);
#endif
cpu_pm_exit();
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..bd6fa02 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS 0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS 0x0204F000
+#define EXYNOS5260_PA_SYSRAM_NS 0x02073000
#define EXYNOS_PA_CHIPID 0x10000000
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 2cdb63e..09ae29a 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -234,6 +234,10 @@
#define EXYNOS5_SYS_WDTRESET (1 << 20)
+#define EXYNOS5260_A7_WDTRST (1 << 24)
+#define EXYNOS5260_A15_WDTRST (1 << 23)
+#define EXYNOS5260_SYS_WDTRESET (EXYNOS5260_A7_WDTRST || EXYNOS5260_A15_WDTRST)
+
#define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000)
#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004)
#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008)
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 1fe075a..d23cdc3 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -50,6 +50,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
"samsung,exynos5250",
+ "samsung,exynos5260",
"samsung,exynos5420",
"samsung,exynos5440",
NULL
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 335beb3..60687aa 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
#define EXYNOS4_CPU_MASK 0xFFFE0000
#define EXYNOS5250_SOC_ID 0x43520000
+#define EXYNOS5260_SOC_ID 0xE5260000
#define EXYNOS5420_SOC_ID 0xE5420000
#define EXYNOS5440_SOC_ID 0xE5440000
#define EXYNOS5_SOC_MASK 0xFFFFF000
@@ -68,6 +69,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5260, EXYNOS5260_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
@@ -148,6 +150,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
# define soc_is_exynos5250() 0
#endif
+#if defined(CONFIG_SOC_EXYNOS5260)
+# define soc_is_exynos5260() is_samsung_exynos5260()
+#else
+# define soc_is_exynos5260() 0
+#endif
+
#if defined(CONFIG_SOC_EXYNOS5420)
# define soc_is_exynos5420() is_samsung_exynos5420()
#else
diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h
index c186786..804597c 100644
--- a/arch/arm/plat-samsung/include/plat/map-s5p.h
+++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
@@ -23,6 +23,7 @@
#define S5P_VA_SYSRAM S3C_ADDR(0x02400000)
#define S5P_VA_SYSRAM_NS S3C_ADDR(0x02410000)
+
#define S5P_VA_DMC0 S3C_ADDR(0x02440000)
#define S5P_VA_DMC1 S3C_ADDR(0x02480000)
#define S5P_VA_SROMC S3C_ADDR(0x024C0000)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data
2013-12-06 15:56 [PATCH 0/7] exynos: add basic support for exynos5260 SoC Rahul Sharma
2013-12-06 15:56 ` [PATCH 1/7] ARM: EXYNOS: initial board " Rahul Sharma
@ 2013-12-06 15:56 ` Rahul Sharma
2013-12-09 4:51 ` Sachin Kamat
2013-12-10 16:04 ` Tomasz Figa
2013-12-06 15:56 ` [PATCH 3/7] ARM: dts: add dts files for exynos5260 SoC Rahul Sharma
` (3 subsequent siblings)
5 siblings, 2 replies; 28+ messages in thread
From: Rahul Sharma @ 2013-12-06 15:56 UTC (permalink / raw)
To: linux-arm-kernel
From: Young-Gun Jang <yg1004.jang@samsung.com>
Add Samsung Exynos5260 SoC specific data to enable pinctrl
support for all platforms based on EXYNOS5260.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
---
.../bindings/pinctrl/samsung-pinctrl.txt | 1 +
drivers/pinctrl/pinctrl-exynos.c | 82 ++++++++++++++++++++
drivers/pinctrl/pinctrl-samsung.c | 2 +
drivers/pinctrl/pinctrl-samsung.h | 1 +
4 files changed, 86 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index 257677d..2b32783 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -16,6 +16,7 @@ Required Properties:
- "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
- "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
+ - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 155b1b3..9a93df6 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -1042,6 +1042,88 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
},
};
+/* pin banks of exynos5260 pin-controller 0 */
+static struct samsung_pin_bank exynos5260_pin_banks0[] = {
+ EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
+ EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
+ EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
+ EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
+ EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
+ EXYNOS_PIN_BANK_EINTG(5, 0x0A0, "gpb2", 0x14),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpb4", 0x1c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
+ EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
+ EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
+ EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
+ EXYNOS_PIN_BANK_EINTG(5, 0x1A0, "gpe1", 0x34),
+ EXYNOS_PIN_BANK_EINTG(4, 0x1C0, "gpf0", 0x38),
+ EXYNOS_PIN_BANK_EINTG(8, 0x1E0, "gpf1", 0x3c),
+ EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
+};
+
+/* pin banks of exynos5260 pin-controller 1 */
+static struct samsung_pin_bank exynos5260_pin_banks1[] = {
+ EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
+ EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
+ EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
+ EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
+ EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
+};
+
+/* pin banks of exynos5260 pin-controller 2 */
+static struct samsung_pin_bank exynos5260_pin_banks2[] = {
+ EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
+ EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5420 SoC includes
+ * four gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl exynos5260_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 data */
+ .pin_banks = exynos5260_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),
+ .geint_con = EXYNOS_GPIO_ECON_OFFSET,
+ .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
+ .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
+ .weint_con = EXYNOS_WKUP_ECON_OFFSET,
+ .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
+ .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
+ .svc = EXYNOS_SVC_OFFSET,
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .label = "exynos5260-gpio-ctrl0",
+ }, {
+ /* pin-controller instance 1 data */
+ .pin_banks = exynos5260_pin_banks1,
+ .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),
+ .geint_con = EXYNOS_GPIO_ECON_OFFSET,
+ .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
+ .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
+ .svc = EXYNOS_SVC_OFFSET,
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .label = "exynos5260-gpio-ctrl1",
+ }, {
+ /* pin-controller instance 2 data */
+ .pin_banks = exynos5260_pin_banks2,
+ .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2),
+ .geint_con = EXYNOS_GPIO_ECON_OFFSET,
+ .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
+ .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
+ .svc = EXYNOS_SVC_OFFSET,
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .label = "exynos5260-gpio-ctrl2",
+ },
+};
+
/* pin banks of exynos5420 pin-controller 0 */
static struct samsung_pin_bank exynos5420_pin_banks0[] = {
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index 47ec2e8..0324d4c 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -1120,6 +1120,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
.data = (void *)exynos4x12_pin_ctrl },
{ .compatible = "samsung,exynos5250-pinctrl",
.data = (void *)exynos5250_pin_ctrl },
+ { .compatible = "samsung,exynos5260-pinctrl",
+ .data = (void *)exynos5260_pin_ctrl },
{ .compatible = "samsung,exynos5420-pinctrl",
.data = (void *)exynos5420_pin_ctrl },
{ .compatible = "samsung,s5pv210-pinctrl",
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
index 30622d9..bab9c21 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -254,6 +254,7 @@ struct samsung_pmx_func {
extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
extern struct samsung_pin_ctrl exynos5250_pin_ctrl[];
+extern struct samsung_pin_ctrl exynos5260_pin_ctrl[];
extern struct samsung_pin_ctrl exynos5420_pin_ctrl[];
extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[];
extern struct samsung_pin_ctrl s3c2412_pin_ctrl[];
--
1.7.9.5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 3/7] ARM: dts: add dts files for exynos5260 SoC
2013-12-06 15:56 [PATCH 0/7] exynos: add basic support for exynos5260 SoC Rahul Sharma
2013-12-06 15:56 ` [PATCH 1/7] ARM: EXYNOS: initial board " Rahul Sharma
2013-12-06 15:56 ` [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data Rahul Sharma
@ 2013-12-06 15:56 ` Rahul Sharma
2013-12-10 17:10 ` Tomasz Figa
2013-12-06 15:56 ` [PATCH 4/7] clk/samsung: add support for multuple clock providers Rahul Sharma
` (2 subsequent siblings)
5 siblings, 1 reply; 28+ messages in thread
From: Rahul Sharma @ 2013-12-06 15:56 UTC (permalink / raw)
To: linux-arm-kernel
From: Arun Kumar K <arun.kk@samsung.com>
The patch adds the dts files for exynos5260 and for xyref
evt0 board.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 586 +++++++++++++++++++++++
arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts | 85 ++++
arch/arm/boot/dts/exynos5260.dtsi | 315 ++++++++++++
4 files changed, 987 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
create mode 100644 arch/arm/boot/dts/exynos5260.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 741bf73..8d26135 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5260-xyref5260-evt0.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
new file mode 100644
index 0000000..67aaee7
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
@@ -0,0 +1,586 @@
+/*
+ * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+ pinctrl at 11600000 {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb1: gpb1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb2: gpb2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb3: gpb3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb4: gpb4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb5: gpb5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpe0: gpe0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpe1: gpe1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf0: gpf0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf1: gpf1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpk0: gpk0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx0: gpx0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx1: gpx1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx2: gpx2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx3: gpx3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ uart0_data: uart0-data {
+ samsung,pins = "gpa0-0", "gpa0-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart0_fctl: uart0-fctl {
+ samsung,pins = "gpa0-2", "gpa0-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart1_data: uart1-data {
+ samsung,pins = "gpa1-0", "gpa1-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart1_fctl: uart1-fctl {
+ samsung,pins = "gpa1-2", "gpa1-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart2_data: uart2-data {
+ samsung,pins = "gpa1-4", "gpa1-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ spi0_bus: spi0-bus {
+ samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ spi1_bus: spi1-bus {
+ samsung,pins = "gpa2-5", "gpa2-6", "gpa2-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ usb3_vbus0_en: usb3-vbus0-en {
+ samsung,pins = "gpa2-4";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2s1_bus: i2s1-bus {
+ samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
+ "gpb0-4";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ pcm1_bus: pcm1-bus {
+ samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
+ "gpb0-4";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ spdif1_bus: spdif1-bus {
+ samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2";
+ samsung,pin-function = <4>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ spi2_bus: spi2-bus {
+ samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c0_hs_bus: i2c0-hs-bus {
+ samsung,pins = "gpb3-0", "gpb3-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c1_hs_bus: i2c1-hs-bus {
+ samsung,pins = "gpb3-2", "gpb3-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c2_hs_bus: i2c2-hs-bus {
+ samsung,pins = "gpb3-4", "gpb3-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c3_hs_bus: i2c3-hs-bus {
+ samsung,pins = "gpb3-6", "gpb3-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c4_bus: i2c4-bus {
+ samsung,pins = "gpb4-0", "gpb4-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c5_bus: i2c5-bus {
+ samsung,pins = "gpb4-2", "gpb4-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c6_bus: i2c6-bus {
+ samsung,pins = "gpb4-4", "gpb4-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c7_bus: i2c7-bus {
+ samsung,pins = "gpb4-6", "gpb4-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c8_bus: i2c8-bus {
+ samsung,pins = "gpb5-0", "gpb5-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c9_bus: i2c9-bus {
+ samsung,pins = "gpb5-2", "gpb5-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c10_bus: i2c10-bus {
+ samsung,pins = "gpb5-4", "gpb5-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c11_bus: i2c11-bus {
+ samsung,pins = "gpb5-6", "gpb5-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ cam_gpio_a: cam-gpio-a {
+ samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3",
+ "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7",
+ "gpe1-0", "gpe1-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ cam_gpio_b: cam-gpio-b {
+ samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3",
+ "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ cam_i2c1_bus: cam-i2c1-bus {
+ samsung,pins = "gpf0-2", "gpf0-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ cam_i2c0_bus: cam-i2c0-bus {
+ samsung,pins = "gpf0-0", "gpf0-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ cam_spi0_bus: cam-spi0-bus {
+ samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ cam_spi1_bus: cam-spi1-bus {
+ samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ hdmi_hpd_irq: hdmi-hpd-irq {
+ samsung,pins = "gpx3-7";
+ samsung,pin-function = <0>;
+ samsung,pin-pud = <1>;
+ samsung,pin-drv = <0>;
+ };
+ };
+
+ pinctrl at 12290000 {
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc2: gpc2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc3: gpc3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc4: gpc4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sd0_clk: sd0-clk {
+ samsung,pins = "gpc0-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_cmd: sd0-cmd {
+ samsung,pins = "gpc0-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_cd: sd0-cd {
+ samsung,pins = "gpc0-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_bus1: sd0-bus-width1 {
+ samsung,pins = "gpc0-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_bus4: sd0-bus-width4 {
+ samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_bus8: sd0-bus-width8 {
+ samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_clk: sd1-clk {
+ samsung,pins = "gpc1-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_cmd: sd1-cmd {
+ samsung,pins = "gpc1-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_cd: sd1-cd {
+ samsung,pins = "gpc1-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_bus1: sd1-bus-width1 {
+ samsung,pins = "gpc1-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_bus4: sd1-bus-width4 {
+ samsung,pins = "gpc1-3", "gpc1-4", "gpc1-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_bus8: sd1-bus-width8 {
+ samsung,pins = "gpc4-0", "gpc4-1", "gpc4-2", "gpc4-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_clk: sd2-clk {
+ samsung,pins = "gpc2-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_cmd: sd2-cmd {
+ samsung,pins = "gpc2-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_cd: sd2-cd {
+ samsung,pins = "gpc2-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_bus1: sd2-bus-width1 {
+ samsung,pins = "gpc2-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_bus4: sd2-bus-width4 {
+ samsung,pins = "gpc2-3", "gpc2-4", "gpc2-5", "gpc2-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+ };
+
+ pinctrl at 128B0000 {
+ gpz0: gpz0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpz1: gpz1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
new file mode 100644
index 0000000..aa1fcda
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
@@ -0,0 +1,85 @@
+/*
+ * SAMSUNG XYREF5260 EVT0 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5260.dtsi"
+
+/ {
+ model = "SAMSUNG XYREF5260 EVT0 board based on EXYNOS5260";
+ compatible = "samsung,xyref5260", "samsung,exynos5260";
+
+ chosen {
+ bootargs = "console=ttySAC2,115200";
+ };
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = "samsung,exynos5260-oscclk";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ serial at 12C00000 {
+ status = "okay";
+ };
+
+ serial at 12C10000 {
+ status = "okay";
+ };
+
+ serial at 12C20000 {
+ status = "okay";
+ };
+
+ serial at 12860000 {
+ status = "okay";
+ };
+
+ dwmmc0 at 12140000 {
+ status = "okay";
+ num-slots = <1>;
+ broken-cd;
+ bypass-smu;
+ supports-highspeed;
+ supports-hs200-mode; /* 200 Mhz */
+ fifo-depth = <0x40>;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <0 4>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+
+ slot at 0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+ };
+
+ dwmmc2 at 12160000 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ fifo-depth = <0x40>;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+
+ slot at 0 {
+ reg = <0>;
+ bus-width = <4>;
+ disable-wp;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
new file mode 100644
index 0000000..fcb8d4f
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -0,0 +1,315 @@
+/*
+ * SAMSUNG EXYNOS5260 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include "skeleton.dtsi"
+#include "exynos5260-pinctrl.dtsi"
+
+#include <dt-bindings/clk/exynos5260-clk.h>
+
+/ {
+ compatible = "samsung,exynos5260";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ pinctrl0 = &pinctrl_0;
+ pinctrl1 = &pinctrl_1;
+ pinctrl2 = &pinctrl_2;
+ };
+
+ chipid at 10000000 {
+ compatible = "samsung,exynos4210-chipid";
+ reg = <0x10000000 0x100>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ cci-control-port = <&cci_control1>;
+ };
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ cci-control-port = <&cci_control1>;
+ };
+ cpu at 2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
+ cci-control-port = <&cci_control0>;
+ };
+ cpu at 3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
+ cci-control-port = <&cci_control0>;
+ };
+ cpu at 4 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x102>;
+ cci-control-port = <&cci_control0>;
+ };
+ cpu at 5 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x103>;
+ cci-control-port = <&cci_control0>;
+ };
+ };
+
+ cmus {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ cmu_top: clock-controller at 0x10010000 {
+ compatible = "exynos5260-cmu-top",
+ "samsung,exynos5260-clock";
+ reg = <0x10010000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ cmu_peri: clock-controller at 0x10200000 {
+ compatible = "exynos5260-cmu-peri", "samsung,exynos5260-clock";
+ reg = <0x10200000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ cmu_egl: clock-controller at 0x10600000 {
+ compatible = "exynos5260-cmu-egl", "samsung,exynos5260-clock";
+ reg = <0x10600000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ cmu_kfc: clock-controller at 0x10700000 {
+ compatible = "exynos5260-cmu-kfc", "samsung,exynos5260-clock";
+ reg = <0x10700000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ cmu_g2d: clock-controller at 0x10A00000 {
+ compatible = "exynos5260-cmu-g2d", "samsung,exynos5260-clock";
+ reg = <0x10A00000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ cmu_mif: clock-controller at 0x10CE0000 {
+ compatible = "exynos5260-cmu-mif", "samsung,exynos5260-clock";
+ reg = <0x10CE0000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ cmu_mfc: clock-controller at 0x11090000 {
+ compatible = "exynos5260-cmu-mfc", "samsung,exynos5260-clock";
+ reg = <0x11090000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ cmu_g3d: clock-controller at 0x11830000 {
+ compatible = "exynos5260-cmu-g3d", "samsung,exynos5260-clock";
+ reg = <0x11830000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ cmu_fsys: clock-controller at 0x122E0000 {
+ compatible = "exynos5260-cmu-fsys", "samsung,exynos5260-clock";
+ reg = <0x122E0000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ cmu_aud: clock-controller at 0x128C0000 {
+ compatible = "exynos5260-cmu-aud", "samsung,exynos5260-clock";
+ reg = <0x128C0000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ cmu_isp: clock-controller at 0x133C0000 {
+ compatible = "exynos5260-cmu-isp", "samsung,exynos5260-clock";
+ reg = <0x133C0000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ cmu_gscl: clock-controller at 0x13F00000 {
+ compatible = "exynos5260-cmu-gscl", "samsung,exynos5260-clock";
+ reg = <0x13F00000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ cmu_disp: clock-controller at 0x14550000 {
+ compatible = "exynos5260-cmu-disp", "samsung,exynos5260-clock";
+ reg = <0x14550000 0x10000>;
+ #clock-cells = <1>;
+ };
+ };
+
+ gic:interrupt-controller at 10481000 {
+ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-controller;
+ reg = <0x10481000 0x1000>,
+ <0x10482000 0x1000>,
+ <0x10484000 0x2000>,
+ <0x10486000 0x2000>;
+ interrupts = <1 9 0xf04>;
+ };
+
+ mct at 100B0000 {
+ compatible = "samsung,exynos4210-mct";
+ reg = <0x100B0000 0xb00>;
+ interrupt-controller;
+ #interrups-cells = <2>;
+ interrupt-parent = <&mct_map>;
+ interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+ <4 0>, <5 0>, <6 0>, <7 0>,
+ <8 0>, <9 0>, <10 0>, <11 0>;
+ clocks = <&cmu_top FIN_PLL>, <&cmu_peri PERI_PCLK_MCT>;
+ clock-names = "fin_pll", "mct";
+
+ mct_map: mct-map {
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = <0x0 0 &gic 0 104 0>,
+ <0x1 0 &gic 0 105 0>,
+ <0x2 0 &gic 0 106 0>,
+ <0x3 0 &gic 0 107 0>,
+ <0x4 0 &gic 0 122 0>,
+ <0x5 0 &gic 0 123 0>,
+ <0x6 0 &gic 0 124 0>,
+ <0x7 0 &gic 0 125 0>,
+ <0x8 0 &gic 0 126 0>,
+ <0x9 0 &gic 0 127 0>,
+ <0xa 0 &gic 0 128 0>,
+ <0xb 0 &gic 0 129 0>;
+ };
+ };
+
+ cci at 10F00000 {
+ compatible = "arm,cci-400";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x10F00000 0x1000>;
+ ranges = <0x0 0x10F00000 0x6000>;
+
+ cci_control0: slave-if at 4000 { /* Please check again */
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x4000 0x1000>; /* Please check again */
+ };
+
+ cci_control1: slave-if at 5000 { /* Please check again */
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x5000 0x1000>; /* Please check again */
+ };
+ };
+
+ pinctrl_0: pinctrl at 11600000 {
+ compatible = "samsung,exynos5260-pinctrl";
+ reg = <0x11600000 0x1000>;
+ interrupts = <0 79 0>; /* GPIO_RT */
+
+ wakeup-interrupt-controller {
+ compatible = "samsung,exynos4210-wakeup-eint";
+ interrupt-parent = <&gic>;
+ interrupts = <0 32 0>;
+ };
+ };
+
+ pinctrl_1: pinctrl at 12290000 {
+ compatible = "samsung,exynos5260-pinctrl";
+ reg = <0x12290000 0x1000>; /* GPIO_FSYS */
+ interrupts = <0 157 0>;
+ };
+
+ pinctrl_2: pinctrl at 128B0000 {
+ compatible = "samsung,exynos5260-pinctrl";
+ reg = <0x128B0000 0x1000>;
+ interrupts = <0 243 0>; /* GPIO_AUD */
+ };
+
+ serial at 12C00000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C00000 0x100>;
+ interrupts = <0 146 0>;
+ clocks = <&cmu_peri PERI_PCLK_UART0>, <&cmu_peri PERI_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "disabled";
+ };
+
+ serial at 12C10000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C10000 0x100>;
+ interrupts = <0 147 0>;
+ clocks = <&cmu_peri PERI_PCLK_UART1>, <&cmu_peri PERI_SCLK_UART1>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "disabled";
+ };
+
+ serial at 12C20000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C20000 0x100>;
+ interrupts = <0 148 0>;
+ clocks = <&cmu_peri PERI_PCLK_UART2>, <&cmu_peri PERI_SCLK_UART2>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "disabled";
+ };
+
+ serial at 12860000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12860000 0x100>;
+ interrupts = <0 145 0>;
+ clocks = <&cmu_aud AUD_PCLK_AUD_UART>, <&cmu_aud AUD_SCLK_AUD_UART>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "disabled";
+ };
+
+ dwmmc_0: dwmmc0 at 12140000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ reg = <0x12140000 0x2000>;
+ interrupts = <0 156 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu_fsys FSYS_HCLK_MMC0>, <&cmu_top TOP_SCLK_MMC0>;
+ clock-names = "biu", "ciu";
+ status = "disabled";
+ };
+
+ dwmmc_1: dwmmc1 at 12150000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ reg = <0x12150000 0x2000>;
+ interrupts = <0 158 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu_fsys FSYS_HCLK_MMC1>, <&cmu_top TOP_SCLK_MMC1>;
+ clock-names = "biu", "ciu";
+ status = "disabled";
+ };
+
+ dwmmc_2: dwmmc2 at 12160000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ reg = <0x12160000 0x2000>;
+ interrupts = <0 159 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu_fsys FSYS_HCLK_MMC2>, <&cmu_top TOP_SCLK_MMC2>;
+ clock-names = "biu", "ciu";
+ status = "disabled";
+ };
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 4/7] clk/samsung: add support for multuple clock providers
2013-12-06 15:56 [PATCH 0/7] exynos: add basic support for exynos5260 SoC Rahul Sharma
` (2 preceding siblings ...)
2013-12-06 15:56 ` [PATCH 3/7] ARM: dts: add dts files for exynos5260 SoC Rahul Sharma
@ 2013-12-06 15:56 ` Rahul Sharma
2013-12-11 11:15 ` Tomasz Figa
2013-12-06 15:56 ` [PATCH 5/7] clk/samsung: add support for pll2550xx Rahul Sharma
2013-12-06 15:56 ` [PATCH 6/7] clk/samsung: add support for pll2650xx Rahul Sharma
5 siblings, 1 reply; 28+ messages in thread
From: Rahul Sharma @ 2013-12-06 15:56 UTC (permalink / raw)
To: linux-arm-kernel
Samsung CCF helper functions do not provide support to
register multiple Clock Providers for a given SoC. Due to
this limitation SoC platforms are not able to use these
helpers for registering mulitple clock providers and are
forced to bypass this layer.
This layer is modified acordingly to enable the support.
Clockfile for exynos4, exynos5250, exynos5420, exynos5440
and S3c64xx are also modified as per changed helper functions.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
---
drivers/clk/samsung/clk-exynos4.c | 47 ++++++++-------
drivers/clk/samsung/clk-exynos5250.c | 26 ++++----
drivers/clk/samsung/clk-exynos5420.c | 24 +++++---
drivers/clk/samsung/clk-exynos5440.c | 18 +++---
drivers/clk/samsung/clk-pll.c | 14 +++--
drivers/clk/samsung/clk-s3c64xx.c | 44 ++++++++------
drivers/clk/samsung/clk.c | 110 +++++++++++++++++++---------------
drivers/clk/samsung/clk.h | 46 ++++++++++----
8 files changed, 195 insertions(+), 134 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index ca2a940..e634ba9 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1093,7 +1093,7 @@ static unsigned long exynos4_get_xom(void)
return xom;
}
-static void __init exynos4_clk_register_finpll(void)
+static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)
{
struct samsung_fixed_rate_clock fclk;
struct clk *clk;
@@ -1116,7 +1116,7 @@ static void __init exynos4_clk_register_finpll(void)
fclk.parent_name = NULL;
fclk.flags = CLK_IS_ROOT;
fclk.fixed_rate = finpll_f;
- samsung_clk_register_fixed_rate(&fclk, 1);
+ samsung_clk_register_fixed_rate(ctx, &fclk, 1);
}
@@ -1226,22 +1226,25 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
static void __init exynos4_clk_init(struct device_node *np,
enum exynos4_soc soc)
{
+ struct samsung_clk_provider *ctx;
exynos4_soc = soc;
reg_base = of_iomap(np, 0);
if (!reg_base)
panic("%s: failed to map registers\n", __func__);
- samsung_clk_init(np, reg_base, nr_clks);
+ ctx = samsung_clk_init(np, reg_base, nr_clks);
+ if (!ctx)
+ panic("%s: unable to allocate context.\n", __func__);
- samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
+ samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
ext_clk_match);
- exynos4_clk_register_finpll();
+ exynos4_clk_register_finpll(ctx);
if (exynos4_soc == EXYNOS4210) {
- samsung_clk_register_mux(exynos4210_mux_early,
+ samsung_clk_register_mux(ctx, exynos4210_mux_early,
ARRAY_SIZE(exynos4210_mux_early));
if (_get_rate("fin_pll") == 24000000) {
@@ -1255,7 +1258,7 @@ static void __init exynos4_clk_init(struct device_node *np,
exynos4210_plls[vpll].rate_table =
exynos4210_vpll_rates;
- samsung_clk_register_pll(exynos4210_plls,
+ samsung_clk_register_pll(ctx, exynos4210_plls,
ARRAY_SIZE(exynos4210_plls), reg_base);
} else {
if (_get_rate("fin_pll") == 24000000) {
@@ -1267,42 +1270,42 @@ static void __init exynos4_clk_init(struct device_node *np,
exynos4x12_vpll_rates;
}
- samsung_clk_register_pll(exynos4x12_plls,
+ samsung_clk_register_pll(ctx, exynos4x12_plls,
ARRAY_SIZE(exynos4x12_plls), reg_base);
}
- samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks,
+ samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,
ARRAY_SIZE(exynos4_fixed_rate_clks));
- samsung_clk_register_mux(exynos4_mux_clks,
+ samsung_clk_register_mux(ctx, exynos4_mux_clks,
ARRAY_SIZE(exynos4_mux_clks));
- samsung_clk_register_div(exynos4_div_clks,
+ samsung_clk_register_div(ctx, exynos4_div_clks,
ARRAY_SIZE(exynos4_div_clks));
- samsung_clk_register_gate(exynos4_gate_clks,
+ samsung_clk_register_gate(ctx, exynos4_gate_clks,
ARRAY_SIZE(exynos4_gate_clks));
if (exynos4_soc == EXYNOS4210) {
- samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks,
+ samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
ARRAY_SIZE(exynos4210_fixed_rate_clks));
- samsung_clk_register_mux(exynos4210_mux_clks,
+ samsung_clk_register_mux(ctx, exynos4210_mux_clks,
ARRAY_SIZE(exynos4210_mux_clks));
- samsung_clk_register_div(exynos4210_div_clks,
+ samsung_clk_register_div(ctx, exynos4210_div_clks,
ARRAY_SIZE(exynos4210_div_clks));
- samsung_clk_register_gate(exynos4210_gate_clks,
+ samsung_clk_register_gate(ctx, exynos4210_gate_clks,
ARRAY_SIZE(exynos4210_gate_clks));
- samsung_clk_register_alias(exynos4210_aliases,
+ samsung_clk_register_alias(ctx, exynos4210_aliases,
ARRAY_SIZE(exynos4210_aliases));
} else {
- samsung_clk_register_mux(exynos4x12_mux_clks,
+ samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
ARRAY_SIZE(exynos4x12_mux_clks));
- samsung_clk_register_div(exynos4x12_div_clks,
+ samsung_clk_register_div(ctx, exynos4x12_div_clks,
ARRAY_SIZE(exynos4x12_div_clks));
- samsung_clk_register_gate(exynos4x12_gate_clks,
+ samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
ARRAY_SIZE(exynos4x12_gate_clks));
- samsung_clk_register_alias(exynos4x12_aliases,
+ samsung_clk_register_alias(ctx, exynos4x12_aliases,
ARRAY_SIZE(exynos4x12_aliases));
}
- samsung_clk_register_alias(exynos4_aliases,
+ samsung_clk_register_alias(ctx, exynos4_aliases,
ARRAY_SIZE(exynos4_aliases));
exynos4_clk_sleep_init();
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 82f14e1..af4f7fd 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -583,6 +583,8 @@ static struct of_device_id ext_clk_match[] __initdata = {
/* register exynox5250 clocks */
static void __init exynos5250_clk_init(struct device_node *np)
{
+ struct samsung_clk_provider *ctx;
+
if (np) {
reg_base = of_iomap(np, 0);
if (!reg_base)
@@ -591,11 +593,14 @@ static void __init exynos5250_clk_init(struct device_node *np)
panic("%s: unable to determine soc\n", __func__);
}
- samsung_clk_init(np, reg_base, nr_clks);
- samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
+ ctx = samsung_clk_init(np, reg_base, nr_clks);
+ if (!ctx)
+ panic("%s: unable to allocate context.\n", __func__);
+
+ samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
ext_clk_match);
- samsung_clk_register_mux(exynos5250_pll_pmux_clks,
+ samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks,
ARRAY_SIZE(exynos5250_pll_pmux_clks));
if (_get_rate("fin_pll") == 24 * MHZ)
@@ -604,17 +609,18 @@ static void __init exynos5250_clk_init(struct device_node *np)
if (_get_rate("mout_vpllsrc") == 24 * MHZ)
exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;
- samsung_clk_register_pll(exynos5250_plls, ARRAY_SIZE(exynos5250_plls),
- reg_base);
- samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
+ samsung_clk_register_pll(ctx, exynos5250_plls,
+ ARRAY_SIZE(exynos5250_plls),
+ reg_base);
+ samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks,
ARRAY_SIZE(exynos5250_fixed_rate_clks));
- samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks,
+ samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks,
ARRAY_SIZE(exynos5250_fixed_factor_clks));
- samsung_clk_register_mux(exynos5250_mux_clks,
+ samsung_clk_register_mux(ctx, exynos5250_mux_clks,
ARRAY_SIZE(exynos5250_mux_clks));
- samsung_clk_register_div(exynos5250_div_clks,
+ samsung_clk_register_div(ctx, exynos5250_div_clks,
ARRAY_SIZE(exynos5250_div_clks));
- samsung_clk_register_gate(exynos5250_gate_clks,
+ samsung_clk_register_gate(ctx, exynos5250_gate_clks,
ARRAY_SIZE(exynos5250_gate_clks));
exynos5250_clk_sleep_init();
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 9de5bfd..e5493cf 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -808,6 +808,8 @@ static struct of_device_id ext_clk_match[] __initdata = {
/* register exynos5420 clocks */
static void __init exynos5420_clk_init(struct device_node *np)
{
+ struct samsung_clk_provider *ctx;
+
if (np) {
reg_base = of_iomap(np, 0);
if (!reg_base)
@@ -816,21 +818,25 @@ static void __init exynos5420_clk_init(struct device_node *np)
panic("%s: unable to determine soc\n", __func__);
}
- samsung_clk_init(np, reg_base, nr_clks);
- samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks,
+ ctx = samsung_clk_init(np, reg_base, nr_clks);
+ if (!ctx)
+ panic("%s: unable to allocate context.\n", __func__);
+
+ samsung_clk_of_register_fixed_ext(ctx, exynos5420_fixed_rate_ext_clks,
ARRAY_SIZE(exynos5420_fixed_rate_ext_clks),
ext_clk_match);
- samsung_clk_register_pll(exynos5420_plls, ARRAY_SIZE(exynos5420_plls),
- reg_base);
- samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks,
+ samsung_clk_register_pll(ctx, exynos5420_plls,
+ ARRAY_SIZE(exynos5420_plls),
+ reg_base);
+ samsung_clk_register_fixed_rate(ctx, exynos5420_fixed_rate_clks,
ARRAY_SIZE(exynos5420_fixed_rate_clks));
- samsung_clk_register_fixed_factor(exynos5420_fixed_factor_clks,
+ samsung_clk_register_fixed_factor(ctx, exynos5420_fixed_factor_clks,
ARRAY_SIZE(exynos5420_fixed_factor_clks));
- samsung_clk_register_mux(exynos5420_mux_clks,
+ samsung_clk_register_mux(ctx, exynos5420_mux_clks,
ARRAY_SIZE(exynos5420_mux_clks));
- samsung_clk_register_div(exynos5420_div_clks,
+ samsung_clk_register_div(ctx, exynos5420_div_clks,
ARRAY_SIZE(exynos5420_div_clks));
- samsung_clk_register_gate(exynos5420_gate_clks,
+ samsung_clk_register_gate(ctx, exynos5420_gate_clks,
ARRAY_SIZE(exynos5420_gate_clks));
exynos5420_clk_sleep_init();
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
index e3e460a..c2f5d3c 100644
--- a/drivers/clk/samsung/clk-exynos5440.c
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -106,6 +106,7 @@ static struct of_device_id ext_clk_match[] __initdata = {
static void __init exynos5440_clk_init(struct device_node *np)
{
void __iomem *reg_base;
+ struct samsung_clk_provider *ctx;
reg_base = of_iomap(np, 0);
if (!reg_base) {
@@ -114,22 +115,25 @@ static void __init exynos5440_clk_init(struct device_node *np)
return;
}
- samsung_clk_init(np, reg_base, nr_clks);
- samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks,
+ ctx = samsung_clk_init(np, reg_base, nr_clks);
+ if (!ctx)
+ panic("%s: unable to allocate context.\n", __func__);
+
+ samsung_clk_of_register_fixed_ext(ctx, exynos5440_fixed_rate_ext_clks,
ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10);
samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10);
- samsung_clk_register_fixed_rate(exynos5440_fixed_rate_clks,
+ samsung_clk_register_fixed_rate(ctx, exynos5440_fixed_rate_clks,
ARRAY_SIZE(exynos5440_fixed_rate_clks));
- samsung_clk_register_fixed_factor(exynos5440_fixed_factor_clks,
+ samsung_clk_register_fixed_factor(ctx, exynos5440_fixed_factor_clks,
ARRAY_SIZE(exynos5440_fixed_factor_clks));
- samsung_clk_register_mux(exynos5440_mux_clks,
+ samsung_clk_register_mux(ctx, exynos5440_mux_clks,
ARRAY_SIZE(exynos5440_mux_clks));
- samsung_clk_register_div(exynos5440_div_clks,
+ samsung_clk_register_div(ctx, exynos5440_div_clks,
ARRAY_SIZE(exynos5440_div_clks));
- samsung_clk_register_gate(exynos5440_gate_clks,
+ samsung_clk_register_gate(ctx, exynos5440_gate_clks,
ARRAY_SIZE(exynos5440_gate_clks));
pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 529e11d..e8e8953 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -710,8 +710,9 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name,
return clk;
}
-static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,
- void __iomem *base)
+static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
+ struct samsung_pll_clock *pll_clk,
+ void __iomem *base)
{
struct samsung_clk_pll *pll;
struct clk *clk;
@@ -804,7 +805,7 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,
return;
}
- samsung_clk_add_lookup(clk, pll_clk->id);
+ samsung_clk_add_lookup(ctx, clk, pll_clk->id);
if (!pll_clk->alias)
return;
@@ -815,11 +816,12 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,
__func__, pll_clk->name, ret);
}
-void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list,
- unsigned int nr_pll, void __iomem *base)
+void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
+ struct samsung_pll_clock *pll_list,
+ unsigned int nr_pll, void __iomem *base)
{
int cnt;
for (cnt = 0; cnt < nr_pll; cnt++)
- _samsung_clk_register_pll(&pll_list[cnt], base);
+ _samsung_clk_register_pll(ctx, &pll_list[cnt], base);
}
diff --git a/drivers/clk/samsung/clk-s3c64xx.c b/drivers/clk/samsung/clk-s3c64xx.c
index a43cbde..b7d06ae 100644
--- a/drivers/clk/samsung/clk-s3c64xx.c
+++ b/drivers/clk/samsung/clk-s3c64xx.c
@@ -442,12 +442,14 @@ static struct samsung_clock_alias s3c6410_clock_aliases[] = {
ALIAS(MEM0_SROM, NULL, "srom"),
};
-static void __init s3c64xx_clk_register_fixed_ext(unsigned long fin_pll_f,
- unsigned long xusbxti_f)
+static void __init s3c64xx_clk_register_fixed_ext(
+ struct samsung_clk_provider *ctx,
+ unsigned long fin_pll_f,
+ unsigned long xusbxti_f)
{
s3c64xx_fixed_rate_ext_clks[0].fixed_rate = fin_pll_f;
s3c64xx_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f;
- samsung_clk_register_fixed_rate(s3c64xx_fixed_rate_ext_clks,
+ samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_ext_clks,
ARRAY_SIZE(s3c64xx_fixed_rate_ext_clks));
}
@@ -456,6 +458,8 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
unsigned long xusbxti_f, bool s3c6400,
void __iomem *base)
{
+ struct samsung_clk_provider *ctx;
+
reg_base = base;
is_s3c6400 = s3c6400;
@@ -465,48 +469,50 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
panic("%s: failed to map registers\n", __func__);
}
- samsung_clk_init(np, reg_base, NR_CLKS);
+ ctx = samsung_clk_init(np, reg_base, NR_CLKS);
+ if (!ctx)
+ panic("%s: unable to allocate context.\n", __func__);
/* Register external clocks. */
if (!np)
- s3c64xx_clk_register_fixed_ext(xtal_f, xusbxti_f);
+ s3c64xx_clk_register_fixed_ext(ctx, xtal_f, xusbxti_f);
/* Register PLLs. */
- samsung_clk_register_pll(s3c64xx_pll_clks,
+ samsung_clk_register_pll(ctx, s3c64xx_pll_clks,
ARRAY_SIZE(s3c64xx_pll_clks), reg_base);
/* Register common internal clocks. */
- samsung_clk_register_fixed_rate(s3c64xx_fixed_rate_clks,
+ samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_clks,
ARRAY_SIZE(s3c64xx_fixed_rate_clks));
- samsung_clk_register_mux(s3c64xx_mux_clks,
+ samsung_clk_register_mux(ctx, s3c64xx_mux_clks,
ARRAY_SIZE(s3c64xx_mux_clks));
- samsung_clk_register_div(s3c64xx_div_clks,
+ samsung_clk_register_div(ctx, s3c64xx_div_clks,
ARRAY_SIZE(s3c64xx_div_clks));
- samsung_clk_register_gate(s3c64xx_gate_clks,
+ samsung_clk_register_gate(ctx, s3c64xx_gate_clks,
ARRAY_SIZE(s3c64xx_gate_clks));
/* Register SoC-specific clocks. */
if (is_s3c6400) {
- samsung_clk_register_mux(s3c6400_mux_clks,
+ samsung_clk_register_mux(ctx, s3c6400_mux_clks,
ARRAY_SIZE(s3c6400_mux_clks));
- samsung_clk_register_div(s3c6400_div_clks,
+ samsung_clk_register_div(ctx, s3c6400_div_clks,
ARRAY_SIZE(s3c6400_div_clks));
- samsung_clk_register_gate(s3c6400_gate_clks,
+ samsung_clk_register_gate(ctx, s3c6400_gate_clks,
ARRAY_SIZE(s3c6400_gate_clks));
- samsung_clk_register_alias(s3c6400_clock_aliases,
+ samsung_clk_register_alias(ctx, s3c6400_clock_aliases,
ARRAY_SIZE(s3c6400_clock_aliases));
} else {
- samsung_clk_register_mux(s3c6410_mux_clks,
+ samsung_clk_register_mux(ctx, s3c6410_mux_clks,
ARRAY_SIZE(s3c6410_mux_clks));
- samsung_clk_register_div(s3c6410_div_clks,
+ samsung_clk_register_div(ctx, s3c6410_div_clks,
ARRAY_SIZE(s3c6410_div_clks));
- samsung_clk_register_gate(s3c6410_gate_clks,
+ samsung_clk_register_gate(ctx, s3c6410_gate_clks,
ARRAY_SIZE(s3c6410_gate_clks));
- samsung_clk_register_alias(s3c6410_clock_aliases,
+ samsung_clk_register_alias(ctx, s3c6410_clock_aliases,
ARRAY_SIZE(s3c6410_clock_aliases));
}
- samsung_clk_register_alias(s3c64xx_clock_aliases,
+ samsung_clk_register_alias(ctx, s3c64xx_clock_aliases,
ARRAY_SIZE(s3c64xx_clock_aliases));
s3c64xx_clk_sleep_init();
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index 91bec3e..20de446 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -15,11 +15,6 @@
#include "clk.h"
static DEFINE_SPINLOCK(lock);
-static struct clk **clk_table;
-static void __iomem *reg_base;
-#ifdef CONFIG_OF
-static struct clk_onecell_data clk_data;
-#endif
void samsung_clk_save(void __iomem *base,
struct samsung_clk_reg_dump *rd,
@@ -55,40 +50,53 @@ struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
}
/* setup the essentials required to support clock lookup using ccf */
-void __init samsung_clk_init(struct device_node *np, void __iomem *base,
- unsigned long nr_clks)
+struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
+ void __iomem *base, unsigned long nr_clks)
{
- reg_base = base;
+ struct samsung_clk_provider *ctx;
+ struct clk **clk_table;
+ int ret;
+
+ if (!np)
+ return NULL;
+
+ ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL);
+ if (!ctx)
+ panic("could not allocate clock provider context.\n");
clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
if (!clk_table)
panic("could not allocate clock lookup table\n");
- if (!np)
- return;
+ ctx->reg_base = base;
+ ctx->clk_data.clks = clk_table;
+ ctx->clk_data.clk_num = nr_clks;
-#ifdef CONFIG_OF
- clk_data.clks = clk_table;
- clk_data.clk_num = nr_clks;
- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-#endif
+ ret = of_clk_add_provider(np, of_clk_src_onecell_get,
+ &ctx->clk_data);
+ if (ret)
+ panic("could not register clock provide\n");
+
+ return ctx;
}
/* add a clock instance to the clock lookup table used for dt based lookup */
-void samsung_clk_add_lookup(struct clk *clk, unsigned int id)
+void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk,
+ unsigned int id)
{
- if (clk_table && id)
- clk_table[id] = clk;
+ if (ctx->clk_data.clks && id)
+ ctx->clk_data.clks[id] = clk;
}
/* register a list of aliases */
-void __init samsung_clk_register_alias(struct samsung_clock_alias *list,
- unsigned int nr_clk)
+void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx,
+ struct samsung_clock_alias *list,
+ unsigned int nr_clk)
{
struct clk *clk;
unsigned int idx, ret;
- if (!clk_table) {
+ if (!ctx->clk_data.clks) {
pr_err("%s: clock table missing\n", __func__);
return;
}
@@ -100,7 +108,7 @@ void __init samsung_clk_register_alias(struct samsung_clock_alias *list,
continue;
}
- clk = clk_table[list->id];
+ clk = ctx->clk_data.clks[list->id];
if (!clk) {
pr_err("%s: failed to find clock %d\n", __func__,
list->id);
@@ -115,7 +123,7 @@ void __init samsung_clk_register_alias(struct samsung_clock_alias *list,
}
/* register a list of fixed clocks */
-void __init samsung_clk_register_fixed_rate(
+void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx,
struct samsung_fixed_rate_clock *list, unsigned int nr_clk)
{
struct clk *clk;
@@ -130,7 +138,7 @@ void __init samsung_clk_register_fixed_rate(
continue;
}
- samsung_clk_add_lookup(clk, list->id);
+ samsung_clk_add_lookup(ctx, clk, list->id);
/*
* Unconditionally add a clock lookup for the fixed rate clocks.
@@ -144,7 +152,7 @@ void __init samsung_clk_register_fixed_rate(
}
/* register a list of fixed factor clocks */
-void __init samsung_clk_register_fixed_factor(
+void __init samsung_clk_register_fixed_factor(struct samsung_clk_provider *ctx,
struct samsung_fixed_factor_clock *list, unsigned int nr_clk)
{
struct clk *clk;
@@ -159,20 +167,22 @@ void __init samsung_clk_register_fixed_factor(
continue;
}
- samsung_clk_add_lookup(clk, list->id);
+ samsung_clk_add_lookup(ctx, clk, list->id);
}
}
/* register a list of mux clocks */
-void __init samsung_clk_register_mux(struct samsung_mux_clock *list,
- unsigned int nr_clk)
+void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
+ struct samsung_mux_clock *list,
+ unsigned int nr_clk)
{
struct clk *clk;
unsigned int idx, ret;
for (idx = 0; idx < nr_clk; idx++, list++) {
clk = clk_register_mux(NULL, list->name, list->parent_names,
- list->num_parents, list->flags, reg_base + list->offset,
+ list->num_parents, list->flags,
+ ctx->reg_base + list->offset,
list->shift, list->width, list->mux_flags, &lock);
if (IS_ERR(clk)) {
pr_err("%s: failed to register clock %s\n", __func__,
@@ -180,7 +190,7 @@ void __init samsung_clk_register_mux(struct samsung_mux_clock *list,
continue;
}
- samsung_clk_add_lookup(clk, list->id);
+ samsung_clk_add_lookup(ctx, clk, list->id);
/* register a clock lookup only if a clock alias is specified */
if (list->alias) {
@@ -194,8 +204,9 @@ void __init samsung_clk_register_mux(struct samsung_mux_clock *list,
}
/* register a list of div clocks */
-void __init samsung_clk_register_div(struct samsung_div_clock *list,
- unsigned int nr_clk)
+void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
+ struct samsung_div_clock *list,
+ unsigned int nr_clk)
{
struct clk *clk;
unsigned int idx, ret;
@@ -203,22 +214,22 @@ void __init samsung_clk_register_div(struct samsung_div_clock *list,
for (idx = 0; idx < nr_clk; idx++, list++) {
if (list->table)
clk = clk_register_divider_table(NULL, list->name,
- list->parent_name, list->flags,
- reg_base + list->offset, list->shift,
- list->width, list->div_flags,
- list->table, &lock);
+ list->parent_name, list->flags,
+ ctx->reg_base + list->offset,
+ list->shift, list->width, list->div_flags,
+ list->table, &lock);
else
clk = clk_register_divider(NULL, list->name,
- list->parent_name, list->flags,
- reg_base + list->offset, list->shift,
- list->width, list->div_flags, &lock);
+ list->parent_name, list->flags,
+ ctx->reg_base + list->offset, list->shift,
+ list->width, list->div_flags, &lock);
if (IS_ERR(clk)) {
pr_err("%s: failed to register clock %s\n", __func__,
list->name);
continue;
}
- samsung_clk_add_lookup(clk, list->id);
+ samsung_clk_add_lookup(ctx, clk, list->id);
/* register a clock lookup only if a clock alias is specified */
if (list->alias) {
@@ -232,15 +243,16 @@ void __init samsung_clk_register_div(struct samsung_div_clock *list,
}
/* register a list of gate clocks */
-void __init samsung_clk_register_gate(struct samsung_gate_clock *list,
- unsigned int nr_clk)
+void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
+ struct samsung_gate_clock *list,
+ unsigned int nr_clk)
{
struct clk *clk;
unsigned int idx, ret;
for (idx = 0; idx < nr_clk; idx++, list++) {
clk = clk_register_gate(NULL, list->name, list->parent_name,
- list->flags, reg_base + list->offset,
+ list->flags, ctx->reg_base + list->offset,
list->bit_idx, list->gate_flags, &lock);
if (IS_ERR(clk)) {
pr_err("%s: failed to register clock %s\n", __func__,
@@ -257,7 +269,7 @@ void __init samsung_clk_register_gate(struct samsung_gate_clock *list,
__func__, list->alias);
}
- samsung_clk_add_lookup(clk, list->id);
+ samsung_clk_add_lookup(ctx, clk, list->id);
}
}
@@ -266,21 +278,21 @@ void __init samsung_clk_register_gate(struct samsung_gate_clock *list,
* tree and register it
*/
#ifdef CONFIG_OF
-void __init samsung_clk_of_register_fixed_ext(
+void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx,
struct samsung_fixed_rate_clock *fixed_rate_clk,
unsigned int nr_fixed_rate_clk,
struct of_device_id *clk_matches)
{
const struct of_device_id *match;
- struct device_node *np;
+ struct device_node *clk_np;
u32 freq;
- for_each_matching_node_and_match(np, clk_matches, &match) {
- if (of_property_read_u32(np, "clock-frequency", &freq))
+ for_each_matching_node_and_match(clk_np, clk_matches, &match) {
+ if (of_property_read_u32(clk_np, "clock-frequency", &freq))
continue;
fixed_rate_clk[(u32)match->data].fixed_rate = freq;
}
- samsung_clk_register_fixed_rate(fixed_rate_clk, nr_fixed_rate_clk);
+ samsung_clk_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk);
}
#endif
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index c7141ba..433bab3 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -21,6 +21,17 @@
#include <linux/of_address.h>
#include "clk-pll.h"
+/* Context node which holds information about the clock provider. */
+/**
+ * struct samsung_clk_provider: information about clock plovider
+ * @reg_base: virtual address for the register base.
+ * @clk_data: holds clock related data like clk* and number of clocks.
+ */
+struct samsung_clk_provider {
+ void __iomem *reg_base;
+ struct clk_onecell_data clk_data;
+};
+
/**
* struct samsung_clock_alias: information about mux clock
* @id: platform specific id of the clock.
@@ -312,29 +323,40 @@ struct samsung_pll_clock {
__PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \
_lock, _con, _rtable, _alias)
-extern void __init samsung_clk_init(struct device_node *np, void __iomem *base,
- unsigned long nr_clks);
+extern struct samsung_clk_provider *__init samsung_clk_init(
+ struct device_node *np, void __iomem *base,
+ unsigned long nr_clks);
extern void __init samsung_clk_of_register_fixed_ext(
+ struct samsung_clk_provider *ctx,
struct samsung_fixed_rate_clock *fixed_rate_clk,
unsigned int nr_fixed_rate_clk,
struct of_device_id *clk_matches);
-extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id);
+extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
+ struct clk *clk, unsigned int id);
-extern void samsung_clk_register_alias(struct samsung_clock_alias *list,
- unsigned int nr_clk);
+extern void samsung_clk_register_alias(struct samsung_clk_provider *ctx,
+ struct samsung_clock_alias *list,
+ unsigned int nr_clk);
extern void __init samsung_clk_register_fixed_rate(
- struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk);
+ struct samsung_clk_provider *ctx,
+ struct samsung_fixed_rate_clock *clk_list,
+ unsigned int nr_clk);
extern void __init samsung_clk_register_fixed_factor(
- struct samsung_fixed_factor_clock *list, unsigned int nr_clk);
-extern void __init samsung_clk_register_mux(struct samsung_mux_clock *clk_list,
+ struct samsung_clk_provider *ctx,
+ struct samsung_fixed_factor_clock *list,
+ unsigned int nr_clk);
+extern void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
+ struct samsung_mux_clock *clk_list,
unsigned int nr_clk);
-extern void __init samsung_clk_register_div(struct samsung_div_clock *clk_list,
+extern void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
+ struct samsung_div_clock *clk_list,
unsigned int nr_clk);
-extern void __init samsung_clk_register_gate(
+extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
struct samsung_gate_clock *clk_list, unsigned int nr_clk);
-extern void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list,
- unsigned int nr_clk, void __iomem *base);
+extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
+ struct samsung_pll_clock *pll_list,
+ unsigned int nr_clk, void __iomem *base);
extern unsigned long _get_rate(const char *clk_name);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 5/7] clk/samsung: add support for pll2550xx
2013-12-06 15:56 [PATCH 0/7] exynos: add basic support for exynos5260 SoC Rahul Sharma
` (3 preceding siblings ...)
2013-12-06 15:56 ` [PATCH 4/7] clk/samsung: add support for multuple clock providers Rahul Sharma
@ 2013-12-06 15:56 ` Rahul Sharma
2013-12-09 8:06 ` Sachin Kamat
2013-12-19 12:01 ` Tomasz Figa
2013-12-06 15:56 ` [PATCH 6/7] clk/samsung: add support for pll2650xx Rahul Sharma
5 siblings, 2 replies; 28+ messages in thread
From: Rahul Sharma @ 2013-12-06 15:56 UTC (permalink / raw)
To: linux-arm-kernel
From: Pankaj Dubey <pankaj.dubey@samsung.com>
exynos5260 use pll2520xx and it has different bitfields
for P,M,S values as compared to pll2550xx. Support for
pll2520xx is added here.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
---
drivers/clk/samsung/clk-pll.c | 107 +++++++++++++++++++++++++++++++++++++++++
drivers/clk/samsung/clk-pll.h | 1 +
2 files changed, 108 insertions(+)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index e8e8953..237a889 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -710,6 +710,107 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name,
return clk;
}
+/*
+ * PLL2550xx Clock Type
+ */
+
+/* Maximum lock time can be 270 * PDIV cycles */
+#define PLL2550XX_LOCK_FACTOR (270)
+
+#define PLL2550XX_MDIV_MASK (0x3FF)
+#define PLL2550XX_PDIV_MASK (0x3F)
+#define PLL2550XX_SDIV_MASK (0x7)
+#define PLL2550XX_LOCK_STAT_MASK (0x1)
+#define PLL2550XX_MDIV_SHIFT (9)
+#define PLL2550XX_PDIV_SHIFT (3)
+#define PLL2550XX_SDIV_SHIFT (0)
+#define PLL2550XX_LOCK_STAT_SHIFT (21)
+
+static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 mdiv, pdiv, sdiv, pll_con;
+ u64 fvco = parent_rate;
+
+ pll_con = __raw_readl(pll->con_reg);
+ mdiv = (pll_con >> PLL2550XX_MDIV_SHIFT) & PLL2550XX_MDIV_MASK;
+ pdiv = (pll_con >> PLL2550XX_PDIV_SHIFT) & PLL2550XX_PDIV_MASK;
+ sdiv = (pll_con >> PLL2550XX_SDIV_SHIFT) & PLL2550XX_SDIV_MASK;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+
+ return (unsigned long)fvco;
+}
+
+static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con)
+{
+ if ((mdiv != ((pll_con >> PLL2550XX_MDIV_SHIFT) &
+ PLL2550XX_MDIV_MASK)) ||
+ (pdiv != ((pll_con >> PLL2550XX_PDIV_SHIFT) &
+ PLL2550XX_PDIV_MASK)))
+ return 1;
+ else
+ return 0;
+}
+
+static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 tmp;
+
+ /* Get required rate settings from table */
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, __clk_get_name(hw->clk));
+ return -EINVAL;
+ }
+
+ tmp = __raw_readl(pll->con_reg);
+
+ if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) {
+ /* If only s change, change just s value only*/
+ tmp &= ~(PLL2550XX_SDIV_MASK << PLL2550XX_SDIV_SHIFT);
+ tmp |= rate->sdiv << PLL2550XX_SDIV_SHIFT;
+ __raw_writel(tmp, pll->con_reg);
+ } else {
+ /* Set PLL lock time. */
+ __raw_writel(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg);
+
+ /* Change PLL PMS values */
+ tmp &= ~((PLL2550XX_MDIV_MASK << PLL2550XX_MDIV_SHIFT) |
+ (PLL2550XX_PDIV_MASK << PLL2550XX_PDIV_SHIFT) |
+ (PLL2550XX_SDIV_MASK << PLL2550XX_SDIV_SHIFT));
+ tmp |= (rate->mdiv << PLL2550XX_MDIV_SHIFT) |
+ (rate->pdiv << PLL2550XX_PDIV_SHIFT) |
+ (rate->sdiv << PLL2550XX_SDIV_SHIFT);
+ __raw_writel(tmp, pll->con_reg);
+
+ /* wait_lock_time */
+ do {
+ cpu_relax();
+ tmp = __raw_readl(pll->con_reg);
+ } while (!(tmp & (PLL2550XX_LOCK_STAT_MASK
+ << PLL2550XX_LOCK_STAT_SHIFT)));
+ }
+
+ return 0;
+}
+
+static const struct clk_ops samsung_pll2550xx_clk_ops = {
+ .recalc_rate = samsung_pll2550xx_recalc_rate,
+ .round_rate = samsung_pll_round_rate,
+ .set_rate = samsung_pll2550xx_set_rate,
+};
+
+static const struct clk_ops samsung_pll2550xx_clk_min_ops = {
+ .recalc_rate = samsung_pll2550xx_recalc_rate,
+};
+
static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
struct samsung_pll_clock *pll_clk,
void __iomem *base)
@@ -787,6 +888,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
else
init.ops = &samsung_pll46xx_clk_ops;
break;
+ case pll_2550xx:
+ if (!pll->rate_table)
+ init.ops = &samsung_pll2550xx_clk_min_ops;
+ else
+ init.ops = &samsung_pll2550xx_clk_ops;
+ break;
default:
pr_warn("%s: Unknown pll type for pll clk %s\n",
__func__, pll_clk->name);
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index 6c39030..e106470 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -25,6 +25,7 @@ enum samsung_pll_type {
pll_4650c,
pll_6552,
pll_6553,
+ pll_2550xx,
};
#define PLL_35XX_RATE(_rate, _m, _p, _s) \
--
1.7.9.5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 6/7] clk/samsung: add support for pll2650xx
2013-12-06 15:56 [PATCH 0/7] exynos: add basic support for exynos5260 SoC Rahul Sharma
` (4 preceding siblings ...)
2013-12-06 15:56 ` [PATCH 5/7] clk/samsung: add support for pll2550xx Rahul Sharma
@ 2013-12-06 15:56 ` Rahul Sharma
2013-12-09 8:09 ` Sachin Kamat
2013-12-19 11:45 ` Tomasz Figa
5 siblings, 2 replies; 28+ messages in thread
From: Rahul Sharma @ 2013-12-06 15:56 UTC (permalink / raw)
To: linux-arm-kernel
Add support for pll2650xx in samsung pll file. This pll variant
is close to pll36xx but uses CON2 registers instead of CON1.
Aud_pll in Exynos5260 is pll2650xx and uses this code.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
---
drivers/clk/samsung/clk-pll.c | 101 +++++++++++++++++++++++++++++++++++++++++
drivers/clk/samsung/clk-pll.h | 2 +-
2 files changed, 102 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 237a889..60c5679 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -811,6 +811,101 @@ static const struct clk_ops samsung_pll2550xx_clk_min_ops = {
.recalc_rate = samsung_pll2550xx_recalc_rate,
};
+/*
+ * PLL2650XX Clock Type
+ */
+
+/* Maximum lock time can be 3000 * PDIV cycles */
+#define PLL2650XX_LOCK_FACTOR (3000)
+
+#define PLL2650XX_MDIV_SHIFT (9)
+#define PLL2650XX_PDIV_SHIFT (3)
+#define PLL2650XX_SDIV_SHIFT (0)
+#define PLL2650XX_KDIV_SHIFT (0)
+#define PLL2650XX_MDIV_MASK (0x1ff)
+#define PLL2650XX_PDIV_MASK (0x3f)
+#define PLL2650XX_SDIV_MASK (0x7)
+#define PLL2650XX_KDIV_MASK (0xffff)
+#define PLL2650XX_PLL_ENABLE_SHIFT (23)
+#define PLL2650XX_PLL_LOCKTIME_SHIFT (21)
+#define PLL2650XX_PLL_FOUTMASK_SHIFT (31)
+
+static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 mdiv, pdiv, sdiv, pll_con0, pll_con2;
+ s16 kdiv;
+ u64 fvco = parent_rate;
+
+ pll_con0 = __raw_readl(pll->con_reg);
+ pll_con2 = __raw_readl(pll->con_reg + 8);
+ mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK;
+ pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK;
+ sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK;
+ kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK);
+
+ fvco *= (mdiv << 16) + kdiv;
+ do_div(fvco, (pdiv << sdiv));
+ fvco >>= 16;
+
+ return (unsigned long)fvco;
+}
+
+static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 tmp, pll_con0, pll_con2;
+ const struct samsung_pll_rate_table *rate;
+
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, __clk_get_name(hw->clk));
+ return -EINVAL;
+ }
+
+ pll_con0 = __raw_readl(pll->con_reg);
+ pll_con2 = __raw_readl(pll->con_reg + 8);
+
+ /* Change PLL PMS values */
+ pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT |
+ PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT |
+ PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT);
+ pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT;
+ pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT;
+ pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT;
+ pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT;
+ pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT;
+
+ pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT);
+ pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK)
+ << PLL2650XX_KDIV_SHIFT;
+
+ /* Set PLL lock time. */
+ __raw_writel(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);
+
+ __raw_writel(pll_con0, pll->con_reg);
+ __raw_writel(pll_con2, pll->con_reg + 8);
+
+ do {
+ tmp = __raw_readl(pll->con_reg);
+ } while (!(tmp & (0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT)));
+
+ return 0;
+}
+
+static const struct clk_ops samsung_pll2650xx_clk_ops = {
+ .recalc_rate = samsung_pll2650xx_recalc_rate,
+ .set_rate = samsung_pll2650xx_set_rate,
+ .round_rate = samsung_pll_round_rate,
+};
+
+static const struct clk_ops samsung_pll2650xx_clk_min_ops = {
+ .recalc_rate = samsung_pll2650xx_recalc_rate,
+};
+
static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
struct samsung_pll_clock *pll_clk,
void __iomem *base)
@@ -894,6 +989,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
else
init.ops = &samsung_pll2550xx_clk_ops;
break;
+ case pll_2650xx:
+ if (!pll->rate_table)
+ init.ops = &samsung_pll2650xx_clk_min_ops;
+ else
+ init.ops = &samsung_pll2650xx_clk_ops;
+ break;
default:
pr_warn("%s: Unknown pll type for pll clk %s\n",
__func__, pll_clk->name);
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index e106470..b326e94 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -26,6 +26,7 @@ enum samsung_pll_type {
pll_6552,
pll_6553,
pll_2550xx,
+ pll_2650xx,
};
#define PLL_35XX_RATE(_rate, _m, _p, _s) \
@@ -93,5 +94,4 @@ struct samsung_pll_rate_table {
extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
const char *pname, const void __iomem *reg_base,
const unsigned long offset);
-
#endif /* __SAMSUNG_CLK_PLL_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data
2013-12-06 15:56 ` [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data Rahul Sharma
@ 2013-12-09 4:51 ` Sachin Kamat
2013-12-09 6:36 ` Rahul Sharma
2014-01-03 9:25 ` Rahul Sharma
2013-12-10 16:04 ` Tomasz Figa
1 sibling, 2 replies; 28+ messages in thread
From: Sachin Kamat @ 2013-12-09 4:51 UTC (permalink / raw)
To: linux-arm-kernel
Hi Rahul, Young-Gun,
On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote:
> From: Young-Gun Jang <yg1004.jang@samsung.com>
>
> Add Samsung Exynos5260 SoC specific data to enable pinctrl
> support for all platforms based on EXYNOS5260.
>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
> Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Author's (Young-Gun Jang) signed-off by is missing here.
[snip]
> +
> +/* pin banks of exynos5260 pin-controller 2 */
> +static struct samsung_pin_bank exynos5260_pin_banks2[] = {
> + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
> + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
> +};
> +
> +/*
> + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5420 SoC includes
s/5420/5260 ?
--
With warm regards,
Sachin
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 1/7] ARM: EXYNOS: initial board support for exynos5260 SoC
2013-12-06 15:56 ` [PATCH 1/7] ARM: EXYNOS: initial board " Rahul Sharma
@ 2013-12-09 6:23 ` Sachin Kamat
2013-12-09 6:33 ` Rahul Sharma
2013-12-23 4:39 ` Rahul Sharma
2013-12-10 15:57 ` Tomasz Figa
1 sibling, 2 replies; 28+ messages in thread
From: Sachin Kamat @ 2013-12-09 6:23 UTC (permalink / raw)
To: linux-arm-kernel
Hi Rahul,
On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote:
> From: Pankaj Dubey <pankaj.dubey@samsung.com>
>
> This patch add basic arch side support for exynos5260 SoC.
>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Since you are posting the patch, your signed off is also required.
[snip]
> void exynos4_restart(enum reboot_mode mode, const char *cmd)
> {
> __raw_writel(0x1, S5P_SWRESET);
> @@ -371,7 +387,8 @@ static void __init exynos4_map_io(void)
> static void __init exynos5_map_io(void)
> {
> iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
> -
> + if (soc_is_exynos5260())
> + iotable_init(exynos5260_iodesc, ARRAY_SIZE(exynos5260_iodesc));
Add this after 5250 to maintain numerical order.
> if (soc_is_exynos5250())
> iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
> }
[snip]
>
> #define S5P_VA_SYSRAM S3C_ADDR(0x02400000)
> #define S5P_VA_SYSRAM_NS S3C_ADDR(0x02410000)
> +
Unnecessary blank line addition.
--
With warm regards,
Sachin
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 1/7] ARM: EXYNOS: initial board support for exynos5260 SoC
2013-12-09 6:23 ` Sachin Kamat
@ 2013-12-09 6:33 ` Rahul Sharma
2013-12-23 4:39 ` Rahul Sharma
1 sibling, 0 replies; 28+ messages in thread
From: Rahul Sharma @ 2013-12-09 6:33 UTC (permalink / raw)
To: linux-arm-kernel
Thanks Sachin,
On 9 December 2013 11:53, Sachin Kamat <sachin.kamat@linaro.org> wrote:
> Hi Rahul,
>
> On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote:
>> From: Pankaj Dubey <pankaj.dubey@samsung.com>
>>
>> This patch add basic arch side support for exynos5260 SoC.
>>
>> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
>> Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
>
> Since you are posting the patch, your signed off is also required.
>
> [snip]
>
>> void exynos4_restart(enum reboot_mode mode, const char *cmd)
>> {
>> __raw_writel(0x1, S5P_SWRESET);
>> @@ -371,7 +387,8 @@ static void __init exynos4_map_io(void)
>> static void __init exynos5_map_io(void)
>> {
>> iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
>> -
>> + if (soc_is_exynos5260())
>> + iotable_init(exynos5260_iodesc, ARRAY_SIZE(exynos5260_iodesc));
>
> Add this after 5250 to maintain numerical order.
>
>> if (soc_is_exynos5250())
>> iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
>> }
>
> [snip]
>>
>> #define S5P_VA_SYSRAM S3C_ADDR(0x02400000)
>> #define S5P_VA_SYSRAM_NS S3C_ADDR(0x02410000)
>> +
> Unnecessary blank line addition.
>
I will correct all these in next version.
Regards,
Rahul Sharma
>
> --
> With warm regards,
> Sachin
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data
2013-12-09 4:51 ` Sachin Kamat
@ 2013-12-09 6:36 ` Rahul Sharma
2014-01-03 9:25 ` Rahul Sharma
1 sibling, 0 replies; 28+ messages in thread
From: Rahul Sharma @ 2013-12-09 6:36 UTC (permalink / raw)
To: linux-arm-kernel
On 9 December 2013 10:21, Sachin Kamat <sachin.kamat@linaro.org> wrote:
> Hi Rahul, Young-Gun,
>
> On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote:
>> From: Young-Gun Jang <yg1004.jang@samsung.com>
>>
>> Add Samsung Exynos5260 SoC specific data to enable pinctrl
>> support for all platforms based on EXYNOS5260.
>>
>> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
>> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
>> Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
>
> Author's (Young-Gun Jang) signed-off by is missing here.
I will add his signed-off.
>
> [snip]
>
>> +
>> +/* pin banks of exynos5260 pin-controller 2 */
>> +static struct samsung_pin_bank exynos5260_pin_banks2[] = {
>> + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
>> + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
>> +};
>> +
>> +/*
>> + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5420 SoC includes
>
> s/5420/5260 ?
>
It should be 5260. I will change this in next version.
Thanks,
Rahul Sharma.
> --
> With warm regards,
> Sachin
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 5/7] clk/samsung: add support for pll2550xx
2013-12-06 15:56 ` [PATCH 5/7] clk/samsung: add support for pll2550xx Rahul Sharma
@ 2013-12-09 8:06 ` Sachin Kamat
2013-12-19 12:01 ` Tomasz Figa
1 sibling, 0 replies; 28+ messages in thread
From: Sachin Kamat @ 2013-12-09 8:06 UTC (permalink / raw)
To: linux-arm-kernel
Hi Rahul,
On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote:
> From: Pankaj Dubey <pankaj.dubey@samsung.com>
>
> exynos5260 use pll2520xx and it has different bitfields
> for P,M,S values as compared to pll2550xx. Support for
> pll2520xx is added here.
This is a bit confusing to me. The commit message says "Support for
pll2520xx is added". However, the patch subject and the entire code looks to
be adding support for 2550xx.
--
With warm regards,
Sachin
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 6/7] clk/samsung: add support for pll2650xx
2013-12-06 15:56 ` [PATCH 6/7] clk/samsung: add support for pll2650xx Rahul Sharma
@ 2013-12-09 8:09 ` Sachin Kamat
2013-12-19 11:45 ` Tomasz Figa
1 sibling, 0 replies; 28+ messages in thread
From: Sachin Kamat @ 2013-12-09 8:09 UTC (permalink / raw)
To: linux-arm-kernel
Hi Rahul,
On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote:
> Add support for pll2650xx in samsung pll file. This pll variant
> is close to pll36xx but uses CON2 registers instead of CON1.
>
> Aud_pll in Exynos5260 is pll2650xx and uses this code.
>
> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
> ---
> drivers/clk/samsung/clk-pll.c | 101 +++++++++++++++++++++++++++++++++++++++++
> drivers/clk/samsung/clk-pll.h | 2 +-
> 2 files changed, 102 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index 237a889..60c5679 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -811,6 +811,101 @@ static const struct clk_ops samsung_pll2550xx_clk_min_ops = {
> .recalc_rate = samsung_pll2550xx_recalc_rate,
> };
>
> +/*
> + * PLL2650XX Clock Type
> + */
> +
> +/* Maximum lock time can be 3000 * PDIV cycles */
> +#define PLL2650XX_LOCK_FACTOR (3000)
> +
> +#define PLL2650XX_MDIV_SHIFT (9)
> +#define PLL2650XX_PDIV_SHIFT (3)
> +#define PLL2650XX_SDIV_SHIFT (0)
> +#define PLL2650XX_KDIV_SHIFT (0)
> +#define PLL2650XX_MDIV_MASK (0x1ff)
> +#define PLL2650XX_PDIV_MASK (0x3f)
> +#define PLL2650XX_SDIV_MASK (0x7)
> +#define PLL2650XX_KDIV_MASK (0xffff)
> +#define PLL2650XX_PLL_ENABLE_SHIFT (23)
> +#define PLL2650XX_PLL_LOCKTIME_SHIFT (21)
> +#define PLL2650XX_PLL_FOUTMASK_SHIFT (31)
nit: Braces are unnecessary.
--
With warm regards,
Sachin
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 1/7] ARM: EXYNOS: initial board support for exynos5260 SoC
2013-12-06 15:56 ` [PATCH 1/7] ARM: EXYNOS: initial board " Rahul Sharma
2013-12-09 6:23 ` Sachin Kamat
@ 2013-12-10 15:57 ` Tomasz Figa
2014-01-03 9:24 ` Rahul Sharma
1 sibling, 1 reply; 28+ messages in thread
From: Tomasz Figa @ 2013-12-10 15:57 UTC (permalink / raw)
To: linux-arm-kernel
Hi Pankaj, Rahul, Arun,
In addition to issues already pointed by Sachin, please also see my
comments inline.
On Friday 06 of December 2013 21:26:25 Rahul Sharma wrote:
> From: Pankaj Dubey <pankaj.dubey@samsung.com>
>
> This patch add basic arch side support for exynos5260 SoC.
>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
> ---
> arch/arm/mach-exynos/Kconfig | 9 +++++++++
> arch/arm/mach-exynos/common.c | 19 ++++++++++++++++++-
> arch/arm/mach-exynos/cpuidle.c | 2 +-
> arch/arm/mach-exynos/include/mach/map.h | 1 +
> arch/arm/mach-exynos/include/mach/regs-pmu.h | 4 ++++
> arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
> arch/arm/plat-samsung/include/plat/cpu.h | 8 ++++++++
> arch/arm/plat-samsung/include/plat/map-s5p.h | 1 +
> 8 files changed, 43 insertions(+), 2 deletions(-)
[snip]
> diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
> index ddbfe87..405c11a 100644
> --- a/arch/arm/mach-exynos/cpuidle.c
> +++ b/arch/arm/mach-exynos/cpuidle.c
> @@ -120,7 +120,7 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
> cpu_suspend(0, idle_finisher);
>
> #ifdef CONFIG_SMP
> - if (!soc_is_exynos5250())
> + if (!soc_is_exynos5250() || soc_is_exynos5260())
The added OR condition doesn't affect the if condition in any way, because
when running on Exynos5260, soc_is_exynos5250() will return false and make
the whole condition evaluate to true.
Shouldn't it be
if (!soc_is_exynos5250() && !soc_is_exynos5260())
if Exynos5260 doesn't need scu_enable(), or left as is if it needs?
> scu_enable(S5P_VA_SCU);
> #endif
> cpu_pm_exit();
> diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
> index 7b046b5..bd6fa02 100644
> --- a/arch/arm/mach-exynos/include/mach/map.h
> +++ b/arch/arm/mach-exynos/include/mach/map.h
> @@ -29,6 +29,7 @@
> #define EXYNOS4210_PA_SYSRAM_NS 0x0203F000
> #define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000
> #define EXYNOS5250_PA_SYSRAM_NS 0x0204F000
> +#define EXYNOS5260_PA_SYSRAM_NS 0x02073000
>
> #define EXYNOS_PA_CHIPID 0x10000000
>
> diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
> index 2cdb63e..09ae29a 100644
> --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
> +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
> @@ -234,6 +234,10 @@
>
> #define EXYNOS5_SYS_WDTRESET (1 << 20)
>
> +#define EXYNOS5260_A7_WDTRST (1 << 24)
> +#define EXYNOS5260_A15_WDTRST (1 << 23)
> +#define EXYNOS5260_SYS_WDTRESET (EXYNOS5260_A7_WDTRST || EXYNOS5260_A15_WDTRST)
> +
Are these definitions needed? I don't see any user in this patch.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data
2013-12-06 15:56 ` [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data Rahul Sharma
2013-12-09 4:51 ` Sachin Kamat
@ 2013-12-10 16:04 ` Tomasz Figa
2014-01-03 9:26 ` Rahul Sharma
1 sibling, 1 reply; 28+ messages in thread
From: Tomasz Figa @ 2013-12-10 16:04 UTC (permalink / raw)
To: linux-arm-kernel
Hi Young-Gun, Pankaj, Rahul, Arun,
Please see my comments inline.
On Friday 06 of December 2013 21:26:26 Rahul Sharma wrote:
> From: Young-Gun Jang <yg1004.jang@samsung.com>
>
> Add Samsung Exynos5260 SoC specific data to enable pinctrl
> support for all platforms based on EXYNOS5260.
[snip]
> diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
> index 155b1b3..9a93df6 100644
> --- a/drivers/pinctrl/pinctrl-exynos.c
> +++ b/drivers/pinctrl/pinctrl-exynos.c
> @@ -1042,6 +1042,88 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
> },
> };
>
> +/* pin banks of exynos5260 pin-controller 0 */
> +static struct samsung_pin_bank exynos5260_pin_banks0[] = {
> + EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
> + EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
> + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
> + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
> + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
> + EXYNOS_PIN_BANK_EINTG(5, 0x0A0, "gpb2", 0x14),
> + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
> + EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpb4", 0x1c),
> + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
> + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
> + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
> + EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
> + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
> + EXYNOS_PIN_BANK_EINTG(5, 0x1A0, "gpe1", 0x34),
> + EXYNOS_PIN_BANK_EINTG(4, 0x1C0, "gpf0", 0x38),
> + EXYNOS_PIN_BANK_EINTG(8, 0x1E0, "gpf1", 0x3c),
> + EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
> + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
> + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
> + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
> + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
nit: Please use lowercase hexadecimal characters. Despite of already
existing code, lowercase is the preferred way.
> +};
> +
> +/* pin banks of exynos5260 pin-controller 1 */
> +static struct samsung_pin_bank exynos5260_pin_banks1[] = {
> + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
> + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
> + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
> + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
> + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
> +};
> +
> +/* pin banks of exynos5260 pin-controller 2 */
> +static struct samsung_pin_bank exynos5260_pin_banks2[] = {
> + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
> + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
> +};
> +
> +/*
> + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5420 SoC includes
> + * four gpio/pin-mux/pinconfig controllers.
Hmm, I can see only three of them below. Is there one left undefined?
Otherwise, the patch looks fine.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 3/7] ARM: dts: add dts files for exynos5260 SoC
2013-12-06 15:56 ` [PATCH 3/7] ARM: dts: add dts files for exynos5260 SoC Rahul Sharma
@ 2013-12-10 17:10 ` Tomasz Figa
2014-01-06 9:40 ` Rahul Sharma
0 siblings, 1 reply; 28+ messages in thread
From: Tomasz Figa @ 2013-12-10 17:10 UTC (permalink / raw)
To: linux-arm-kernel
Hi Pankaj, Rahul, Arun,
Please split generic SoC dtsi files and board dts files into separate
patches. Also please see my comments inline.
On Friday 06 of December 2013 21:26:27 Rahul Sharma wrote:
> From: Arun Kumar K <arun.kk@samsung.com>
>
> The patch adds the dts files for exynos5260 and for xyref
> evt0 board.
[snip]
> + gpx0: gpx0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
Just to make sure, all your GPX banks are muxed type, with wake-up
interrupts muxed to a single GIC interrupt line, right?
> + };
[snip]
> + cam_gpio_a: cam-gpio-a {
> + samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3",
> + "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7",
> + "gpe1-0", "gpe1-1";
> + samsung,pin-function = <2>;
Incorrect indentation.
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
[snip]
> + hdmi_hpd_irq: hdmi-hpd-irq {
> + samsung,pins = "gpx3-7";
> + samsung,pin-function = <0>;
Function 0 is input, not a special function. It shouldn't be handled
this way. If a board needs to set up pull-up/down and driver strength
for GPIO pins then it should add its own board-specific pinconf nodes
with just pin-pud and/or pin-drv properties and without pin-function.
> + samsung,pin-pud = <1>;
> + samsung,pin-drv = <0>;
> + };
> + };
[snip]
> + sd0_bus1: sd0-bus-width1 {
> + samsung,pins = "gpc0-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd0_bus4: sd0-bus-width4 {
> + samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd0_bus8: sd0-bus-width8 {
> + samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <3>;
> + };
This is inconsistent. To specify 1- and 4-bit SD busses you need to
include reference to just one pinconf node (sd0_bus1 or sd0_bus4), but
for 8-bit bus you need to specify both sd0_bus4 and sd0_bus8.
Please make the nodes exclusive, so you always need to specify all
possible configurations with given wiring (e.g. with 4 wires, you can
run in 1-bit and 4-bit modes, not just 4-bit).
Same for remaining instances of SD bus.
[snip]
> diff --git a/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
> new file mode 100644
> index 0000000..aa1fcda
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
> @@ -0,0 +1,85 @@
> +/*
> + * SAMSUNG XYREF5260 EVT0 board device tree source
> + *
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +/dts-v1/;
> +#include "exynos5260.dtsi"
> +
> +/ {
> + model = "SAMSUNG XYREF5260 EVT0 board based on EXYNOS5260";
> + compatible = "samsung,xyref5260", "samsung,exynos5260";
> +
Shouldn't you have a memory node here?
> + chosen {
> + bootargs = "console=ttySAC2,115200";
> + };
> +
> + fixed-rate-clocks {
> + oscclk {
> + compatible = "samsung,exynos5260-oscclk";
> + clock-frequency = <24000000>;
> + };
> + };
Please use generic fixed clock bindings. You can take [1] as an example
how to use them.
[1] arch/arm/boot/dts/s3c6410-smdk6410.dtsi
> +
> + serial at 12C00000 {
> + status = "okay";
> + };
> +
> + serial at 12C10000 {
> + status = "okay";
> + };
> +
> + serial at 12C20000 {
> + status = "okay";
> + };
> +
> + serial at 12860000 {
Is it the correct UART address? It seems a bit off compared to addresses
of other ports.
> + status = "okay";
> + };
> +
> + dwmmc0 at 12140000 {
> + status = "okay";
> + num-slots = <1>;
> + broken-cd;
> + bypass-smu;
This is not a valid property, according to binding documentation.
> + supports-highspeed;
> + supports-hs200-mode; /* 200 Mhz */
Neither is this one.
> + fifo-depth = <0x40>;
This is a property of the SoC, not the board.
> + card-detect-delay = <200>;
> + samsung,dw-mshc-ciu-div = <3>;
> + samsung,dw-mshc-sdr-timing = <0 4>;
> + samsung,dw-mshc-ddr-timing = <0 2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
> +
> + slot at 0 {
> + reg = <0>;
> + bus-width = <8>;
> + };
> + };
> +
> + dwmmc2 at 12160000 {
> + status = "okay";
> + num-slots = <1>;
> + supports-highspeed;
> + fifo-depth = <0x40>;
See above.
> + card-detect-delay = <200>;
> + samsung,dw-mshc-ciu-div = <3>;
> + samsung,dw-mshc-sdr-timing = <2 3>;
> + samsung,dw-mshc-ddr-timing = <1 2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
> +
> + slot at 0 {
> + reg = <0>;
> + bus-width = <4>;
> + disable-wp;
> + };
> + };
> +};
> diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
> new file mode 100644
> index 0000000..fcb8d4f
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos5260.dtsi
> @@ -0,0 +1,315 @@
> +/*
> + * SAMSUNG EXYNOS5260 SoC device tree source
> + *
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include "skeleton.dtsi"
> +#include "exynos5260-pinctrl.dtsi"
> +
> +#include <dt-bindings/clk/exynos5260-clk.h>
This won't compile, because this file hasn't been added yet by previous
patches.
Isn't it possible to reuse some of the definitions from exynos5.dtsi? How
much different is this SoC from other SoCs from the series?
> +
> +/ {
> + compatible = "samsung,exynos5260";
> + interrupt-parent = <&gic>;
> +
> + aliases {
> + pinctrl0 = &pinctrl_0;
> + pinctrl1 = &pinctrl_1;
> + pinctrl2 = &pinctrl_2;
> + };
> +
> + chipid at 10000000 {
> + compatible = "samsung,exynos4210-chipid";
> + reg = <0x10000000 0x100>;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0>;
> + cci-control-port = <&cci_control1>;
> + };
> + cpu at 1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <1>;
> + cci-control-port = <&cci_control1>;
> + };
> + cpu at 2 {
@unit-address suffix must match the first entry of reg property.
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x100>;
> + cci-control-port = <&cci_control0>;
> + };
> + cpu at 3 {
Ditto.
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x101>;
> + cci-control-port = <&cci_control0>;
> + };
> + cpu at 4 {
Ditto.
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x102>;
> + cci-control-port = <&cci_control0>;
> + };
> + cpu at 5 {
Ditto.
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x103>;
> + cci-control-port = <&cci_control0>;
> + };
> + };
> +
> + cmus {
You need compatible = "simple-bus" here if you need the nodes below
to be instantiated.
However I'm not sure if there is a point in placing them inside
a simple-bus. This needs more thought, so please give me a bit
more time to think over this and patches 4 and 7.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + cmu_top: clock-controller at 0x10010000 {
coding style: There should be no 0x prefix in @unit-address suffix.
+ all the CMU instances below.
[snip]
> +
> + gic:interrupt-controller at 10481000 {
coding style: There should be a space after the colon ending the label.
> + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + #size-cells = <0>;
> + interrupt-controller;
> + reg = <0x10481000 0x1000>,
> + <0x10482000 0x1000>,
> + <0x10484000 0x2000>,
> + <0x10486000 0x2000>;
> + interrupts = <1 9 0xf04>;
> + };
> +
> + mct at 100B0000 {
> + compatible = "samsung,exynos4210-mct";
> + reg = <0x100B0000 0xb00>;
nit: Inconsistent hexadecimal character case, on Exynos in dts* files
upper case should be used.
Also the reg size looks a bit suspicious, as it's not even page aligned.
Is it the whole area used by the MCT block, not just the used registers?
> + interrupt-controller;
MCT is not an interrupt controller.
> + #interrups-cells = <2>;
Ditto. This is a property specific to interrupt controllers.
> + interrupt-parent = <&mct_map>;
> + interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
> + <4 0>, <5 0>, <6 0>, <7 0>,
> + <8 0>, <9 0>, <10 0>, <11 0>;
> + clocks = <&cmu_top FIN_PLL>, <&cmu_peri PERI_PCLK_MCT>;
> + clock-names = "fin_pll", "mct";
> +
> + mct_map: mct-map {
> + #interrupt-cells = <2>;
Why two cells are needed? Using just one woudl simplify interrupt
specifiers above and interrupt-map specifiers below.
> + #address-cells = <0>;
> + #size-cells = <0>;
> + interrupt-map = <0x0 0 &gic 0 104 0>,
> + <0x1 0 &gic 0 105 0>,
> + <0x2 0 &gic 0 106 0>,
> + <0x3 0 &gic 0 107 0>,
> + <0x4 0 &gic 0 122 0>,
> + <0x5 0 &gic 0 123 0>,
> + <0x6 0 &gic 0 124 0>,
> + <0x7 0 &gic 0 125 0>,
> + <0x8 0 &gic 0 126 0>,
> + <0x9 0 &gic 0 127 0>,
> + <0xa 0 &gic 0 128 0>,
> + <0xb 0 &gic 0 129 0>;
> + };
> + };
> +
> + cci at 10F00000 {
> + compatible = "arm,cci-400";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x10F00000 0x1000>;
> + ranges = <0x0 0x10F00000 0x6000>;
> +
> + cci_control0: slave-if at 4000 { /* Please check again */
Huh? Please check again and send correct data.
> + compatible = "arm,cci-400-ctrl-if";
> + interface-type = "ace";
> + reg = <0x4000 0x1000>; /* Please check again */
> + };
> +
> + cci_control1: slave-if at 5000 { /* Please check again */
> + compatible = "arm,cci-400-ctrl-if";
> + interface-type = "ace";
> + reg = <0x5000 0x1000>; /* Please check again */
> + };
> + };
> +
> + pinctrl_0: pinctrl at 11600000 {
> + compatible = "samsung,exynos5260-pinctrl";
> + reg = <0x11600000 0x1000>;
> + interrupts = <0 79 0>; /* GPIO_RT */
Instead of using such comment, maybe it would be better to rename
labels of pinctrl nodes to be more meaningful, such as pinctrl_rt,
pinctrl_fsys and pinctrl_aud?
> +
> + wakeup-interrupt-controller {
> + compatible = "samsung,exynos4210-wakeup-eint";
> + interrupt-parent = <&gic>;
> + interrupts = <0 32 0>;
> + };
> + };
[snip]
> +
> + dwmmc_0: dwmmc0 at 12140000 {
Please use generic "mmc@" names for MMC nodes and move fifo-depth property
here to SoC-level dtsi.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 4/7] clk/samsung: add support for multuple clock providers
2013-12-06 15:56 ` [PATCH 4/7] clk/samsung: add support for multuple clock providers Rahul Sharma
@ 2013-12-11 11:15 ` Tomasz Figa
2014-01-06 11:35 ` Rahul Sharma
0 siblings, 1 reply; 28+ messages in thread
From: Tomasz Figa @ 2013-12-11 11:15 UTC (permalink / raw)
To: linux-arm-kernel
Hi Rahul,
Please see my comments inline.
On Friday 06 of December 2013 21:26:28 Rahul Sharma wrote:
> Samsung CCF helper functions do not provide support to
> register multiple Clock Providers for a given SoC. Due to
> this limitation SoC platforms are not able to use these
> helpers for registering mulitple clock providers and are
> forced to bypass this layer.
>
> This layer is modified acordingly to enable the support.
>
> Clockfile for exynos4, exynos5250, exynos5420, exynos5440
> and S3c64xx are also modified as per changed helper functions.
[snip]
> diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
> index 91bec3e..20de446 100644
> --- a/drivers/clk/samsung/clk.c
> +++ b/drivers/clk/samsung/clk.c
> @@ -15,11 +15,6 @@
> #include "clk.h"
>
> static DEFINE_SPINLOCK(lock);
IMHO you can also move the spinlock into samsung_clk_provider struct, to
have more fine grained locking, as you shouldn't need to lock between
particular providers, just multiple requests for one.
> -static struct clk **clk_table;
> -static void __iomem *reg_base;
> -#ifdef CONFIG_OF
> -static struct clk_onecell_data clk_data;
> -#endif
>
> void samsung_clk_save(void __iomem *base,
> struct samsung_clk_reg_dump *rd,
> @@ -55,40 +50,53 @@ struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
> }
>
> /* setup the essentials required to support clock lookup using ccf */
> -void __init samsung_clk_init(struct device_node *np, void __iomem *base,
> - unsigned long nr_clks)
> +struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
> + void __iomem *base, unsigned long nr_clks)
> {
> - reg_base = base;
> + struct samsung_clk_provider *ctx;
> + struct clk **clk_table;
> + int ret;
> +
> + if (!np)
> + return NULL;
This check is incorrect. It's completely correct to call this function
with NULL np, when booted without DT and this was handled correctly
before this patch. Please keep the same behavior.
> +
> + ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL);
> + if (!ctx)
> + panic("could not allocate clock provider context.\n");
>
> clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
> if (!clk_table)
> panic("could not allocate clock lookup table\n");
>
> - if (!np)
> - return;
> + ctx->reg_base = base;
> + ctx->clk_data.clks = clk_table;
> + ctx->clk_data.clk_num = nr_clks;
>
> -#ifdef CONFIG_OF
> - clk_data.clks = clk_table;
> - clk_data.clk_num = nr_clks;
> - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
> -#endif
> + ret = of_clk_add_provider(np, of_clk_src_onecell_get,
> + &ctx->clk_data);
> + if (ret)
> + panic("could not register clock provide\n");
> +
> + return ctx;
> }
[snip]
> diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
> index c7141ba..433bab3 100644
> --- a/drivers/clk/samsung/clk.h
> +++ b/drivers/clk/samsung/clk.h
> @@ -21,6 +21,17 @@
> #include <linux/of_address.h>
> #include "clk-pll.h"
>
> +/* Context node which holds information about the clock provider. */
> +/**
> + * struct samsung_clk_provider: information about clock plovider
typo: s/plovider/provider/
> + * @reg_base: virtual address for the register base.
> + * @clk_data: holds clock related data like clk* and number of clocks.
> + */
Why two comments? The kerneldoc one should be enough.
> +struct samsung_clk_provider {
> + void __iomem *reg_base;
> + struct clk_onecell_data clk_data;
> +};
> +
> /**
> * struct samsung_clock_alias: information about mux clock
> * @id: platform specific id of the clock.
> @@ -312,29 +323,40 @@ struct samsung_pll_clock {
> __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \
> _lock, _con, _rtable, _alias)
>
> -extern void __init samsung_clk_init(struct device_node *np, void __iomem *base,
> - unsigned long nr_clks);
> +extern struct samsung_clk_provider *__init samsung_clk_init(
> + struct device_node *np, void __iomem *base,
> + unsigned long nr_clks);
> extern void __init samsung_clk_of_register_fixed_ext(
> + struct samsung_clk_provider *ctx,
> struct samsung_fixed_rate_clock *fixed_rate_clk,
> unsigned int nr_fixed_rate_clk,
> struct of_device_id *clk_matches);
>
> -extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id);
> +extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
> + struct clk *clk, unsigned int id);
>
> -extern void samsung_clk_register_alias(struct samsung_clock_alias *list,
> - unsigned int nr_clk);
> +extern void samsung_clk_register_alias(struct samsung_clk_provider *ctx,
> + struct samsung_clock_alias *list,
> + unsigned int nr_clk);
> extern void __init samsung_clk_register_fixed_rate(
> - struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk);
> + struct samsung_clk_provider *ctx,
> + struct samsung_fixed_rate_clock *clk_list,
> + unsigned int nr_clk);
> extern void __init samsung_clk_register_fixed_factor(
> - struct samsung_fixed_factor_clock *list, unsigned int nr_clk);
> -extern void __init samsung_clk_register_mux(struct samsung_mux_clock *clk_list,
> + struct samsung_clk_provider *ctx,
> + struct samsung_fixed_factor_clock *list,
> + unsigned int nr_clk);
> +extern void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
> + struct samsung_mux_clock *clk_list,
> unsigned int nr_clk);
> -extern void __init samsung_clk_register_div(struct samsung_div_clock *clk_list,
> +extern void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
> + struct samsung_div_clock *clk_list,
> unsigned int nr_clk);
> -extern void __init samsung_clk_register_gate(
> +extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
> struct samsung_gate_clock *clk_list, unsigned int nr_clk);
> -extern void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list,
> - unsigned int nr_clk, void __iomem *base);
> +extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
> + struct samsung_pll_clock *pll_list,
> + unsigned int nr_clk, void __iomem *base);
>
> extern unsigned long _get_rate(const char *clk_name);
>
nit: Please keep the indentation consistent in all the function prototypes
above.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 6/7] clk/samsung: add support for pll2650xx
2013-12-06 15:56 ` [PATCH 6/7] clk/samsung: add support for pll2650xx Rahul Sharma
2013-12-09 8:09 ` Sachin Kamat
@ 2013-12-19 11:45 ` Tomasz Figa
2014-01-06 11:44 ` Rahul Sharma
1 sibling, 1 reply; 28+ messages in thread
From: Tomasz Figa @ 2013-12-19 11:45 UTC (permalink / raw)
To: linux-arm-kernel
Hi Rahul,
On Friday 06 of December 2013 21:26:30 Rahul Sharma wrote:
> Add support for pll2650xx in samsung pll file. This pll variant
> is close to pll36xx but uses CON2 registers instead of CON1.
If the ops are otherwise idential, why not reuse the ops for pll36xx
and use CON1 or CON2 register conditionally based on pll->type field?
(Just as it is already done for pll4600, 4650 and 4650c.)
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 5/7] clk/samsung: add support for pll2550xx
2013-12-06 15:56 ` [PATCH 5/7] clk/samsung: add support for pll2550xx Rahul Sharma
2013-12-09 8:06 ` Sachin Kamat
@ 2013-12-19 12:01 ` Tomasz Figa
2014-01-06 11:36 ` Rahul Sharma
1 sibling, 1 reply; 28+ messages in thread
From: Tomasz Figa @ 2013-12-19 12:01 UTC (permalink / raw)
To: linux-arm-kernel
Hi Pankaj, Rahul, Arun,
On Friday 06 of December 2013 21:26:29 Rahul Sharma wrote:
> From: Pankaj Dubey <pankaj.dubey@samsung.com>
>
> exynos5260 use pll2520xx and it has different bitfields
> for P,M,S values as compared to pll2550xx. Support for
> pll2520xx is added here.
>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
> Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
> ---
> drivers/clk/samsung/clk-pll.c | 107 +++++++++++++++++++++++++++++++++++++++++
> drivers/clk/samsung/clk-pll.h | 1 +
> 2 files changed, 108 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index e8e8953..237a889 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -710,6 +710,107 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name,
> return clk;
> }
>
> +/*
> + * PLL2550xx Clock Type
> + */
> +
> +/* Maximum lock time can be 270 * PDIV cycles */
> +#define PLL2550XX_LOCK_FACTOR (270)
> +
> +#define PLL2550XX_MDIV_MASK (0x3FF)
> +#define PLL2550XX_PDIV_MASK (0x3F)
> +#define PLL2550XX_SDIV_MASK (0x7)
> +#define PLL2550XX_LOCK_STAT_MASK (0x1)
> +#define PLL2550XX_MDIV_SHIFT (9)
> +#define PLL2550XX_PDIV_SHIFT (3)
> +#define PLL2550XX_SDIV_SHIFT (0)
> +#define PLL2550XX_LOCK_STAT_SHIFT (21)
> +
> +static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct samsung_clk_pll *pll = to_clk_pll(hw);
> + u32 mdiv, pdiv, sdiv, pll_con;
> + u64 fvco = parent_rate;
> +
> + pll_con = __raw_readl(pll->con_reg);
> + mdiv = (pll_con >> PLL2550XX_MDIV_SHIFT) & PLL2550XX_MDIV_MASK;
> + pdiv = (pll_con >> PLL2550XX_PDIV_SHIFT) & PLL2550XX_PDIV_MASK;
> + sdiv = (pll_con >> PLL2550XX_SDIV_SHIFT) & PLL2550XX_SDIV_MASK;
> +
> + fvco *= mdiv;
> + do_div(fvco, (pdiv << sdiv));
> +
> + return (unsigned long)fvco;
> +}
> +
> +static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con)
> +{
> + if ((mdiv != ((pll_con >> PLL2550XX_MDIV_SHIFT) &
> + PLL2550XX_MDIV_MASK)) ||
> + (pdiv != ((pll_con >> PLL2550XX_PDIV_SHIFT) &
> + PLL2550XX_PDIV_MASK)))
> + return 1;
> + else
> + return 0;
This doesn't look too good. Can you make this consistent with
implementations of this helper for other PLLs, such as
samsung_pll35xx_mp_change()?
> +}
> +
> +static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate,
> + unsigned long prate)
> +{
> + struct samsung_clk_pll *pll = to_clk_pll(hw);
> + const struct samsung_pll_rate_table *rate;
> + u32 tmp;
> +
> + /* Get required rate settings from table */
> + rate = samsung_get_pll_settings(pll, drate);
> + if (!rate) {
> + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
> + drate, __clk_get_name(hw->clk));
> + return -EINVAL;
> + }
> +
> + tmp = __raw_readl(pll->con_reg);
> +
> + if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) {
> + /* If only s change, change just s value only*/
> + tmp &= ~(PLL2550XX_SDIV_MASK << PLL2550XX_SDIV_SHIFT);
> + tmp |= rate->sdiv << PLL2550XX_SDIV_SHIFT;
> + __raw_writel(tmp, pll->con_reg);
> + } else {
Please make coding style of this function consistent with implementations
of this operation for other PLLs, such as samsung_pll35xx_set_rate().
Otherwise the patch looks fine.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 1/7] ARM: EXYNOS: initial board support for exynos5260 SoC
2013-12-09 6:23 ` Sachin Kamat
2013-12-09 6:33 ` Rahul Sharma
@ 2013-12-23 4:39 ` Rahul Sharma
1 sibling, 0 replies; 28+ messages in thread
From: Rahul Sharma @ 2013-12-23 4:39 UTC (permalink / raw)
To: linux-arm-kernel
Thanks Sachin,
On 9 December 2013 11:53, Sachin Kamat <sachin.kamat@linaro.org> wrote:
> Hi Rahul,
>
> On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote:
>> From: Pankaj Dubey <pankaj.dubey@samsung.com>
>>
>> This patch add basic arch side support for exynos5260 SoC.
>>
>> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
>> Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
>
> Since you are posting the patch, your signed off is also required.
Right. I will add my Sign off.
>
> [snip]
>
>> void exynos4_restart(enum reboot_mode mode, const char *cmd)
>> {
>> __raw_writel(0x1, S5P_SWRESET);
>> @@ -371,7 +387,8 @@ static void __init exynos4_map_io(void)
>> static void __init exynos5_map_io(void)
>> {
>> iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
>> -
>> + if (soc_is_exynos5260())
>> + iotable_init(exynos5260_iodesc, ARRAY_SIZE(exynos5260_iodesc));
>
> Add this after 5250 to maintain numerical order.
ok.
>
>> if (soc_is_exynos5250())
>> iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
>> }
>
> [snip]
>>
>> #define S5P_VA_SYSRAM S3C_ADDR(0x02400000)
>> #define S5P_VA_SYSRAM_NS S3C_ADDR(0x02410000)
>> +
> Unnecessary blank line addition.
I will remove this.
Regards,
Rahul Sharma.
>
>
> --
> With warm regards,
> Sachin
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 1/7] ARM: EXYNOS: initial board support for exynos5260 SoC
2013-12-10 15:57 ` Tomasz Figa
@ 2014-01-03 9:24 ` Rahul Sharma
0 siblings, 0 replies; 28+ messages in thread
From: Rahul Sharma @ 2014-01-03 9:24 UTC (permalink / raw)
To: linux-arm-kernel
Hi Tomasz,
Sorry for responding late.
On 10 December 2013 21:27, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi Pankaj, Rahul, Arun,
>
> In addition to issues already pointed by Sachin, please also see my
> comments inline.
>
> On Friday 06 of December 2013 21:26:25 Rahul Sharma wrote:
>> From: Pankaj Dubey <pankaj.dubey@samsung.com>
>>
>> This patch add basic arch side support for exynos5260 SoC.
>>
>> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
>> Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
>> ---
>> arch/arm/mach-exynos/Kconfig | 9 +++++++++
>> arch/arm/mach-exynos/common.c | 19 ++++++++++++++++++-
>> arch/arm/mach-exynos/cpuidle.c | 2 +-
>> arch/arm/mach-exynos/include/mach/map.h | 1 +
>> arch/arm/mach-exynos/include/mach/regs-pmu.h | 4 ++++
>> arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
>> arch/arm/plat-samsung/include/plat/cpu.h | 8 ++++++++
>> arch/arm/plat-samsung/include/plat/map-s5p.h | 1 +
>> 8 files changed, 43 insertions(+), 2 deletions(-)
> [snip]
>> diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
>> index ddbfe87..405c11a 100644
>> --- a/arch/arm/mach-exynos/cpuidle.c
>> +++ b/arch/arm/mach-exynos/cpuidle.c
>> @@ -120,7 +120,7 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
>> cpu_suspend(0, idle_finisher);
>>
>> #ifdef CONFIG_SMP
>> - if (!soc_is_exynos5250())
>> + if (!soc_is_exynos5250() || soc_is_exynos5260())
>
> The added OR condition doesn't affect the if condition in any way, because
> when running on Exynos5260, soc_is_exynos5250() will return false and make
> the whole condition evaluate to true.
>
> Shouldn't it be
>
> if (!soc_is_exynos5250() && !soc_is_exynos5260())
>
> if Exynos5260 doesn't need scu_enable(), or left as is if it needs?
>
Actually we don't need to call scu_enable() for 5260. Hence leaving it as it is.
>> scu_enable(S5P_VA_SCU);
>> #endif
>> cpu_pm_exit();
>> diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
>> index 7b046b5..bd6fa02 100644
>> --- a/arch/arm/mach-exynos/include/mach/map.h
>> +++ b/arch/arm/mach-exynos/include/mach/map.h
>> @@ -29,6 +29,7 @@
>> #define EXYNOS4210_PA_SYSRAM_NS 0x0203F000
>> #define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000
>> #define EXYNOS5250_PA_SYSRAM_NS 0x0204F000
>> +#define EXYNOS5260_PA_SYSRAM_NS 0x02073000
>>
>> #define EXYNOS_PA_CHIPID 0x10000000
>>
>> diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
>> index 2cdb63e..09ae29a 100644
>> --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
>> +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
>> @@ -234,6 +234,10 @@
>>
>> #define EXYNOS5_SYS_WDTRESET (1 << 20)
>>
>> +#define EXYNOS5260_A7_WDTRST (1 << 24)
>> +#define EXYNOS5260_A15_WDTRST (1 << 23)
>> +#define EXYNOS5260_SYS_WDTRESET (EXYNOS5260_A7_WDTRST || EXYNOS5260_A15_WDTRST)
>> +
>
> Are these definitions needed? I don't see any user in this patch.
>
Removed these definitions.
Regards,
Rahul Sharma.
> Best regards,
> Tomasz
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data
2013-12-09 4:51 ` Sachin Kamat
2013-12-09 6:36 ` Rahul Sharma
@ 2014-01-03 9:25 ` Rahul Sharma
1 sibling, 0 replies; 28+ messages in thread
From: Rahul Sharma @ 2014-01-03 9:25 UTC (permalink / raw)
To: linux-arm-kernel
Hi Sachin,
On 9 December 2013 10:21, Sachin Kamat <sachin.kamat@linaro.org> wrote:
> Hi Rahul, Young-Gun,
>
> On 6 December 2013 21:26, Rahul Sharma <rahul.sharma@samsung.com> wrote:
>> From: Young-Gun Jang <yg1004.jang@samsung.com>
>>
>> Add Samsung Exynos5260 SoC specific data to enable pinctrl
>> support for all platforms based on EXYNOS5260.
>>
>> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
>> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
>> Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
>
> Author's (Young-Gun Jang) signed-off by is missing here.
>
done.
> [snip]
>
>> +
>> +/* pin banks of exynos5260 pin-controller 2 */
>> +static struct samsung_pin_bank exynos5260_pin_banks2[] = {
>> + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
>> + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
>> +};
>> +
>> +/*
>> + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5420 SoC includes
>
> s/5420/5260 ?
done.
Regards,
Rahul Sharma.
>
> --
> With warm regards,
> Sachin
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data
2013-12-10 16:04 ` Tomasz Figa
@ 2014-01-03 9:26 ` Rahul Sharma
0 siblings, 0 replies; 28+ messages in thread
From: Rahul Sharma @ 2014-01-03 9:26 UTC (permalink / raw)
To: linux-arm-kernel
Tomasz,
On 10 December 2013 21:34, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi Young-Gun, Pankaj, Rahul, Arun,
>
> Please see my comments inline.
>
> On Friday 06 of December 2013 21:26:26 Rahul Sharma wrote:
>> From: Young-Gun Jang <yg1004.jang@samsung.com>
>>
>> Add Samsung Exynos5260 SoC specific data to enable pinctrl
>> support for all platforms based on EXYNOS5260.
> [snip]
>> diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
>> index 155b1b3..9a93df6 100644
>> --- a/drivers/pinctrl/pinctrl-exynos.c
>> +++ b/drivers/pinctrl/pinctrl-exynos.c
>> @@ -1042,6 +1042,88 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
>> },
>> };
>>
>> +/* pin banks of exynos5260 pin-controller 0 */
>> +static struct samsung_pin_bank exynos5260_pin_banks0[] = {
>> + EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
>> + EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
>> + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
>> + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
>> + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
>> + EXYNOS_PIN_BANK_EINTG(5, 0x0A0, "gpb2", 0x14),
>> + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
>> + EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpb4", 0x1c),
>> + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
>> + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
>> + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
>> + EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
>> + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
>> + EXYNOS_PIN_BANK_EINTG(5, 0x1A0, "gpe1", 0x34),
>> + EXYNOS_PIN_BANK_EINTG(4, 0x1C0, "gpf0", 0x38),
>> + EXYNOS_PIN_BANK_EINTG(8, 0x1E0, "gpf1", 0x3c),
>> + EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
>> + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
>> + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
>> + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
>> + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
>
> nit: Please use lowercase hexadecimal characters. Despite of already
> existing code, lowercase is the preferred way.
>
Changed.
>> +};
>> +
>> +/* pin banks of exynos5260 pin-controller 1 */
>> +static struct samsung_pin_bank exynos5260_pin_banks1[] = {
>> + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
>> + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
>> + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
>> + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
>> + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
>> +};
>> +
>> +/* pin banks of exynos5260 pin-controller 2 */
>> +static struct samsung_pin_bank exynos5260_pin_banks2[] = {
>> + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
>> + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
>> +};
>> +
>> +/*
>> + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5420 SoC includes
>> + * four gpio/pin-mux/pinconfig controllers.
>
> Hmm, I can see only three of them below. Is there one left undefined?
There are only three. I updated the comment.
regards,
Rahul Sharma
>
> Otherwise, the patch looks fine.
>
> Best regards,
> Tomasz
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 3/7] ARM: dts: add dts files for exynos5260 SoC
2013-12-10 17:10 ` Tomasz Figa
@ 2014-01-06 9:40 ` Rahul Sharma
0 siblings, 0 replies; 28+ messages in thread
From: Rahul Sharma @ 2014-01-06 9:40 UTC (permalink / raw)
To: linux-arm-kernel
Hi Tomasz,
On 10 December 2013 22:40, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi Pankaj, Rahul, Arun,
>
> Please split generic SoC dtsi files and board dts files into separate
> patches. Also please see my comments inline.
I will split them to SoC and Board DT patches.
>
> On Friday 06 of December 2013 21:26:27 Rahul Sharma wrote:
>> From: Arun Kumar K <arun.kk@samsung.com>
>>
>> The patch adds the dts files for exynos5260 and for xyref
>> evt0 board.
> [snip]
>> + gpx0: gpx0 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>
> Just to make sure, all your GPX banks are muxed type, with wake-up
> interrupts muxed to a single GIC interrupt line, right?
There is no combiner in 5260. Each GPX bank is connected one GIC interrupt
line.
>
>> + };
> [snip]
>> + cam_gpio_a: cam-gpio-a {
>> + samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3",
>> + "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7",
>> + "gpe1-0", "gpe1-1";
>> + samsung,pin-function = <2>;
>
> Incorrect indentation.
>
Done.
>> + samsung,pin-pud = <0>;
>> + samsung,pin-drv = <0>;
>> + };
> [snip]
>> + hdmi_hpd_irq: hdmi-hpd-irq {
>> + samsung,pins = "gpx3-7";
>> + samsung,pin-function = <0>;
>
> Function 0 is input, not a special function. It shouldn't be handled
> this way. If a board needs to set up pull-up/down and driver strength
> for GPIO pins then it should add its own board-specific pinconf nodes
> with just pin-pud and/or pin-drv properties and without pin-function.
I moved this node to Board file. I hope that is correct.
>
>> + samsung,pin-pud = <1>;
>> + samsung,pin-drv = <0>;
>> + };
>> + };
> [snip]
>> + sd0_bus1: sd0-bus-width1 {
>> + samsung,pins = "gpc0-3";
>> + samsung,pin-function = <2>;
>> + samsung,pin-pud = <3>;
>> + samsung,pin-drv = <3>;
>> + };
>> +
>> + sd0_bus4: sd0-bus-width4 {
>> + samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6";
>> + samsung,pin-function = <2>;
>> + samsung,pin-pud = <3>;
>> + samsung,pin-drv = <3>;
>> + };
>> +
>> + sd0_bus8: sd0-bus-width8 {
>> + samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3";
>> + samsung,pin-function = <2>;
>> + samsung,pin-pud = <3>;
>> + samsung,pin-drv = <3>;
>> + };
>
> This is inconsistent. To specify 1- and 4-bit SD busses you need to
> include reference to just one pinconf node (sd0_bus1 or sd0_bus4), but
> for 8-bit bus you need to specify both sd0_bus4 and sd0_bus8.
>
> Please make the nodes exclusive, so you always need to specify all
> possible configurations with given wiring (e.g. with 4 wires, you can
> run in 1-bit and 4-bit modes, not just 4-bit).
>
Ok. I will remove "gpc0-3" from sdX_bus4.
> Same for remaining instances of SD bus.
>
> [snip]
>
>> diff --git a/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
>> new file mode 100644
>> index 0000000..aa1fcda
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
>> @@ -0,0 +1,85 @@
>> +/*
>> + * SAMSUNG XYREF5260 EVT0 board device tree source
>> + *
>> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
>> + * http://www.samsung.com
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> +*/
>> +
>> +/dts-v1/;
>> +#include "exynos5260.dtsi"
>> +
>> +/ {
>> + model = "SAMSUNG XYREF5260 EVT0 board based on EXYNOS5260";
>> + compatible = "samsung,xyref5260", "samsung,exynos5260";
>> +
>
> Shouldn't you have a memory node here?
I added memory node here.
>
>> + chosen {
>> + bootargs = "console=ttySAC2,115200";
>> + };
>> +
>> + fixed-rate-clocks {
>> + oscclk {
>> + compatible = "samsung,exynos5260-oscclk";
>> + clock-frequency = <24000000>;
>> + };
>> + };
>
> Please use generic fixed clock bindings. You can take [1] as an example
> how to use them.
>
> [1] arch/arm/boot/dts/s3c6410-smdk6410.dtsi
Ok. I will changes this.
>
>> +
>> + serial at 12C00000 {
>> + status = "okay";
>> + };
>> +
>> + serial at 12C10000 {
>> + status = "okay";
>> + };
>> +
>> + serial at 12C20000 {
>> + status = "okay";
>> + };
>> +
>> + serial at 12860000 {
>
> Is it the correct UART address? It seems a bit off compared to addresses
> of other ports.
>
This is correct.
>> + status = "okay";
>> + };
>> +
>> + dwmmc0 at 12140000 {
>> + status = "okay";
>> + num-slots = <1>;
>> + broken-cd;
>> + bypass-smu;
>
> This is not a valid property, according to binding documentation.
>
>> + supports-highspeed;
>> + supports-hs200-mode; /* 200 Mhz */
>
> Neither is this one.
>
>> + fifo-depth = <0x40>;
>
> This is a property of the SoC, not the board.
>
>> + card-detect-delay = <200>;
>> + samsung,dw-mshc-ciu-div = <3>;
>> + samsung,dw-mshc-sdr-timing = <0 4>;
>> + samsung,dw-mshc-ddr-timing = <0 2>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
>> +
>> + slot at 0 {
>> + reg = <0>;
>> + bus-width = <8>;
>> + };
>> + };
>> +
>> + dwmmc2 at 12160000 {
>> + status = "okay";
>> + num-slots = <1>;
>> + supports-highspeed;
>> + fifo-depth = <0x40>;
>
> See above.
I will remove them. These are optional properties which are not being referred
in the mainline driver.
>
>> + card-detect-delay = <200>;
>> + samsung,dw-mshc-ciu-div = <3>;
>> + samsung,dw-mshc-sdr-timing = <2 3>;
>> + samsung,dw-mshc-ddr-timing = <1 2>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
>> +
>> + slot at 0 {
>> + reg = <0>;
>> + bus-width = <4>;
>> + disable-wp;
>> + };
>> + };
>> +};
>> diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
>> new file mode 100644
>> index 0000000..fcb8d4f
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/exynos5260.dtsi
>> @@ -0,0 +1,315 @@
>> +/*
>> + * SAMSUNG EXYNOS5260 SoC device tree source
>> + *
>> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
>> + * http://www.samsung.com
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> +*/
>> +
>> +#include "skeleton.dtsi"
>> +#include "exynos5260-pinctrl.dtsi"
>> +
>> +#include <dt-bindings/clk/exynos5260-clk.h>
>
> This won't compile, because this file hasn't been added yet by previous
> patches.
>
I will reorder the patches to ensure build doesn't break.
> Isn't it possible to reuse some of the definitions from exynos5.dtsi? How
> much different is this SoC from other SoCs from the series?
It is quite different than other Exynos5 SoCs specially the physical
address of the
IPs.
>
>> +
>> +/ {
>> + compatible = "samsung,exynos5260";
>> + interrupt-parent = <&gic>;
>> +
>> + aliases {
>> + pinctrl0 = &pinctrl_0;
>> + pinctrl1 = &pinctrl_1;
>> + pinctrl2 = &pinctrl_2;
>> + };
>> +
>> + chipid at 10000000 {
>> + compatible = "samsung,exynos4210-chipid";
>> + reg = <0x10000000 0x100>;
>> + };
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu at 0 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a15";
>> + reg = <0>;
>> + cci-control-port = <&cci_control1>;
>> + };
>> + cpu at 1 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a15";
>> + reg = <1>;
>> + cci-control-port = <&cci_control1>;
>> + };
>> + cpu at 2 {
>
> @unit-address suffix must match the first entry of reg property.
Ok. I will change this.
>
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a7";
>> + reg = <0x100>;
>> + cci-control-port = <&cci_control0>;
>> + };
>> + cpu at 3 {
>
> Ditto.
>
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a7";
>> + reg = <0x101>;
>> + cci-control-port = <&cci_control0>;
>> + };
>> + cpu at 4 {
>
> Ditto.
>
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a7";
>> + reg = <0x102>;
>> + cci-control-port = <&cci_control0>;
>> + };
>> + cpu at 5 {
>
> Ditto.
>
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a7";
>> + reg = <0x103>;
>> + cci-control-port = <&cci_control0>;
>> + };
>> + };
>> +
>> + cmus {
>
> You need compatible = "simple-bus" here if you need the nodes below
> to be instantiated.
>
> However I'm not sure if there is a point in placing them inside
> a simple-bus. This needs more thought, so please give me a bit
> more time to think over this and patches 4 and 7.
Please let me know if you have a better solution.
>
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + cmu_top: clock-controller at 0x10010000 {
>
> coding style: There should be no 0x prefix in @unit-address suffix.
ok. Done.
> + all the CMU instances below.
>
> [snip]
>> +
>> + gic:interrupt-controller at 10481000 {
>
> coding style: There should be a space after the colon ending the label.
>
Done.
>> + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
>> + #interrupt-cells = <3>;
>> + #address-cells = <0>;
>> + #size-cells = <0>;
>> + interrupt-controller;
>> + reg = <0x10481000 0x1000>,
>> + <0x10482000 0x1000>,
>> + <0x10484000 0x2000>,
>> + <0x10486000 0x2000>;
>> + interrupts = <1 9 0xf04>;
>> + };
>> +
>> + mct at 100B0000 {
>> + compatible = "samsung,exynos4210-mct";
>> + reg = <0x100B0000 0xb00>;
>
> nit: Inconsistent hexadecimal character case, on Exynos in dts* files
> upper case should be used.
>
> Also the reg size looks a bit suspicious, as it's not even page aligned.
> Is it the whole area used by the MCT block, not just the used registers?
>
Done.
>> + interrupt-controller;
>
> MCT is not an interrupt controller.
>
>> + #interrups-cells = <2>;
>
> Ditto. This is a property specific to interrupt controllers.
>
>> + interrupt-parent = <&mct_map>;
>> + interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
>> + <4 0>, <5 0>, <6 0>, <7 0>,
>> + <8 0>, <9 0>, <10 0>, <11 0>;
>> + clocks = <&cmu_top FIN_PLL>, <&cmu_peri PERI_PCLK_MCT>;
>> + clock-names = "fin_pll", "mct";
>> +
>> + mct_map: mct-map {
>> + #interrupt-cells = <2>;
>
> Why two cells are needed? Using just one woudl simplify interrupt
> specifiers above and interrupt-map specifiers below.
>
Done.
>> + #address-cells = <0>;
>> + #size-cells = <0>;
>> + interrupt-map = <0x0 0 &gic 0 104 0>,
>> + <0x1 0 &gic 0 105 0>,
>> + <0x2 0 &gic 0 106 0>,
>> + <0x3 0 &gic 0 107 0>,
>> + <0x4 0 &gic 0 122 0>,
>> + <0x5 0 &gic 0 123 0>,
>> + <0x6 0 &gic 0 124 0>,
>> + <0x7 0 &gic 0 125 0>,
>> + <0x8 0 &gic 0 126 0>,
>> + <0x9 0 &gic 0 127 0>,
>> + <0xa 0 &gic 0 128 0>,
>> + <0xb 0 &gic 0 129 0>;
>> + };
>> + };
>> +
>> + cci at 10F00000 {
>> + compatible = "arm,cci-400";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + reg = <0x10F00000 0x1000>;
>> + ranges = <0x0 0x10F00000 0x6000>;
>> +
>> + cci_control0: slave-if at 4000 { /* Please check again */
>
> Huh? Please check again and send correct data.
>
>> + compatible = "arm,cci-400-ctrl-if";
>> + interface-type = "ace";
>> + reg = <0x4000 0x1000>; /* Please check again */
>> + };
>> +
>> + cci_control1: slave-if at 5000 { /* Please check again */
>> + compatible = "arm,cci-400-ctrl-if";
>> + interface-type = "ace";
>> + reg = <0x5000 0x1000>; /* Please check again */
>> + };
>> + };
>> +
>> + pinctrl_0: pinctrl at 11600000 {
>> + compatible = "samsung,exynos5260-pinctrl";
>> + reg = <0x11600000 0x1000>;
>> + interrupts = <0 79 0>; /* GPIO_RT */
>
> Instead of using such comment, maybe it would be better to rename
> labels of pinctrl nodes to be more meaningful, such as pinctrl_rt,
> pinctrl_fsys and pinctrl_aud?
I removed the comments.
>
>> +
>> + wakeup-interrupt-controller {
>> + compatible = "samsung,exynos4210-wakeup-eint";
>> + interrupt-parent = <&gic>;
>> + interrupts = <0 32 0>;
>> + };
>> + };
> [snip]
>> +
>> + dwmmc_0: dwmmc0 at 12140000 {
>
> Please use generic "mmc@" names for MMC nodes and move fifo-depth property
> here to SoC-level dtsi.
Done.
Regards,
Rahul Sharma.
>
> Best regards,
> Tomasz
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 4/7] clk/samsung: add support for multuple clock providers
2013-12-11 11:15 ` Tomasz Figa
@ 2014-01-06 11:35 ` Rahul Sharma
0 siblings, 0 replies; 28+ messages in thread
From: Rahul Sharma @ 2014-01-06 11:35 UTC (permalink / raw)
To: linux-arm-kernel
Hi Tomasz,
On 11 December 2013 16:45, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi Rahul,
>
> Please see my comments inline.
>
> On Friday 06 of December 2013 21:26:28 Rahul Sharma wrote:
>> Samsung CCF helper functions do not provide support to
>> register multiple Clock Providers for a given SoC. Due to
>> this limitation SoC platforms are not able to use these
>> helpers for registering mulitple clock providers and are
>> forced to bypass this layer.
>>
>> This layer is modified acordingly to enable the support.
>>
>> Clockfile for exynos4, exynos5250, exynos5420, exynos5440
>> and S3c64xx are also modified as per changed helper functions.
> [snip]
>> diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
>> index 91bec3e..20de446 100644
>> --- a/drivers/clk/samsung/clk.c
>> +++ b/drivers/clk/samsung/clk.c
>> @@ -15,11 +15,6 @@
>> #include "clk.h"
>>
>> static DEFINE_SPINLOCK(lock);
>
> IMHO you can also move the spinlock into samsung_clk_provider struct, to
> have more fine grained locking, as you shouldn't need to lock between
> particular providers, just multiple requests for one.
>
Done.
>> -static struct clk **clk_table;
>> -static void __iomem *reg_base;
>> -#ifdef CONFIG_OF
>> -static struct clk_onecell_data clk_data;
>> -#endif
>>
>> void samsung_clk_save(void __iomem *base,
>> struct samsung_clk_reg_dump *rd,
>> @@ -55,40 +50,53 @@ struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
>> }
>>
>> /* setup the essentials required to support clock lookup using ccf */
>> -void __init samsung_clk_init(struct device_node *np, void __iomem *base,
>> - unsigned long nr_clks)
>> +struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
>> + void __iomem *base, unsigned long nr_clks)
>> {
>> - reg_base = base;
>> + struct samsung_clk_provider *ctx;
>> + struct clk **clk_table;
>> + int ret;
>> +
>> + if (!np)
>> + return NULL;
>
> This check is incorrect. It's completely correct to call this function
> with NULL np, when booted without DT and this was handled correctly
> before this patch. Please keep the same behavior.
>
Done.
>> +
>> + ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL);
>> + if (!ctx)
>> + panic("could not allocate clock provider context.\n");
>>
>> clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
>> if (!clk_table)
>> panic("could not allocate clock lookup table\n");
>>
>> - if (!np)
>> - return;
>> + ctx->reg_base = base;
>> + ctx->clk_data.clks = clk_table;
>> + ctx->clk_data.clk_num = nr_clks;
>>
>> -#ifdef CONFIG_OF
>> - clk_data.clks = clk_table;
>> - clk_data.clk_num = nr_clks;
>> - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
>> -#endif
>> + ret = of_clk_add_provider(np, of_clk_src_onecell_get,
>> + &ctx->clk_data);
>> + if (ret)
>> + panic("could not register clock provide\n");
>> +
>> + return ctx;
>> }
> [snip]
>> diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
>> index c7141ba..433bab3 100644
>> --- a/drivers/clk/samsung/clk.h
>> +++ b/drivers/clk/samsung/clk.h
>> @@ -21,6 +21,17 @@
>> #include <linux/of_address.h>
>> #include "clk-pll.h"
>>
>> +/* Context node which holds information about the clock provider. */
>> +/**
>> + * struct samsung_clk_provider: information about clock plovider
>
> typo: s/plovider/provider/
Ok.
>
>> + * @reg_base: virtual address for the register base.
>> + * @clk_data: holds clock related data like clk* and number of clocks.
>> + */
>
> Why two comments? The kerneldoc one should be enough.
>
>> +struct samsung_clk_provider {
>> + void __iomem *reg_base;
>> + struct clk_onecell_data clk_data;
>> +};
>> +
>> /**
>> * struct samsung_clock_alias: information about mux clock
>> * @id: platform specific id of the clock.
>> @@ -312,29 +323,40 @@ struct samsung_pll_clock {
>> __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \
>> _lock, _con, _rtable, _alias)
>>
>> -extern void __init samsung_clk_init(struct device_node *np, void __iomem *base,
>> - unsigned long nr_clks);
>> +extern struct samsung_clk_provider *__init samsung_clk_init(
>> + struct device_node *np, void __iomem *base,
>> + unsigned long nr_clks);
>> extern void __init samsung_clk_of_register_fixed_ext(
>> + struct samsung_clk_provider *ctx,
>> struct samsung_fixed_rate_clock *fixed_rate_clk,
>> unsigned int nr_fixed_rate_clk,
>> struct of_device_id *clk_matches);
>>
>> -extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id);
>> +extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
>> + struct clk *clk, unsigned int id);
>>
>> -extern void samsung_clk_register_alias(struct samsung_clock_alias *list,
>> - unsigned int nr_clk);
>> +extern void samsung_clk_register_alias(struct samsung_clk_provider *ctx,
>> + struct samsung_clock_alias *list,
>> + unsigned int nr_clk);
>> extern void __init samsung_clk_register_fixed_rate(
>> - struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk);
>> + struct samsung_clk_provider *ctx,
>> + struct samsung_fixed_rate_clock *clk_list,
>> + unsigned int nr_clk);
>> extern void __init samsung_clk_register_fixed_factor(
>> - struct samsung_fixed_factor_clock *list, unsigned int nr_clk);
>> -extern void __init samsung_clk_register_mux(struct samsung_mux_clock *clk_list,
>> + struct samsung_clk_provider *ctx,
>> + struct samsung_fixed_factor_clock *list,
>> + unsigned int nr_clk);
>> +extern void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
>> + struct samsung_mux_clock *clk_list,
>> unsigned int nr_clk);
>> -extern void __init samsung_clk_register_div(struct samsung_div_clock *clk_list,
>> +extern void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
>> + struct samsung_div_clock *clk_list,
>> unsigned int nr_clk);
>> -extern void __init samsung_clk_register_gate(
>> +extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
>> struct samsung_gate_clock *clk_list, unsigned int nr_clk);
>> -extern void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list,
>> - unsigned int nr_clk, void __iomem *base);
>> +extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
>> + struct samsung_pll_clock *pll_list,
>> + unsigned int nr_clk, void __iomem *base);
>>
>> extern unsigned long _get_rate(const char *clk_name);
>>
>
> nit: Please keep the indentation consistent in all the function prototypes
> above.
ok.
regards,
Rahul Sharma.
>
> Best regards,
> Tomasz
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 5/7] clk/samsung: add support for pll2550xx
2013-12-19 12:01 ` Tomasz Figa
@ 2014-01-06 11:36 ` Rahul Sharma
0 siblings, 0 replies; 28+ messages in thread
From: Rahul Sharma @ 2014-01-06 11:36 UTC (permalink / raw)
To: linux-arm-kernel
Hi Tomasz,
On 19 December 2013 17:31, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi Pankaj, Rahul, Arun,
>
> On Friday 06 of December 2013 21:26:29 Rahul Sharma wrote:
>> From: Pankaj Dubey <pankaj.dubey@samsung.com>
>>
>> exynos5260 use pll2520xx and it has different bitfields
>> for P,M,S values as compared to pll2550xx. Support for
>> pll2520xx is added here.
>>
>> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
>> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
>> Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
>> ---
>> drivers/clk/samsung/clk-pll.c | 107 +++++++++++++++++++++++++++++++++++++++++
>> drivers/clk/samsung/clk-pll.h | 1 +
>> 2 files changed, 108 insertions(+)
>>
>> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
>> index e8e8953..237a889 100644
>> --- a/drivers/clk/samsung/clk-pll.c
>> +++ b/drivers/clk/samsung/clk-pll.c
>> @@ -710,6 +710,107 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name,
>> return clk;
>> }
>>
>> +/*
>> + * PLL2550xx Clock Type
>> + */
>> +
>> +/* Maximum lock time can be 270 * PDIV cycles */
>> +#define PLL2550XX_LOCK_FACTOR (270)
>> +
>> +#define PLL2550XX_MDIV_MASK (0x3FF)
>> +#define PLL2550XX_PDIV_MASK (0x3F)
>> +#define PLL2550XX_SDIV_MASK (0x7)
>> +#define PLL2550XX_LOCK_STAT_MASK (0x1)
>> +#define PLL2550XX_MDIV_SHIFT (9)
>> +#define PLL2550XX_PDIV_SHIFT (3)
>> +#define PLL2550XX_SDIV_SHIFT (0)
>> +#define PLL2550XX_LOCK_STAT_SHIFT (21)
>> +
>> +static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw,
>> + unsigned long parent_rate)
>> +{
>> + struct samsung_clk_pll *pll = to_clk_pll(hw);
>> + u32 mdiv, pdiv, sdiv, pll_con;
>> + u64 fvco = parent_rate;
>> +
>> + pll_con = __raw_readl(pll->con_reg);
>> + mdiv = (pll_con >> PLL2550XX_MDIV_SHIFT) & PLL2550XX_MDIV_MASK;
>> + pdiv = (pll_con >> PLL2550XX_PDIV_SHIFT) & PLL2550XX_PDIV_MASK;
>> + sdiv = (pll_con >> PLL2550XX_SDIV_SHIFT) & PLL2550XX_SDIV_MASK;
>> +
>> + fvco *= mdiv;
>> + do_div(fvco, (pdiv << sdiv));
>> +
>> + return (unsigned long)fvco;
>> +}
>> +
>> +static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con)
>> +{
>> + if ((mdiv != ((pll_con >> PLL2550XX_MDIV_SHIFT) &
>> + PLL2550XX_MDIV_MASK)) ||
>> + (pdiv != ((pll_con >> PLL2550XX_PDIV_SHIFT) &
>> + PLL2550XX_PDIV_MASK)))
>> + return 1;
>> + else
>> + return 0;
>
> This doesn't look too good. Can you make this consistent with
> implementations of this helper for other PLLs, such as
> samsung_pll35xx_mp_change()?
I have changed this in V2.
>
>> +}
>> +
>> +static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate,
>> + unsigned long prate)
>> +{
>> + struct samsung_clk_pll *pll = to_clk_pll(hw);
>> + const struct samsung_pll_rate_table *rate;
>> + u32 tmp;
>> +
>> + /* Get required rate settings from table */
>> + rate = samsung_get_pll_settings(pll, drate);
>> + if (!rate) {
>> + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
>> + drate, __clk_get_name(hw->clk));
>> + return -EINVAL;
>> + }
>> +
>> + tmp = __raw_readl(pll->con_reg);
>> +
>> + if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) {
>> + /* If only s change, change just s value only*/
>> + tmp &= ~(PLL2550XX_SDIV_MASK << PLL2550XX_SDIV_SHIFT);
>> + tmp |= rate->sdiv << PLL2550XX_SDIV_SHIFT;
>> + __raw_writel(tmp, pll->con_reg);
>> + } else {
>
> Please make coding style of this function consistent with implementations
> of this operation for other PLLs, such as samsung_pll35xx_set_rate().
>
> Otherwise the patch looks fine.
Ok.
Regards,
Rahul Sharma.
>
> Best regards,
> Tomasz
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 6/7] clk/samsung: add support for pll2650xx
2013-12-19 11:45 ` Tomasz Figa
@ 2014-01-06 11:44 ` Rahul Sharma
2014-01-08 0:37 ` Tomasz Figa
0 siblings, 1 reply; 28+ messages in thread
From: Rahul Sharma @ 2014-01-06 11:44 UTC (permalink / raw)
To: linux-arm-kernel
Hi Tomasz,
On 19 December 2013 17:15, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi Rahul,
>
> On Friday 06 of December 2013 21:26:30 Rahul Sharma wrote:
>> Add support for pll2650xx in samsung pll file. This pll variant
>> is close to pll36xx but uses CON2 registers instead of CON1.
>
> If the ops are otherwise idential, why not reuse the ops for pll36xx
> and use CON1 or CON2 register conditionally based on pll->type field?
> (Just as it is already done for pll4600, 4650 and 4650c.)
>
I verified the difference and found that pll2650xx is fairly
different in terms of
Bit Fields, Con2 register, and additional PLL config bits than pll36xx. Due to
this, I have to add lot of if-else code based on pll type which
doesn't looks clean.
Regards,
Rahul Sharma.
> Best regards,
> Tomasz
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 6/7] clk/samsung: add support for pll2650xx
2014-01-06 11:44 ` Rahul Sharma
@ 2014-01-08 0:37 ` Tomasz Figa
0 siblings, 0 replies; 28+ messages in thread
From: Tomasz Figa @ 2014-01-08 0:37 UTC (permalink / raw)
To: linux-arm-kernel
On Monday 06 of January 2014 17:14:48 Rahul Sharma wrote:
> Hi Tomasz,
>
> On 19 December 2013 17:15, Tomasz Figa <t.figa@samsung.com> wrote:
> > Hi Rahul,
> >
> > On Friday 06 of December 2013 21:26:30 Rahul Sharma wrote:
> >> Add support for pll2650xx in samsung pll file. This pll variant
> >> is close to pll36xx but uses CON2 registers instead of CON1.
> >
> > If the ops are otherwise idential, why not reuse the ops for pll36xx
> > and use CON1 or CON2 register conditionally based on pll->type field?
> > (Just as it is already done for pll4600, 4650 and 4650c.)
> >
>
> I verified the difference and found that pll2650xx is fairly
> different in terms of
> Bit Fields, Con2 register, and additional PLL config bits than pll36xx. Due to
> this, I have to add lot of if-else code based on pll type which
> doesn't looks clean.
Fair enough.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2014-01-08 0:37 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-12-06 15:56 [PATCH 0/7] exynos: add basic support for exynos5260 SoC Rahul Sharma
2013-12-06 15:56 ` [PATCH 1/7] ARM: EXYNOS: initial board " Rahul Sharma
2013-12-09 6:23 ` Sachin Kamat
2013-12-09 6:33 ` Rahul Sharma
2013-12-23 4:39 ` Rahul Sharma
2013-12-10 15:57 ` Tomasz Figa
2014-01-03 9:24 ` Rahul Sharma
2013-12-06 15:56 ` [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data Rahul Sharma
2013-12-09 4:51 ` Sachin Kamat
2013-12-09 6:36 ` Rahul Sharma
2014-01-03 9:25 ` Rahul Sharma
2013-12-10 16:04 ` Tomasz Figa
2014-01-03 9:26 ` Rahul Sharma
2013-12-06 15:56 ` [PATCH 3/7] ARM: dts: add dts files for exynos5260 SoC Rahul Sharma
2013-12-10 17:10 ` Tomasz Figa
2014-01-06 9:40 ` Rahul Sharma
2013-12-06 15:56 ` [PATCH 4/7] clk/samsung: add support for multuple clock providers Rahul Sharma
2013-12-11 11:15 ` Tomasz Figa
2014-01-06 11:35 ` Rahul Sharma
2013-12-06 15:56 ` [PATCH 5/7] clk/samsung: add support for pll2550xx Rahul Sharma
2013-12-09 8:06 ` Sachin Kamat
2013-12-19 12:01 ` Tomasz Figa
2014-01-06 11:36 ` Rahul Sharma
2013-12-06 15:56 ` [PATCH 6/7] clk/samsung: add support for pll2650xx Rahul Sharma
2013-12-09 8:09 ` Sachin Kamat
2013-12-19 11:45 ` Tomasz Figa
2014-01-06 11:44 ` Rahul Sharma
2014-01-08 0:37 ` Tomasz Figa
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