[PATCH v5 0/4] ARM: BCM5301X: initial support for the BCM5301X/BCM470X SoCs with ARM CPU

[PATCH v5 0/4] ARM: BCM5301X: initial support for the BCM5301X/BCM470X SoCs with ARM CPU

[Hauke Mehrtens]

I am working on mainlining this SoC again which I started in Summer 
2013.

This adds initial support for Broadcom network SoC from the BCM5301X 
and BCM470X line.

The vendor BSP also uses BCM5301X for this SoC, so I just toke that.

I haven't found a better solution than the abort handler for the memory fault.

I do not have any documentation, only the vendor source code published 
by Asus and Netgear to conform with the GPL, it would be nice to get 
some documentation for this Soc like this
https://www.broadcom.com/collateral/pg/440X-PG02-R.pdf
for the Broadcom BCM440X Ethernet controller.

With some additional patches I got Ethernet working with ~250 MBit/s.

A bootlog can be found here:
http://hauke-m.de/files/openwrt/devices/R6250/openwrt-boot-2014-01-05.txt


Changes since v4:
 * removed bcm5301x_timer_init(), this function is not needed
 * removed GENERIC_TIME this is dead
 * made fault handler check for code and just catch the first fault.

Changes since v3:
 * rebase on Linus 3.13-rc7
 * split the workaround into an own patch
 * add L2 cache controller to Device tree
 * rename config option
 * add local-timer and SCU entry to device tree

Changes since v2:
 * use vendor prefix brcm
 * move code to arch/arm/mach-bcm/
 * cleanup arch/arm/mach-bcm/bcm5301x.c
 * rename to bcm5301x
 * split into more patches

Changes since v1:
 * add file Documentation/devicetree/bindings/arm/bcm4708.txt
 * rename bcm5301x to bcm4708 in dts files
 * use preprocessor includes in dts file
 * add CONFIG_ARCH_BCM53XX to multi_v7_defconfig
 * remove init_machine callback
 * rename vendor prefix from brcm to bcm
 * split into two patches 

Hauke Mehrtens (4):
  ARM: BCM5301X: initial support for the BCM5301X/BCM470X SoCs with ARM
    CPU
  ARM: BCM5301X: add early debugging support
  ARM: BCM5301X: add dts files for BCM4708 SoC
  ARM: BCM5301X: workaround suppress fault

 Documentation/devicetree/bindings/arm/bcm4708.txt |    8 ++
 MAINTAINERS                                       |    7 ++
 arch/arm/Kconfig.debug                            |    7 ++
 arch/arm/boot/dts/Makefile                        |    1 +
 arch/arm/boot/dts/bcm4708-netgear-r6250.dts       |   20 ++++
 arch/arm/boot/dts/bcm4708.dtsi                    |  102 +++++++++++++++++++++
 arch/arm/configs/multi_v7_defconfig               |    1 +
 arch/arm/mach-bcm/Kconfig                         |   26 ++++++
 arch/arm/mach-bcm/Makefile                        |    1 +
 arch/arm/mach-bcm/bcm_5301x.c                     |   61 ++++++++++++
 10 files changed, 234 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm4708.txt
 create mode 100644 arch/arm/boot/dts/bcm4708-netgear-r6250.dts
 create mode 100644 arch/arm/boot/dts/bcm4708.dtsi
 create mode 100644 arch/arm/mach-bcm/bcm_5301x.c

-- 
1.7.10.4

[PATCH v5 1/4] ARM: BCM5301X: initial support for the BCM5301X/BCM470X SoCs with ARM CPU

[Hauke Mehrtens]

This patch adds support for the BCM5301X/BCM470X SoCs with an ARM CPUs.
Currently just booting to a shell is working and nothing else, no
Ethernet, wifi, flash, ...
I have some pending patches to make Ethernet work for this device.
Mostly device tree support for bcma is missing.

This SoC is used in small office and home router with Broadcom SoCs.
This code should support the BCM4707, BCM4708, BCM4709, BCM53010,
BCM53011 and BCM53012 SoC. It uses one or two ARM Cortex A9
Cores, some highlights are 2 PCIe 2.0 controllers, 4 Gigabit Ethernet
MACs and a USB 3.0 host controller.

This SoC uses a dual core CPU, but this is currently not implemented.
More information about this SoC can be found here:
http://www.anandtech.com/show/5925/broadcom-announces-bcm4708x-and-bcm5301x-socs-for-80211ac-routers

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
 Documentation/devicetree/bindings/arm/bcm4708.txt |    8 ++++++
 MAINTAINERS                                       |    7 ++++++
 arch/arm/configs/multi_v7_defconfig               |    1 +
 arch/arm/mach-bcm/Kconfig                         |   26 +++++++++++++++++++
 arch/arm/mach-bcm/Makefile                        |    1 +
 arch/arm/mach-bcm/bcm_5301x.c                     |   28 +++++++++++++++++++++
 6 files changed, 71 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm4708.txt
 create mode 100644 arch/arm/mach-bcm/bcm_5301x.c

diff --git a/Documentation/devicetree/bindings/arm/bcm4708.txt b/Documentation/devicetree/bindings/arm/bcm4708.txt
new file mode 100644
index 0000000..6b0f49f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm4708.txt
@@ -0,0 +1,8 @@
+Broadcom BCM4708 device tree bindings
+-------------------------------------------
+
+Boards with the BCM4708 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "brcm,bcm4708";
diff --git a/MAINTAINERS b/MAINTAINERS
index 6c20792..2d98736 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1862,6 +1862,13 @@ F:	arch/arm/boot/dts/bcm2835*
 F:	arch/arm/configs/bcm2835_defconfig
 F:	drivers/*/*bcm2835*
 
+BROADCOM BCM5301X ARM ARCHICTURE
+M:	Hauke Mehrtens <hauke@hauke-m.de>
+L:	linux-arm-kernel at lists.infradead.org
+S:	Maintained
+F:	arch/arm/mach-bcm/bcm_5301x.c
+F:	arch/arm/boot/dts/bcm470*
+
 BROADCOM TG3 GIGABIT ETHERNET DRIVER
 M:	Nithin Nayak Sujir <nsujir@broadcom.com>
 M:	Michael Chan <mchan@broadcom.com>
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index c1df4e9..e7909ce 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -6,6 +6,7 @@ CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BCM_5301X=y
 CONFIG_ARCH_BCM_MOBILE=y
 CONFIG_GPIO_PCA953X=y
 CONFIG_ARCH_HIGHBANK=y
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 9fe6d88..6d6f562 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -31,6 +31,32 @@ config ARCH_BCM_MOBILE
 	  BCM11130, BCM11140, BCM11351, BCM28145 and
 	  BCM28155 variants.
 
+config ARCH_BCM_5301X
+	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
+	depends on MMU
+	select ARM_GIC
+	select CACHE_L2X0
+	select HAVE_ARM_SCU if SMP
+	select HAVE_ARM_TWD if SMP
+	select HAVE_SMP
+	select COMMON_CLK
+	select GENERIC_CLOCKEVENTS
+	select ARM_GLOBAL_TIMER
+	select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
+	select MIGHT_HAVE_PCI
+	help
+	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
+
+	  This is a network SoC line mostly used in home routers and
+	  wifi access points.
+	  This inclused the following SoC: BCM53010, BCM53011, BCM53012,
+	  BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707,
+	  BCM4708 and BCM4709.
+
+	  Do not confuse this with the BCM4760 which is a totally
+	  different SoC or with the older BCM47XX and BCM53XX based
+	  network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index c2ccd5a..0164913 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -13,3 +13,4 @@
 obj-$(CONFIG_ARCH_BCM_MOBILE)	:= board_bcm281xx.o bcm_kona_smc.o bcm_kona_smc_asm.o kona.o
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_bcm_kona_smc_asm.o	:=-Wa,-march=armv7-a$(plus_sec)
+obj-$(CONFIG_ARCH_BCM_5301X)	+= bcm_5301x.o
diff --git a/arch/arm/mach-bcm/bcm_5301x.c b/arch/arm/mach-bcm/bcm_5301x.c
new file mode 100644
index 0000000..ef9740a
--- /dev/null
+++ b/arch/arm/mach-bcm/bcm_5301x.c
@@ -0,0 +1,28 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ *
+ * Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+#include <linux/of_platform.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <asm/mach/arch.h>
+
+
+static void __init bcm5301x_dt_init(void)
+{
+	l2x0_of_init(0, ~0UL);
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char __initconst *bcm5301x_dt_compat[] = {
+	"brcm,bcm4708",
+	NULL,
+};
+
+DT_MACHINE_START(BCM5301X, "BCM5301X")
+	.init_machine	= bcm5301x_dt_init,
+	.dt_compat	= bcm5301x_dt_compat,
+MACHINE_END
-- 
1.7.10.4

[PATCH v5 2/4] ARM: BCM5301X: add early debugging support

[Hauke Mehrtens]

This adds support for early debugging of BCM5301X SoC.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/Kconfig.debug |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 5765abf..16bd36e 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -94,6 +94,11 @@ choice
 		depends on ARCH_BCM2835
 		select DEBUG_UART_PL01X
 
+	config DEBUG_BCM_5301X
+		bool "Kernel low-level debugging on BCM5301X UART1"
+		depends on ARCH_BCM_5301X
+		select DEBUG_UART_PL01X
+
 	config DEBUG_CLPS711X_UART1
 		bool "Kernel low-level debugging messages via UART1"
 		depends on ARCH_CLPS711X
@@ -988,6 +993,7 @@ config DEBUG_UART_PHYS
 	default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
 	default 0x20068000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3
 	default 0x20201000 if DEBUG_BCM2835
+	default 0x18000300 if DEBUG_BCM_5301X
 	default 0x4000e400 if DEBUG_LL_UART_EFM32
 	default 0x40090000 if ARCH_LPC32XX
 	default 0x40100000 if DEBUG_PXA_UART1
@@ -1029,6 +1035,7 @@ config DEBUG_UART_VIRT
 	default 0xf0009000 if DEBUG_CNS3XXX
 	default 0xf01fb000 if DEBUG_NOMADIK_UART
 	default 0xf0201000 if DEBUG_BCM2835
+	default 0xf1000300 if DEBUG_BCM_5301X
 	default 0xf11f1000 if ARCH_VERSATILE
 	default 0xf1600000 if ARCH_INTEGRATOR
 	default 0xf1c28000 if DEBUG_SUNXI_UART0
-- 
1.7.10.4

[PATCH v5 3/4] ARM: BCM5301X: add dts files for BCM4708 SoC

[Hauke Mehrtens]

This uses the newly added BCM5301X SoC code.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/boot/dts/Makefile                  |    1 +
 arch/arm/boot/dts/bcm4708-netgear-r6250.dts |   20 ++++++
 arch/arm/boot/dts/bcm4708.dtsi              |  102 +++++++++++++++++++++++++++
 3 files changed, 123 insertions(+)
 create mode 100644 arch/arm/boot/dts/bcm4708-netgear-r6250.dts
 create mode 100644 arch/arm/boot/dts/bcm4708.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d57c1a6..9c385bb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -45,6 +45,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
 dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \
 	bcm28155-ap.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
+dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
 dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
 	da850-evm.dtb
 dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
new file mode 100644
index 0000000..34875f6
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
@@ -0,0 +1,20 @@
+/*
+ * Broadcom BCM470X / BCM5301X arm platform code.
+ *
+ * Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+/dts-v1/;
+
+#include "bcm4708.dtsi"
+
+/ {
+	compatible = "netgear,r6250v1", "brcm,bcm4708";
+	model = "Netgear R6250 V1 (BCM4708)";
+
+	memory {
+		reg = <0x00000000 0x08000000>;
+	};
+};
diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi
new file mode 100644
index 0000000..36937f1
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708.dtsi
@@ -0,0 +1,102 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ *
+ * Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "brcm,bcm4708";
+	model = "Broadcom BCM4708";
+	interrupt-parent = <&gic>;
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0>;
+		};
+		cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <1>;
+		};
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* As long as we do not have a real clock driver us this
+		 * fixed clock */
+		clk_periph: periph {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <400000000>;
+		};
+	};
+
+	uart at 18000300 {
+		compatible = "ns16550";
+		reg = <0x18000300 0x100>;
+		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <100000000>;
+	};
+
+	uart at 18000400 {
+		compatible = "ns16550";
+		reg = <0x18000400 0x100>;
+		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <100000000>;
+	};
+
+	scu at 19020000 {
+		compatible = "arm,cortex-a9-scu";
+		reg = <0x19020000 0x100>;
+	};
+
+	timer at 19020200 {
+		compatible = "arm,cortex-a9-global-timer";
+		reg = <0x19020200 0x100>;
+		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk_periph>;
+	};
+
+	local-timer at 19020600 {
+		compatible = "arm,cortex-a9-twd-timer";
+		reg = <0x19020600 0x100>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk_periph>;
+	};
+
+	gic: interrupt-controller at 19021000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		interrupt-controller;
+		reg = <0x19021000 0x1000>,
+		      <0x19020100 0x100>;
+	};
+
+	L2: cache-controller at 19022000 {
+		compatible = "arm,pl310-cache";
+		reg = <0x19022000 0x1000>;
+		cache-unified;
+		cache-level = <2>;
+	};
+};
-- 
1.7.10.4

[PATCH v5 4/4] ARM: BCM5301X: workaround suppress fault

[Hauke Mehrtens]

Without this patch I am getting a unhandled fault exception like this
one after "Freeing unused kernel memory":

Freeing unused kernel memory: 1260K (c02c1000 - c03fc000)
Unhandled fault: imprecise external abort (0x1c06) at 0xb6f89005
Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007

The address which is here 0xb6f89005 changes from boot to boot, with a
new build the changes are bigger. With kernel 3.10 I have also seen
this fault at different places in the boot process, but starting with
3.11 they are mostly occurring after the "Freeing unused kernel memory"
message. I never was able to completely boot to userspace without this
handler. The abort code is constant 0x1c06. This fault just happens
once in the boot process I have never seen it happing twice or more.

I also tried changing the CPSR.A bit to 0 in init_early, with this code
like Afzal suggested, but that did not change anything:
asm volatile("mrs r12, cpsr\n"
	"bic r12, r12, #0x00000100\n"
	"msr cpsr_c, r12" ::: "r12", "cc", "memory");

Disabling the L2 cache by building with CONFIG_CACHE_L2X0 unset did not
help.

This workaround was copied from the vendor code including most of the
comments. It says it they think this is caused by the CFE boot loader
used on this device. I do not have any access to any datasheet or
errata document to check this.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 arch/arm/mach-bcm/bcm_5301x.c |   33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm/mach-bcm/bcm_5301x.c b/arch/arm/mach-bcm/bcm_5301x.c
index ef9740a..edff6976 100644
--- a/arch/arm/mach-bcm/bcm_5301x.c
+++ b/arch/arm/mach-bcm/bcm_5301x.c
@@ -9,8 +9,40 @@
 #include <asm/hardware/cache-l2x0.h>
 
 #include <asm/mach/arch.h>
+#include <asm/siginfo.h>
+#include <asm/signal.h>
 
 
+static bool first_fault = true;
+
+static int bcm5301x_abort_handler(unsigned long addr, unsigned int fsr,
+				 struct pt_regs *regs)
+{
+	if (fsr == 0x1c06 && first_fault) {
+		first_fault = false;
+
+		/*
+		 * These faults with code 0x1c06 happens for no good reason,
+		 * possibly left over from the CFE boot loader.
+		 */
+		pr_warn("External imprecise Data abort at addr=%#lx, fsr=%#x ignored.\n",
+		addr, fsr);
+
+		/* Returning non-zero causes fault display and panic */
+		return 0;
+	}
+
+	/* Others should cause a fault */
+	return 1;
+}
+
+static void __init bcm5301x_init_early(void)
+{
+	/* Install our hook */
+	hook_fault_code(16 + 6, bcm5301x_abort_handler, SIGBUS, BUS_OBJERR,
+			"imprecise external abort");
+}
+
 static void __init bcm5301x_dt_init(void)
 {
 	l2x0_of_init(0, ~0UL);
@@ -23,6 +55,7 @@ static const char __initconst *bcm5301x_dt_compat[] = {
 };
 
 DT_MACHINE_START(BCM5301X, "BCM5301X")
+	.init_early	= bcm5301x_init_early,
 	.init_machine	= bcm5301x_dt_init,
 	.dt_compat	= bcm5301x_dt_compat,
 MACHINE_END
-- 
1.7.10.4

[PATCH v5 3/4] ARM: BCM5301X: add dts files for BCM4708 SoC

[Thomas Petazzoni]

Dear Hauke Mehrtens,

On Mon,  6 Jan 2014 00:46:40 +0100, Hauke Mehrtens wrote:

> +	uart at 18000300 {
> +		compatible = "ns16550";
> +		reg = <0x18000300 0x100>;
> +		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> +		clock-frequency = <100000000>;
> +	};
> +
> +	uart at 18000400 {
> +		compatible = "ns16550";
> +		reg = <0x18000400 0x100>;
> +		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> +		clock-frequency = <100000000>;
> +	};
> +
> +	scu at 19020000 {
> +		compatible = "arm,cortex-a9-scu";
> +		reg = <0x19020000 0x100>;
> +	};
> +
> +	timer at 19020200 {
> +		compatible = "arm,cortex-a9-global-timer";
> +		reg = <0x19020200 0x100>;
> +		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&clk_periph>;
> +	};
> +
> +	local-timer at 19020600 {
> +		compatible = "arm,cortex-a9-twd-timer";
> +		reg = <0x19020600 0x100>;
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&clk_periph>;
> +	};
> +
> +	gic: interrupt-controller at 19021000 {
> +		compatible = "arm,cortex-a9-gic";
> +		#interrupt-cells = <3>;
> +		#address-cells = <0>;
> +		interrupt-controller;
> +		reg = <0x19021000 0x1000>,
> +		      <0x19020100 0x100>;
> +	};
> +
> +	L2: cache-controller at 19022000 {
> +		compatible = "arm,pl310-cache";
> +		reg = <0x19022000 0x1000>;
> +		cache-unified;
> +		cache-level = <2>;
> +	};

I don't know if that has been discussed before, but most of the DTS
group the internal SoC peripherals in some top-level node that
represents the internal bus (or busses) of the SoC, like:

	<some bus name> {
		uart at ... {
			...
		};

		gic at ... {
			...
		};
	};

This allows to have the in-SoC peripherals cleanly separated from other
things in the DTS. It would also you to use a ranges = <...> property
to do an address translation on this bus, and replace the absolute
addresses for each of the peripherals by offsets relative to the base
address of where all peripherals are mapped.

That said, having this top-level node is most likely not a requirement,
so my comment is mainly meant to open the discussion. I'm sure Arnd
will give his opinion on this :)

Best regards,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH v5 4/4] ARM: BCM5301X: workaround suppress fault

[Arnd Bergmann]

On Monday 06 January 2014, Hauke Mehrtens wrote:
> Without this patch I am getting a unhandled fault exception like this
> one after "Freeing unused kernel memory":
> 
> Freeing unused kernel memory: 1260K (c02c1000 - c03fc000)
> Unhandled fault: imprecise external abort (0x1c06) at 0xb6f89005
> Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007
> 
> The address which is here 0xb6f89005 changes from boot to boot, with a
> new build the changes are bigger. With kernel 3.10 I have also seen
> this fault at different places in the boot process, but starting with
> 3.11 they are mostly occurring after the "Freeing unused kernel memory"
> message. I never was able to completely boot to userspace without this
> handler. The abort code is constant 0x1c06. This fault just happens
> once in the boot process I have never seen it happing twice or more.
> 
> I also tried changing the CPSR.A bit to 0 in init_early, with this code
> like Afzal suggested, but that did not change anything:
> asm volatile("mrs r12, cpsr\n"
>         "bic r12, r12, #0x00000100\n"
>         "msr cpsr_c, r12" ::: "r12", "cc", "memory");
> 
> Disabling the L2 cache by building with CONFIG_CACHE_L2X0 unset did not
> help.
> 
> This workaround was copied from the vendor code including most of the
> comments. It says it they think this is caused by the CFE boot loader
> used on this device. I do not have any access to any datasheet or
> errata document to check this.
> 
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

Acked-by: Arnd Bergmann <arnd@arndb.de>

[PATCH v5 3/4] ARM: BCM5301X: add dts files for BCM4708 SoC

[Hauke Mehrtens]

On 01/06/2014 02:00 AM, Thomas Petazzoni wrote:
> Dear Hauke Mehrtens,
> 
> On Mon,  6 Jan 2014 00:46:40 +0100, Hauke Mehrtens wrote:
> 
>> +	uart at 18000300 {
>> +		compatible = "ns16550";
>> +		reg = <0x18000300 0x100>;
>> +		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>> +		clock-frequency = <100000000>;
>> +	};
>> +
>> +	uart at 18000400 {
>> +		compatible = "ns16550";
>> +		reg = <0x18000400 0x100>;
>> +		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>> +		clock-frequency = <100000000>;
>> +	};
>> +
>> +	scu at 19020000 {
>> +		compatible = "arm,cortex-a9-scu";
>> +		reg = <0x19020000 0x100>;
>> +	};
>> +
>> +	timer at 19020200 {
>> +		compatible = "arm,cortex-a9-global-timer";
>> +		reg = <0x19020200 0x100>;
>> +		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&clk_periph>;
>> +	};
>> +
>> +	local-timer at 19020600 {
>> +		compatible = "arm,cortex-a9-twd-timer";
>> +		reg = <0x19020600 0x100>;
>> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&clk_periph>;
>> +	};
>> +
>> +	gic: interrupt-controller at 19021000 {
>> +		compatible = "arm,cortex-a9-gic";
>> +		#interrupt-cells = <3>;
>> +		#address-cells = <0>;
>> +		interrupt-controller;
>> +		reg = <0x19021000 0x1000>,
>> +		      <0x19020100 0x100>;
>> +	};
>> +
>> +	L2: cache-controller at 19022000 {
>> +		compatible = "arm,pl310-cache";
>> +		reg = <0x19022000 0x1000>;
>> +		cache-unified;
>> +		cache-level = <2>;
>> +	};
> 
> I don't know if that has been discussed before, but most of the DTS
> group the internal SoC peripherals in some top-level node that
> represents the internal bus (or busses) of the SoC, like:
> 
> 	<some bus name> {
> 		uart at ... {
> 			...
> 		};
> 
> 		gic at ... {
> 			...
> 		};
> 	};
> 
> This allows to have the in-SoC peripherals cleanly separated from other
> things in the DTS. It would also you to use a ranges = <...> property
> to do an address translation on this bus, and replace the absolute
> addresses for each of the peripherals by offsets relative to the base
> address of where all peripherals are mapped.
> 
> That said, having this top-level node is most likely not a requirement,
> so my comment is mainly meant to open the discussion. I'm sure Arnd
> will give his opinion on this :)
> 

I spited it up like it was done for the rockchip SoCs.
One dtsi file for a line of SoCs, one for the specific SoC and one for
the device. How does this ranges stuff work, do you have an example for me?

Hauke

[PATCH v5 3/4] ARM: BCM5301X: add dts files for BCM4708 SoC

[Arnd Bergmann]

On Monday 06 January 2014, Hauke Mehrtens wrote:
> On 01/06/2014 02:00 AM, Thomas Petazzoni wrote:

> > I don't know if that has been discussed before, but most of the DTS
> > group the internal SoC peripherals in some top-level node that
> > represents the internal bus (or busses) of the SoC, like:
> > 
> > 	<some bus name> {
> > 		uart at ... {
> > 			...
> > 		};
> > 
> > 		gic at ... {
> > 			...
> > 		};
> > 	};
> > 
> > This allows to have the in-SoC peripherals cleanly separated from other
> > things in the DTS. It would also you to use a ranges = <...> property
> > to do an address translation on this bus, and replace the absolute
> > addresses for each of the peripherals by offsets relative to the base
> > address of where all peripherals are mapped.
> > 
> > That said, having this top-level node is most likely not a requirement,
> > so my comment is mainly meant to open the discussion. I'm sure Arnd
> > will give his opinion on this :)
> > 
> 
> I spited it up like it was done for the rockchip SoCs.
> One dtsi file for a line of SoCs, one for the specific SoC and one for
> the device. How does this ranges stuff work, do you have an example for me?

kirkwood.dtsi has some good examples. For instance there is a UART at
0xf1012000, which gets described as a device at local address 0x12000,
and a parent bus that translates the global 1MB range at 0xf1000000 to
local address range 0x00000000. The organization of the buses should
match the physical layout of the chip as described in the data sheet.

Note that in case of kirkwood, the 1MB register range is actually
relocatable and the devices are described using offsets in the data
sheet. On other SoCs the internal bus still uses a full 32-bit
address. It still makes sense to split up the device nodes by buses
then, but the you may want a ranges property like 

	ranges = <0x190000000 0x19000000 0x01000000>;

rather than 

	ranges = <0 0x19000000 0x01000000>;

in that case, so the addresses in the device nodes still match
the numbers from the data sheet. You can also have an empty "ranges"
property that just states that all addresses are available on the
bus, if that is what the hardware does.

	Arnd