[PATCH v2 0/8] DMAEngine support for sun4i, sun5i & sun7i

[PATCH v2 0/8] DMAEngine support for sun4i, sun5i & sun7i

[Emilio López]

Hi everyone,

As part of Google Summer of Code, I've tasked myself with implementing
DMA support for the earlier Allwinner platforms. This second round of
patches is the result of said effort.

The first patch is the actual driver to support these platforms. Patches
three, four and five add the corresponding DMA node to the sun4i,
sun5i and sun7i device trees.

The second patch, involving the sunxi SPI driver, lets users do SPI
transfers of >=64 bytes by using DMA. The first round of patches also
had a patch for 8250_dw letting it use DMA as well, but there were some
issues causing underruns and "too much work for IRQ", so I have dropped
them. It's worth noting that Allwinner themselves don't use DMA
transfers on their 8250 driver on the SDK.

Patches six, seven and eight add the DMA properties to SPI so the first
two patches can be used. Patches nine, ten and eleven are *only intended
for testing*, and add a dummy SPIdev device to cubieboard, cubietruck
and A10S-OLinuXino to facilitate testing with spidev_test.

My main testing procedure for SPI has been modified versions of
spidev_test from the kernel tree, with and without shorting MISO and
MOSI. For memory to memory transfers, I have used dmatest.ko with
various configurations. I have done testing on a cubieboard (A10, sun4i)
and cubietruck (A20, sun7i) as well as an A10S-OLinuXino.

You will find some extra remarks on individual patches after their
descriptions. All comments are welcome.

Thanks!

Emilio L?pez (8):
  dma: sun4i: Add support for the DMA engine on sun[457]i SoCs
  spi: sun4i: add DMA support
  ARM: sun4i: Add node to represent the DMA controller
  ARM: sun5i: Add nodes to represent the DMA controllers
  ARM: sun7i: Add node to represent the DMA controller
  ARM: sun4i: enable DMA on SPI
  ARM: sun5i: enable DMA on SPI
  ARM: sun7i: enable DMA on SPI

 .../devicetree/bindings/dma/sun4i-dma.txt          |   45 +
 arch/arm/boot/dts/sun4i-a10.dtsi                   |   16 +
 arch/arm/boot/dts/sun5i-a10s.dtsi                  |   14 +
 arch/arm/boot/dts/sun5i-a13.dtsi                   |   14 +
 arch/arm/boot/dts/sun7i-a20.dtsi                   |   16 +
 drivers/dma/Kconfig                                |   10 +
 drivers/dma/Makefile                               |    1 +
 drivers/dma/sun4i-dma.c                            | 1025 ++++++++++++++++++++
 drivers/spi/spi-sun4i.c                            |  155 ++-
 9 files changed, 1285 insertions(+), 11 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/dma/sun4i-dma.txt
 create mode 100644 drivers/dma/sun4i-dma.c

-- 
2.0.1

[PATCH v2 1/8] dma: sun4i: Add support for the DMA engine on sun[457]i SoCs

[Emilio López]

This patch adds support for the DMA engine present on Allwinner A10,
A13, A10S and A20 SoCs. This engine has two kinds of channels: normal
and dedicated. The main difference is in the mode of operation;
while a single normal channel may be operating at any given time,
dedicated channels may operate simultaneously provided there is no
overlap of source or destination.

Hardware documentation can be found on A10 User Manual (section 12), A13
User Manual (section 14) and A20 User Manual (section 1.12)

Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---

Changes from v1:
 * address comments from Chen-Yu and Maxime
 * fix issue converting bus width
 * switch to using a threaded IRQ instead of a tasklet on
   recommendation from Maxime
 * fix issue setting magic timing parameter for SPI transfers
 * fix an issue with list handling reported by the kbuild 0-DAY robot (thanks!)
 * drop a lot of unused #define
 * probably some more stuff I'm forgetting

 .../devicetree/bindings/dma/sun4i-dma.txt          |   45 +
 drivers/dma/Kconfig                                |   10 +
 drivers/dma/Makefile                               |    1 +
 drivers/dma/sun4i-dma.c                            | 1025 ++++++++++++++++++++
 4 files changed, 1081 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/sun4i-dma.txt
 create mode 100644 drivers/dma/sun4i-dma.c

diff --git a/Documentation/devicetree/bindings/dma/sun4i-dma.txt b/Documentation/devicetree/bindings/dma/sun4i-dma.txt
new file mode 100644
index 0000000..f5661a5
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/sun4i-dma.txt
@@ -0,0 +1,45 @@
+Allwinner A10 DMA Controller
+
+This driver follows the generic DMA bindings defined in dma.txt.
+
+Required properties:
+
+- compatible:	Must be "allwinner,sun4i-a10-dma"
+- reg:		Should contain the registers base address and length
+- interrupts:	Should contain a reference to the interrupt used by this device
+- clocks:	Should contain a reference to the parent AHB clock
+- #dma-cells :	Should be 1, a single cell holding a line request number
+
+Example:
+	dma: dma-controller at 01c02000 {
+		compatible = "allwinner,sun4i-a10-dma";
+		reg = <0x01c02000 0x1000>;
+		interrupts = <27>;
+		clocks = <&ahb_gates 6>;
+		#dma-cells = <1>;
+	};
+
+Clients:
+
+DMA clients connected to the Allwinner A10 DMA controller must use the
+format described in the dma.txt file, using a three-cell specifier for
+each channel: a phandle plus two integer cells.
+The three cells in order are:
+
+1. A phandle pointing to the DMA controller.
+2. Whether it is using normal (0) or dedicated (1) channels
+2. The port ID as specified in the datasheet
+
+Example:
+	spi2: spi at 01c17000 {
+		compatible = "allwinner,sun4i-a10-spi";
+		reg = <0x01c17000 0x1000>;
+		interrupts = <0 12 4>;
+		clocks = <&ahb_gates 22>, <&spi2_clk>;
+		clock-names = "ahb", "mod";
+		dmas = <&dma 1 29>, <&dma 1 28>;
+		dma-names = "rx", "tx";
+		status = "disabled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 1eca7b9..cfa6e0a 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -375,6 +375,16 @@ config XILINX_VDMA
 	  channels, Memory Mapped to Stream (MM2S) and Stream to
 	  Memory Mapped (S2MM) for the data transfers.
 
+config SUN4I_DMA
+	tristate "Allwinner A10/A10S/A13/A20 DMA support"
+	depends on (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || (COMPILE_TEST && OF && ARM))
+	select DMA_ENGINE
+	select DMA_OF
+	select DMA_VIRTUAL_CHANNELS
+	help
+	  Enable support for the DMA controller present in the sun4i,
+	  sun5i and sun7i Allwinner ARM SoCs.
+
 config DMA_ENGINE
 	bool
 
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index c779e1e..430de61 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -47,3 +47,4 @@ obj-$(CONFIG_MOXART_DMA) += moxart-dma.o
 obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
 obj-$(CONFIG_QCOM_BAM_DMA) += qcom_bam_dma.o
 obj-y += xilinx/
+obj-$(CONFIG_SUN4I_DMA) += sun4i-dma.o
diff --git a/drivers/dma/sun4i-dma.c b/drivers/dma/sun4i-dma.c
new file mode 100644
index 0000000..24fa391
--- /dev/null
+++ b/drivers/dma/sun4i-dma.c
@@ -0,0 +1,1025 @@
+/*
+ * Copyright (C) 2014 Emilio L?pez
+ * Emilio L?pez <emilio@elopez.com.ar>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/bitmap.h>
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/dmaengine.h>
+#include <linux/dmapool.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of_dma.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include "virt-dma.h"
+
+/** Normal DMA register values **/
+
+/* Normal DMA source/destination data request type values */
+#define NDMA_DRQ_TYPE_SDRAM			0x16
+#define NDMA_DRQ_TYPE_LIMIT			(0x1F + 1)
+
+/** Normal DMA register layout **/
+
+/* Normal DMA configuration register layout */
+#define NDMA_CFG_LOADING			BIT(31)
+#define NDMA_CFG_CONT_MODE			BIT(30)
+#define NDMA_CFG_WAIT_STATE(n)			((n) << 27)
+#define NDMA_CFG_DEST_DATA_WIDTH(width)		((width) << 25)
+#define NDMA_CFG_DEST_BURST_LENGTH(len)		((len) << 23)
+#define NDMA_CFG_DEST_NON_SECURE		BIT(22)
+#define NDMA_CFG_DEST_FIXED_ADDR		BIT(21)
+#define NDMA_CFG_DEST_DRQ_TYPE(type)		((type) << 16)
+#define NDMA_CFG_BYTE_COUNT_MODE_REMAIN		BIT(15)
+#define NDMA_CFG_SRC_DATA_WIDTH(width)		((width) << 9)
+#define NDMA_CFG_SRC_BURST_LENGTH(len)		((len) << 7)
+#define NDMA_CFG_SRC_NON_SECURE			BIT(6)
+#define NDMA_CFG_SRC_FIXED_ADDR			BIT(5)
+#define NDMA_CFG_SRC_DRQ_TYPE(type)		((type) << 0)
+
+/** Dedicated DMA register values **/
+
+/* Dedicated DMA source/destination address mode values */
+#define DDMA_ADDR_MODE_LINEAR			0
+#define DDMA_ADDR_MODE_IO			1
+#define DDMA_ADDR_MODE_HORIZONTAL_PAGE		2
+#define DDMA_ADDR_MODE_VERTICAL_PAGE		3
+
+/* Dedicated DMA source/destination data request type values */
+#define DDMA_DRQ_TYPE_SDRAM			0x1
+#define DDMA_DRQ_TYPE_LIMIT			(0x1F + 1)
+
+/** Dedicated DMA register layout **/
+
+/* Dedicated DMA configuration register layout */
+#define DDMA_CFG_LOADING			BIT(31)
+#define DDMA_CFG_BUSY				BIT(30)
+#define DDMA_CFG_CONT_MODE			BIT(29)
+#define DDMA_CFG_DEST_NON_SECURE		BIT(28)
+#define DDMA_CFG_DEST_DATA_WIDTH(width)		((width) << 25)
+#define DDMA_CFG_DEST_BURST_LENGTH(len)		((len) << 23)
+#define DDMA_CFG_DEST_ADDR_MODE(mode)		((mode) << 21)
+#define DDMA_CFG_DEST_DRQ_TYPE(type)		((type) << 16)
+#define DDMA_CFG_BYTE_COUNT_MODE_REMAIN		BIT(15)
+#define DDMA_CFG_SRC_NON_SECURE			BIT(12)
+#define DDMA_CFG_SRC_DATA_WIDTH(width)		((width) << 9)
+#define DDMA_CFG_SRC_BURST_LENGTH(len)		((len) << 7)
+#define DDMA_CFG_SRC_ADDR_MODE(mode)		((mode) << 5)
+#define DDMA_CFG_SRC_DRQ_TYPE(type)		((type) << 0)
+
+/* Dedicated DMA parameter register layout */
+#define DDMA_PARA_DEST_DATA_BLK_SIZE(n)		(((n) - 1) << 24)
+#define DDMA_PARA_DEST_WAIT_CYCLES(n)		(((n) - 1) << 16)
+#define DDMA_PARA_SRC_DATA_BLK_SIZE(n)		(((n) - 1) << 8)
+#define DDMA_PARA_SRC_WAIT_CYCLES(n)		(((n) - 1) << 0)
+
+/** DMA register offsets **/
+
+/* General register offsets */
+#define DMA_IRQ_ENABLE_REG			0x0
+#define DMA_IRQ_PENDING_STATUS_REG		0x4
+
+/* Normal DMA register offsets */
+#define NDMA_CHANNEL_REG_BASE(n)		(0x100 + (n) * 0x20)
+#define NDMA_CFG_REG				0x0
+#define NDMA_SRC_ADDR_REG			0x4
+#define NDMA_DEST_ADDR_REG			0x8
+#define NDMA_BYTE_COUNT_REG			0xC
+
+/* Dedicated DMA register offsets */
+#define DDMA_CHANNEL_REG_BASE(n)		(0x300 + (n) * 0x20)
+#define DDMA_CFG_REG				0x0
+#define DDMA_SRC_ADDR_REG			0x4
+#define DDMA_DEST_ADDR_REG			0x8
+#define DDMA_BYTE_COUNT_REG			0xC
+#define DDMA_PARA_REG				0x18
+
+/** DMA Driver **/
+
+/*
+ * Normal DMA has 8 channels, and Dedicated DMA has another 8, so that's
+ * 16 channels. As for endpoints, there's 29 and 21 respectively. Given
+ * that the Normal DMA endpoints (other than SDRAM) can be used as tx/rx,
+ * we need 78 vchans in total
+ */
+#define NDMA_NR_MAX_CHANNELS	8
+#define DDMA_NR_MAX_CHANNELS	8
+#define DMA_NR_MAX_CHANNELS	(NDMA_NR_MAX_CHANNELS + DDMA_NR_MAX_CHANNELS)
+#define NDMA_NR_MAX_VCHANS	(29 * 2 - 1)
+#define DDMA_NR_MAX_VCHANS	21
+#define DMA_NR_MAX_VCHANS	(NDMA_NR_MAX_VCHANS + DDMA_NR_MAX_VCHANS)
+
+/* This set of DDMA timing parameters were found experimentally while
+ * working with the SPI driver and seem to make it behave correctly */
+#define DDMA_MAGIC_SPI_PARAMETERS	(DDMA_PARA_DEST_DATA_BLK_SIZE(1) | \
+					DDMA_PARA_SRC_DATA_BLK_SIZE(1) | \
+					DDMA_PARA_DEST_WAIT_CYCLES(2) | \
+					DDMA_PARA_SRC_WAIT_CYCLES(2))
+
+struct sun4i_dma_pchan {
+	/* Register base of channel */
+	void __iomem			*base;
+	/* vchan currently being serviced */
+	struct sun4i_dma_vchan		*vchan;
+	/* Is this a dedicated pchan? */
+	int				is_dedicated;
+};
+
+struct sun4i_dma_vchan {
+	struct virt_dma_chan		vc;
+	struct dma_slave_config		cfg;
+	struct sun4i_dma_pchan		*pchan;
+	struct sun4i_dma_promise	*processing;
+	struct sun4i_dma_contract	*contract;
+	u8				endpoint;
+	int				is_dedicated;
+};
+
+struct sun4i_dma_promise {
+	u32				cfg;
+	u32				para;
+	dma_addr_t			src;
+	dma_addr_t			dst;
+	size_t				len;
+	struct list_head		list;
+};
+
+/* A contract is a set of promises */
+struct sun4i_dma_contract {
+	struct virt_dma_desc		vd;
+	struct list_head		demands;
+	struct list_head		completed_demands;
+};
+
+struct sun4i_dma_dev {
+	DECLARE_BITMAP(pchans_used, DMA_NR_MAX_CHANNELS);
+	struct dma_device		slave;
+	struct sun4i_dma_pchan		*pchans;
+	struct sun4i_dma_vchan		*vchans;
+	void __iomem			*base;
+	struct clk			*clk;
+	int				irq;
+	spinlock_t			lock;
+};
+
+static struct sun4i_dma_dev *to_sun4i_dma_dev(struct dma_device *dev)
+{
+	return container_of(dev, struct sun4i_dma_dev, slave);
+}
+
+static struct sun4i_dma_vchan *to_sun4i_dma_vchan(struct dma_chan *chan)
+{
+	return container_of(chan, struct sun4i_dma_vchan, vc.chan);
+}
+
+static struct sun4i_dma_contract *to_sun4i_dma_contract(struct virt_dma_desc *vd)
+{
+	return container_of(vd, struct sun4i_dma_contract, vd);
+}
+
+static struct device *chan2dev(struct dma_chan *chan)
+{
+	return &chan->dev->device;
+}
+
+static int convert_burst(u32 maxburst)
+{
+	if (maxburst > 8)
+		return -EINVAL;
+
+	/* 1 -> 0, 4 -> 1, 8 -> 2 */
+	return (maxburst >> 2);
+}
+
+static int convert_buswidth(enum dma_slave_buswidth addr_width)
+{
+	if (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES)
+		return -EINVAL;
+
+	/* 8 (1 byte) -> 0, 16 (2 bytes) -> 1, 32 (4 bytes) -> 2 */
+	return (addr_width >> 1);
+}
+
+static int sun4i_dma_alloc_chan_resources(struct dma_chan *chan)
+{
+	return 0;
+}
+
+static void sun4i_dma_free_chan_resources(struct dma_chan *chan)
+{
+	struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
+
+	vchan_free_chan_resources(&vchan->vc);
+}
+
+static struct sun4i_dma_pchan *find_and_use_pchan(struct sun4i_dma_dev *priv,
+						  struct sun4i_dma_vchan *vchan)
+{
+	struct sun4i_dma_pchan *pchan = NULL, *pchans = priv->pchans;
+	unsigned long flags;
+	int i, max;
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	/*
+	 * pchans 0-NDMA_NR_MAX_CHANNELS are normal, and
+	 * NDMA_NR_MAX_CHANNELS+ are dedicated ones
+	 */
+	if (vchan->is_dedicated) {
+		i = NDMA_NR_MAX_CHANNELS;
+		max = DMA_NR_MAX_CHANNELS;
+	} else {
+		i = 0;
+		max = NDMA_NR_MAX_CHANNELS;
+	}
+
+	for_each_clear_bit_from(i, &priv->pchans_used, max) {
+		pchan = &pchans[i];
+		pchan->vchan = vchan;
+		set_bit(i, priv->pchans_used);
+		break;
+	}
+
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	return pchan;
+}
+
+static void release_pchan(struct sun4i_dma_dev *priv,
+			  struct sun4i_dma_pchan *pchan)
+{
+	unsigned long flags;
+	int nr = pchan - priv->pchans;
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	clear_bit(nr, priv->pchans_used);
+	pchan->vchan = NULL;
+
+	spin_unlock_irqrestore(&priv->lock, flags);
+}
+
+static void configure_pchan(struct sun4i_dma_pchan *pchan,
+			    struct sun4i_dma_promise *d)
+{
+	/*
+	 * Configure addresses and misc parameters depending on type
+	 * DDMA has an extra field with timing parameters
+	 */
+	if (pchan->is_dedicated) {
+		writel_relaxed(d->src, pchan->base + DDMA_SRC_ADDR_REG);
+		writel_relaxed(d->dst, pchan->base + DDMA_DEST_ADDR_REG);
+		writel_relaxed(d->len, pchan->base + DDMA_BYTE_COUNT_REG);
+		writel_relaxed(d->para, pchan->base + DDMA_PARA_REG);
+		writel_relaxed(d->cfg, pchan->base + DDMA_CFG_REG);
+	} else {
+		writel_relaxed(d->src, pchan->base + NDMA_SRC_ADDR_REG);
+		writel_relaxed(d->dst, pchan->base + NDMA_DEST_ADDR_REG);
+		writel_relaxed(d->len, pchan->base + NDMA_BYTE_COUNT_REG);
+		writel_relaxed(d->cfg, pchan->base + NDMA_CFG_REG);
+	}
+}
+
+static void set_pchan_interrupt(struct sun4i_dma_dev *priv,
+				struct sun4i_dma_pchan *pchan,
+				int half, int end)
+{
+	u32 reg = readl_relaxed(priv->base + DMA_IRQ_ENABLE_REG);
+	int pchan_number = pchan - priv->pchans;
+
+	if (half)
+		reg |= BIT(pchan_number * 2);
+	else
+		reg &= ~BIT(pchan_number * 2);
+
+	if (end)
+		reg |= BIT(pchan_number * 2 + 1);
+	else
+		reg &= ~BIT(pchan_number * 2 + 1);
+
+	writel_relaxed(reg, priv->base + DMA_IRQ_ENABLE_REG);
+}
+
+static int execute_vchan_pending(struct sun4i_dma_dev *priv,
+				 struct sun4i_dma_vchan *vchan)
+{
+	struct sun4i_dma_promise *promise = NULL;
+	struct sun4i_dma_contract *contract = NULL;
+	struct sun4i_dma_pchan *pchan;
+	struct virt_dma_desc *vd;
+	int ret;
+
+	lockdep_assert_held(&vchan->vc.lock);
+
+	/* We need a pchan to do anything, so secure one if available */
+	pchan = find_and_use_pchan(priv, vchan);
+	if (!pchan)
+		return -EBUSY;
+
+	/*
+	 * Channel endpoints must not be repeated, so if this vchan
+	 * has already submitted some work, we can't do anything else
+	 */
+	if (vchan->processing) {
+		dev_dbg(chan2dev(&vchan->vc.chan),
+			"processing something to this endpoint already\n");
+		ret = -EBUSY;
+		goto release_pchan;
+	}
+
+	do {
+		/* Figure out which contract we're working with today */
+		vd = vchan_next_desc(&vchan->vc);
+		if (!vd) {
+			dev_dbg(chan2dev(&vchan->vc.chan),
+				"No pending contract found");
+			ret = 0;
+			goto release_pchan;
+		}
+
+		contract = to_sun4i_dma_contract(vd);
+		if (list_empty(&contract->demands)) {
+			/* The contract has been completed so mark it as such */
+			list_del(&contract->vd.node);
+			vchan_cookie_complete(&contract->vd);
+			dev_dbg(chan2dev(&vchan->vc.chan),
+				"Empty contract found and marked complete");
+		}
+	} while (list_empty(&contract->demands));
+
+	/* Now find out what we need to do */
+	promise = list_first_entry(&contract->demands,
+				   struct sun4i_dma_promise, list);
+	vchan->processing = promise;
+
+	/* ... and make it reality */
+	if (promise) {
+		vchan->contract = contract;
+		set_pchan_interrupt(priv, pchan, 0, 1);
+		configure_pchan(pchan, promise);
+	}
+
+	return 0;
+
+release_pchan:
+	release_pchan(priv, pchan);
+	return ret;
+}
+
+/**
+ * Generate a promise, to be used in a normal DMA contract.
+ *
+ * A NDMA promise contains all the information required to program the
+ * normal part of the DMA Engine and get data copied. A non-executed
+ * promise will live in the demands list on a contract. Once it has been
+ * completed, it will be moved to the completed demands list for later freeing.
+ * All linked promises will be freed when the corresponding contract is freed
+ */
+static struct sun4i_dma_promise *
+generate_ndma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_t dest,
+		      size_t len, struct dma_slave_config *sconfig)
+{
+	struct sun4i_dma_promise *promise;
+	int ret;
+
+	promise = kzalloc(sizeof(*promise), GFP_NOWAIT);
+	if (!promise)
+		return NULL;
+
+	promise->src = src;
+	promise->dst = dest;
+	promise->len = len;
+	promise->cfg = NDMA_CFG_LOADING | NDMA_CFG_BYTE_COUNT_MODE_REMAIN;
+
+	/* Source burst */
+	ret = convert_burst(sconfig->src_maxburst);
+	if (IS_ERR_VALUE(ret))
+		goto fail;
+	promise->cfg |= NDMA_CFG_SRC_BURST_LENGTH(ret);
+
+	/* Destination burst */
+	ret = convert_burst(sconfig->dst_maxburst);
+	if (IS_ERR_VALUE(ret))
+		goto fail;
+	promise->cfg |= NDMA_CFG_DEST_BURST_LENGTH(ret);
+
+	/* Source bus width */
+	ret = convert_buswidth(sconfig->src_addr_width);
+	if (IS_ERR_VALUE(ret))
+		goto fail;
+	promise->cfg |= NDMA_CFG_SRC_DATA_WIDTH(ret);
+
+	/* Destination bus width */
+	ret = convert_buswidth(sconfig->dst_addr_width);
+	if (IS_ERR_VALUE(ret))
+		goto fail;
+	promise->cfg |= NDMA_CFG_DEST_DATA_WIDTH(ret);
+
+	return promise;
+
+fail:
+	kfree(promise);
+	return NULL;
+}
+
+/**
+ * Generate a promise, to be used in a dedicated DMA contract.
+ *
+ * A DDMA promise contains all the information required to program the
+ * Dedicated part of the DMA Engine and get data copied. A non-executed
+ * promise will live in the demands list on a contract. Once it has been
+ * completed, it will be moved to the completed demands list for later freeing.
+ * All linked promises will be freed when the corresponding contract is freed
+ */
+static struct sun4i_dma_promise *
+generate_ddma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_t dest,
+		      size_t len, struct dma_slave_config *sconfig)
+{
+	struct sun4i_dma_promise *promise;
+	int ret;
+
+	promise = kzalloc(sizeof(*promise), GFP_NOWAIT);
+	if (!promise)
+		return NULL;
+
+	promise->src = src;
+	promise->dst = dest;
+	promise->len = len;
+	promise->cfg = DDMA_CFG_LOADING | DDMA_CFG_BYTE_COUNT_MODE_REMAIN;
+
+	/* Source burst */
+	ret = convert_burst(sconfig->src_maxburst);
+	if (IS_ERR_VALUE(ret))
+		goto fail;
+	promise->cfg |= DDMA_CFG_SRC_BURST_LENGTH(ret);
+
+	/* Destination burst */
+	ret = convert_burst(sconfig->dst_maxburst);
+	if (IS_ERR_VALUE(ret))
+		goto fail;
+	promise->cfg |= DDMA_CFG_DEST_BURST_LENGTH(ret);
+
+	/* Source bus width */
+	ret = convert_buswidth(sconfig->src_addr_width);
+	if (IS_ERR_VALUE(ret))
+		goto fail;
+	promise->cfg |= DDMA_CFG_SRC_DATA_WIDTH(ret);
+
+	/* Destination bus width */
+	ret = convert_buswidth(sconfig->dst_addr_width);
+	if (IS_ERR_VALUE(ret))
+		goto fail;
+	promise->cfg |= DDMA_CFG_DEST_DATA_WIDTH(ret);
+
+	return promise;
+
+fail:
+	kfree(promise);
+	return NULL;
+}
+
+/**
+ * Generate a contract
+ *
+ * Contracts function as DMA descriptors. As our hardware does not support
+ * linked lists, we need to implement SG via software. We use a contract
+ * to hold all the pieces of the request and process them serially one
+ * after another. Each piece is represented as a promise.
+ */
+static struct sun4i_dma_contract *generate_dma_contract(void)
+{
+	struct sun4i_dma_contract *contract;
+
+	contract = kzalloc(sizeof(*contract), GFP_NOWAIT);
+	if (!contract)
+		return NULL;
+
+	INIT_LIST_HEAD(&contract->demands);
+	INIT_LIST_HEAD(&contract->completed_demands);
+
+	return contract;
+}
+
+/**
+ * Free a contract and all its associated promises
+ */
+static void sun4i_dma_free_contract(struct virt_dma_desc *vd)
+{
+	struct sun4i_dma_contract *contract = to_sun4i_dma_contract(vd);
+	struct sun4i_dma_promise *promise;
+
+	/* Free all the demands and completed demands */
+	list_for_each_entry(promise, &contract->demands, list) {
+		kfree(promise);
+	}
+
+	list_for_each_entry(promise, &contract->completed_demands, list) {
+		kfree(promise);
+	}
+
+	kfree(contract);
+}
+
+static struct dma_async_tx_descriptor *
+sun4i_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest,
+			  dma_addr_t src, size_t len, unsigned long flags)
+{
+	struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
+	struct dma_slave_config *sconfig = &vchan->cfg;
+	struct sun4i_dma_promise *promise;
+	struct sun4i_dma_contract *contract;
+
+	contract = generate_dma_contract();
+	if (!contract)
+		return NULL;
+
+	if (vchan->is_dedicated)
+		promise = generate_ddma_promise(chan, src, dest, len, sconfig);
+	else
+		promise = generate_ndma_promise(chan, src, dest, len, sconfig);
+
+	if (!promise) {
+		kfree(contract);
+		return NULL;
+	}
+
+	/* Configure memcpy mode */
+	if (vchan->is_dedicated) {
+		promise->cfg |= DDMA_CFG_SRC_DRQ_TYPE(DDMA_DRQ_TYPE_SDRAM) |
+				DDMA_CFG_DEST_DRQ_TYPE(DDMA_DRQ_TYPE_SDRAM);
+	} else {
+		promise->cfg |= NDMA_CFG_SRC_DRQ_TYPE(NDMA_DRQ_TYPE_SDRAM) |
+				NDMA_CFG_DEST_DRQ_TYPE(NDMA_DRQ_TYPE_SDRAM);
+	}
+
+	/* Fill the contract with our only promise */
+	list_add_tail(&promise->list, &contract->demands);
+
+	/* And add it to the vchan */
+	return vchan_tx_prep(&vchan->vc, &contract->vd, flags);
+}
+
+static struct dma_async_tx_descriptor *
+sun4i_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
+			unsigned int sg_len, enum dma_transfer_direction dir,
+			unsigned long flags, void *context)
+{
+	struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
+	struct dma_slave_config *sconfig = &vchan->cfg;
+	struct sun4i_dma_promise *promise;
+	struct sun4i_dma_contract *contract;
+	struct scatterlist *sg;
+	dma_addr_t srcaddr, dstaddr;
+	u32 endpoints, para;
+	int i;
+
+	if (!sgl)
+		return NULL;
+
+	if (!is_slave_direction(dir)) {
+		dev_err(chan2dev(chan), "Invalid DMA direction\n");
+		return NULL;
+	}
+
+	contract = generate_dma_contract();
+	if (!contract)
+		return NULL;
+
+	/* Figure out endpoints */
+	if (vchan->is_dedicated && dir == DMA_MEM_TO_DEV) {
+		endpoints = DDMA_CFG_SRC_DRQ_TYPE(DDMA_DRQ_TYPE_SDRAM) |
+			    DDMA_CFG_SRC_ADDR_MODE(DDMA_ADDR_MODE_LINEAR) |
+			    DDMA_CFG_DEST_DRQ_TYPE(vchan->endpoint) |
+			    DDMA_CFG_DEST_ADDR_MODE(DDMA_ADDR_MODE_IO);
+	} else if (!vchan->is_dedicated && dir == DMA_MEM_TO_DEV) {
+		endpoints = NDMA_CFG_SRC_DRQ_TYPE(NDMA_DRQ_TYPE_SDRAM) |
+			    NDMA_CFG_DEST_DRQ_TYPE(vchan->endpoint) |
+			    NDMA_CFG_DEST_FIXED_ADDR;
+	} else if (vchan->is_dedicated) {
+		endpoints = DDMA_CFG_SRC_DRQ_TYPE(vchan->endpoint) |
+			    DDMA_CFG_SRC_ADDR_MODE(DDMA_ADDR_MODE_IO) |
+			    DDMA_CFG_DEST_DRQ_TYPE(DDMA_DRQ_TYPE_SDRAM) |
+			    DDMA_CFG_DEST_ADDR_MODE(DDMA_ADDR_MODE_LINEAR);
+	} else {
+		endpoints = NDMA_CFG_SRC_DRQ_TYPE(vchan->endpoint) |
+			    NDMA_CFG_SRC_FIXED_ADDR |
+			    NDMA_CFG_DEST_DRQ_TYPE(NDMA_DRQ_TYPE_SDRAM);
+	}
+
+	for_each_sg(sgl, sg, sg_len, i) {
+		/* Figure out addresses */
+		if (dir == DMA_MEM_TO_DEV) {
+			srcaddr = sg_dma_address(sg);
+			dstaddr = sconfig->dst_addr;
+		} else {
+			srcaddr = sconfig->src_addr;
+			dstaddr = sg_dma_address(sg);
+		}
+
+		/* TODO: should this be configurable? */
+		para = DDMA_MAGIC_SPI_PARAMETERS;
+
+		/* And make a suitable promise */
+		if (vchan->is_dedicated)
+			promise = generate_ddma_promise(chan, srcaddr, dstaddr,
+							sg_dma_len(sg), sconfig);
+		else
+			promise = generate_ndma_promise(chan, srcaddr, dstaddr,
+							sg_dma_len(sg), sconfig);
+
+		if (!promise)
+			return NULL; /* TODO */
+
+		promise->cfg |= endpoints;
+		promise->para = para;
+
+		/* Then add it to the contract */
+		list_add_tail(&promise->list, &contract->demands);
+	}
+
+	/*
+	 * Once we've got all the promises ready, add the contract
+	 * to the pending list on the vchan
+	 */
+	return vchan_tx_prep(&vchan->vc, &contract->vd, flags);
+}
+
+static int sun4i_dma_terminate_all(struct sun4i_dma_vchan *vchan)
+{
+	struct sun4i_dma_pchan *pchan = vchan->pchan;
+	LIST_HEAD(head);
+	unsigned long flags, timeout;
+	u32 d_busy = DDMA_CFG_LOADING | DDMA_CFG_BUSY;
+	u32 n_busy = NDMA_CFG_LOADING;
+
+
+	spin_lock_irqsave(&vchan->vc.lock, flags);
+	vchan_get_all_descriptors(&vchan->vc, &head);
+	spin_unlock_irqrestore(&vchan->vc.lock, flags);
+
+	/* If this vchan is operating, wait until it's no longer busy */
+	if (pchan) {
+		timeout = jiffies + msecs_to_jiffies(2000);
+		if (pchan->is_dedicated) {
+			while (readl(pchan->base + DDMA_CFG_REG) & d_busy)
+				if (time_after(jiffies, timeout))
+					return -ETIMEDOUT;
+		} else {
+			while (readl(pchan->base + NDMA_CFG_REG) & n_busy)
+				if (time_after(jiffies, timeout))
+					return -ETIMEDOUT;
+		}
+	}
+
+	spin_lock_irqsave(&vchan->vc.lock, flags);
+	vchan_dma_desc_free_list(&vchan->vc, &head);
+	spin_unlock_irqrestore(&vchan->vc.lock, flags);
+
+	return 0;
+}
+
+static int sun4i_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+			     unsigned long arg)
+{
+	struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
+	int ret = 0;
+
+	switch (cmd) {
+	case DMA_RESUME:
+	case DMA_PAUSE:
+		ret = -EINVAL;
+		break;
+
+	case DMA_TERMINATE_ALL:
+		dev_dbg(chan2dev(chan), "Terminating everything on channel\n");
+		ret = sun4i_dma_terminate_all(vchan);
+		break;
+
+	case DMA_SLAVE_CONFIG:
+		memcpy(&vchan->cfg, (void *)arg, sizeof(vchan->cfg));
+		break;
+
+	default:
+		ret = -ENXIO;
+		break;
+	}
+
+	return ret;
+}
+
+static struct dma_chan *sun4i_dma_of_xlate(struct of_phandle_args *dma_spec,
+					   struct of_dma *ofdma)
+{
+	struct sun4i_dma_dev *priv = ofdma->of_dma_data;
+	struct sun4i_dma_vchan *vchan;
+	struct dma_chan *chan;
+	u8 is_dedicated = dma_spec->args[0];
+	u8 endpoint = dma_spec->args[1];
+
+	/* Check if type is Normal or Dedicated */
+	if (is_dedicated != 0 && is_dedicated != 1)
+		return NULL;
+
+	/* Make sure the endpoint looks sane */
+	if ((is_dedicated && endpoint >= DDMA_DRQ_TYPE_LIMIT) ||
+	    (!is_dedicated && endpoint >= NDMA_DRQ_TYPE_LIMIT))
+		return NULL;
+
+	chan = dma_get_any_slave_channel(&priv->slave);
+	if (!chan)
+		return NULL;
+
+	/* Assign the endpoint to the vchan */
+	vchan = to_sun4i_dma_vchan(chan);
+	vchan->is_dedicated = is_dedicated;
+	vchan->endpoint = endpoint;
+
+	return chan;
+}
+
+static enum dma_status sun4i_dma_tx_status(struct dma_chan *chan,
+					   dma_cookie_t cookie,
+					   struct dma_tx_state *state)
+{
+	struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
+	struct sun4i_dma_pchan *pchan = vchan->pchan;
+	struct sun4i_dma_contract *contract;
+	struct sun4i_dma_promise *promise;
+	struct virt_dma_desc *vd;
+	unsigned long flags;
+	enum dma_status ret;
+	size_t bytes = 0;
+
+	ret = dma_cookie_status(chan, cookie, state);
+	if (ret == DMA_COMPLETE)
+		return ret;
+
+	spin_lock_irqsave(&vchan->vc.lock, flags);
+	vd = vchan_find_desc(&vchan->vc, cookie);
+	if (!vd) /* TODO */
+		goto exit;
+	contract = to_sun4i_dma_contract(vd);
+
+	list_for_each_entry(promise, &contract->demands, list) {
+		bytes += promise->len;
+	}
+
+	/*
+	 * The hardware is configured to return the remaining byte
+	 * quantity. If possible, replace the first listed element's
+	 * full size with the actual remaining amount
+	 */
+	promise = list_first_entry_or_null(&contract->demands,
+					   struct sun4i_dma_promise, list);
+	if (promise && pchan) {
+		bytes -= promise->len;
+		if (pchan->is_dedicated)
+			bytes += readl(pchan->base + DDMA_BYTE_COUNT_REG);
+		else
+			bytes += readl(pchan->base + NDMA_BYTE_COUNT_REG);
+	}
+
+exit:
+
+	dma_set_residue(state, bytes);
+	spin_unlock_irqrestore(&vchan->vc.lock, flags);
+
+	return ret;
+}
+
+static void sun4i_dma_issue_pending(struct dma_chan *chan)
+{
+	struct sun4i_dma_dev *priv = to_sun4i_dma_dev(chan->device);
+	struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
+	unsigned long flags;
+
+	spin_lock_irqsave(&vchan->vc.lock, flags);
+
+	/*
+	 * If there are pending transactions for this vchan, push one of
+	 * them into the engine to get the ball rolling.
+	 */
+	if (vchan_issue_pending(&vchan->vc))
+		execute_vchan_pending(priv, vchan);
+
+	spin_unlock_irqrestore(&vchan->vc.lock, flags);
+}
+
+static irqreturn_t sun4i_dma_interrupt(int irq, void *dev_id)
+{
+	struct sun4i_dma_dev *priv = dev_id;
+	struct sun4i_dma_pchan *pchans = priv->pchans, *pchan;
+	struct sun4i_dma_vchan *vchan;
+	struct sun4i_dma_contract *contract;
+	unsigned long pendirq, irqs;
+	int bit;
+
+	pendirq = readl_relaxed(priv->base + DMA_IRQ_PENDING_STATUS_REG);
+	irqs = readl_relaxed(priv->base + DMA_IRQ_ENABLE_REG);
+
+	for_each_set_bit(bit, &pendirq, 32) {
+		pchan = &pchans[bit >> 1];
+		vchan = pchan->vchan;
+		contract = vchan->contract;
+
+		/*
+		 * Disable the IRQ and free the pchan if it's an end
+		 * interrupt (odd bit)
+		 */
+		if (bit & 1) {
+			spin_lock(&vchan->vc.lock);
+			/*
+			 * Move the promise into the completed list now that
+			 * we're done with it
+			 */
+			list_del(&vchan->processing->list);
+			list_add_tail(&vchan->processing->list, &contract->completed_demands);
+			vchan->processing = NULL;
+			vchan->pchan = NULL;
+			spin_unlock(&vchan->vc.lock);
+
+			irqs &= ~BIT(bit);
+			release_pchan(priv, pchan);
+		}
+	}
+
+	writel_relaxed(irqs, priv->base + DMA_IRQ_ENABLE_REG);
+
+	/* Writing 1 to the pending field will clear the pending interrupt */
+	writel_relaxed(pendirq, priv->base + DMA_IRQ_PENDING_STATUS_REG);
+
+	return IRQ_WAKE_THREAD;
+}
+
+static irqreturn_t sun4i_dma_submit_work(int irq, void *dev_id)
+{
+	struct sun4i_dma_dev *priv = dev_id;
+	struct sun4i_dma_vchan *vchan;
+	int i;
+
+	for (i = 0; i < DMA_NR_MAX_VCHANS; i++) {
+		vchan = &priv->vchans[i];
+		spin_lock_irq(&vchan->vc.lock);
+		execute_vchan_pending(priv, vchan);
+		spin_unlock_irq(&vchan->vc.lock);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int sun4i_dma_probe(struct platform_device *pdev)
+{
+	struct sun4i_dma_dev *priv;
+	struct resource *res;
+	int i, j, ret;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(priv->base))
+		return PTR_ERR(priv->base);
+
+	priv->irq = platform_get_irq(pdev, 0);
+	if (priv->irq < 0) {
+		dev_err(&pdev->dev, "Cannot claim IRQ\n");
+		return priv->irq;
+	}
+
+	priv->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(&pdev->dev, "No clock specified\n");
+		return PTR_ERR(priv->clk);
+	}
+
+	platform_set_drvdata(pdev, priv);
+	spin_lock_init(&priv->lock);
+
+	dma_cap_zero(priv->slave.cap_mask);
+	dma_cap_set(DMA_PRIVATE, priv->slave.cap_mask);
+	dma_cap_set(DMA_MEMCPY, priv->slave.cap_mask);
+	dma_cap_set(DMA_SLAVE, priv->slave.cap_mask);
+
+	INIT_LIST_HEAD(&priv->slave.channels);
+	priv->slave.device_alloc_chan_resources	= sun4i_dma_alloc_chan_resources;
+	priv->slave.device_free_chan_resources	= sun4i_dma_free_chan_resources;
+	priv->slave.device_tx_status		= sun4i_dma_tx_status;
+	priv->slave.device_issue_pending	= sun4i_dma_issue_pending;
+	priv->slave.device_prep_slave_sg	= sun4i_dma_prep_slave_sg;
+	priv->slave.device_prep_dma_memcpy	= sun4i_dma_prep_dma_memcpy;
+	priv->slave.device_control		= sun4i_dma_control;
+	priv->slave.chancnt			= DDMA_NR_MAX_VCHANS;
+
+	priv->slave.dev = &pdev->dev;
+
+	priv->pchans = devm_kcalloc(&pdev->dev, DMA_NR_MAX_CHANNELS,
+				    sizeof(struct sun4i_dma_pchan), GFP_KERNEL);
+	priv->vchans = devm_kcalloc(&pdev->dev, DMA_NR_MAX_VCHANS,
+				    sizeof(struct sun4i_dma_vchan), GFP_KERNEL);
+	if (!priv->vchans || !priv->pchans)
+		return -ENOMEM;
+
+	/*
+	 * [0..NDMA_NR_MAX_CHANNELS) are normal pchans, and
+	 * [NDMA_NR_MAX_CHANNELS..DMA_NR_MAX_CHANNELS) are dedicated ones
+	 */
+	for (i = 0; i < NDMA_NR_MAX_CHANNELS; i++)
+		priv->pchans[i].base = priv->base + NDMA_CHANNEL_REG_BASE(i);
+
+	for (j = 0; i < DMA_NR_MAX_CHANNELS; i++, j++) {
+		priv->pchans[i].base = priv->base + DDMA_CHANNEL_REG_BASE(j);
+		priv->pchans[i].is_dedicated = 1;
+	}
+
+	for (i = 0; i < DMA_NR_MAX_VCHANS; i++) {
+		struct sun4i_dma_vchan *vchan = &priv->vchans[i];
+
+		spin_lock_init(&vchan->vc.lock);
+		vchan->vc.desc_free = sun4i_dma_free_contract;
+		vchan_init(&vchan->vc, &priv->slave);
+	}
+
+	ret = clk_prepare_enable(priv->clk);
+	if (ret) {
+		dev_err(&pdev->dev, "Couldn't enable the clock\n");
+		return ret;
+	}
+
+	ret = devm_request_threaded_irq(&pdev->dev, priv->irq,
+					sun4i_dma_interrupt,
+					sun4i_dma_submit_work,
+					0, dev_name(&pdev->dev), priv);
+	if (ret) {
+		dev_err(&pdev->dev, "Cannot request IRQ\n");
+		goto err_clk_disable;
+	}
+
+	ret = dma_async_device_register(&priv->slave);
+	if (ret) {
+		dev_warn(&pdev->dev, "Failed to register DMA engine device\n");
+		goto err_clk_disable;
+	}
+
+	ret = of_dma_controller_register(pdev->dev.of_node, sun4i_dma_of_xlate,
+					 priv);
+	if (ret) {
+		dev_err(&pdev->dev, "of_dma_controller_register failed\n");
+		goto err_dma_unregister;
+	}
+
+	dev_dbg(&pdev->dev, "Successfully probed SUN4I_DMA\n");
+
+	return 0;
+
+err_dma_unregister:
+	dma_async_device_unregister(&priv->slave);
+err_clk_disable:
+	clk_disable_unprepare(priv->clk);
+	return ret;
+}
+
+static int sun4i_dma_remove(struct platform_device *pdev)
+{
+	struct sun4i_dma_dev *priv = platform_get_drvdata(pdev);
+
+	/* Disable IRQ so no more work is scheduled */
+	disable_irq(priv->irq);
+
+	of_dma_controller_free(pdev->dev.of_node);
+	dma_async_device_unregister(&priv->slave);
+
+	clk_disable_unprepare(priv->clk);
+
+	return 0;
+}
+
+static struct of_device_id sun4i_dma_match[] = {
+	{ .compatible = "allwinner,sun4i-a10-dma" },
+	{ /* sentinel */ },
+};
+
+static struct platform_driver sun4i_dma_driver = {
+	.probe	= sun4i_dma_probe,
+	.remove	= sun4i_dma_remove,
+	.driver	= {
+		.name		= "sun4i-dma",
+		.of_match_table	= sun4i_dma_match,
+	},
+};
+
+module_platform_driver(sun4i_dma_driver);
+
+MODULE_DESCRIPTION("Allwinner A10 Dedicated DMA Controller Driver");
+MODULE_AUTHOR("Emilio L?pez <emilio@elopez.com.ar>");
+MODULE_LICENSE("GPL");
-- 
2.0.1

[PATCH v2 2/8] spi: sun4i: add DMA support

[Emilio López]

This patch adds DMA support for 64 byte transfers on the sun4i SPI
controller. Bigger transfers did not seem to work when tested, and if
the hardware actually supports those, it will need further
investigation as to how to issue them correctly.

Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---

Changes from v1:
 * remove 64 byte limitation on transfers
 * wrap stuff so it fits better in 80 cols

 drivers/spi/spi-sun4i.c | 155 ++++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 144 insertions(+), 11 deletions(-)

diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c
index 85204c9..e674100 100644
--- a/drivers/spi/spi-sun4i.c
+++ b/drivers/spi/spi-sun4i.c
@@ -14,6 +14,8 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/device.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/module.h>
@@ -34,6 +36,7 @@
 #define SUN4I_CTL_CPHA				BIT(2)
 #define SUN4I_CTL_CPOL				BIT(3)
 #define SUN4I_CTL_CS_ACTIVE_LOW			BIT(4)
+#define SUN4I_CTL_DMAMC_DEDICATED		BIT(5)
 #define SUN4I_CTL_LMTF				BIT(6)
 #define SUN4I_CTL_TF_RST			BIT(8)
 #define SUN4I_CTL_RF_RST			BIT(9)
@@ -51,6 +54,8 @@
 #define SUN4I_INT_STA_REG		0x10
 
 #define SUN4I_DMA_CTL_REG		0x14
+#define SUN4I_DMA_CTL_RF_READY			BIT(0)
+#define SUN4I_DMA_CTL_TF_NOT_FULL		BIT(10)
 
 #define SUN4I_WAIT_REG			0x18
 
@@ -84,6 +89,9 @@ struct sun4i_spi {
 	const u8		*tx_buf;
 	u8			*rx_buf;
 	int			len;
+
+	struct dma_chan		*rx_dma_chan;
+	struct dma_chan		*tx_dma_chan;
 };
 
 static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg)
@@ -130,6 +138,24 @@ static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len)
 	}
 }
 
+static bool sun4i_spi_can_dma(struct spi_master *master,
+			      struct spi_device *spi,
+			      struct spi_transfer *tfr)
+{
+	return tfr->len >= SUN4I_FIFO_DEPTH;
+}
+
+static int sun4i_spi_prepare_message(struct spi_master *master,
+				     struct spi_message *msg)
+{
+	struct sun4i_spi *sspi = spi_master_get_devdata(master);
+
+	master->dma_rx = sspi->rx_dma_chan;
+	master->dma_tx = sspi->tx_dma_chan;
+
+	return 0;
+}
+
 static void sun4i_spi_set_cs(struct spi_device *spi, bool enable)
 {
 	struct sun4i_spi *sspi = spi_master_get_devdata(spi->master);
@@ -169,15 +195,12 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
 				  struct spi_transfer *tfr)
 {
 	struct sun4i_spi *sspi = spi_master_get_devdata(master);
+	struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
 	unsigned int mclk_rate, div, timeout;
 	unsigned int tx_len = 0;
 	int ret = 0;
 	u32 reg;
 
-	/* We don't support transfer larger than the FIFO */
-	if (tfr->len > SUN4I_FIFO_DEPTH)
-		return -EINVAL;
-
 	reinit_completion(&sspi->done);
 	sspi->tx_buf = tfr->tx_buf;
 	sspi->rx_buf = tfr->rx_buf;
@@ -186,7 +209,6 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
 	/* Clear pending interrupts */
 	sun4i_spi_write(sspi, SUN4I_INT_STA_REG, ~0);
 
-
 	reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
 
 	/* Reset FIFOs */
@@ -269,12 +291,63 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
 	sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));
 	sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));
 
-	/* Fill the TX FIFO */
-	sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
-
 	/* Enable the interrupts */
 	sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC);
 
+	if (sun4i_spi_can_dma(master, spi, tfr)) {
+		dev_dbg(&sspi->master->dev, "Using DMA mode for transfer\n");
+
+		if (sspi->tx_buf) {
+			desc_tx = dmaengine_prep_slave_sg(sspi->tx_dma_chan,
+					tfr->tx_sg.sgl, tfr->tx_sg.nents,
+					DMA_TO_DEVICE,
+					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+			if (!desc_tx) {
+				dev_err(&sspi->master->dev,
+					"Couldn't prepare dma slave\n");
+				return -EIO;
+			}
+
+			dmaengine_submit(desc_tx);
+		}
+
+		if (sspi->rx_buf) {
+			desc_rx = dmaengine_prep_slave_sg(sspi->rx_dma_chan,
+					tfr->rx_sg.sgl, tfr->rx_sg.nents,
+					DMA_FROM_DEVICE,
+					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+			if (!desc_rx) {
+				dev_err(&sspi->master->dev,
+					"Couldn't prepare dma slave\n");
+				return -EIO;
+			}
+
+			dmaengine_submit(desc_rx);
+		}
+
+		/* Enable DMA requests */
+		reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
+		sun4i_spi_write(sspi, SUN4I_CTL_REG,
+				reg | SUN4I_CTL_DMAMC_DEDICATED);
+		sun4i_spi_write(sspi, SUN4I_DMA_CTL_REG,
+				SUN4I_DMA_CTL_TF_NOT_FULL |
+				SUN4I_DMA_CTL_RF_READY);
+
+		dma_async_issue_pending(sspi->rx_dma_chan);
+		dma_async_issue_pending(sspi->tx_dma_chan);
+	} else {
+		dev_dbg(&sspi->master->dev, "Using PIO mode for transfer\n");
+
+		/* Disable DMA requests */
+		reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
+		sun4i_spi_write(sspi, SUN4I_CTL_REG,
+				reg & ~SUN4I_CTL_DMAMC_DEDICATED);
+		sun4i_spi_write(sspi, SUN4I_DMA_CTL_REG, 0);
+
+		/* Fill the TX FIFO */
+		sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
+	}
+
 	/* Start the transfer */
 	reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
 	sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
@@ -286,7 +359,12 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
 		goto out;
 	}
 
-	sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
+	if (sun4i_spi_can_dma(master, spi, tfr) && desc_rx) {
+		/* The receive transfer should be the last one to finish */
+		dma_wait_for_async_tx(desc_rx);
+	} else {
+		sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
+	}
 
 out:
 	sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);
@@ -351,6 +429,7 @@ static int sun4i_spi_runtime_suspend(struct device *dev)
 
 static int sun4i_spi_probe(struct platform_device *pdev)
 {
+	struct dma_slave_config dma_sconfig;
 	struct spi_master *master;
 	struct sun4i_spi *sspi;
 	struct resource	*res;
@@ -386,7 +465,10 @@ static int sun4i_spi_probe(struct platform_device *pdev)
 		goto err_free_master;
 	}
 
+	init_completion(&sspi->done);
 	sspi->master = master;
+	master->can_dma = sun4i_spi_can_dma;
+	master->prepare_message = sun4i_spi_prepare_message;
 	master->set_cs = sun4i_spi_set_cs;
 	master->transfer_one = sun4i_spi_transfer_one;
 	master->num_chipselect = 4;
@@ -409,7 +491,45 @@ static int sun4i_spi_probe(struct platform_device *pdev)
 		goto err_free_master;
 	}
 
-	init_completion(&sspi->done);
+	sspi->tx_dma_chan = dma_request_slave_channel_reason(&pdev->dev, "tx");
+	if (IS_ERR(sspi->tx_dma_chan)) {
+		dev_err(&pdev->dev, "Unable to acquire DMA channel TX\n");
+		ret = PTR_ERR(sspi->tx_dma_chan);
+		goto err_free_master;
+	}
+
+	dma_sconfig.direction = DMA_MEM_TO_DEV;
+	dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+	dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+	dma_sconfig.dst_addr = res->start + SUN4I_TXDATA_REG;
+	dma_sconfig.src_maxburst = 1;
+	dma_sconfig.dst_maxburst = 1;
+
+	ret = dmaengine_slave_config(sspi->tx_dma_chan, &dma_sconfig);
+	if (ret) {
+		dev_err(&pdev->dev, "Unable to configure TX DMA slave\n");
+		goto err_tx_dma_release;
+	}
+
+	sspi->rx_dma_chan = dma_request_slave_channel_reason(&pdev->dev, "rx");
+	if (IS_ERR(sspi->rx_dma_chan)) {
+		dev_err(&pdev->dev, "Unable to acquire DMA channel RX\n");
+		ret = PTR_ERR(sspi->rx_dma_chan);
+		goto err_tx_dma_release;
+	}
+
+	dma_sconfig.direction = DMA_DEV_TO_MEM;
+	dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+	dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+	dma_sconfig.src_addr = res->start + SUN4I_RXDATA_REG;
+	dma_sconfig.src_maxburst = 1;
+	dma_sconfig.dst_maxburst = 1;
+
+	ret = dmaengine_slave_config(sspi->rx_dma_chan, &dma_sconfig);
+	if (ret) {
+		dev_err(&pdev->dev, "Unable to configure RX DMA slave\n");
+		goto err_rx_dma_release;
+	}
 
 	/*
 	 * This wake-up/shutdown pattern is to be able to have the
@@ -418,7 +538,7 @@ static int sun4i_spi_probe(struct platform_device *pdev)
 	ret = sun4i_spi_runtime_resume(&pdev->dev);
 	if (ret) {
 		dev_err(&pdev->dev, "Couldn't resume the device\n");
-		goto err_free_master;
+		goto err_rx_dma_release;
 	}
 
 	pm_runtime_set_active(&pdev->dev);
@@ -436,6 +556,10 @@ static int sun4i_spi_probe(struct platform_device *pdev)
 err_pm_disable:
 	pm_runtime_disable(&pdev->dev);
 	sun4i_spi_runtime_suspend(&pdev->dev);
+err_rx_dma_release:
+	dma_release_channel(sspi->rx_dma_chan);
+err_tx_dma_release:
+	dma_release_channel(sspi->tx_dma_chan);
 err_free_master:
 	spi_master_put(master);
 	return ret;
@@ -443,8 +567,17 @@ err_free_master:
 
 static int sun4i_spi_remove(struct platform_device *pdev)
 {
+	struct spi_master *master = platform_get_drvdata(pdev);
+	struct sun4i_spi *sspi = spi_master_get_devdata(master);
+
+	if (pm_runtime_active(&pdev->dev))
+		sun4i_spi_runtime_suspend(&pdev->dev);
+
 	pm_runtime_disable(&pdev->dev);
 
+	dma_release_channel(sspi->rx_dma_chan);
+	dma_release_channel(sspi->tx_dma_chan);
+
 	return 0;
 }
 
-- 
2.0.1

[PATCH v2 3/8] ARM: sun4i: Add node to represent the DMA controller

[Emilio López]

Let's add a node to represent the A10 DMA controller on the device tree.

Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index d96e179..f17cbeb 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -339,6 +339,14 @@
 		#size-cells = <1>;
 		ranges;
 
+	        dma: dma-controller at 01c02000 {
+	                compatible = "allwinner,sun4i-a10-dma";
+	                reg = <0x01c02000 0x1000>;
+	                interrupts = <27>;
+	                clocks = <&ahb_gates 6>;
+			#dma-cells = <2>;
+	        };
+
 		spi0: spi at 01c05000 {
 			compatible = "allwinner,sun4i-a10-spi";
 			reg = <0x01c05000 0x1000>;
-- 
2.0.1

[PATCH v2 4/8] ARM: sun5i: Add nodes to represent the DMA controllers

[Emilio López]

The A10S and A13 SoCs have sun4i-compatible DMA controllers. Let's add
the corresponding nodes to represent them on the device tree.

Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---

Note that I have only tested on A10S, if anyone with an A13 device could
test as well, that would be great!

 arch/arm/boot/dts/sun5i-a10s.dtsi | 8 ++++++++
 arch/arm/boot/dts/sun5i-a13.dtsi  | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index b64f705..3708817 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -300,6 +300,14 @@
 		#size-cells = <1>;
 		ranges;
 
+	        dma: dma-controller at 01c02000 {
+	                compatible = "allwinner,sun4i-a10-dma";
+	                reg = <0x01c02000 0x1000>;
+	                interrupts = <27>;
+	                clocks = <&ahb_gates 6>;
+			#dma-cells = <2>;
+	        };
+
 		spi0: spi at 01c05000 {
 			compatible = "allwinner,sun4i-a10-spi";
 			reg = <0x01c05000 0x1000>;
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 3b2a94c..1f1adf2 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -298,6 +298,14 @@
 		#size-cells = <1>;
 		ranges;
 
+	        dma: dma-controller at 01c02000 {
+	                compatible = "allwinner,sun4i-a10-dma";
+	                reg = <0x01c02000 0x1000>;
+	                interrupts = <27>;
+	                clocks = <&ahb_gates 6>;
+			#dma-cells = <2>;
+	        };
+
 		spi0: spi at 01c05000 {
 			compatible = "allwinner,sun4i-a10-spi";
 			reg = <0x01c05000 0x1000>;
-- 
2.0.1

[PATCH v2 5/8] ARM: sun7i: Add node to represent the DMA controller

[Emilio López]

The A20 SoC has a sun4i-compatible DMA controller. Let's add a node to
represent it on the device tree.

Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 01e9466..8cd3534 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -423,6 +423,14 @@
 			interrupts = <0 0 4>;
 		};
 
+	        dma: dma-controller at 01c02000 {
+	                compatible = "allwinner,sun4i-a10-dma";
+	                reg = <0x01c02000 0x1000>;
+	                interrupts = <0 27 4>;
+	                clocks = <&ahb_gates 6>;
+			#dma-cells = <2>;
+	        };
+
 		spi0: spi at 01c05000 {
 			compatible = "allwinner,sun4i-a10-spi";
 			reg = <0x01c05000 0x1000>;
-- 
2.0.1

[PATCH v2 6/8] ARM: sun4i: enable DMA on SPI

[Emilio López]

All of our SPI controllers support DMA transfers, so let's add the
properties here so they can be used when it's best to do so.

Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index f17cbeb..56d02af 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -353,6 +353,8 @@
 			interrupts = <10>;
 			clocks = <&ahb_gates 20>, <&spi0_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 27>, <&dma 1 26>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -364,6 +366,8 @@
 			interrupts = <11>;
 			clocks = <&ahb_gates 21>, <&spi1_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 9>, <&dma 1 8>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -459,6 +463,8 @@
 			interrupts = <12>;
 			clocks = <&ahb_gates 22>, <&spi2_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 29>, <&dma 1 28>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -498,6 +504,8 @@
 			interrupts = <50>;
 			clocks = <&ahb_gates 23>, <&spi3_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 31>, <&dma 1 30>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
-- 
2.0.1

[PATCH v2 7/8] ARM: sun5i: enable DMA on SPI

[Emilio López]

All of our SPI controllers support DMA transfers, so let's add the
properties here so they can be used when it's best to do so.

Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
 arch/arm/boot/dts/sun5i-a10s.dtsi | 6 ++++++
 arch/arm/boot/dts/sun5i-a13.dtsi  | 6 ++++++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 3708817..12f26f3 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -314,6 +314,8 @@
 			interrupts = <10>;
 			clocks = <&ahb_gates 20>, <&spi0_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 27>, <&dma 1 26>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -325,6 +327,8 @@
 			interrupts = <11>;
 			clocks = <&ahb_gates 21>, <&spi1_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 9>, <&dma 1 8>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -411,6 +415,8 @@
 			interrupts = <12>;
 			clocks = <&ahb_gates 22>, <&spi2_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 29>, <&dma 1 28>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 1f1adf2..4bbf455 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -312,6 +312,8 @@
 			interrupts = <10>;
 			clocks = <&ahb_gates 20>, <&spi0_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 27>, <&dma 1 26>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -323,6 +325,8 @@
 			interrupts = <11>;
 			clocks = <&ahb_gates 21>, <&spi1_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 9>, <&dma 1 8>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -384,6 +388,8 @@
 			interrupts = <12>;
 			clocks = <&ahb_gates 22>, <&spi2_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 29>, <&dma 1 28>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
-- 
2.0.1

[PATCH v2 8/8] ARM: sun7i: enable DMA on SPI

[Emilio López]

All of our SPI controllers support DMA transfers, so let's add the
properties here so they can be used when it's best to do so.

Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 8cd3534..804dc01 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -437,6 +437,8 @@
 			interrupts = <0 10 4>;
 			clocks = <&ahb_gates 20>, <&spi0_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 27>, <&dma 1 26>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -448,6 +450,8 @@
 			interrupts = <0 11 4>;
 			clocks = <&ahb_gates 21>, <&spi1_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 9>, <&dma 1 8>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -543,6 +547,8 @@
 			interrupts = <0 12 4>;
 			clocks = <&ahb_gates 22>, <&spi2_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 29>, <&dma 1 28>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -582,6 +588,8 @@
 			interrupts = <0 50 4>;
 			clocks = <&ahb_gates 23>, <&spi3_clk>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 1 31>, <&dma 1 30>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
-- 
2.0.1

[PATCH v2 9/8] ARM: sun4i: cubieboard: add an SPIdev device for testing

[Emilio López]

---
 arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 12 ++++++++++++
 arch/arm/boot/dts/sun4i-a10.dtsi           |  7 +++++++
 2 files changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index c200eac..c7a4c4e 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -71,6 +71,18 @@
 			status = "okay";
 		};
 
+		spi0: spi at 01c05000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi0_pins_a>;
+			status = "okay";
+
+			dac0: dh2228 at 2 {
+				compatible = "rohm,dh2228fv";
+				reg = <2>;
+				spi-max-frequency = <100000>;
+			};
+		};
+
 		pinctrl at 01c20800 {
 			led_pins_cubieboard: led_pins at 0 {
 				allwinner,pins = "PH20", "PH21";
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 56d02af..63c0ff6 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -585,6 +585,13 @@
 				allwinner,pull = <0>;
 			};
 
+			spi0_pins_a: spi0 at 0 {
+				allwinner,pins = "PI10", "PI11", "PI12", "PI13";
+				allwinner,function = "spi0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
 			emac_pins_a: emac0 at 0 {
 				allwinner,pins = "PA0", "PA1", "PA2",
 						"PA3", "PA4", "PA5", "PA6",
-- 
2.0.1

[PATCH v2 10/8] ARM: sun7i: cubietruck: add an SPIdev device for testing

[Emilio López]

---
 arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index b87fea9..4ef421f 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -66,6 +66,18 @@
 			status = "okay";
 		};
 
+		spi2: spi at 01c17000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi2_pins_a>;
+			status = "okay";
+
+			dac0: dh2228 at 2 {
+				compatible = "rohm,dh2228fv";
+				reg = <2>;
+				spi-max-frequency = <100000>;
+			};
+		};
+
 		pinctrl at 01c20800 {
 			mmc3_pins_a: mmc3 at 0 {
 				/* AP6210 requires pull-up */
-- 
2.0.1

[PATCH v2 11/8] ARM: sun5i: a10s-olinuxino-micro: add an SPIdev device for testing

[Emilio López]

---
 arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 12 ++++++++++++
 arch/arm/boot/dts/sun5i-a10s.dtsi                |  7 +++++++
 2 files changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index ea9519d..3f19e57 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -68,6 +68,18 @@
 			status = "okay";
 		};
 
+		spi2: spi at 01c17000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi2_pins_a>;
+			status = "okay";
+
+			dac0: dh2228 at 2 {
+				compatible = "rohm,dh2228fv";
+				reg = <2>;
+				spi-max-frequency = <100000>;
+			};
+		};
+
 		pinctrl at 01c20800 {
 			mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin at 0 {
 				allwinner,pins = "PG1";
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 12f26f3..814cddb 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -506,6 +506,13 @@
 				allwinner,drive = <2>;
 				allwinner,pull = <0>;
 			};
+
+			spi2_pins_a: spi2 at 0 {
+				allwinner,pins = "PB11", "PB12", "PB13", "PB14";
+				allwinner,function = "spi2";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
 		};
 
 		timer at 01c20c00 {
-- 
2.0.1

[PATCH v2 10/8] ARM: sun7i: cubietruck: add an SPIdev device for testing

[Sergei Shtylyov]

Hello.

On 07/06/2014 08:05 AM, Emilio L?pez wrote:

    You need to sign off on your patches, else they couldn't be applied.

> ---
>   arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 12 ++++++++++++
>   1 file changed, 12 insertions(+)

> diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
> index b87fea9..4ef421f 100644
> --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
> @@ -66,6 +66,18 @@
>   			status = "okay";
>   		};
>
> +		spi2: spi at 01c17000 {
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&spi2_pins_a>;
> +			status = "okay";
> +
> +			dac0: dh2228 at 2 {

    The ePAPR standard [1] says:

The name of a node should be somewhat generic, reflecting the function of the 
device and not its precise programming model.

> +				compatible = "rohm,dh2228fv";
> +				reg = <2>;
> +				spi-max-frequency = <100000>;
> +			};
> +		};
> +

[1] http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf

WBR, Sergei

[PATCH v2 10/8] ARM: sun7i: cubietruck: add an SPIdev device for testing

[Emilio López]

Hi,

El 06/07/14 12:21, Sergei Shtylyov escribi?:
> Hello.
>
> On 07/06/2014 08:05 AM, Emilio L?pez wrote:
>
>     You need to sign off on your patches, else they couldn't be applied.

That's kind of the point here. These patches are just intended for 
testing. From the cover letter:

"""Patches nine, ten and eleven are *only intended
for testing*, and add a dummy SPIdev device to cubieboard, cubietruck
and A10S-OLinuXino to facilitate testing with spidev_test."""

Cheers,

Emilio

[PATCH v2 2/8] spi: sun4i: add DMA support

[Emilio López]

El 06/07/14 01:05, Emilio L?pez escribi?:
> This patch adds DMA support for 64 byte transfers on the sun4i SPI
> controller. Bigger transfers did not seem to work when tested, and if
> the hardware actually supports those, it will need further
> investigation as to how to issue them correctly.

It seems I forgot to update this commit message; it should be something 
like:

This patch adds support for 64 byte or bigger transfers on the
sun4i SPI controller. Said transfers will be performed via DMA.

Many thanks to patapovich on #linux-sunxi for making me notice this.

Cheers,

Emilio

[PATCH v2 8/8] ARM: sun7i: enable DMA on SPI

[Chen-Yu Tsai]

Hi,

On Sun, Jul 6, 2014 at 12:05 PM, Emilio L?pez <emilio@elopez.com.ar> wrote:
> All of our SPI controllers support DMA transfers, so let's add the
> properties here so they can be used when it's best to do so.
>
> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>

Numbers are good.

Reviewed-by: Chen-Yu Tsai <wens@csie.org>


> ---
>  arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
> index 8cd3534..804dc01 100644
> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
> @@ -437,6 +437,8 @@
>                         interrupts = <0 10 4>;
>                         clocks = <&ahb_gates 20>, <&spi0_clk>;
>                         clock-names = "ahb", "mod";
> +                       dmas = <&dma 1 27>, <&dma 1 26>;
> +                       dma-names = "rx", "tx";
>                         status = "disabled";
>                         #address-cells = <1>;
>                         #size-cells = <0>;
> @@ -448,6 +450,8 @@
>                         interrupts = <0 11 4>;
>                         clocks = <&ahb_gates 21>, <&spi1_clk>;
>                         clock-names = "ahb", "mod";
> +                       dmas = <&dma 1 9>, <&dma 1 8>;
> +                       dma-names = "rx", "tx";
>                         status = "disabled";
>                         #address-cells = <1>;
>                         #size-cells = <0>;
> @@ -543,6 +547,8 @@
>                         interrupts = <0 12 4>;
>                         clocks = <&ahb_gates 22>, <&spi2_clk>;
>                         clock-names = "ahb", "mod";
> +                       dmas = <&dma 1 29>, <&dma 1 28>;
> +                       dma-names = "rx", "tx";
>                         status = "disabled";
>                         #address-cells = <1>;
>                         #size-cells = <0>;
> @@ -582,6 +588,8 @@
>                         interrupts = <0 50 4>;
>                         clocks = <&ahb_gates 23>, <&spi3_clk>;
>                         clock-names = "ahb", "mod";
> +                       dmas = <&dma 1 31>, <&dma 1 30>;
> +                       dma-names = "rx", "tx";
>                         status = "disabled";
>                         #address-cells = <1>;
>                         #size-cells = <0>;
> --
> 2.0.1

[PATCH v2 7/8] ARM: sun5i: enable DMA on SPI

[Chen-Yu Tsai]

On Sun, Jul 6, 2014 at 12:05 PM, Emilio L?pez <emilio@elopez.com.ar> wrote:
> All of our SPI controllers support DMA transfers, so let's add the
> properties here so they can be used when it's best to do so.
>
> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>

Numbers are good.

Reviewed-by: Chen-Yu Tsai <wens@csie.org>

> ---
>  arch/arm/boot/dts/sun5i-a10s.dtsi | 6 ++++++
>  arch/arm/boot/dts/sun5i-a13.dtsi  | 6 ++++++
>  2 files changed, 12 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
> index 3708817..12f26f3 100644
> --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
> +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
> @@ -314,6 +314,8 @@
>                         interrupts = <10>;
>                         clocks = <&ahb_gates 20>, <&spi0_clk>;
>                         clock-names = "ahb", "mod";
> +                       dmas = <&dma 1 27>, <&dma 1 26>;
> +                       dma-names = "rx", "tx";
>                         status = "disabled";
>                         #address-cells = <1>;
>                         #size-cells = <0>;
> @@ -325,6 +327,8 @@
>                         interrupts = <11>;
>                         clocks = <&ahb_gates 21>, <&spi1_clk>;
>                         clock-names = "ahb", "mod";
> +                       dmas = <&dma 1 9>, <&dma 1 8>;
> +                       dma-names = "rx", "tx";
>                         status = "disabled";
>                         #address-cells = <1>;
>                         #size-cells = <0>;
> @@ -411,6 +415,8 @@
>                         interrupts = <12>;
>                         clocks = <&ahb_gates 22>, <&spi2_clk>;
>                         clock-names = "ahb", "mod";
> +                       dmas = <&dma 1 29>, <&dma 1 28>;
> +                       dma-names = "rx", "tx";
>                         status = "disabled";
>                         #address-cells = <1>;
>                         #size-cells = <0>;
> diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
> index 1f1adf2..4bbf455 100644
> --- a/arch/arm/boot/dts/sun5i-a13.dtsi
> +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
> @@ -312,6 +312,8 @@
>                         interrupts = <10>;
>                         clocks = <&ahb_gates 20>, <&spi0_clk>;
>                         clock-names = "ahb", "mod";
> +                       dmas = <&dma 1 27>, <&dma 1 26>;
> +                       dma-names = "rx", "tx";
>                         status = "disabled";
>                         #address-cells = <1>;
>                         #size-cells = <0>;
> @@ -323,6 +325,8 @@
>                         interrupts = <11>;
>                         clocks = <&ahb_gates 21>, <&spi1_clk>;
>                         clock-names = "ahb", "mod";
> +                       dmas = <&dma 1 9>, <&dma 1 8>;
> +                       dma-names = "rx", "tx";
>                         status = "disabled";
>                         #address-cells = <1>;
>                         #size-cells = <0>;
> @@ -384,6 +388,8 @@
>                         interrupts = <12>;
>                         clocks = <&ahb_gates 22>, <&spi2_clk>;
>                         clock-names = "ahb", "mod";
> +                       dmas = <&dma 1 29>, <&dma 1 28>;
> +                       dma-names = "rx", "tx";
>                         status = "disabled";
>                         #address-cells = <1>;
>                         #size-cells = <0>;
> --
> 2.0.1

[PATCH v2 6/8] ARM: sun4i: enable DMA on SPI

[Chen-Yu Tsai]

On Sun, Jul 6, 2014 at 12:05 PM, Emilio L?pez <emilio@elopez.com.ar> wrote:
> All of our SPI controllers support DMA transfers, so let's add the
> properties here so they can be used when it's best to do so.
>
> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>

Numbers are good.

Reviewed-by: Chen-Yu Tsai <wens@csie.org>


> ---
>  arch/arm/boot/dts/sun4i-a10.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
> index f17cbeb..56d02af 100644
> --- a/arch/arm/boot/dts/sun4i-a10.dtsi
> +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
> @@ -353,6 +353,8 @@
>                         interrupts = <10>;
>                         clocks = <&ahb_gates 20>, <&spi0_clk>;
>                         clock-names = "ahb", "mod";
> +                       dmas = <&dma 1 27>, <&dma 1 26>;
> +                       dma-names = "rx", "tx";
>                         status = "disabled";
>                         #address-cells = <1>;
>                         #size-cells = <0>;
> @@ -364,6 +366,8 @@
>                         interrupts = <11>;
>                         clocks = <&ahb_gates 21>, <&spi1_clk>;
>                         clock-names = "ahb", "mod";
> +                       dmas = <&dma 1 9>, <&dma 1 8>;
> +                       dma-names = "rx", "tx";
>                         status = "disabled";
>                         #address-cells = <1>;
>                         #size-cells = <0>;
> @@ -459,6 +463,8 @@
>                         interrupts = <12>;
>                         clocks = <&ahb_gates 22>, <&spi2_clk>;
>                         clock-names = "ahb", "mod";
> +                       dmas = <&dma 1 29>, <&dma 1 28>;
> +                       dma-names = "rx", "tx";
>                         status = "disabled";
>                         #address-cells = <1>;
>                         #size-cells = <0>;
> @@ -498,6 +504,8 @@
>                         interrupts = <50>;
>                         clocks = <&ahb_gates 23>, <&spi3_clk>;
>                         clock-names = "ahb", "mod";
> +                       dmas = <&dma 1 31>, <&dma 1 30>;
> +                       dma-names = "rx", "tx";
>                         status = "disabled";
>                         #address-cells = <1>;
>                         #size-cells = <0>;
> --
> 2.0.1

[PATCH v2 5/8] ARM: sun7i: Add node to represent the DMA controller

[Chen-Yu Tsai]

On Sun, Jul 6, 2014 at 12:05 PM, Emilio L?pez <emilio@elopez.com.ar> wrote:
> The A20 SoC has a sun4i-compatible DMA controller. Let's add a node to
> represent it on the device tree.
>
> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
> ---
>  arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
> index 01e9466..8cd3534 100644
> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
> @@ -423,6 +423,14 @@
>                         interrupts = <0 0 4>;
>                 };
>
> +               dma: dma-controller at 01c02000 {
> +                       compatible = "allwinner,sun4i-a10-dma";
> +                       reg = <0x01c02000 0x1000>;
> +                       interrupts = <0 27 4>;
> +                       clocks = <&ahb_gates 6>;
> +                       #dma-cells = <2>;
> +               };

Whitespace errors, otherwise good.

Reviewed-by: Chen-Yu Tsai <wens@csie.org>


> +
>                 spi0: spi at 01c05000 {
>                         compatible = "allwinner,sun4i-a10-spi";
>                         reg = <0x01c05000 0x1000>;
> --
> 2.0.1

[PATCH v2 4/8] ARM: sun5i: Add nodes to represent the DMA controllers

[Chen-Yu Tsai]

On Sun, Jul 6, 2014 at 12:05 PM, Emilio L?pez <emilio@elopez.com.ar> wrote:
> The A10S and A13 SoCs have sun4i-compatible DMA controllers. Let's add
> the corresponding nodes to represent them on the device tree.
>
> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
> ---
>
> Note that I have only tested on A10S, if anyone with an A13 device could
> test as well, that would be great!
>
>  arch/arm/boot/dts/sun5i-a10s.dtsi | 8 ++++++++
>  arch/arm/boot/dts/sun5i-a13.dtsi  | 8 ++++++++
>  2 files changed, 16 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
> index b64f705..3708817 100644
> --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
> +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
> @@ -300,6 +300,14 @@
>                 #size-cells = <1>;
>                 ranges;
>
> +               dma: dma-controller at 01c02000 {
> +                       compatible = "allwinner,sun4i-a10-dma";
> +                       reg = <0x01c02000 0x1000>;
> +                       interrupts = <27>;
> +                       clocks = <&ahb_gates 6>;
> +                       #dma-cells = <2>;
> +               };
> +
>                 spi0: spi at 01c05000 {
>                         compatible = "allwinner,sun4i-a10-spi";
>                         reg = <0x01c05000 0x1000>;
> diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
> index 3b2a94c..1f1adf2 100644
> --- a/arch/arm/boot/dts/sun5i-a13.dtsi
> +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
> @@ -298,6 +298,14 @@
>                 #size-cells = <1>;
>                 ranges;
>
> +               dma: dma-controller at 01c02000 {
> +                       compatible = "allwinner,sun4i-a10-dma";
> +                       reg = <0x01c02000 0x1000>;
> +                       interrupts = <27>;
> +                       clocks = <&ahb_gates 6>;
> +                       #dma-cells = <2>;
> +               };

Whitespace errors, otherwise good.

Reviewed-by: Chen-Yu Tsai <wens@csie.org>


> +
>                 spi0: spi at 01c05000 {
>                         compatible = "allwinner,sun4i-a10-spi";
>                         reg = <0x01c05000 0x1000>;
> --
> 2.0.1

[PATCH v2 3/8] ARM: sun4i: Add node to represent the DMA controller

[Chen-Yu Tsai]

On Sun, Jul 6, 2014 at 12:05 PM, Emilio L?pez <emilio@elopez.com.ar> wrote:
> Let's add a node to represent the A10 DMA controller on the device tree.
>
> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
> ---
>  arch/arm/boot/dts/sun4i-a10.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
> index d96e179..f17cbeb 100644
> --- a/arch/arm/boot/dts/sun4i-a10.dtsi
> +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
> @@ -339,6 +339,14 @@
>                 #size-cells = <1>;
>                 ranges;
>
> +               dma: dma-controller at 01c02000 {
> +                       compatible = "allwinner,sun4i-a10-dma";
> +                       reg = <0x01c02000 0x1000>;
> +                       interrupts = <27>;
> +                       clocks = <&ahb_gates 6>;
> +                       #dma-cells = <2>;

Whitespace errors, otherwise good.

Reviewed-by: Chen-Yu Tsai <wens@csie.org>


> +               };
> +
>                 spi0: spi at 01c05000 {
>                         compatible = "allwinner,sun4i-a10-spi";
>                         reg = <0x01c05000 0x1000>;
> --
> 2.0.1

[PATCH v2 1/8] dma: sun4i: Add support for the DMA engine on sun[457]i SoCs

[Chen-Yu Tsai]

Hi,

On Sun, Jul 6, 2014 at 12:05 PM, Emilio L?pez <emilio@elopez.com.ar> wrote:
> This patch adds support for the DMA engine present on Allwinner A10,
> A13, A10S and A20 SoCs. This engine has two kinds of channels: normal
> and dedicated. The main difference is in the mode of operation;
> while a single normal channel may be operating at any given time,
> dedicated channels may operate simultaneously provided there is no
> overlap of source or destination.
>
> Hardware documentation can be found on A10 User Manual (section 12), A13
> User Manual (section 14) and A20 User Manual (section 1.12)
>
> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
> ---
>
> Changes from v1:
>  * address comments from Chen-Yu and Maxime
>  * fix issue converting bus width
>  * switch to using a threaded IRQ instead of a tasklet on
>    recommendation from Maxime
>  * fix issue setting magic timing parameter for SPI transfers
>  * fix an issue with list handling reported by the kbuild 0-DAY robot (thanks!)
>  * drop a lot of unused #define
>  * probably some more stuff I'm forgetting
>
>  .../devicetree/bindings/dma/sun4i-dma.txt          |   45 +
>  drivers/dma/Kconfig                                |   10 +
>  drivers/dma/Makefile                               |    1 +
>  drivers/dma/sun4i-dma.c                            | 1025 ++++++++++++++++++++
>  4 files changed, 1081 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/dma/sun4i-dma.txt
>  create mode 100644 drivers/dma/sun4i-dma.c
>
> diff --git a/Documentation/devicetree/bindings/dma/sun4i-dma.txt b/Documentation/devicetree/bindings/dma/sun4i-dma.txt
> new file mode 100644
> index 0000000..f5661a5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/sun4i-dma.txt
> @@ -0,0 +1,45 @@
> +Allwinner A10 DMA Controller
> +
> +This driver follows the generic DMA bindings defined in dma.txt.
> +
> +Required properties:
> +
> +- compatible:  Must be "allwinner,sun4i-a10-dma"
> +- reg:         Should contain the registers base address and length
> +- interrupts:  Should contain a reference to the interrupt used by this device
> +- clocks:      Should contain a reference to the parent AHB clock
> +- #dma-cells : Should be 1, a single cell holding a line request number

Oops, we missed this one. Should be 2, first cell denoting normal or
dedicated dma, second cell holding the request line number.

> +
> +Example:
> +       dma: dma-controller at 01c02000 {
> +               compatible = "allwinner,sun4i-a10-dma";
> +               reg = <0x01c02000 0x1000>;
> +               interrupts = <27>;
> +               clocks = <&ahb_gates 6>;
> +               #dma-cells = <1>;

This should match the change above.

> +       };
> +
> +Clients:
> +
> +DMA clients connected to the Allwinner A10 DMA controller must use the
> +format described in the dma.txt file, using a three-cell specifier for
> +each channel: a phandle plus two integer cells.
> +The three cells in order are:
> +
> +1. A phandle pointing to the DMA controller.
> +2. Whether it is using normal (0) or dedicated (1) channels
> +2. The port ID as specified in the datasheet

3.?

> +
> +Example:
> +       spi2: spi at 01c17000 {
> +               compatible = "allwinner,sun4i-a10-spi";
> +               reg = <0x01c17000 0x1000>;
> +               interrupts = <0 12 4>;
> +               clocks = <&ahb_gates 22>, <&spi2_clk>;
> +               clock-names = "ahb", "mod";
> +               dmas = <&dma 1 29>, <&dma 1 28>;
> +               dma-names = "rx", "tx";
> +               status = "disabled";
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +       };

[...]

Thanks again!


Cheers
ChenYu

[PATCH v2 10/8] ARM: sun7i: cubietruck: add an SPIdev device for testing

[Maxime Ripard]

Hi Emilio,

On Sun, Jul 06, 2014 at 02:30:54PM -0300, Emilio L?pez wrote:
> Hi,
> 
> El 06/07/14 12:21, Sergei Shtylyov escribi?:
> >Hello.
> >
> >On 07/06/2014 08:05 AM, Emilio L?pez wrote:
> >
> >    You need to sign off on your patches, else they couldn't be applied.
> 
> That's kind of the point here. These patches are just intended for
> testing. From the cover letter:
> 
> """Patches nine, ten and eleven are *only intended
> for testing*, and add a dummy SPIdev device to cubieboard, cubietruck
> and A10S-OLinuXino to facilitate testing with spidev_test."""

Then stop posting them. It just confuses every one here.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v2 0/8] DMAEngine support for sun4i, sun5i & sun7i

[jonsmirl at gmail.com]

ALSA SOC needs support for cyclic DMA. Here's my attempt at
implementing it, but I have not succeeded in getting it working with
ALSA yet.

Code based on previous generation of this patch series....
Let me know if you are interested in the ALSA code supporting the on-chip codec.

+static struct dma_async_tx_descriptor *sun4i_dma_prep_dma_cyclic(
+ struct dma_chan *chan, dma_addr_t buf, size_t len,
+ size_t period_len, enum dma_transfer_direction dir,
+ unsigned long flags, void *context) {
+ struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
+ struct dma_slave_config *sconfig = &vchan->cfg;
+ struct sun4i_ddma_promise *promise;
+ struct sun4i_ddma_contract *contract;
+ dma_addr_t src, dest;
+
+ if (!is_slave_direction(dir)) {
+ dev_err(chan2dev(chan), "Invalid DMA direction\n");
+ return NULL;
+ }
+
+ contract = generate_ddma_contract();
+ if (!contract)
+ return NULL;
+
+ /* Figure out addresses */
+ if (dir == DMA_MEM_TO_DEV) {
+ src = buf;
+ dest = sconfig->dst_addr;
+ } else {
+ src = sconfig->src_addr;
+ dest = buf;
+ }
+
+ if (vchan->is_dedicated)
+ promise = generate_ddma_promise(chan, src, dest, len, sconfig);
+ else
+ promise = generate_ndma_promise(chan, src, dest, len, sconfig);
+
+ if (!promise) {
+ kfree(contract);
+ return NULL;
+ }
+
+ /* Figure out endpoints */
+ if (vchan->is_dedicated && dir == DMA_MEM_TO_DEV) {
+ promise->cfg |= DDMA_CFG_CONT_MODE |
DDMA_CFG_SRC_DRQ_TYPE(DDMA_DRQ_TYPE_SDRAM) |
+    DDMA_CFG_SRC_ADDR_MODE(DDMA_ADDR_MODE_LINEAR) |
+    DDMA_CFG_DEST_DRQ_TYPE(vchan->endpoint) |
+    DDMA_CFG_DEST_ADDR_MODE(DDMA_ADDR_MODE_IO);
+ } else if (!vchan->is_dedicated && dir == DMA_MEM_TO_DEV) {
+ promise->cfg |= NDMA_CFG_CONT_MODE |
NDMA_CFG_SRC_DRQ_TYPE(NDMA_DRQ_TYPE_SDRAM) |
+    NDMA_CFG_DEST_DRQ_TYPE(vchan->endpoint) |
+    NDMA_CFG_DEST_FIXED_ADDR;
+ } else if (vchan->is_dedicated) {
+ promise->cfg |= DDMA_CFG_CONT_MODE | DDMA_CFG_SRC_DRQ_TYPE(vchan->endpoint) |
+    DDMA_CFG_SRC_ADDR_MODE(DDMA_ADDR_MODE_IO) |
+    DDMA_CFG_DEST_DRQ_TYPE(DDMA_DRQ_TYPE_SDRAM) |
+    DDMA_CFG_DEST_ADDR_MODE(DDMA_ADDR_MODE_LINEAR);
+ } else {
+ promise->cfg |= NDMA_CFG_CONT_MODE | NDMA_CFG_SRC_DRQ_TYPE(vchan->endpoint) |
+    NDMA_CFG_SRC_FIXED_ADDR |
+    NDMA_CFG_DEST_DRQ_TYPE(NDMA_DRQ_TYPE_SDRAM);
+ }
+
+ /* Fill the contract with our only promise */
+ list_add_tail(&promise->list, &contract->demands);
+
+ /* And add it to the vchan */
+ return vchan_tx_prep(&vchan->vc, &contract->vd, flags);
+}
+

+static int sun4i_dma_device_slave_caps(struct dma_chan *dchan,
+      struct dma_slave_caps *caps)
+{
+ caps->src_addr_widths = 32;
+ caps->dstn_addr_widths = 32;
+ caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
+ caps->cmd_pause = true;
+ caps->cmd_terminate = true;
+ caps->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
+
+ return 0;
+}
+
 static int sun4i_dma_probe(struct platform_device *pdev)
 {
  struct sun4i_ddma_dev *priv;
@@ -962,7 +1057,9 @@ static int sun4i_dma_probe(struct platform_device *pdev)
  priv->slave.device_issue_pending = sun4i_dma_issue_pending;
  priv->slave.device_prep_slave_sg = sun4i_dma_prep_slave_sg;
  priv->slave.device_prep_dma_memcpy = sun4i_dma_prep_dma_memcpy;
+ priv->slave.device_prep_dma_cyclic = sun4i_dma_prep_dma_cyclic;
  priv->slave.device_control = sun4i_dma_control;
+ priv->slave.device_slave_caps = sun4i_dma_device_slave_caps;
  priv->slave.chancnt = DDMA_NR_MAX_VCHANS;

  priv->slave.dev = &pdev->dev;

On Sun, Jul 6, 2014 at 12:05 AM, Emilio L?pez <emilio@elopez.com.ar> wrote:
> Hi everyone,
>
> As part of Google Summer of Code, I've tasked myself with implementing
> DMA support for the earlier Allwinner platforms. This second round of
> patches is the result of said effort.
>
> The first patch is the actual driver to support these platforms. Patches
> three, four and five add the corresponding DMA node to the sun4i,
> sun5i and sun7i device trees.
>
> The second patch, involving the sunxi SPI driver, lets users do SPI
> transfers of >=64 bytes by using DMA. The first round of patches also
> had a patch for 8250_dw letting it use DMA as well, but there were some
> issues causing underruns and "too much work for IRQ", so I have dropped
> them. It's worth noting that Allwinner themselves don't use DMA
> transfers on their 8250 driver on the SDK.
>
> Patches six, seven and eight add the DMA properties to SPI so the first
> two patches can be used. Patches nine, ten and eleven are *only intended
> for testing*, and add a dummy SPIdev device to cubieboard, cubietruck
> and A10S-OLinuXino to facilitate testing with spidev_test.
>
> My main testing procedure for SPI has been modified versions of
> spidev_test from the kernel tree, with and without shorting MISO and
> MOSI. For memory to memory transfers, I have used dmatest.ko with
> various configurations. I have done testing on a cubieboard (A10, sun4i)
> and cubietruck (A20, sun7i) as well as an A10S-OLinuXino.
>
> You will find some extra remarks on individual patches after their
> descriptions. All comments are welcome.
>
> Thanks!
>
> Emilio L?pez (8):
>   dma: sun4i: Add support for the DMA engine on sun[457]i SoCs
>   spi: sun4i: add DMA support
>   ARM: sun4i: Add node to represent the DMA controller
>   ARM: sun5i: Add nodes to represent the DMA controllers
>   ARM: sun7i: Add node to represent the DMA controller
>   ARM: sun4i: enable DMA on SPI
>   ARM: sun5i: enable DMA on SPI
>   ARM: sun7i: enable DMA on SPI
>
>  .../devicetree/bindings/dma/sun4i-dma.txt          |   45 +
>  arch/arm/boot/dts/sun4i-a10.dtsi                   |   16 +
>  arch/arm/boot/dts/sun5i-a10s.dtsi                  |   14 +
>  arch/arm/boot/dts/sun5i-a13.dtsi                   |   14 +
>  arch/arm/boot/dts/sun7i-a20.dtsi                   |   16 +
>  drivers/dma/Kconfig                                |   10 +
>  drivers/dma/Makefile                               |    1 +
>  drivers/dma/sun4i-dma.c                            | 1025 ++++++++++++++++++++
>  drivers/spi/spi-sun4i.c                            |  155 ++-
>  9 files changed, 1285 insertions(+), 11 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/dma/sun4i-dma.txt
>  create mode 100644 drivers/dma/sun4i-dma.c
>
> --
> 2.0.1
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel



-- 
Jon Smirl
jonsmirl at gmail.com

[PATCH v2 1/8] dma: sun4i: Add support for the DMA engine on sun[457]i SoCs

[jonsmirl at gmail.com]

On Sun, Jul 6, 2014 at 12:05 AM, Emilio L?pez <emilio@elopez.com.ar> wrote:
> This patch adds support for the DMA engine present on Allwinner A10,

ALSA only programs in the destination bus width and burst. So the
source buswidth is DMA_SLAVE_BUSWIDTH_UNDEFINED = 0.

In this driver that results in the source buswidth being set to 8 and
burst set to 1 for the source which disagree with what the Allwinner
code does. To agree with the Allwinner code
DMA_SLAVE_BUSWIDTH_UNDEFINED should cause the dest width/burst to get
copied to the src width/burst.

void snd_dmaengine_pcm_set_config_from_dai_data(
const struct snd_pcm_substream *substream,
const struct snd_dmaengine_dai_dma_data *dma_data,
struct dma_slave_config *slave_config)
{
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
slave_config->dst_addr = dma_data->addr;
slave_config->dst_maxburst = dma_data->maxburst;
if (dma_data->addr_width != DMA_SLAVE_BUSWIDTH_UNDEFINED)
slave_config->dst_addr_width = dma_data->addr_width;
} else {
slave_config->src_addr = dma_data->addr;
slave_config->src_maxburst = dma_data->maxburst;
if (dma_data->addr_width != DMA_SLAVE_BUSWIDTH_UNDEFINED)
slave_config->src_addr_width = dma_data->addr_width;
}

slave_config->slave_id = dma_data->slave_id;
}
EXPORT_SYMBOL_GPL(snd_dmaengine_pcm_set_config_from_dai_data);

[PATCH v2 2/8] spi: sun4i: add DMA support

[Maxime Ripard]

Hi Emilio,

On Sun, Jul 06, 2014 at 01:05:09AM -0300, Emilio L?pez wrote:
> This patch adds DMA support for 64 byte transfers on the sun4i SPI
> controller. Bigger transfers did not seem to work when tested, and if
> the hardware actually supports those, it will need further
> investigation as to how to issue them correctly.
> 
> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>

This patch looks fine from a quick look, but you should put Mark Brown
in the recipients, since he's the SPI maintainer, and will probably
have a sharper look.

Thanks!
Maxim

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v2 2/8] spi: sun4i: add DMA support

[Emilio López]

Hi,

El 10/07/14 09:22, Maxime Ripard escribi?:
> Hi Emilio,
>
> On Sun, Jul 06, 2014 at 01:05:09AM -0300, Emilio L?pez wrote:
>> This patch adds DMA support for 64 byte transfers on the sun4i SPI
>> controller. Bigger transfers did not seem to work when tested, and if
>> the hardware actually supports those, it will need further
>> investigation as to how to issue them correctly.
>>
>> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
>
> This patch looks fine from a quick look, but you should put Mark Brown
> in the recipients, since he's the SPI maintainer, and will probably
> have a sharper look.

Thanks for the heads up, I'll Cc him as well as the SPI list on v3

Cheers!

Emilio

[PATCH v2 1/8] dma: sun4i: Add support for the DMA engine on sun[457]i SoCs

[Maxime Ripard]

On Sun, Jul 06, 2014 at 01:05:08AM -0300, Emilio L?pez wrote:
> This patch adds support for the DMA engine present on Allwinner A10,
> A13, A10S and A20 SoCs. This engine has two kinds of channels: normal
> and dedicated. The main difference is in the mode of operation;
> while a single normal channel may be operating at any given time,
> dedicated channels may operate simultaneously provided there is no
> overlap of source or destination.
> 
> Hardware documentation can be found on A10 User Manual (section 12), A13
> User Manual (section 14) and A20 User Manual (section 1.12)
> 
> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
> ---
> 
> Changes from v1:
>  * address comments from Chen-Yu and Maxime
>  * fix issue converting bus width
>  * switch to using a threaded IRQ instead of a tasklet on
>    recommendation from Maxime
>  * fix issue setting magic timing parameter for SPI transfers
>  * fix an issue with list handling reported by the kbuild 0-DAY robot (thanks!)
>  * drop a lot of unused #define
>  * probably some more stuff I'm forgetting
> 
>  .../devicetree/bindings/dma/sun4i-dma.txt          |   45 +
>  drivers/dma/Kconfig                                |   10 +
>  drivers/dma/Makefile                               |    1 +
>  drivers/dma/sun4i-dma.c                            | 1025 ++++++++++++++++++++
>  4 files changed, 1081 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/dma/sun4i-dma.txt
>  create mode 100644 drivers/dma/sun4i-dma.c
> 
> diff --git a/Documentation/devicetree/bindings/dma/sun4i-dma.txt b/Documentation/devicetree/bindings/dma/sun4i-dma.txt
> new file mode 100644
> index 0000000..f5661a5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/sun4i-dma.txt
> @@ -0,0 +1,45 @@
> +Allwinner A10 DMA Controller
> +
> +This driver follows the generic DMA bindings defined in dma.txt.
> +
> +Required properties:
> +
> +- compatible:	Must be "allwinner,sun4i-a10-dma"
> +- reg:		Should contain the registers base address and length
> +- interrupts:	Should contain a reference to the interrupt used by this device
> +- clocks:	Should contain a reference to the parent AHB clock
> +- #dma-cells :	Should be 1, a single cell holding a line request number
> +
> +Example:
> +	dma: dma-controller at 01c02000 {
> +		compatible = "allwinner,sun4i-a10-dma";
> +		reg = <0x01c02000 0x1000>;
> +		interrupts = <27>;
> +		clocks = <&ahb_gates 6>;
> +		#dma-cells = <1>;
> +	};
> +
> +Clients:
> +
> +DMA clients connected to the Allwinner A10 DMA controller must use the
> +format described in the dma.txt file, using a three-cell specifier for
> +each channel: a phandle plus two integer cells.
> +The three cells in order are:
> +
> +1. A phandle pointing to the DMA controller.
> +2. Whether it is using normal (0) or dedicated (1) channels
> +2. The port ID as specified in the datasheet
> +
> +Example:
> +	spi2: spi at 01c17000 {
> +		compatible = "allwinner,sun4i-a10-spi";
> +		reg = <0x01c17000 0x1000>;
> +		interrupts = <0 12 4>;
> +		clocks = <&ahb_gates 22>, <&spi2_clk>;
> +		clock-names = "ahb", "mod";
> +		dmas = <&dma 1 29>, <&dma 1 28>;
> +		dma-names = "rx", "tx";
> +		status = "disabled";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +	};
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index 1eca7b9..cfa6e0a 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -375,6 +375,16 @@ config XILINX_VDMA
>  	  channels, Memory Mapped to Stream (MM2S) and Stream to
>  	  Memory Mapped (S2MM) for the data transfers.
>  
> +config SUN4I_DMA
> +	tristate "Allwinner A10/A10S/A13/A20 DMA support"

I'm not that fond of having an exhaustive list here. If some other SoC
we didn't thought of or get a new SoC that uses this controller, this
list won't be exhaustive anymore, which is even worse.

Just mention the A10.

> +	depends on (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || (COMPILE_TEST && OF && ARM))

This pretty much defeats the purpose of COMPILE_TEST

> +	select DMA_ENGINE
> +	select DMA_OF
> +	select DMA_VIRTUAL_CHANNELS

I guess you could default to y for the SoCs where it's relevant.

> +	help
> +	  Enable support for the DMA controller present in the sun4i,
> +	  sun5i and sun7i Allwinner ARM SoCs.
> +
>  config DMA_ENGINE
>  	bool
>  
> diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
> index c779e1e..430de61 100644
> --- a/drivers/dma/Makefile
> +++ b/drivers/dma/Makefile
> @@ -47,3 +47,4 @@ obj-$(CONFIG_MOXART_DMA) += moxart-dma.o
>  obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
>  obj-$(CONFIG_QCOM_BAM_DMA) += qcom_bam_dma.o
>  obj-y += xilinx/
> +obj-$(CONFIG_SUN4I_DMA) += sun4i-dma.o
> diff --git a/drivers/dma/sun4i-dma.c b/drivers/dma/sun4i-dma.c
> new file mode 100644
> index 0000000..24fa391
> --- /dev/null
> +++ b/drivers/dma/sun4i-dma.c
> @@ -0,0 +1,1025 @@
> +/*
> + * Copyright (C) 2014 Emilio L?pez
> + * Emilio L?pez <emilio@elopez.com.ar>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include <linux/bitmap.h>
> +#include <linux/bitops.h>
> +#include <linux/clk.h>
> +#include <linux/dmaengine.h>
> +#include <linux/dmapool.h>
> +#include <linux/interrupt.h>
> +#include <linux/module.h>
> +#include <linux/of_dma.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +
> +#include "virt-dma.h"
> +
> +/** Normal DMA register values **/
> +
> +/* Normal DMA source/destination data request type values */
> +#define NDMA_DRQ_TYPE_SDRAM			0x16
> +#define NDMA_DRQ_TYPE_LIMIT			(0x1F + 1)

Hmmm, I'm unsure what this is about... What is it supposed to do, and
how is it different from BIT(5) ?

> +
> +/** Normal DMA register layout **/
> +
> +/* Normal DMA configuration register layout */
> +#define NDMA_CFG_LOADING			BIT(31)
> +#define NDMA_CFG_CONT_MODE			BIT(30)
> +#define NDMA_CFG_WAIT_STATE(n)			((n) << 27)
> +#define NDMA_CFG_DEST_DATA_WIDTH(width)		((width) << 25)
> +#define NDMA_CFG_DEST_BURST_LENGTH(len)		((len) << 23)
> +#define NDMA_CFG_DEST_NON_SECURE		BIT(22)
> +#define NDMA_CFG_DEST_FIXED_ADDR		BIT(21)
> +#define NDMA_CFG_DEST_DRQ_TYPE(type)		((type) << 16)
> +#define NDMA_CFG_BYTE_COUNT_MODE_REMAIN		BIT(15)
> +#define NDMA_CFG_SRC_DATA_WIDTH(width)		((width) << 9)
> +#define NDMA_CFG_SRC_BURST_LENGTH(len)		((len) << 7)
> +#define NDMA_CFG_SRC_NON_SECURE			BIT(6)
> +#define NDMA_CFG_SRC_FIXED_ADDR			BIT(5)
> +#define NDMA_CFG_SRC_DRQ_TYPE(type)		((type) << 0)
> +
> +/** Dedicated DMA register values **/
> +
> +/* Dedicated DMA source/destination address mode values */
> +#define DDMA_ADDR_MODE_LINEAR			0
> +#define DDMA_ADDR_MODE_IO			1
> +#define DDMA_ADDR_MODE_HORIZONTAL_PAGE		2
> +#define DDMA_ADDR_MODE_VERTICAL_PAGE		3
> +
> +/* Dedicated DMA source/destination data request type values */
> +#define DDMA_DRQ_TYPE_SDRAM			0x1
> +#define DDMA_DRQ_TYPE_LIMIT			(0x1F + 1)
> +
> +/** Dedicated DMA register layout **/
> +
> +/* Dedicated DMA configuration register layout */
> +#define DDMA_CFG_LOADING			BIT(31)
> +#define DDMA_CFG_BUSY				BIT(30)
> +#define DDMA_CFG_CONT_MODE			BIT(29)
> +#define DDMA_CFG_DEST_NON_SECURE		BIT(28)
> +#define DDMA_CFG_DEST_DATA_WIDTH(width)		((width) << 25)
> +#define DDMA_CFG_DEST_BURST_LENGTH(len)		((len) << 23)
> +#define DDMA_CFG_DEST_ADDR_MODE(mode)		((mode) << 21)
> +#define DDMA_CFG_DEST_DRQ_TYPE(type)		((type) << 16)
> +#define DDMA_CFG_BYTE_COUNT_MODE_REMAIN		BIT(15)
> +#define DDMA_CFG_SRC_NON_SECURE			BIT(12)
> +#define DDMA_CFG_SRC_DATA_WIDTH(width)		((width) << 9)
> +#define DDMA_CFG_SRC_BURST_LENGTH(len)		((len) << 7)
> +#define DDMA_CFG_SRC_ADDR_MODE(mode)		((mode) << 5)
> +#define DDMA_CFG_SRC_DRQ_TYPE(type)		((type) << 0)
> +
> +/* Dedicated DMA parameter register layout */
> +#define DDMA_PARA_DEST_DATA_BLK_SIZE(n)		(((n) - 1) << 24)
> +#define DDMA_PARA_DEST_WAIT_CYCLES(n)		(((n) - 1) << 16)
> +#define DDMA_PARA_SRC_DATA_BLK_SIZE(n)		(((n) - 1) << 8)
> +#define DDMA_PARA_SRC_WAIT_CYCLES(n)		(((n) - 1) << 0)
> +
> +/** DMA register offsets **/
> +
> +/* General register offsets */
> +#define DMA_IRQ_ENABLE_REG			0x0
> +#define DMA_IRQ_PENDING_STATUS_REG		0x4
> +
> +/* Normal DMA register offsets */
> +#define NDMA_CHANNEL_REG_BASE(n)		(0x100 + (n) * 0x20)
> +#define NDMA_CFG_REG				0x0
> +#define NDMA_SRC_ADDR_REG			0x4
> +#define NDMA_DEST_ADDR_REG			0x8
> +#define NDMA_BYTE_COUNT_REG			0xC
> +
> +/* Dedicated DMA register offsets */
> +#define DDMA_CHANNEL_REG_BASE(n)		(0x300 + (n) * 0x20)
> +#define DDMA_CFG_REG				0x0
> +#define DDMA_SRC_ADDR_REG			0x4
> +#define DDMA_DEST_ADDR_REG			0x8
> +#define DDMA_BYTE_COUNT_REG			0xC
> +#define DDMA_PARA_REG				0x18
> +
> +/** DMA Driver **/
> +
> +/*
> + * Normal DMA has 8 channels, and Dedicated DMA has another 8, so that's
> + * 16 channels. As for endpoints, there's 29 and 21 respectively. Given
> + * that the Normal DMA endpoints (other than SDRAM) can be used as tx/rx,
> + * we need 78 vchans in total
> + */
> +#define NDMA_NR_MAX_CHANNELS	8
> +#define DDMA_NR_MAX_CHANNELS	8
> +#define DMA_NR_MAX_CHANNELS	(NDMA_NR_MAX_CHANNELS + DDMA_NR_MAX_CHANNELS)
> +#define NDMA_NR_MAX_VCHANS	(29 * 2 - 1)
> +#define DDMA_NR_MAX_VCHANS	21
> +#define DMA_NR_MAX_VCHANS	(NDMA_NR_MAX_VCHANS + DDMA_NR_MAX_VCHANS)
> +
> +/* This set of DDMA timing parameters were found experimentally while
> + * working with the SPI driver and seem to make it behave correctly */
> +#define DDMA_MAGIC_SPI_PARAMETERS	(DDMA_PARA_DEST_DATA_BLK_SIZE(1) | \
> +					DDMA_PARA_SRC_DATA_BLK_SIZE(1) | \
> +					DDMA_PARA_DEST_WAIT_CYCLES(2) | \
> +					DDMA_PARA_SRC_WAIT_CYCLES(2))
> +
> +struct sun4i_dma_pchan {
> +	/* Register base of channel */
> +	void __iomem			*base;
> +	/* vchan currently being serviced */
> +	struct sun4i_dma_vchan		*vchan;
> +	/* Is this a dedicated pchan? */
> +	int				is_dedicated;
> +};
> +
> +struct sun4i_dma_vchan {
> +	struct virt_dma_chan		vc;
> +	struct dma_slave_config		cfg;
> +	struct sun4i_dma_pchan		*pchan;
> +	struct sun4i_dma_promise	*processing;
> +	struct sun4i_dma_contract	*contract;
> +	u8				endpoint;
> +	int				is_dedicated;
> +};
> +
> +struct sun4i_dma_promise {
> +	u32				cfg;
> +	u32				para;
> +	dma_addr_t			src;
> +	dma_addr_t			dst;
> +	size_t				len;
> +	struct list_head		list;
> +};
> +
> +/* A contract is a set of promises */
> +struct sun4i_dma_contract {
> +	struct virt_dma_desc		vd;
> +	struct list_head		demands;
> +	struct list_head		completed_demands;
> +};
> +
> +struct sun4i_dma_dev {
> +	DECLARE_BITMAP(pchans_used, DMA_NR_MAX_CHANNELS);
> +	struct dma_device		slave;
> +	struct sun4i_dma_pchan		*pchans;
> +	struct sun4i_dma_vchan		*vchans;
> +	void __iomem			*base;
> +	struct clk			*clk;
> +	int				irq;
> +	spinlock_t			lock;
> +};
> +
> +static struct sun4i_dma_dev *to_sun4i_dma_dev(struct dma_device *dev)
> +{
> +	return container_of(dev, struct sun4i_dma_dev, slave);
> +}
> +
> +static struct sun4i_dma_vchan *to_sun4i_dma_vchan(struct dma_chan *chan)
> +{
> +	return container_of(chan, struct sun4i_dma_vchan, vc.chan);
> +}
> +
> +static struct sun4i_dma_contract *to_sun4i_dma_contract(struct virt_dma_desc *vd)
> +{
> +	return container_of(vd, struct sun4i_dma_contract, vd);
> +}
> +
> +static struct device *chan2dev(struct dma_chan *chan)
> +{
> +	return &chan->dev->device;
> +}
> +
> +static int convert_burst(u32 maxburst)
> +{
> +	if (maxburst > 8)
> +		return -EINVAL;
> +
> +	/* 1 -> 0, 4 -> 1, 8 -> 2 */
> +	return (maxburst >> 2);
> +}
> +
> +static int convert_buswidth(enum dma_slave_buswidth addr_width)
> +{
> +	if (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES)
> +		return -EINVAL;
> +
> +	/* 8 (1 byte) -> 0, 16 (2 bytes) -> 1, 32 (4 bytes) -> 2 */
> +	return (addr_width >> 1);
> +}
> +
> +static int sun4i_dma_alloc_chan_resources(struct dma_chan *chan)
> +{
> +	return 0;
> +}
> +
> +static void sun4i_dma_free_chan_resources(struct dma_chan *chan)
> +{
> +	struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
> +
> +	vchan_free_chan_resources(&vchan->vc);
> +}
> +
> +static struct sun4i_dma_pchan *find_and_use_pchan(struct sun4i_dma_dev *priv,
> +						  struct sun4i_dma_vchan *vchan)
> +{
> +	struct sun4i_dma_pchan *pchan = NULL, *pchans = priv->pchans;
> +	unsigned long flags;
> +	int i, max;
> +
> +	spin_lock_irqsave(&priv->lock, flags);
> +
> +	/*
> +	 * pchans 0-NDMA_NR_MAX_CHANNELS are normal, and
> +	 * NDMA_NR_MAX_CHANNELS+ are dedicated ones
> +	 */
> +	if (vchan->is_dedicated) {
> +		i = NDMA_NR_MAX_CHANNELS;
> +		max = DMA_NR_MAX_CHANNELS;
> +	} else {
> +		i = 0;
> +		max = NDMA_NR_MAX_CHANNELS;
> +	}
> +
> +	for_each_clear_bit_from(i, &priv->pchans_used, max) {
> +		pchan = &pchans[i];
> +		pchan->vchan = vchan;
> +		set_bit(i, priv->pchans_used);
> +		break;
> +	}
> +
> +	spin_unlock_irqrestore(&priv->lock, flags);
> +
> +	return pchan;
> +}
> +
> +static void release_pchan(struct sun4i_dma_dev *priv,
> +			  struct sun4i_dma_pchan *pchan)
> +{
> +	unsigned long flags;
> +	int nr = pchan - priv->pchans;
> +
> +	spin_lock_irqsave(&priv->lock, flags);
> +
> +	clear_bit(nr, priv->pchans_used);
> +	pchan->vchan = NULL;
> +
> +	spin_unlock_irqrestore(&priv->lock, flags);
> +}
> +
> +static void configure_pchan(struct sun4i_dma_pchan *pchan,
> +			    struct sun4i_dma_promise *d)
> +{
> +	/*
> +	 * Configure addresses and misc parameters depending on type
> +	 * DDMA has an extra field with timing parameters
> +	 */
> +	if (pchan->is_dedicated) {
> +		writel_relaxed(d->src, pchan->base + DDMA_SRC_ADDR_REG);
> +		writel_relaxed(d->dst, pchan->base + DDMA_DEST_ADDR_REG);
> +		writel_relaxed(d->len, pchan->base + DDMA_BYTE_COUNT_REG);
> +		writel_relaxed(d->para, pchan->base + DDMA_PARA_REG);
> +		writel_relaxed(d->cfg, pchan->base + DDMA_CFG_REG);
> +	} else {
> +		writel_relaxed(d->src, pchan->base + NDMA_SRC_ADDR_REG);
> +		writel_relaxed(d->dst, pchan->base + NDMA_DEST_ADDR_REG);
> +		writel_relaxed(d->len, pchan->base + NDMA_BYTE_COUNT_REG);
> +		writel_relaxed(d->cfg, pchan->base + NDMA_CFG_REG);
> +	}
> +}
> +
> +static void set_pchan_interrupt(struct sun4i_dma_dev *priv,
> +				struct sun4i_dma_pchan *pchan,
> +				int half, int end)
> +{
> +	u32 reg = readl_relaxed(priv->base + DMA_IRQ_ENABLE_REG);
> +	int pchan_number = pchan - priv->pchans;
> +
> +	if (half)
> +		reg |= BIT(pchan_number * 2);
> +	else
> +		reg &= ~BIT(pchan_number * 2);
> +
> +	if (end)
> +		reg |= BIT(pchan_number * 2 + 1);
> +	else
> +		reg &= ~BIT(pchan_number * 2 + 1);
> +
> +	writel_relaxed(reg, priv->base + DMA_IRQ_ENABLE_REG);

I don't see any interrupts here. Is this suppose to be called with a
lock taken? If so, it should be mentionned in some comment.

> +}
> +
> +static int execute_vchan_pending(struct sun4i_dma_dev *priv,
> +				 struct sun4i_dma_vchan *vchan)
> +{
> +	struct sun4i_dma_promise *promise = NULL;
> +	struct sun4i_dma_contract *contract = NULL;
> +	struct sun4i_dma_pchan *pchan;
> +	struct virt_dma_desc *vd;
> +	int ret;
> +
> +	lockdep_assert_held(&vchan->vc.lock);
> +
> +	/* We need a pchan to do anything, so secure one if available */
> +	pchan = find_and_use_pchan(priv, vchan);
> +	if (!pchan)
> +		return -EBUSY;
> +
> +	/*
> +	 * Channel endpoints must not be repeated, so if this vchan
> +	 * has already submitted some work, we can't do anything else
> +	 */
> +	if (vchan->processing) {
> +		dev_dbg(chan2dev(&vchan->vc.chan),
> +			"processing something to this endpoint already\n");
> +		ret = -EBUSY;
> +		goto release_pchan;
> +	}
> +
> +	do {
> +		/* Figure out which contract we're working with today */
> +		vd = vchan_next_desc(&vchan->vc);
> +		if (!vd) {
> +			dev_dbg(chan2dev(&vchan->vc.chan),
> +				"No pending contract found");
> +			ret = 0;
> +			goto release_pchan;
> +		}
> +
> +		contract = to_sun4i_dma_contract(vd);
> +		if (list_empty(&contract->demands)) {
> +			/* The contract has been completed so mark it as such */
> +			list_del(&contract->vd.node);
> +			vchan_cookie_complete(&contract->vd);
> +			dev_dbg(chan2dev(&vchan->vc.chan),
> +				"Empty contract found and marked complete");
> +		}
> +	} while (list_empty(&contract->demands));
> +
> +	/* Now find out what we need to do */
> +	promise = list_first_entry(&contract->demands,
> +				   struct sun4i_dma_promise, list);
> +	vchan->processing = promise;
> +
> +	/* ... and make it reality */
> +	if (promise) {
> +		vchan->contract = contract;
> +		set_pchan_interrupt(priv, pchan, 0, 1);
> +		configure_pchan(pchan, promise);
> +	}
> +
> +	return 0;
> +
> +release_pchan:
> +	release_pchan(priv, pchan);
> +	return ret;
> +}
> +
> +/**
> + * Generate a promise, to be used in a normal DMA contract.
> + *
> + * A NDMA promise contains all the information required to program the
> + * normal part of the DMA Engine and get data copied. A non-executed
> + * promise will live in the demands list on a contract. Once it has been
> + * completed, it will be moved to the completed demands list for later freeing.
> + * All linked promises will be freed when the corresponding contract is freed
> + */
> +static struct sun4i_dma_promise *
> +generate_ndma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_t dest,
> +		      size_t len, struct dma_slave_config *sconfig)
> +{
> +	struct sun4i_dma_promise *promise;
> +	int ret;
> +
> +	promise = kzalloc(sizeof(*promise), GFP_NOWAIT);
> +	if (!promise)
> +		return NULL;
> +
> +	promise->src = src;
> +	promise->dst = dest;
> +	promise->len = len;
> +	promise->cfg = NDMA_CFG_LOADING | NDMA_CFG_BYTE_COUNT_MODE_REMAIN;
> +
> +	/* Source burst */
> +	ret = convert_burst(sconfig->src_maxburst);
> +	if (IS_ERR_VALUE(ret))
> +		goto fail;
> +	promise->cfg |= NDMA_CFG_SRC_BURST_LENGTH(ret);
> +
> +	/* Destination burst */
> +	ret = convert_burst(sconfig->dst_maxburst);
> +	if (IS_ERR_VALUE(ret))
> +		goto fail;
> +	promise->cfg |= NDMA_CFG_DEST_BURST_LENGTH(ret);
> +
> +	/* Source bus width */
> +	ret = convert_buswidth(sconfig->src_addr_width);
> +	if (IS_ERR_VALUE(ret))
> +		goto fail;
> +	promise->cfg |= NDMA_CFG_SRC_DATA_WIDTH(ret);
> +
> +	/* Destination bus width */
> +	ret = convert_buswidth(sconfig->dst_addr_width);
> +	if (IS_ERR_VALUE(ret))
> +		goto fail;
> +	promise->cfg |= NDMA_CFG_DEST_DATA_WIDTH(ret);
> +
> +	return promise;
> +
> +fail:
> +	kfree(promise);
> +	return NULL;
> +}
> +
> +/**
> + * Generate a promise, to be used in a dedicated DMA contract.
> + *
> + * A DDMA promise contains all the information required to program the
> + * Dedicated part of the DMA Engine and get data copied. A non-executed
> + * promise will live in the demands list on a contract. Once it has been
> + * completed, it will be moved to the completed demands list for later freeing.
> + * All linked promises will be freed when the corresponding contract is freed
> + */
> +static struct sun4i_dma_promise *
> +generate_ddma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_t dest,
> +		      size_t len, struct dma_slave_config *sconfig)
> +{
> +	struct sun4i_dma_promise *promise;
> +	int ret;
> +
> +	promise = kzalloc(sizeof(*promise), GFP_NOWAIT);
> +	if (!promise)
> +		return NULL;
> +
> +	promise->src = src;
> +	promise->dst = dest;
> +	promise->len = len;
> +	promise->cfg = DDMA_CFG_LOADING | DDMA_CFG_BYTE_COUNT_MODE_REMAIN;
> +
> +	/* Source burst */
> +	ret = convert_burst(sconfig->src_maxburst);
> +	if (IS_ERR_VALUE(ret))
> +		goto fail;
> +	promise->cfg |= DDMA_CFG_SRC_BURST_LENGTH(ret);
> +
> +	/* Destination burst */
> +	ret = convert_burst(sconfig->dst_maxburst);
> +	if (IS_ERR_VALUE(ret))
> +		goto fail;
> +	promise->cfg |= DDMA_CFG_DEST_BURST_LENGTH(ret);
> +
> +	/* Source bus width */
> +	ret = convert_buswidth(sconfig->src_addr_width);
> +	if (IS_ERR_VALUE(ret))
> +		goto fail;
> +	promise->cfg |= DDMA_CFG_SRC_DATA_WIDTH(ret);
> +
> +	/* Destination bus width */
> +	ret = convert_buswidth(sconfig->dst_addr_width);
> +	if (IS_ERR_VALUE(ret))
> +		goto fail;
> +	promise->cfg |= DDMA_CFG_DEST_DATA_WIDTH(ret);
> +
> +	return promise;
> +
> +fail:
> +	kfree(promise);
> +	return NULL;
> +}
> +
> +/**
> + * Generate a contract
> + *
> + * Contracts function as DMA descriptors. As our hardware does not support
> + * linked lists, we need to implement SG via software. We use a contract
> + * to hold all the pieces of the request and process them serially one
> + * after another. Each piece is represented as a promise.
> + */
> +static struct sun4i_dma_contract *generate_dma_contract(void)
> +{
> +	struct sun4i_dma_contract *contract;
> +
> +	contract = kzalloc(sizeof(*contract), GFP_NOWAIT);
> +	if (!contract)
> +		return NULL;
> +
> +	INIT_LIST_HEAD(&contract->demands);
> +	INIT_LIST_HEAD(&contract->completed_demands);
> +
> +	return contract;
> +}
> +
> +/**
> + * Free a contract and all its associated promises
> + */
> +static void sun4i_dma_free_contract(struct virt_dma_desc *vd)
> +{
> +	struct sun4i_dma_contract *contract = to_sun4i_dma_contract(vd);
> +	struct sun4i_dma_promise *promise;
> +
> +	/* Free all the demands and completed demands */
> +	list_for_each_entry(promise, &contract->demands, list) {
> +		kfree(promise);
> +	}
> +
> +	list_for_each_entry(promise, &contract->completed_demands, list) {
> +		kfree(promise);
> +	}
>

Those brackets are useless.

> +	kfree(contract);
> +}
> +
> +static struct dma_async_tx_descriptor *
> +sun4i_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest,
> +			  dma_addr_t src, size_t len, unsigned long flags)
> +{
> +	struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
> +	struct dma_slave_config *sconfig = &vchan->cfg;
> +	struct sun4i_dma_promise *promise;
> +	struct sun4i_dma_contract *contract;
> +
> +	contract = generate_dma_contract();
> +	if (!contract)
> +		return NULL;
> +
> +	if (vchan->is_dedicated)
> +		promise = generate_ddma_promise(chan, src, dest, len, sconfig);
> +	else
> +		promise = generate_ndma_promise(chan, src, dest, len, sconfig);
> +
> +	if (!promise) {
> +		kfree(contract);
> +		return NULL;
> +	}
> +
> +	/* Configure memcpy mode */
> +	if (vchan->is_dedicated) {
> +		promise->cfg |= DDMA_CFG_SRC_DRQ_TYPE(DDMA_DRQ_TYPE_SDRAM) |
> +				DDMA_CFG_DEST_DRQ_TYPE(DDMA_DRQ_TYPE_SDRAM);
> +	} else {
> +		promise->cfg |= NDMA_CFG_SRC_DRQ_TYPE(NDMA_DRQ_TYPE_SDRAM) |
> +				NDMA_CFG_DEST_DRQ_TYPE(NDMA_DRQ_TYPE_SDRAM);
> +	}
> +
> +	/* Fill the contract with our only promise */
> +	list_add_tail(&promise->list, &contract->demands);
> +
> +	/* And add it to the vchan */
> +	return vchan_tx_prep(&vchan->vc, &contract->vd, flags);
> +}
> +
> +static struct dma_async_tx_descriptor *
> +sun4i_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
> +			unsigned int sg_len, enum dma_transfer_direction dir,
> +			unsigned long flags, void *context)
> +{
> +	struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
> +	struct dma_slave_config *sconfig = &vchan->cfg;
> +	struct sun4i_dma_promise *promise;
> +	struct sun4i_dma_contract *contract;
> +	struct scatterlist *sg;
> +	dma_addr_t srcaddr, dstaddr;
> +	u32 endpoints, para;
> +	int i;
> +
> +	if (!sgl)
> +		return NULL;
> +
> +	if (!is_slave_direction(dir)) {
> +		dev_err(chan2dev(chan), "Invalid DMA direction\n");
> +		return NULL;
> +	}
> +
> +	contract = generate_dma_contract();
> +	if (!contract)
> +		return NULL;
> +
> +	/* Figure out endpoints */
> +	if (vchan->is_dedicated && dir == DMA_MEM_TO_DEV) {
> +		endpoints = DDMA_CFG_SRC_DRQ_TYPE(DDMA_DRQ_TYPE_SDRAM) |
> +			    DDMA_CFG_SRC_ADDR_MODE(DDMA_ADDR_MODE_LINEAR) |
> +			    DDMA_CFG_DEST_DRQ_TYPE(vchan->endpoint) |
> +			    DDMA_CFG_DEST_ADDR_MODE(DDMA_ADDR_MODE_IO);
> +	} else if (!vchan->is_dedicated && dir == DMA_MEM_TO_DEV) {
> +		endpoints = NDMA_CFG_SRC_DRQ_TYPE(NDMA_DRQ_TYPE_SDRAM) |
> +			    NDMA_CFG_DEST_DRQ_TYPE(vchan->endpoint) |
> +			    NDMA_CFG_DEST_FIXED_ADDR;
> +	} else if (vchan->is_dedicated) {
> +		endpoints = DDMA_CFG_SRC_DRQ_TYPE(vchan->endpoint) |
> +			    DDMA_CFG_SRC_ADDR_MODE(DDMA_ADDR_MODE_IO) |
> +			    DDMA_CFG_DEST_DRQ_TYPE(DDMA_DRQ_TYPE_SDRAM) |
> +			    DDMA_CFG_DEST_ADDR_MODE(DDMA_ADDR_MODE_LINEAR);
> +	} else {
> +		endpoints = NDMA_CFG_SRC_DRQ_TYPE(vchan->endpoint) |
> +			    NDMA_CFG_SRC_FIXED_ADDR |
> +			    NDMA_CFG_DEST_DRQ_TYPE(NDMA_DRQ_TYPE_SDRAM);
> +	}
> +
> +	for_each_sg(sgl, sg, sg_len, i) {
> +		/* Figure out addresses */
> +		if (dir == DMA_MEM_TO_DEV) {
> +			srcaddr = sg_dma_address(sg);
> +			dstaddr = sconfig->dst_addr;
> +		} else {
> +			srcaddr = sconfig->src_addr;
> +			dstaddr = sg_dma_address(sg);
> +		}
> +
> +		/* TODO: should this be configurable? */
> +		para = DDMA_MAGIC_SPI_PARAMETERS;

What is it? Is it supposed to change from one client device to
another?

> +
> +		/* And make a suitable promise */
> +		if (vchan->is_dedicated)
> +			promise = generate_ddma_promise(chan, srcaddr, dstaddr,
> +							sg_dma_len(sg), sconfig);
> +		else
> +			promise = generate_ndma_promise(chan, srcaddr, dstaddr,
> +							sg_dma_len(sg), sconfig);
> +
> +		if (!promise)
> +			return NULL; /* TODO */

TODO what?

> +
> +		promise->cfg |= endpoints;
> +		promise->para = para;
> +
> +		/* Then add it to the contract */
> +		list_add_tail(&promise->list, &contract->demands);
> +	}
> +
> +	/*
> +	 * Once we've got all the promises ready, add the contract
> +	 * to the pending list on the vchan
> +	 */
> +	return vchan_tx_prep(&vchan->vc, &contract->vd, flags);
> +}
> +
> +static int sun4i_dma_terminate_all(struct sun4i_dma_vchan *vchan)
> +{
> +	struct sun4i_dma_pchan *pchan = vchan->pchan;
> +	LIST_HEAD(head);
> +	unsigned long flags, timeout;
> +	u32 d_busy = DDMA_CFG_LOADING | DDMA_CFG_BUSY;
> +	u32 n_busy = NDMA_CFG_LOADING;
> +
> +
> +	spin_lock_irqsave(&vchan->vc.lock, flags);
> +	vchan_get_all_descriptors(&vchan->vc, &head);
> +	spin_unlock_irqrestore(&vchan->vc.lock, flags);
> +
> +	/* If this vchan is operating, wait until it's no longer busy */
> +	if (pchan) {
> +		timeout = jiffies + msecs_to_jiffies(2000);
> +		if (pchan->is_dedicated) {
> +			while (readl(pchan->base + DDMA_CFG_REG) & d_busy)
> +				if (time_after(jiffies, timeout))
> +					return -ETIMEDOUT;
> +		} else {
> +			while (readl(pchan->base + NDMA_CFG_REG) & n_busy)
> +				if (time_after(jiffies, timeout))
> +					return -ETIMEDOUT;
> +		}
> +	}
> +
> +	spin_lock_irqsave(&vchan->vc.lock, flags);
> +	vchan_dma_desc_free_list(&vchan->vc, &head);
> +	spin_unlock_irqrestore(&vchan->vc.lock, flags);
> +
> +	return 0;
> +}
> +
> +static int sun4i_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
> +			     unsigned long arg)
> +{
> +	struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
> +	int ret = 0;
> +
> +	switch (cmd) {
> +	case DMA_RESUME:
> +	case DMA_PAUSE:
> +		ret = -EINVAL;
> +		break;
> +
> +	case DMA_TERMINATE_ALL:
> +		dev_dbg(chan2dev(chan), "Terminating everything on channel\n");
> +		ret = sun4i_dma_terminate_all(vchan);
> +		break;
> +
> +	case DMA_SLAVE_CONFIG:
> +		memcpy(&vchan->cfg, (void *)arg, sizeof(vchan->cfg));
> +		break;
> +
> +	default:
> +		ret = -ENXIO;
> +		break;
> +	}
> +
> +	return ret;
> +}
> +
> +static struct dma_chan *sun4i_dma_of_xlate(struct of_phandle_args *dma_spec,
> +					   struct of_dma *ofdma)
> +{
> +	struct sun4i_dma_dev *priv = ofdma->of_dma_data;
> +	struct sun4i_dma_vchan *vchan;
> +	struct dma_chan *chan;
> +	u8 is_dedicated = dma_spec->args[0];
> +	u8 endpoint = dma_spec->args[1];
> +
> +	/* Check if type is Normal or Dedicated */
> +	if (is_dedicated != 0 && is_dedicated != 1)
> +		return NULL;
> +
> +	/* Make sure the endpoint looks sane */
> +	if ((is_dedicated && endpoint >= DDMA_DRQ_TYPE_LIMIT) ||
> +	    (!is_dedicated && endpoint >= NDMA_DRQ_TYPE_LIMIT))
> +		return NULL;
> +
> +	chan = dma_get_any_slave_channel(&priv->slave);
> +	if (!chan)
> +		return NULL;
> +
> +	/* Assign the endpoint to the vchan */
> +	vchan = to_sun4i_dma_vchan(chan);
> +	vchan->is_dedicated = is_dedicated;
> +	vchan->endpoint = endpoint;
> +
> +	return chan;
> +}
> +
> +static enum dma_status sun4i_dma_tx_status(struct dma_chan *chan,
> +					   dma_cookie_t cookie,
> +					   struct dma_tx_state *state)
> +{
> +	struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
> +	struct sun4i_dma_pchan *pchan = vchan->pchan;
> +	struct sun4i_dma_contract *contract;
> +	struct sun4i_dma_promise *promise;
> +	struct virt_dma_desc *vd;
> +	unsigned long flags;
> +	enum dma_status ret;
> +	size_t bytes = 0;
> +
> +	ret = dma_cookie_status(chan, cookie, state);
> +	if (ret == DMA_COMPLETE)
> +		return ret;
> +
> +	spin_lock_irqsave(&vchan->vc.lock, flags);
> +	vd = vchan_find_desc(&vchan->vc, cookie);
> +	if (!vd) /* TODO */

TODO what?

> +		goto exit;
> +	contract = to_sun4i_dma_contract(vd);
> +
> +	list_for_each_entry(promise, &contract->demands, list) {
> +		bytes += promise->len;
> +	}

Useless brackets

> +	/*
> +	 * The hardware is configured to return the remaining byte
> +	 * quantity. If possible, replace the first listed element's
> +	 * full size with the actual remaining amount
> +	 */
> +	promise = list_first_entry_or_null(&contract->demands,
> +					   struct sun4i_dma_promise, list);
> +	if (promise && pchan) {
> +		bytes -= promise->len;
> +		if (pchan->is_dedicated)
> +			bytes += readl(pchan->base + DDMA_BYTE_COUNT_REG);
> +		else
> +			bytes += readl(pchan->base + NDMA_BYTE_COUNT_REG);
> +	}
> +
> +exit:
> +
> +	dma_set_residue(state, bytes);
> +	spin_unlock_irqrestore(&vchan->vc.lock, flags);
> +
> +	return ret;
> +}
> +
> +static void sun4i_dma_issue_pending(struct dma_chan *chan)
> +{
> +	struct sun4i_dma_dev *priv = to_sun4i_dma_dev(chan->device);
> +	struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&vchan->vc.lock, flags);
> +
> +	/*
> +	 * If there are pending transactions for this vchan, push one of
> +	 * them into the engine to get the ball rolling.
> +	 */
> +	if (vchan_issue_pending(&vchan->vc))
> +		execute_vchan_pending(priv, vchan);
> +
> +	spin_unlock_irqrestore(&vchan->vc.lock, flags);
> +}
> +
> +static irqreturn_t sun4i_dma_interrupt(int irq, void *dev_id)
> +{
> +	struct sun4i_dma_dev *priv = dev_id;
> +	struct sun4i_dma_pchan *pchans = priv->pchans, *pchan;
> +	struct sun4i_dma_vchan *vchan;
> +	struct sun4i_dma_contract *contract;
> +	unsigned long pendirq, irqs;
> +	int bit;
> +
> +	pendirq = readl_relaxed(priv->base + DMA_IRQ_PENDING_STATUS_REG);
> +	irqs = readl_relaxed(priv->base + DMA_IRQ_ENABLE_REG);
> +
> +	for_each_set_bit(bit, &pendirq, 32) {
> +		pchan = &pchans[bit >> 1];
> +		vchan = pchan->vchan;
> +		contract = vchan->contract;
> +
> +		/*
> +		 * Disable the IRQ and free the pchan if it's an end
> +		 * interrupt (odd bit)
> +		 */
> +		if (bit & 1) {
> +			spin_lock(&vchan->vc.lock);
> +			/*
> +			 * Move the promise into the completed list now that
> +			 * we're done with it
> +			 */
> +			list_del(&vchan->processing->list);
> +			list_add_tail(&vchan->processing->list, &contract->completed_demands);
> +			vchan->processing = NULL;
> +			vchan->pchan = NULL;
> +			spin_unlock(&vchan->vc.lock);
> +
> +			irqs &= ~BIT(bit);
> +			release_pchan(priv, pchan);
> +		}
> +	}
> +
> +	writel_relaxed(irqs, priv->base + DMA_IRQ_ENABLE_REG);
> +
> +	/* Writing 1 to the pending field will clear the pending interrupt */
> +	writel_relaxed(pendirq, priv->base + DMA_IRQ_PENDING_STATUS_REG);
> +
> +	return IRQ_WAKE_THREAD;
> +}
> +
> +static irqreturn_t sun4i_dma_submit_work(int irq, void *dev_id)
> +{
> +	struct sun4i_dma_dev *priv = dev_id;
> +	struct sun4i_dma_vchan *vchan;
> +	int i;
> +
> +	for (i = 0; i < DMA_NR_MAX_VCHANS; i++) {
> +		vchan = &priv->vchans[i];
> +		spin_lock_irq(&vchan->vc.lock);
> +		execute_vchan_pending(priv, vchan);
> +		spin_unlock_irq(&vchan->vc.lock);
> +	}
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static int sun4i_dma_probe(struct platform_device *pdev)
> +{
> +	struct sun4i_dma_dev *priv;
> +	struct resource *res;
> +	int i, j, ret;
> +
> +	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	priv->base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(priv->base))
> +		return PTR_ERR(priv->base);
> +
> +	priv->irq = platform_get_irq(pdev, 0);
> +	if (priv->irq < 0) {
> +		dev_err(&pdev->dev, "Cannot claim IRQ\n");
> +		return priv->irq;
> +	}
> +
> +	priv->clk = devm_clk_get(&pdev->dev, NULL);
> +	if (IS_ERR(priv->clk)) {
> +		dev_err(&pdev->dev, "No clock specified\n");
> +		return PTR_ERR(priv->clk);
> +	}
> +
> +	platform_set_drvdata(pdev, priv);
> +	spin_lock_init(&priv->lock);
> +
> +	dma_cap_zero(priv->slave.cap_mask);
> +	dma_cap_set(DMA_PRIVATE, priv->slave.cap_mask);
> +	dma_cap_set(DMA_MEMCPY, priv->slave.cap_mask);
> +	dma_cap_set(DMA_SLAVE, priv->slave.cap_mask);
> +
> +	INIT_LIST_HEAD(&priv->slave.channels);
> +	priv->slave.device_alloc_chan_resources	= sun4i_dma_alloc_chan_resources;
> +	priv->slave.device_free_chan_resources	= sun4i_dma_free_chan_resources;
> +	priv->slave.device_tx_status		= sun4i_dma_tx_status;
> +	priv->slave.device_issue_pending	= sun4i_dma_issue_pending;
> +	priv->slave.device_prep_slave_sg	= sun4i_dma_prep_slave_sg;
> +	priv->slave.device_prep_dma_memcpy	= sun4i_dma_prep_dma_memcpy;
> +	priv->slave.device_control		= sun4i_dma_control;
> +	priv->slave.chancnt			= DDMA_NR_MAX_VCHANS;
> +
> +	priv->slave.dev = &pdev->dev;
> +
> +	priv->pchans = devm_kcalloc(&pdev->dev, DMA_NR_MAX_CHANNELS,
> +				    sizeof(struct sun4i_dma_pchan), GFP_KERNEL);
> +	priv->vchans = devm_kcalloc(&pdev->dev, DMA_NR_MAX_VCHANS,
> +				    sizeof(struct sun4i_dma_vchan), GFP_KERNEL);
> +	if (!priv->vchans || !priv->pchans)
> +		return -ENOMEM;
> +
> +	/*
> +	 * [0..NDMA_NR_MAX_CHANNELS) are normal pchans, and
> +	 * [NDMA_NR_MAX_CHANNELS..DMA_NR_MAX_CHANNELS) are dedicated ones
> +	 */
> +	for (i = 0; i < NDMA_NR_MAX_CHANNELS; i++)
> +		priv->pchans[i].base = priv->base + NDMA_CHANNEL_REG_BASE(i);
> +
> +	for (j = 0; i < DMA_NR_MAX_CHANNELS; i++, j++) {
> +		priv->pchans[i].base = priv->base + DDMA_CHANNEL_REG_BASE(j);
> +		priv->pchans[i].is_dedicated = 1;
> +	}
> +
> +	for (i = 0; i < DMA_NR_MAX_VCHANS; i++) {
> +		struct sun4i_dma_vchan *vchan = &priv->vchans[i];
> +
> +		spin_lock_init(&vchan->vc.lock);
> +		vchan->vc.desc_free = sun4i_dma_free_contract;
> +		vchan_init(&vchan->vc, &priv->slave);
> +	}
> +
> +	ret = clk_prepare_enable(priv->clk);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Couldn't enable the clock\n");
> +		return ret;
> +	}
> +
> +	ret = devm_request_threaded_irq(&pdev->dev, priv->irq,
> +					sun4i_dma_interrupt,
> +					sun4i_dma_submit_work,
> +					0, dev_name(&pdev->dev), priv);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Cannot request IRQ\n");
> +		goto err_clk_disable;
> +	}
> +
> +	ret = dma_async_device_register(&priv->slave);
> +	if (ret) {
> +		dev_warn(&pdev->dev, "Failed to register DMA engine device\n");
> +		goto err_clk_disable;
> +	}
> +
> +	ret = of_dma_controller_register(pdev->dev.of_node, sun4i_dma_of_xlate,
> +					 priv);
> +	if (ret) {
> +		dev_err(&pdev->dev, "of_dma_controller_register failed\n");
> +		goto err_dma_unregister;
> +	}
> +
> +	dev_dbg(&pdev->dev, "Successfully probed SUN4I_DMA\n");
> +
> +	return 0;
> +
> +err_dma_unregister:
> +	dma_async_device_unregister(&priv->slave);
> +err_clk_disable:
> +	clk_disable_unprepare(priv->clk);
> +	return ret;
> +}
> +
> +static int sun4i_dma_remove(struct platform_device *pdev)
> +{
> +	struct sun4i_dma_dev *priv = platform_get_drvdata(pdev);
> +
> +	/* Disable IRQ so no more work is scheduled */
> +	disable_irq(priv->irq);
> +
> +	of_dma_controller_free(pdev->dev.of_node);
> +	dma_async_device_unregister(&priv->slave);
> +
> +	clk_disable_unprepare(priv->clk);
> +
> +	return 0;
> +}
> +
> +static struct of_device_id sun4i_dma_match[] = {
> +	{ .compatible = "allwinner,sun4i-a10-dma" },
> +	{ /* sentinel */ },
> +};
> +
> +static struct platform_driver sun4i_dma_driver = {
> +	.probe	= sun4i_dma_probe,
> +	.remove	= sun4i_dma_remove,
> +	.driver	= {
> +		.name		= "sun4i-dma",
> +		.of_match_table	= sun4i_dma_match,
> +	},
> +};
> +
> +module_platform_driver(sun4i_dma_driver);
> +
> +MODULE_DESCRIPTION("Allwinner A10 Dedicated DMA Controller Driver");
> +MODULE_AUTHOR("Emilio L?pez <emilio@elopez.com.ar>");
> +MODULE_LICENSE("GPL");
> -- 
> 2.0.1

Thanks!

Maxime


-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v2 1/8] dma: sun4i: Add support for the DMA engine on sun[457]i SoCs

[Emilio López]

Hi Maxime,

El 17/07/14 17:56, Maxime Ripard escribi?:
> On Sun, Jul 06, 2014 at 01:05:08AM -0300, Emilio L?pez wrote:
>> This patch adds support for the DMA engine present on Allwinner A10,
>> A13, A10S and A20 SoCs. This engine has two kinds of channels: normal
>> and dedicated. The main difference is in the mode of operation;
>> while a single normal channel may be operating at any given time,
>> dedicated channels may operate simultaneously provided there is no
>> overlap of source or destination.
>>
>> Hardware documentation can be found on A10 User Manual (section 12), A13
>> User Manual (section 14) and A20 User Manual (section 1.12)
>>
>> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
>> ---
>>(...)
>>
>> +config SUN4I_DMA
>> +	tristate "Allwinner A10/A10S/A13/A20 DMA support"
>
> I'm not that fond of having an exhaustive list here. If some other SoC
> we didn't thought of or get a new SoC that uses this controller, this
> list won't be exhaustive anymore, which is even worse.
>
> Just mention the A10.

Ok

>> +	depends on (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || (COMPILE_TEST && OF && ARM))
>
> This pretty much defeats the purpose of COMPILE_TEST

QCOM_BAM_DMA does it that way; it's better to get some coverage than 
none I guess?

>
>> +	select DMA_ENGINE
>> +	select DMA_OF
>> +	select DMA_VIRTUAL_CHANNELS
>
> I guess you could default to y for the SoCs where it's relevant.

Sounds good.

>
>> +	help
>> +	  Enable support for the DMA controller present in the sun4i,
>> +	  sun5i and sun7i Allwinner ARM SoCs.
>> +
(...)
>> +
>> +/** Normal DMA register values **/
>> +
>> +/* Normal DMA source/destination data request type values */
>> +#define NDMA_DRQ_TYPE_SDRAM			0x16
>> +#define NDMA_DRQ_TYPE_LIMIT			(0x1F + 1)
>
> Hmmm, I'm unsure what this is about... What is it supposed to do, and
> how is it different from BIT(5) ?

if (val < NDMA_DRQ_TYPE_LIMIT)
	/* valid value */
else
	/* invalid value */

0x1F is the last valid value

(...)
>> +
>> +static void set_pchan_interrupt(struct sun4i_dma_dev *priv,
>> +				struct sun4i_dma_pchan *pchan,
>> +				int half, int end)
>> +{
>> +	u32 reg = readl_relaxed(priv->base + DMA_IRQ_ENABLE_REG);
>> +	int pchan_number = pchan - priv->pchans;
>> +
>> +	if (half)
>> +		reg |= BIT(pchan_number * 2);
>> +	else
>> +		reg &= ~BIT(pchan_number * 2);
>> +
>> +	if (end)
>> +		reg |= BIT(pchan_number * 2 + 1);
>> +	else
>> +		reg &= ~BIT(pchan_number * 2 + 1);
>> +
>> +	writel_relaxed(reg, priv->base + DMA_IRQ_ENABLE_REG);
>
> I don't see any interrupts here.

Hm?

> Is this suppose to be called with a
> lock taken? If so, it should be mentionned in some comment.

Good point, this should probably take a lock, I'll get it fixed.

(...)
>> +{
>> +	struct sun4i_dma_contract *contract = to_sun4i_dma_contract(vd);
>> +	struct sun4i_dma_promise *promise;
>> +
>> +	/* Free all the demands and completed demands */
>> +	list_for_each_entry(promise, &contract->demands, list) {
>> +		kfree(promise);
>> +	}
>> +
>> +	list_for_each_entry(promise, &contract->completed_demands, list) {
>> +		kfree(promise);
>> +	}
>>
>
> Those brackets are useless.

Indeed, dropped.

>> +	for_each_sg(sgl, sg, sg_len, i) {
>> +		/* Figure out addresses */
>> +		if (dir == DMA_MEM_TO_DEV) {
>> +			srcaddr = sg_dma_address(sg);
>> +			dstaddr = sconfig->dst_addr;
>> +		} else {
>> +			srcaddr = sconfig->src_addr;
>> +			dstaddr = sg_dma_address(sg);
>> +		}
>> +
>> +		/* TODO: should this be configurable? */
>> +		para = DDMA_MAGIC_SPI_PARAMETERS;
>
> What is it? Is it supposed to change from one client device to
> another?

These are the magic DMA engine timings that keep SPI going. I haven't 
seen any interface on DMAEngine to configure timings, and so far they 
seem to work for everything we support, so I've kept them here. I don't 
know if other devices need different timings because, as usual, we only 
have the "para" bitfield meanings, but no comment on what the values 
should be when doing a certain operation :|

>> +
>> +		/* And make a suitable promise */
>> +		if (vchan->is_dedicated)
>> +			promise = generate_ddma_promise(chan, srcaddr, dstaddr,
>> +							sg_dma_len(sg), sconfig);
>> +		else
>> +			promise = generate_ndma_promise(chan, srcaddr, dstaddr,
>> +							sg_dma_len(sg), sconfig);
>> +
>> +		if (!promise)
>> +			return NULL; /* TODO */
>
> TODO what?

/* TODO: properly kfree the promises generated in the loop */

(...)
>> +static enum dma_status sun4i_dma_tx_status(struct dma_chan *chan,
>> +					   dma_cookie_t cookie,
>> +					   struct dma_tx_state *state)
>> +{
>> +	struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
>> +	struct sun4i_dma_pchan *pchan = vchan->pchan;
>> +	struct sun4i_dma_contract *contract;
>> +	struct sun4i_dma_promise *promise;
>> +	struct virt_dma_desc *vd;
>> +	unsigned long flags;
>> +	enum dma_status ret;
>> +	size_t bytes = 0;
>> +
>> +	ret = dma_cookie_status(chan, cookie, state);
>> +	if (ret == DMA_COMPLETE)
>> +		return ret;
>> +
>> +	spin_lock_irqsave(&vchan->vc.lock, flags);
>> +	vd = vchan_find_desc(&vchan->vc, cookie);
>> +	if (!vd) /* TODO */
>
> TODO what?
>

/* TODO: remove the TODO */

>> +		goto exit;
>> +	contract = to_sun4i_dma_contract(vd);
>> +
>> +	list_for_each_entry(promise, &contract->demands, list) {
>> +		bytes += promise->len;
>> +	}
>
> Useless brackets

Dropped

Thanks for taking the time to review this!

Cheers,

Emilio

[PATCH v2 1/8] dma: sun4i: Add support for the DMA engine on sun[457]i SoCs

[Maxime Ripard]

Hi,

On Thu, Jul 17, 2014 at 06:45:00PM -0300, Emilio L?pez wrote:
> >>+	depends on (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || (COMPILE_TEST && OF && ARM))
> >
> >This pretty much defeats the purpose of COMPILE_TEST
> 
> QCOM_BAM_DMA does it that way; it's better to get some coverage than
> none I guess?

You'll get that kind of coverage with multi_v7 already, so that looks
quite redundant.

> >>+	help
> >>+	  Enable support for the DMA controller present in the sun4i,
> >>+	  sun5i and sun7i Allwinner ARM SoCs.
> >>+
> (...)
> >>+
> >>+/** Normal DMA register values **/
> >>+
> >>+/* Normal DMA source/destination data request type values */
> >>+#define NDMA_DRQ_TYPE_SDRAM			0x16
> >>+#define NDMA_DRQ_TYPE_LIMIT			(0x1F + 1)
> >
> >Hmmm, I'm unsure what this is about... What is it supposed to do, and
> >how is it different from BIT(5) ?
> 
> if (val < NDMA_DRQ_TYPE_LIMIT)
> 	/* valid value */
> else
> 	/* invalid value */
> 
> 0x1F is the last valid value

Ok.

> >>+
> >>+static void set_pchan_interrupt(struct sun4i_dma_dev *priv,
> >>+				struct sun4i_dma_pchan *pchan,
> >>+				int half, int end)
> >>+{
> >>+	u32 reg = readl_relaxed(priv->base + DMA_IRQ_ENABLE_REG);
> >>+	int pchan_number = pchan - priv->pchans;
> >>+
> >>+	if (half)
> >>+		reg |= BIT(pchan_number * 2);
> >>+	else
> >>+		reg &= ~BIT(pchan_number * 2);
> >>+
> >>+	if (end)
> >>+		reg |= BIT(pchan_number * 2 + 1);
> >>+	else
> >>+		reg &= ~BIT(pchan_number * 2 + 1);
> >>+
> >>+	writel_relaxed(reg, priv->base + DMA_IRQ_ENABLE_REG);
> >
> >I don't see any interrupts here.
> 
> Hm?

I'm not sure, but I think I meant spinlocks, it doesn't make much
sense otherwise.

> >>+	for_each_sg(sgl, sg, sg_len, i) {
> >>+		/* Figure out addresses */
> >>+		if (dir == DMA_MEM_TO_DEV) {
> >>+			srcaddr = sg_dma_address(sg);
> >>+			dstaddr = sconfig->dst_addr;
> >>+		} else {
> >>+			srcaddr = sconfig->src_addr;
> >>+			dstaddr = sg_dma_address(sg);
> >>+		}
> >>+
> >>+		/* TODO: should this be configurable? */
> >>+		para = DDMA_MAGIC_SPI_PARAMETERS;
> >
> >What is it? Is it supposed to change from one client device to
> >another?
> 
> These are the magic DMA engine timings that keep SPI going. I
> haven't seen any interface on DMAEngine to configure timings, and so
> far they seem to work for everything we support, so I've kept them
> here. I don't know if other devices need different timings because,
> as usual, we only have the "para" bitfield meanings, but no comment
> on what the values should be when doing a certain operation :|

If it works for everything you tested so far, I guess you can leave it
that way, only adding what you just replied to the TODO.

> >>+static enum dma_status sun4i_dma_tx_status(struct dma_chan *chan,
> >>+					   dma_cookie_t cookie,
> >>+					   struct dma_tx_state *state)
> >>+{
> >>+	struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
> >>+	struct sun4i_dma_pchan *pchan = vchan->pchan;
> >>+	struct sun4i_dma_contract *contract;
> >>+	struct sun4i_dma_promise *promise;
> >>+	struct virt_dma_desc *vd;
> >>+	unsigned long flags;
> >>+	enum dma_status ret;
> >>+	size_t bytes = 0;
> >>+
> >>+	ret = dma_cookie_status(chan, cookie, state);
> >>+	if (ret == DMA_COMPLETE)
> >>+		return ret;
> >>+
> >>+	spin_lock_irqsave(&vchan->vc.lock, flags);
> >>+	vd = vchan_find_desc(&vchan->vc, cookie);
> >>+	if (!vd) /* TODO */
> >
> >TODO what?
> >
> 
> /* TODO: remove the TODO */

:)

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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