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* [PATCH] clocksource: sirf: disable counter before re-setting it
@ 2014-07-23 14:03 Barry Song
  2014-08-18  9:24 ` Barry Song
  0 siblings, 1 reply; 3+ messages in thread
From: Barry Song @ 2014-07-23 14:03 UTC (permalink / raw)
  To: linux-arm-kernel

From: Hao Liu <Hao.Liu@csr.com>

according to HW spec, we have to disable counter before setting
it, if we don't this, in pressure test, sometimes the timer might
not generate interrupt any more.

and this patch also fixes a typo for register set by changing 0x7
to 0x3. 0x7 is loop mode in HW, but here we are using oneshot 0x3.

Signed-off-by: Hao Liu <Hao.Liu@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
---
 drivers/clocksource/timer-marco.c |    5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/clocksource/timer-marco.c b/drivers/clocksource/timer-marco.c
index 330e930..caf7a20 100644
--- a/drivers/clocksource/timer-marco.c
+++ b/drivers/clocksource/timer-marco.c
@@ -63,7 +63,7 @@ static inline void sirfsoc_timer_count_disable(int idx)
 /* enable count and interrupt */
 static inline void sirfsoc_timer_count_enable(int idx)
 {
-	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7,
+	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3,
 		sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
 }
 
@@ -103,6 +103,9 @@ static int sirfsoc_timer_set_next_event(unsigned long delta,
 {
 	int cpu = smp_processor_id();
 
+	/* disable timer first, then modify the related registers */
+	sirfsoc_timer_count_disable(cpu);
+
 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
 		4 * cpu);
 	writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 3+ messages in thread

* [PATCH] clocksource: sirf: disable counter before re-setting it
  2014-07-23 14:03 [PATCH] clocksource: sirf: disable counter before re-setting it Barry Song
@ 2014-08-18  9:24 ` Barry Song
  2014-08-21  1:50   ` Daniel Lezcano
  0 siblings, 1 reply; 3+ messages in thread
From: Barry Song @ 2014-08-18  9:24 UTC (permalink / raw)
  To: linux-arm-kernel

2014-07-23 22:03 GMT+08:00 Barry Song <21cnbao@gmail.com>:
> From: Hao Liu <Hao.Liu@csr.com>
>
> according to HW spec, we have to disable counter before setting
> it, if we don't this, in pressure test, sometimes the timer might
> not generate interrupt any more.
>
> and this patch also fixes a typo for register set by changing 0x7
> to 0x3. 0x7 is loop mode in HW, but here we are using oneshot 0x3.
>
> Signed-off-by: Hao Liu <Hao.Liu@csr.com>
> Signed-off-by: Barry Song <Baohua.Song@csr.com>
> ---

Hi Daniel,
did you miss this one?

>  drivers/clocksource/timer-marco.c |    5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clocksource/timer-marco.c b/drivers/clocksource/timer-marco.c
> index 330e930..caf7a20 100644
> --- a/drivers/clocksource/timer-marco.c
> +++ b/drivers/clocksource/timer-marco.c
> @@ -63,7 +63,7 @@ static inline void sirfsoc_timer_count_disable(int idx)
>  /* enable count and interrupt */
>  static inline void sirfsoc_timer_count_enable(int idx)
>  {
> -       writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7,
> +       writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3,
>                 sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
>  }
>
> @@ -103,6 +103,9 @@ static int sirfsoc_timer_set_next_event(unsigned long delta,
>  {
>         int cpu = smp_processor_id();
>
> +       /* disable timer first, then modify the related registers */
> +       sirfsoc_timer_count_disable(cpu);
> +
>         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
>                 4 * cpu);
>         writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
> --
> 1.7.9.5
>

-barry

^ permalink raw reply	[flat|nested] 3+ messages in thread

* [PATCH] clocksource: sirf: disable counter before re-setting it
  2014-08-18  9:24 ` Barry Song
@ 2014-08-21  1:50   ` Daniel Lezcano
  0 siblings, 0 replies; 3+ messages in thread
From: Daniel Lezcano @ 2014-08-21  1:50 UTC (permalink / raw)
  To: linux-arm-kernel

On 08/18/2014 11:24 AM, Barry Song wrote:
> 2014-07-23 22:03 GMT+08:00 Barry Song <21cnbao@gmail.com>:
>> From: Hao Liu <Hao.Liu@csr.com>
>>
>> according to HW spec, we have to disable counter before setting
>> it, if we don't this, in pressure test, sometimes the timer might
>> not generate interrupt any more.
>>
>> and this patch also fixes a typo for register set by changing 0x7
>> to 0x3. 0x7 is loop mode in HW, but here we are using oneshot 0x3.
>>
>> Signed-off-by: Hao Liu <Hao.Liu@csr.com>
>> Signed-off-by: Barry Song <Baohua.Song@csr.com>
>> ---
>
> Hi Daniel,
> did you miss this one?

Nope, I have it locally. Let me review it in details next week when I 
return from the kernel summit.

Thanks

   -- Daniel


>
>>   drivers/clocksource/timer-marco.c |    5 ++++-
>>   1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clocksource/timer-marco.c b/drivers/clocksource/timer-marco.c
>> index 330e930..caf7a20 100644
>> --- a/drivers/clocksource/timer-marco.c
>> +++ b/drivers/clocksource/timer-marco.c
>> @@ -63,7 +63,7 @@ static inline void sirfsoc_timer_count_disable(int idx)
>>   /* enable count and interrupt */
>>   static inline void sirfsoc_timer_count_enable(int idx)
>>   {
>> -       writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7,
>> +       writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3,
>>                  sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
>>   }
>>
>> @@ -103,6 +103,9 @@ static int sirfsoc_timer_set_next_event(unsigned long delta,
>>   {
>>          int cpu = smp_processor_id();
>>
>> +       /* disable timer first, then modify the related registers */
>> +       sirfsoc_timer_count_disable(cpu);
>> +
>>          writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
>>                  4 * cpu);
>>          writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
>> --
>> 1.7.9.5
>>
>
> -barry
>


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^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2014-08-21  1:50 UTC | newest]

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2014-07-23 14:03 [PATCH] clocksource: sirf: disable counter before re-setting it Barry Song
2014-08-18  9:24 ` Barry Song
2014-08-21  1:50   ` Daniel Lezcano

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