[PATCH 1/4] pinctrl: rockchip: Set wake_enabled

[PATCH 1/4] pinctrl: rockchip: Set wake_enabled

[Doug Anderson]

The rockchip pinctrl driver uses irq_gc_set_wake() but doesn't setup
the .wake_enabled member.  That means that we can never actually use a
pin for wakeup.  When "irq_set_irq_wake()" tries to call through it
will always get a failure from set_irq_wake_real() and will then set
wake_depth to 0.  Assuming you can resume you'll later get an error
message about "Unbalanced IRQ x wake disable".

Signed-off-by: Doug Anderson <dianders@chromium.org>
---
 drivers/pinctrl/pinctrl-rockchip.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 016f457..230d8f3 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1563,6 +1563,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
 		gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
 		gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
 		gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
+		gc->wake_enabled = IRQ_MSK(bank->nr_pins);
 
 		irq_set_handler_data(bank->irq, bank);
 		irq_set_chained_handler(bank->irq, rockchip_irq_demux);
-- 
2.1.0.rc2.206.gedb03e5

[PATCH 2/4] pinctrl: rockchip: Don't call pinctrl_gpio_direction_output() in pin_config_set()

[Doug Anderson]

The Rockchip pinctrl driver was calling
rockchip_gpio_direction_output() in the pin_config_set() callback.
This was just a shortcut for:
* rockchip_gpio_set()
* pinctrl_gpio_direction_output()

Unfortunately it's not so good to call pinctrl_gpio_direction_output()
from pin_config_set().  Specifically when initting hogs you'll get an
error.

Let's refactor a little so we can call
_rockchip_pmx_gpio_set_direction() directly.

Signed-off-by: Doug Anderson <dianders@chromium.org>
---
 drivers/pinctrl/pinctrl-rockchip.c | 42 +++++++++++++++++++++++---------------
 1 file changed, 26 insertions(+), 16 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 230d8f3..65efb88 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -856,22 +856,16 @@ static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
  * function called from the gpiolib interface).
  */
-static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
-					      struct pinctrl_gpio_range *range,
-					      unsigned offset, bool input)
+static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *gc,
+					    unsigned offset, bool input)
 {
-	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 	struct rockchip_pin_bank *bank;
-	struct gpio_chip *chip;
 	int pin, ret;
+	unsigned long flags;
 	u32 data;
 
-	chip = range->gc;
-	bank = gc_to_pin_bank(chip);
-	pin = offset - chip->base;
-
-	dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
-		 offset, range->name, pin, input ? "input" : "output");
+	bank = gc_to_pin_bank(gc);
+	pin = offset - gc->base;
 
 	ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
 	if (ret < 0)
@@ -888,6 +882,22 @@ static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 	return 0;
 }
 
+static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
+					      struct pinctrl_gpio_range *range,
+					      unsigned offset, bool input)
+{
+	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+	struct gpio_chip *chip;
+	int pin;
+
+	chip = range->gc;
+	pin = offset - chip->base;
+	dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
+		 offset, range->name, pin, input ? "input" : "output");
+
+	return _rockchip_pmx_gpio_set_direction(range->gc, offset, input);
+}
+
 static const struct pinmux_ops rockchip_pmx_ops = {
 	.get_functions_count	= rockchip_pmx_get_funcs_count,
 	.get_function_name	= rockchip_pmx_get_func_name,
@@ -917,8 +927,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
 	return false;
 }
 
-static int rockchip_gpio_direction_output(struct gpio_chip *gc,
-					  unsigned offset, int value);
+static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
 
 /* set the pin config settings for a specified pin */
@@ -959,9 +968,10 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 				return rc;
 			break;
 		case PIN_CONFIG_OUTPUT:
-			rc = rockchip_gpio_direction_output(&bank->gpio_chip,
-							    pin - bank->pin_base,
-							    arg);
+			rockchip_gpio_set(&bank->gpio_chip,
+					  pin - bank->pin_base, arg);
+			rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
+					  pin - bank->pin_base, false);
 			if (rc)
 				return rc;
 			break;
-- 
2.1.0.rc2.206.gedb03e5

[PATCH 3/4] pinctrl: rockchip: Parse pin groups before calling pinctrl_register()

[Doug Anderson]

Just like in (529301c pinctrl: samsung: Parse pin groups before
calling pinctrl_register()), Rockchip also needs to parse pin groups
earlier to make hogs work.

Signed-off-by: Doug Anderson <dianders@chromium.org>
---
 drivers/pinctrl/pinctrl-rockchip.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 65efb88..14a5683 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1263,6 +1263,10 @@ static int rockchip_pinctrl_register(struct platform_device *pdev,
 		}
 	}
 
+	ret = rockchip_pinctrl_parse_dt(pdev, info);
+	if (ret)
+		return ret;
+
 	info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
 	if (!info->pctl_dev) {
 		dev_err(&pdev->dev, "could not register pinctrl driver\n");
@@ -1280,12 +1284,6 @@ static int rockchip_pinctrl_register(struct platform_device *pdev,
 		pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
 	}
 
-	ret = rockchip_pinctrl_parse_dt(pdev, info);
-	if (ret) {
-		pinctrl_unregister(info->pctl_dev);
-		return ret;
-	}
-
 	return 0;
 }
 
-- 
2.1.0.rc2.206.gedb03e5

[PATCH 4/4] pinctrl: rockchip: Protect read-modify-write with the spinlock

[Doug Anderson]

There were a few instances where the rockchip pinctrl driver would do
read-modify-write with no spinlock.  Add a spinlock for these cases.

Signed-off-by: Doug Anderson <dianders@chromium.org>
---
 drivers/pinctrl/pinctrl-rockchip.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 14a5683..669e5e8 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -871,6 +871,8 @@ static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *gc,
 	if (ret < 0)
 		return ret;
 
+	spin_lock_irqsave(&bank->slock, flags);
+
 	data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
 	/* set bit to 1 for output, 0 for input */
 	if (!input)
@@ -879,6 +881,8 @@ static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *gc,
 		data &= ~BIT(pin);
 	writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
 
+	spin_unlock_irqrestore(&bank->slock, flags);
+
 	return 0;
 }
 
@@ -1395,6 +1399,7 @@ static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
 	u32 polarity = 0, data = 0;
 	u32 pend;
 	bool edge_changed = false;
+	unsigned long flags;
 
 	dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
 
@@ -1440,10 +1445,14 @@ static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
 
 	if (bank->toggle_edge_mode && edge_changed) {
 		/* Interrupt params should only be set with ints disabled */
+		spin_lock_irqsave(&bank->slock, flags);
+
 		data = readl_relaxed(bank->reg_base + GPIO_INTEN);
 		writel_relaxed(0, bank->reg_base + GPIO_INTEN);
 		writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
 		writel(data, bank->reg_base + GPIO_INTEN);
+
+		spin_unlock_irqrestore(&bank->slock, flags);
 	}
 
 	chained_irq_exit(chip, desc);
@@ -1457,6 +1466,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
 	u32 polarity;
 	u32 level;
 	u32 data;
+	unsigned long flags;
 	int ret;
 
 	/* make sure the pin is configured as gpio input */
@@ -1464,15 +1474,20 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
 	if (ret < 0)
 		return ret;
 
+	spin_lock_irqsave(&bank->slock, flags);
+
 	data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
 	data &= ~mask;
 	writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
 
+	spin_unlock_irqrestore(&bank->slock, flags);
+
 	if (type & IRQ_TYPE_EDGE_BOTH)
 		__irq_set_handler_locked(d->irq, handle_edge_irq);
 	else
 		__irq_set_handler_locked(d->irq, handle_level_irq);
 
+	spin_lock_irqsave(&bank->slock, flags);
 	irq_gc_lock(gc);
 
 	level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
@@ -1522,6 +1537,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
 	writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
 
 	irq_gc_unlock(gc);
+	spin_unlock_irqrestore(&bank->slock, flags);
 
 	return 0;
 }
-- 
2.1.0.rc2.206.gedb03e5

[PATCH 4/4] pinctrl: rockchip: Protect read-modify-write with the spinlock

[Doug Anderson]

Hi,

On Mon, Oct 20, 2014 at 4:27 PM, Doug Anderson <dianders@chromium.org> wrote:
> @@ -1464,15 +1474,20 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
>         if (ret < 0)
>                 return ret;
>
> +       spin_lock_irqsave(&bank->slock, flags);
> +
>         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
>         data &= ~mask;
>         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
>
> +       spin_unlock_irqrestore(&bank->slock, flags);
> +
>         if (type & IRQ_TYPE_EDGE_BOTH)
>                 __irq_set_handler_locked(d->irq, handle_edge_irq);
>         else
>                 __irq_set_handler_locked(d->irq, handle_level_irq);
>
> +       spin_lock_irqsave(&bank->slock, flags);
>         irq_gc_lock(gc);
>
>         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
> @@ -1522,6 +1537,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
>         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
>
>         irq_gc_unlock(gc);
> +       spin_unlock_irqrestore(&bank->slock, flags);

I just reviewed this again myself and I realized that there was an
error path case that I missed.  I'll plan to spin tomorrow and include
any extra feedback people have.

I'll also note that I'd love any extra scrutiny people have on this
patch.  I'm submitting it totally based on code inspection and am
nowhere near an expert on this driver.  I mostly just looked for all
of the read/modify/wites using writel and added the lock...

-Doug

[PATCH 1/4] pinctrl: rockchip: Set wake_enabled

[Chris Zhong]

Tested-by: Chris Zhong <zyw@rock-chips.com>

On 10/20/2014 04:27 PM, Doug Anderson wrote:
> The rockchip pinctrl driver uses irq_gc_set_wake() but doesn't setup
> the .wake_enabled member.  That means that we can never actually use a
> pin for wakeup.  When "irq_set_irq_wake()" tries to call through it
> will always get a failure from set_irq_wake_real() and will then set
> wake_depth to 0.  Assuming you can resume you'll later get an error
> message about "Unbalanced IRQ x wake disable".
>
> Signed-off-by: Doug Anderson <dianders@chromium.org>
> ---
>   drivers/pinctrl/pinctrl-rockchip.c | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
> index 016f457..230d8f3 100644
> --- a/drivers/pinctrl/pinctrl-rockchip.c
> +++ b/drivers/pinctrl/pinctrl-rockchip.c
> @@ -1563,6 +1563,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
>   		gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
>   		gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
>   		gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
> +		gc->wake_enabled = IRQ_MSK(bank->nr_pins);
>   
>   		irq_set_handler_data(bank->irq, bank);
>   		irq_set_chained_handler(bank->irq, rockchip_irq_demux);

[PATCH 2/4] pinctrl: rockchip: Don't call pinctrl_gpio_direction_output() in pin_config_set()

[Chris Zhong]

On 10/20/2014 04:27 PM, Doug Anderson wrote:
> The Rockchip pinctrl driver was calling
> rockchip_gpio_direction_output() in the pin_config_set() callback.
> This was just a shortcut for:
> * rockchip_gpio_set()
> * pinctrl_gpio_direction_output()
>
> Unfortunately it's not so good to call pinctrl_gpio_direction_output()
> from pin_config_set().  Specifically when initting hogs you'll get an
> error.
>
> Let's refactor a little so we can call
> _rockchip_pmx_gpio_set_direction() directly.
>
> Signed-off-by: Doug Anderson <dianders@chromium.org>
> ---
>   drivers/pinctrl/pinctrl-rockchip.c | 42 +++++++++++++++++++++++---------------
>   1 file changed, 26 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
> index 230d8f3..65efb88 100644
> --- a/drivers/pinctrl/pinctrl-rockchip.c
> +++ b/drivers/pinctrl/pinctrl-rockchip.c
> @@ -856,22 +856,16 @@ static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
>    * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
>    * function called from the gpiolib interface).
>    */
> -static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
> -					      struct pinctrl_gpio_range *range,
> -					      unsigned offset, bool input)
> +static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *gc,
> +					    unsigned offset, bool input)
>   {
> -	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
>   	struct rockchip_pin_bank *bank;
> -	struct gpio_chip *chip;
>   	int pin, ret;
> +	unsigned long flags;
>   	u32 data;
>   
> -	chip = range->gc;
> -	bank = gc_to_pin_bank(chip);
> -	pin = offset - chip->base;
> -
> -	dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
> -		 offset, range->name, pin, input ? "input" : "output");
> +	bank = gc_to_pin_bank(gc);
> +	pin = offset - gc->base;
>   
>   	ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
>   	if (ret < 0)
> @@ -888,6 +882,22 @@ static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
>   	return 0;
>   }
>   
> +static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
> +					      struct pinctrl_gpio_range *range,
> +					      unsigned offset, bool input)
> +{
> +	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +	struct gpio_chip *chip;
> +	int pin;
> +
> +	chip = range->gc;
> +	pin = offset - chip->base;
> +	dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
> +		 offset, range->name, pin, input ? "input" : "output");
> +
> +	return _rockchip_pmx_gpio_set_direction(range->gc, offset, input);
> +}
> +
>   static const struct pinmux_ops rockchip_pmx_ops = {
>   	.get_functions_count	= rockchip_pmx_get_funcs_count,
>   	.get_function_name	= rockchip_pmx_get_func_name,
> @@ -917,8 +927,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
>   	return false;
>   }
>   
> -static int rockchip_gpio_direction_output(struct gpio_chip *gc,
> -					  unsigned offset, int value);
> +static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
>   static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
>   
>   /* set the pin config settings for a specified pin */
> @@ -959,9 +968,10 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
>   				return rc;
>   			break;
>   		case PIN_CONFIG_OUTPUT:
> -			rc = rockchip_gpio_direction_output(&bank->gpio_chip,
> -							    pin - bank->pin_base,
> -							    arg);
> +			rockchip_gpio_set(&bank->gpio_chip,
> +					  pin - bank->pin_base, arg);
> +			rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
> +					  pin - bank->pin_base, false);
>   			if (rc)
>   				return rc;
>   			break;
Tested-by: Chris Zhong <zyw@rock-chips.com>

[PATCH 3/4] pinctrl: rockchip: Parse pin groups before calling pinctrl_register()

[Chris Zhong]

On 10/20/2014 04:27 PM, Doug Anderson wrote:
> Just like in (529301c pinctrl: samsung: Parse pin groups before
> calling pinctrl_register()), Rockchip also needs to parse pin groups
> earlier to make hogs work.
>
> Signed-off-by: Doug Anderson <dianders@chromium.org>
> ---
>   drivers/pinctrl/pinctrl-rockchip.c | 10 ++++------
>   1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
> index 65efb88..14a5683 100644
> --- a/drivers/pinctrl/pinctrl-rockchip.c
> +++ b/drivers/pinctrl/pinctrl-rockchip.c
> @@ -1263,6 +1263,10 @@ static int rockchip_pinctrl_register(struct platform_device *pdev,
>   		}
>   	}
>   
> +	ret = rockchip_pinctrl_parse_dt(pdev, info);
> +	if (ret)
> +		return ret;
> +
>   	info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
>   	if (!info->pctl_dev) {
>   		dev_err(&pdev->dev, "could not register pinctrl driver\n");
> @@ -1280,12 +1284,6 @@ static int rockchip_pinctrl_register(struct platform_device *pdev,
>   		pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
>   	}
>   
> -	ret = rockchip_pinctrl_parse_dt(pdev, info);
> -	if (ret) {
> -		pinctrl_unregister(info->pctl_dev);
> -		return ret;
> -	}
> -
>   	return 0;
>   }
>   

Tested-by: Chris Zhong <zyw@rock-chips.com>

[PATCH 2/4] pinctrl: rockchip: Don't call pinctrl_gpio_direction_output() in pin_config_set()

[Doug Anderson]

Hi,

On Mon, Oct 20, 2014 at 4:27 PM, Doug Anderson <dianders@chromium.org> wrote:
> @@ -959,9 +968,10 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
>                                 return rc;
>                         break;
>                 case PIN_CONFIG_OUTPUT:
> -                       rc = rockchip_gpio_direction_output(&bank->gpio_chip,
> -                                                           pin - bank->pin_base,
> -                                                           arg);
> +                       rockchip_gpio_set(&bank->gpio_chip,
> +                                         pin - bank->pin_base, arg);
> +                       rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
> +                                         pin - bank->pin_base, false);

I think something here is not quite right.  I did more testing today
and noticed that I'm getting failures in some cases.  I think I've got
the offset wrong, but I'm digging.  Please hold off review of this
patch till the next version.

[PATCH 1/4] pinctrl: rockchip: Set wake_enabled

[Linus Walleij]

On Tue, Oct 21, 2014 at 1:27 AM, Doug Anderson <dianders@chromium.org> wrote:

> The rockchip pinctrl driver uses irq_gc_set_wake() but doesn't setup
> the .wake_enabled member.  That means that we can never actually use a
> pin for wakeup.  When "irq_set_irq_wake()" tries to call through it
> will always get a failure from set_irq_wake_real() and will then set
> wake_depth to 0.  Assuming you can resume you'll later get an error
> message about "Unbalanced IRQ x wake disable".
>
> Signed-off-by: Doug Anderson <dianders@chromium.org>

Heiko, are you looking at this patch series? Need you Reviewed-by
to merge this stuff.

Yours,
Linus Walleij

[PATCH 1/4] pinctrl: rockchip: Set wake_enabled

[Doug Anderson]

Linus,

On Tue, Oct 28, 2014 at 8:51 AM, Linus Walleij <linus.walleij@linaro.org> wrote:
> On Tue, Oct 21, 2014 at 1:27 AM, Doug Anderson <dianders@chromium.org> wrote:
>
>> The rockchip pinctrl driver uses irq_gc_set_wake() but doesn't setup
>> the .wake_enabled member.  That means that we can never actually use a
>> pin for wakeup.  When "irq_set_irq_wake()" tries to call through it
>> will always get a failure from set_irq_wake_real() and will then set
>> wake_depth to 0.  Assuming you can resume you'll later get an error
>> message about "Unbalanced IRQ x wake disable".
>>
>> Signed-off-by: Doug Anderson <dianders@chromium.org>
>
> Heiko, are you looking at this patch series? Need you Reviewed-by
> to merge this stuff.

See Heiko's review on the latest version of this series (v2).

https://patchwork.kernel.org/patch/5126811/
https://patchwork.kernel.org/patch/5126941/
https://patchwork.kernel.org/patch/5126971/
https://patchwork.kernel.org/patch/5126801/

-Doug