[PATCH RFC 0/7] ARM: shmobile: sh73a0: DT PM domain support

[PATCH RFC 0/7] ARM: shmobile: sh73a0: DT PM domain support

[Geert Uytterhoeven]

	Hi Simon, Magnus,

This patch series enables DT support for PM domains on the Renesas SH-Mobile
AG5 (sh73a0) SoC.  It is marked "RFC" due to the addition of memory-controllers
nodes without bindings in patch [5/7] and [7/7].

This series builds further on the series "[PATCH v5 0/8] ARM: shmobile:
R-Mobile: DT PM domain support", which added similar support for R-Mobile A1
(r8a7740).  Due to the similarity of the SYSC System-Controller on the various
SH-Mobile/R-Mobile SoCs, and the abstraction of PM domains in DT, the same
driver can handle sh73a0 after some small modifications, without changing the
DT bindings.

Compared to r8a7740, the only significant change is the move of the
memory-controller(s) to separate PM domains on sh73a0 (and also on R-Mobile
APE6 (r8a73a4)). Hence a provision must be made to not turn off these PM
domains inadvertently. Please see patch [5/7] ("[RFC] ARM: shmobile: sh73a0
dtsi: Add PM domain support"), and the follow-up patch for r8a7740 [7/7]
("[RFC] ARM: shmobile: r8a7740 dtsi: Add missing memory-controller node") for
more details.

This was tested on kzm9g-multiplatform.
Functionality-wise, it behaves the same as the legacy (non-DT) version (modulo
missing DT support in some device drivers).

Thanks for your comments!

Dependencies:
  - [PATCH v5 0/8] ARM: shmobile: R-Mobile: DT PM domain support,
  - [[PATCH v5 0/6] sh73a0 common clock framework implementation,
  - [PATCH 2/2] ARM: shmobile: sh73a0 dtsi: Add missing INTCA0 clock for
    irqpin module.

Geert Uytterhoeven (7):
  PM / Domains: Document SH-Mobile AG5 (sh73a0) binding
  ARM: shmobile: R-Mobile: Consolidate rmobile_pd_suspend_*()
  ARM: shmobile: R-Mobile: Generalize adding/looking up special PM
    domains
  ARM: shmobile: R-Mobile: Special-case PM domains containing SBSCs
  [RFC] ARM: shmobile: sh73a0 dtsi: Add PM domain support
  drivers: sh: Disable PM runtime for multi-platform sh73a0 with genpd
  [RFC] ARM: shmobile: r8a7740 dtsi: Add missing memory-controller node

 .../bindings/power/renesas,sysc-rmobile.txt        |   1 +
 arch/arm/boot/dts/r8a7740.dtsi                     |   6 +
 arch/arm/boot/dts/sh73a0.dtsi                      | 159 ++++++++++++++++++++-
 arch/arm/mach-shmobile/pm-rmobile.c                | 159 +++++++++++++--------
 drivers/sh/pm_runtime.c                            |   4 +-
 5 files changed, 268 insertions(+), 61 deletions(-)

-- 
1.9.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH 1/7] PM / Domains: Document SH-Mobile AG5 (sh73a0) binding

[Geert Uytterhoeven]

SH-Mobile AG5 (sh73a0) can be handled by the existing bindings.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt b/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt
index 89ca3f35aec69750..061971bb387f7b27 100644
--- a/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt
+++ b/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt
@@ -12,6 +12,7 @@ Required properties:
 	      fallback.
 	      Examples with soctypes are:
 		- "renesas,sysc-r8a7740" (R-Mobile A1)
+		- "renesas,sysc-sh73a0" (SH-Mobile AG5)
 - reg: Two address start and address range blocks for the device:
          - The first block refers to the normally accessible registers,
          - the second block refers to the registers protected by the HPB
-- 
1.9.1

[PATCH 2/7] ARM: shmobile: R-Mobile: Consolidate rmobile_pd_suspend_*()

[Geert Uytterhoeven]

Consolidate the identical rmobile_pd_suspend_*() routines that just
return -EBUSY to prevent a PM domain from being powered down into a
single rmobile_pd_suspend_busy().

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm/mach-shmobile/pm-rmobile.c | 28 +++++++++++++---------------
 1 file changed, 13 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c
index 5e01a28110e24034..3d383d3dcd4ec640 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.c
+++ b/arch/arm/mach-shmobile/pm-rmobile.c
@@ -209,11 +209,10 @@ void rmobile_add_devices_to_domains(struct pm_domain_device data[],
 
 #else /* !CONFIG_ARCH_SHMOBILE_LEGACY */
 
-static int rmobile_pd_suspend_cpu(void)
+static int rmobile_pd_suspend_busy(void)
 {
 	/*
-	 * This domain contains the CPU core and therefore it should
-	 * only be turned off if the CPU is not in use.
+	 * This domain should not be turned off.
 	 */
 	return -EBUSY;
 }
@@ -227,16 +226,6 @@ static int rmobile_pd_suspend_console(void)
 	return console_suspend_enabled ? 0 : -EBUSY;
 }
 
-static int rmobile_pd_suspend_debug(void)
-{
-	/*
-	 * This domain contains the Coresight-ETM hardware block and
-	 * therefore it should only be turned off if the debug module is
-	 * not in use.
-	 */
-	return -EBUSY;
-}
-
 #define MAX_NUM_CPU_PDS		8
 
 static unsigned int num_cpu_pds __initdata;
@@ -310,17 +299,26 @@ static void __init rmobile_setup_pm_domain(struct device_node *np,
 	const char *name = pd->genpd.name;
 
 	if (pd_contains_cpu(np)) {
+		/*
+		 * This domain contains the CPU core and therefore it should
+		 * only be turned off if the CPU is not in use.
+		 */
 		pr_debug("PM domain %s contains CPU\n", name);
 		pd->gov = &pm_domain_always_on_gov;
-		pd->suspend = rmobile_pd_suspend_cpu;
+		pd->suspend = rmobile_pd_suspend_busy;
 	} else if (np == console_pd) {
 		pr_debug("PM domain %s contains serial console\n", name);
 		pd->gov = &pm_domain_always_on_gov;
 		pd->suspend = rmobile_pd_suspend_console;
 	} else if (np == debug_pd) {
+		/*
+		 * This domain contains the Coresight-ETM hardware block and
+		 * therefore it should only be turned off if the debug module is
+		 * not in use.
+		 */
 		pr_debug("PM domain %s contains Coresight-ETM\n", name);
 		pd->gov = &pm_domain_always_on_gov;
-		pd->suspend = rmobile_pd_suspend_debug;
+		pd->suspend = rmobile_pd_suspend_busy;
 	}
 
 	rmobile_init_pm_domain(pd);
-- 
1.9.1

[PATCH 3/7] ARM: shmobile: R-Mobile: Generalize adding/looking up special PM domains

[Geert Uytterhoeven]

Make adding special PM domains to an array, and looking them up
later, more generic, so it can be used for all special hardware blocks.
The type of PM domain is also stored, so rmobile_setup_pm_domain() can
use a switch() statement instead of a chain of if/else statements.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm/mach-shmobile/pm-rmobile.c | 107 ++++++++++++++++++++++--------------
 1 file changed, 67 insertions(+), 40 deletions(-)

diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c
index 3d383d3dcd4ec640..774a8e276049a202 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.c
+++ b/arch/arm/mach-shmobile/pm-rmobile.c
@@ -226,71 +226,89 @@ static int rmobile_pd_suspend_console(void)
 	return console_suspend_enabled ? 0 : -EBUSY;
 }
 
-#define MAX_NUM_CPU_PDS		8
+enum pd_types {
+	PD_NORMAL,
+	PD_CPU,
+	PD_CONSOLE,
+	PD_DEBUG,
+};
 
-static unsigned int num_cpu_pds __initdata;
-static struct device_node *cpu_pds[MAX_NUM_CPU_PDS] __initdata;
-static struct device_node *console_pd __initdata;
-static struct device_node *debug_pd __initdata;
+#define MAX_NUM_SPECIAL_PDS	16
 
-static void __init get_special_pds(void)
+static struct special_pd {
+	struct device_node *pd;
+	enum pd_types type;
+} special_pds[MAX_NUM_SPECIAL_PDS] __initdata;
+
+static unsigned int num_special_pds __initdata;
+
+static void __init add_special_pd(struct device_node *np, enum pd_types type)
 {
-	struct device_node *np, *pd;
 	unsigned int i;
+	struct device_node *pd;
 
-	/* PM domains containing CPUs */
-	for_each_node_by_type(np, "cpu") {
-		pd = of_parse_phandle(np, "power-domains", 0);
-		if (!pd)
-			continue;
+	pd = of_parse_phandle(np, "power-domains", 0);
+	if (!pd)
+		return;
 
-		for (i = 0; i < num_cpu_pds; i++)
-			if (pd == cpu_pds[i])
-				break;
-
-		if (i < num_cpu_pds) {
-			of_node_put(pd);
-			continue;
-		}
+	for (i = 0; i < num_special_pds; i++)
+		if (pd == special_pds[i].pd && type == special_pds[i].type)
+			break;
 
-		if (num_cpu_pds == MAX_NUM_CPU_PDS) {
-			pr_warn("Too many CPU PM domains\n");
-			of_node_put(pd);
-			continue;
-		}
+	if (i < num_special_pds) {
+		of_node_put(pd);
+		return;
+	}
 
-		cpu_pds[num_cpu_pds++] = pd;
+	if (num_special_pds == ARRAY_SIZE(special_pds)) {
+		pr_warn("Too many special PM domains\n");
+		of_node_put(pd);
+		return;
 	}
 
+	pr_debug("Special PM domain %s type %d for %s\n", pd->name, type,
+		 np->full_name);
+
+	special_pds[num_special_pds].pd = pd;
+	special_pds[num_special_pds].type = type;
+	num_special_pds++;
+}
+
+static void __init get_special_pds(void)
+{
+	struct device_node *np;
+
+	/* PM domains containing CPUs */
+	for_each_node_by_type(np, "cpu")
+		add_special_pd(np, PD_CPU);
+
 	/* PM domain containing console */
 	if (of_stdout)
-		console_pd = of_parse_phandle(of_stdout, "power-domains", 0);
+		add_special_pd(of_stdout, PD_CONSOLE);
 
 	/* PM domain containing Coresight-ETM */
 	np = of_find_compatible_node(NULL, NULL, "arm,coresight-etm3x");
 	if (np)
-		debug_pd = of_parse_phandle(np, "power-domains", 0);
+		add_special_pd(np, PD_DEBUG);
 }
 
 static void __init put_special_pds(void)
 {
 	unsigned int i;
 
-	for (i = 0; i < num_cpu_pds; i++)
-		of_node_put(cpu_pds[i]);
-	of_node_put(console_pd);
-	of_node_put(debug_pd);
+	for (i = 0; i < num_special_pds; i++)
+		of_node_put(special_pds[i].pd);
 }
 
-static bool __init pd_contains_cpu(const struct device_node *pd)
+static enum pd_types __init pd_type(const struct device_node *pd)
 {
 	unsigned int i;
 
-	for (i = 0; i < num_cpu_pds; i++)
-		if (pd == cpu_pds[i])
-			return true;
+	for (i = 0; i < num_special_pds; i++)
+		if (pd == special_pds[i].pd)
+			return special_pds[i].type;
 
-	return false;
+	return PD_NORMAL;
 }
 
 static void __init rmobile_setup_pm_domain(struct device_node *np,
@@ -298,7 +316,8 @@ static void __init rmobile_setup_pm_domain(struct device_node *np,
 {
 	const char *name = pd->genpd.name;
 
-	if (pd_contains_cpu(np)) {
+	switch (pd_type(np)) {
+	case PD_CPU:
 		/*
 		 * This domain contains the CPU core and therefore it should
 		 * only be turned off if the CPU is not in use.
@@ -306,11 +325,15 @@ static void __init rmobile_setup_pm_domain(struct device_node *np,
 		pr_debug("PM domain %s contains CPU\n", name);
 		pd->gov = &pm_domain_always_on_gov;
 		pd->suspend = rmobile_pd_suspend_busy;
-	} else if (np == console_pd) {
+		break;
+
+	case PD_CONSOLE:
 		pr_debug("PM domain %s contains serial console\n", name);
 		pd->gov = &pm_domain_always_on_gov;
 		pd->suspend = rmobile_pd_suspend_console;
-	} else if (np == debug_pd) {
+		break;
+
+	case PD_DEBUG:
 		/*
 		 * This domain contains the Coresight-ETM hardware block and
 		 * therefore it should only be turned off if the debug module is
@@ -319,6 +342,10 @@ static void __init rmobile_setup_pm_domain(struct device_node *np,
 		pr_debug("PM domain %s contains Coresight-ETM\n", name);
 		pd->gov = &pm_domain_always_on_gov;
 		pd->suspend = rmobile_pd_suspend_busy;
+		break;
+
+	case PD_NORMAL:
+		break;
 	}
 
 	rmobile_init_pm_domain(pd);
-- 
1.9.1

[PATCH 4/7] ARM: shmobile: R-Mobile: Special-case PM domains containing SBSCs

[Geert Uytterhoeven]

Add a special case for PM domains containing a memory controller like
the SDRAM Bus State Controller (SBSC). Such a PM domain must not be
turned off if SDRAM is in use.

On sh73a0 PM domains A4BC0 and A4BC1 each contain an SDRAM Bus State
Controller (SBSC1 resp. SBSC2). On r8a73a4 PM domain A3BC contains a DDR
Bus Controller (DBSC).  In both cases, there are no other devices in
these PM domains, so they were eligible for power down, crashing the
system.

On r8a7740 the DDR3 Bus State Controller (DBSC3) is located in A4S,
whose child domain A3SM contains the CPU core. Hence A4S is never turned
off, and no crash happened.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm/mach-shmobile/pm-rmobile.c | 28 ++++++++++++++++++++++++----
 1 file changed, 24 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c
index 774a8e276049a202..4bae656a83b4fca3 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.c
+++ b/arch/arm/mach-shmobile/pm-rmobile.c
@@ -231,6 +231,7 @@ enum pd_types {
 	PD_CPU,
 	PD_CONSOLE,
 	PD_DEBUG,
+	PD_SBSC,
 };
 
 #define MAX_NUM_SPECIAL_PDS	16
@@ -242,6 +243,14 @@ static struct special_pd {
 
 static unsigned int num_special_pds __initdata;
 
+static const struct of_device_id special_ids[] __initconst = {
+	{ .compatible = "arm,coresight-etm3x", .data = (void *)PD_DEBUG },
+	{ .compatible = "renesas,dbsc-r8a73a4", .data = (void *)PD_SBSC, },
+	{ .compatible = "renesas,dbsc3-r8a7740", .data = (void *)PD_SBSC, },
+	{ .compatible = "renesas,sbsc-sh73a0", .data = (void *)PD_SBSC, },
+	{ /* sentinel */ },
+};
+
 static void __init add_special_pd(struct device_node *np, enum pd_types type)
 {
 	unsigned int i;
@@ -277,6 +286,7 @@ static void __init add_special_pd(struct device_node *np, enum pd_types type)
 static void __init get_special_pds(void)
 {
 	struct device_node *np;
+	const struct of_device_id *id;
 
 	/* PM domains containing CPUs */
 	for_each_node_by_type(np, "cpu")
@@ -286,10 +296,9 @@ static void __init get_special_pds(void)
 	if (of_stdout)
 		add_special_pd(of_stdout, PD_CONSOLE);
 
-	/* PM domain containing Coresight-ETM */
-	np = of_find_compatible_node(NULL, NULL, "arm,coresight-etm3x");
-	if (np)
-		add_special_pd(np, PD_DEBUG);
+	/* PM domains containing other special devices */
+	for_each_matching_node_and_match(np, special_ids, &id)
+		add_special_pd(np, (enum pd_types)id->data);
 }
 
 static void __init put_special_pds(void)
@@ -344,6 +353,17 @@ static void __init rmobile_setup_pm_domain(struct device_node *np,
 		pd->suspend = rmobile_pd_suspend_busy;
 		break;
 
+	case PD_SBSC:
+		/*
+		 * This domain contains the SDRAM Bus State Controller and
+		 * therefore it should only be turned off if SDRAM is not in
+		 * use.
+		 */
+		pr_debug("PM domain %s contains SBSC\n", name);
+		pd->gov = &pm_domain_always_on_gov;
+		pd->suspend = rmobile_pd_suspend_busy;
+		break;
+
 	case PD_NORMAL:
 		break;
 	}
-- 
1.9.1

[PATCH 5/7] [RFC] ARM: shmobile: sh73a0 dtsi: Add PM domain support

[Geert Uytterhoeven]

Add a device node for the System Controller, with subnodes that
represent the hardware power area hierarchy.
Hook up all devices to their respective PM domains.

Add memory-controller nodes for the SDRAM Bus State Controllers (SBSC1
and SBSC2), which lie in the A4BC0 resp. A4BC1 PM domains, to prevent
them from being powered down.
There are no documented bindings for the SBSC yet (so far there's still
no need for a driver), but all properties follow the standard
conventions.

Note that unlike on R-Mobile A1 (r8a7740), PM domain D4 can be powered
down without ill effects on s2ram behavior, just like on SH-Mobile AP4
(sh7372).  Hence we can postpone adding a (minimal) device node for the
Coresight-ETM hardware block.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Question: Should I make sbsc1 and sbsc2 minimal nodes for now, i.e. only
	  retain their "compatible" and "power-domains" properties?
---
 arch/arm/boot/dts/sh73a0.dtsi | 159 +++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 157 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index c7ab55e55e23f8cb..0ba0892d21a7affd 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -26,12 +26,14 @@
 			compatible = "arm,cortex-a9";
 			reg = <0>;
 			clock-frequency = <1196000000>;
+			power-domains = <&pd_a2sl>;
 		};
 		cpu at 1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <1>;
 			clock-frequency = <1196000000>;
+			power-domains = <&pd_a2sl>;
 		};
 	};
 
@@ -43,6 +45,24 @@
 		      <0xf0000100 0x100>;
 	};
 
+	sbsc2: memory-controller at fb400000 {
+		compatible = "renesas,sbsc-sh73a0";
+		reg = <0xfb400000 0x400>;
+		interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 38 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "sec", "temp";
+		power-domains = <&pd_a4bc1>;
+	};
+
+	sbsc1: memory-controller at fe400000 {
+		compatible = "renesas,sbsc-sh73a0";
+		reg = <0xfe400000 0x400>;
+		interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 36 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "sec", "temp";
+		power-domains = <&pd_a4bc0>;
+	};
+
 	pmu {
 		compatible = "arm,cortex-a9-pmu";
 		interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>,
@@ -53,11 +73,12 @@
 		compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
 		reg = <0xe6138000 0x200>;
 		interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
+		clock-names = "fck";
+		power-domains = <&pd_c5>;
 
 		renesas,channels-mask = <0x3f>;
 
-		clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
-		clock-names = "fck";
 		status = "disabled";
 	};
 
@@ -79,6 +100,7 @@
 			      0 7 IRQ_TYPE_LEVEL_HIGH
 			      0 8 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
+		power-domains = <&pd_a4s>;
 	};
 
 	irqpin1: irqpin at e6900004 {
@@ -99,6 +121,7 @@
 			      0 15 IRQ_TYPE_LEVEL_HIGH
 			      0 16 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
+		power-domains = <&pd_a4s>;
 		control-parent;
 	};
 
@@ -120,6 +143,7 @@
 			      0 23 IRQ_TYPE_LEVEL_HIGH
 			      0 24 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
+		power-domains = <&pd_a4s>;
 	};
 
 	irqpin3: irqpin at e690000c {
@@ -140,6 +164,7 @@
 			      0 31 IRQ_TYPE_LEVEL_HIGH
 			      0 32 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
+		power-domains = <&pd_a4s>;
 	};
 
 	i2c0: i2c at e6820000 {
@@ -152,6 +177,7 @@
 			      0 169 IRQ_TYPE_LEVEL_HIGH
 			      0 170 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
+		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
 
@@ -165,6 +191,7 @@
 			      0 53 IRQ_TYPE_LEVEL_HIGH
 			      0 54 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
+		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
 
@@ -178,6 +205,7 @@
 			      0 173 IRQ_TYPE_LEVEL_HIGH
 			      0 174 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
+		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
 
@@ -191,6 +219,7 @@
 			      0 185 IRQ_TYPE_LEVEL_HIGH
 			      0 186 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
+		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
 
@@ -204,6 +233,7 @@
 			      0 189 IRQ_TYPE_LEVEL_HIGH
 			      0 190 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
+		power-domains = <&pd_c5>;
 		status = "disabled";
 	};
 
@@ -213,6 +243,7 @@
 		interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
 			      0 141 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
+		power-domains = <&pd_a3sp>;
 		reg-io-width = <4>;
 		status = "disabled";
 	};
@@ -224,6 +255,7 @@
 			      0 84 IRQ_TYPE_LEVEL_HIGH
 			      0 85 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
+		power-domains = <&pd_a3sp>;
 		cap-sd-highspeed;
 		status = "disabled";
 	};
@@ -235,6 +267,7 @@
 		interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
 			      0 89 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
+		power-domains = <&pd_a3sp>;
 		toshiba,mmc-wrprotect-disable;
 		cap-sd-highspeed;
 		status = "disabled";
@@ -246,6 +279,7 @@
 		interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
 			      0 105 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
+		power-domains = <&pd_a3sp>;
 		toshiba,mmc-wrprotect-disable;
 		cap-sd-highspeed;
 		status = "disabled";
@@ -257,6 +291,7 @@
 		interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
 		clock-names = "sci_ick";
+		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
 
@@ -266,6 +301,7 @@
 		interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
 		clock-names = "sci_ick";
+		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
 
@@ -275,6 +311,7 @@
 		interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
 		clock-names = "sci_ick";
+		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
 
@@ -284,6 +321,7 @@
 		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
 		clock-names = "sci_ick";
+		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
 
@@ -293,6 +331,7 @@
 		interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
 		clock-names = "sci_ick";
+		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
 
@@ -302,6 +341,7 @@
 		interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
 		clock-names = "sci_ick";
+		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
 
@@ -311,6 +351,7 @@
 		interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
 		clock-names = "sci_ick";
+		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
 
@@ -320,6 +361,7 @@
 		interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
 		clock-names = "sci_ick";
+		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
 
@@ -329,6 +371,7 @@
 		interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
 		clock-names = "sci_ick";
+		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
 
@@ -347,6 +390,117 @@
 			<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
 			<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
 			<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
+		power-domains = <&pd_c5>;
+	};
+
+	sysc: system-controller at e6180000 {
+		compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
+		reg = <0xe6180000 8000>, <0xe6188000 8000>;
+
+		pm-domains {
+			pd_c5: c5 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				#power-domain-cells = <0>;
+
+				pd_c4: c4 at 0 {
+					reg = <0>;
+					#power-domain-cells = <0>;
+				};
+
+				pd_d4: d4 at 1 {
+					reg = <1>;
+					#power-domain-cells = <0>;
+				};
+
+				pd_a4bc0: a4bc0 at 4 {
+					reg = <4>;
+					#power-domain-cells = <0>;
+				};
+
+				pd_a4bc1: a4bc1 at 5 {
+					reg = <5>;
+					#power-domain-cells = <0>;
+				};
+
+				pd_a4lc0: a4lc0 at 6 {
+					reg = <6>;
+					#power-domain-cells = <0>;
+				};
+
+				pd_a4lc1: a4lc1 at 7 {
+					reg = <7>;
+					#power-domain-cells = <0>;
+				};
+
+				pd_a4mp: a4mp at 8 {
+					reg = <8>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					#power-domain-cells = <0>;
+
+					pd_a3mp: a3mp at 9 {
+						reg = <9>;
+						#power-domain-cells = <0>;
+					};
+
+					pd_a3vc: a3vc at 10 {
+						reg = <10>;
+						#power-domain-cells = <0>;
+					};
+				};
+
+				pd_a4rm: a4rm at 12 {
+					reg = <12>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					#power-domain-cells = <0>;
+
+					pd_a3r: a3r at 13 {
+						reg = <13>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+						#power-domain-cells = <0>;
+
+						pd_a2rv: a2rv at 14 {
+							reg = <14>;
+							#address-cells = <1>;
+							#size-cells = <0>;
+							#power-domain-cells = <0>;
+						};
+					};
+				};
+
+				pd_a4s: a4s at 16 {
+					reg = <16>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					#power-domain-cells = <0>;
+
+					pd_a3sp: a3sp at 17 {
+						reg = <17>;
+						#power-domain-cells = <0>;
+					};
+
+					pd_a3sg: a3sg at 18 {
+						reg = <18>;
+						#power-domain-cells = <0>;
+					};
+
+					pd_a3sm: a3sm at 19 {
+						reg = <19>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+						#power-domain-cells = <0>;
+
+						pd_a2sl: a2sl at 20 {
+							reg = <20>;
+							#power-domain-cells = <0>;
+						};
+					};
+				};
+			};
+		};
 	};
 
 	sh_fsi2: sound at ec230000 {
@@ -354,6 +508,7 @@
 		compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
 		reg = <0xec230000 0x400>;
 		interrupts = <0 146 0x4>;
+		power-domains = <&pd_a4mp>;
 		status = "disabled";
 	};
 
-- 
1.9.1

[PATCH 6/7] drivers: sh: Disable PM runtime for multi-platform sh73a0 with genpd

[Geert Uytterhoeven]

If the default PM domain using PM_CLK is used for PM runtime, the real PM
domain(s) cannot be registered from DT later.

Hence do not enable it when running a multi-platform kernel with genpd
support on an sh73a0. The R-Mobile PM domain driver will take care of
PM runtime management of the module clocks.

The default PM domain is still needed for:
  - platforms without genpd support,
  - the legacy (non-DT) case, where genpd may take over later, except
    for the C5 "always on" PM domain.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/sh/pm_runtime.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/sh/pm_runtime.c b/drivers/sh/pm_runtime.c
index 85cc89fd3e7d7cb7..2e6f1efadedca1b0 100644
--- a/drivers/sh/pm_runtime.c
+++ b/drivers/sh/pm_runtime.c
@@ -83,6 +83,7 @@ static int __init sh_pm_runtime_init(void)
 		    !of_machine_is_compatible("renesas,r8a73a4") &&
 #ifndef CONFIG_PM_GENERIC_DOMAINS_OF
 		    !of_machine_is_compatible("renesas,r8a7740") &&
+		    !of_machine_is_compatible("renesas,sh73a0") &&
 #endif
 		    !of_machine_is_compatible("renesas,r8a7778") &&
 		    !of_machine_is_compatible("renesas,r8a7779") &&
@@ -91,8 +92,7 @@ static int __init sh_pm_runtime_init(void)
 		    !of_machine_is_compatible("renesas,r8a7792") &&
 		    !of_machine_is_compatible("renesas,r8a7793") &&
 		    !of_machine_is_compatible("renesas,r8a7794") &&
-		    !of_machine_is_compatible("renesas,sh7372") &&
-		    !of_machine_is_compatible("renesas,sh73a0"))
+		    !of_machine_is_compatible("renesas,sh7372"))
 			return 0;
 	}
 
-- 
1.9.1

[PATCH 7/7] [RFC] ARM: shmobile: r8a7740 dtsi: Add missing memory-controller node

[Geert Uytterhoeven]

Add a memory-controller node for the DDR3 Bus State Controller (DBSC3),
which lies in the A4S PM domain.
There are no documented bindings for the DBSC3 yet (so far there's still
no need for a driver), but all of its properties follow the standard
conventions.

This has no visible effect for now, as A4S is never turned off because
its child domain A3SM contains the CPU core.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Question: Should I make dbsc3 a minimal node for now, i.e. retain only
	  its "compatible" and "power-domains" properties?
---
 arch/arm/boot/dts/r8a7740.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 95723764431a3e5d..173d4340bba1c4fa 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -37,6 +37,12 @@
 		      <0xc2000000 0x1000>;
 	};
 
+	dbsc3: memory-controller at fe400000 {
+		compatible = "renesas,dbsc3-r8a7740";
+		reg = <0xfe400000 0x400>;
+		power-domains = <&pd_a4s>;
+	};
+
 	pmu {
 		compatible = "arm,cortex-a9-pmu";
 		interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
-- 
1.9.1