* [PATCH 0/5] Qualcomm PCIe and PCIe/PHY drivers
@ 2014-12-12 17:13 Stanimir Varbanov
2014-12-12 17:13 ` [PATCH 1/5] DT: phy: qcom: Add PCIe PHY devicetree bindings Stanimir Varbanov
` (4 more replies)
0 siblings, 5 replies; 14+ messages in thread
From: Stanimir Varbanov @ 2014-12-12 17:13 UTC (permalink / raw)
To: linux-arm-kernel
This patchset introduces a Qualcomm PCIe root complex driver for
Snapdragon 805 (APQ8084). It also adds a PCIe PHY driver in generic
phy framework. The PCIe hardware use Designware IP core plus
Qualcomm application specific hw.
The first two patches add a PHY driver binding document and the
PHY driver. Patches 3/5 and 4/5 add PCIe DT document and the driver.
Last 5/5 adds APQ8084 in mach-qcom as next multiplatform Qualcomm
SoC.
Comments are welcome!
regards,
Stan
Stanimir Varbanov (5):
DT: phy: qcom: Add PCIe PHY devicetree bindings
phy: qcom: Add Qualcomm PCIe PHY
DT: PCI: qcom: Document PCIe devicetree bindings
PCI: qcom: Add Qualcomm PCIe controller driver
ARM: qcom: Add Qualcomm APQ8084 SoC
.../devicetree/bindings/pci/qcom,pcie.txt | 159 ++++++++
.../devicetree/bindings/phy/qcom-pcie-phy.txt | 62 +++
arch/arm/mach-qcom/Kconfig | 7 +
drivers/pci/host/Kconfig | 9 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-qcom.c | 415 ++++++++++++++++++++
drivers/phy/Kconfig | 7 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-qcom-pcie.c | 311 +++++++++++++++
9 files changed, 972 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.txt
create mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie-phy.txt
create mode 100644 drivers/pci/host/pcie-qcom.c
create mode 100644 drivers/phy/phy-qcom-pcie.c
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/5] DT: phy: qcom: Add PCIe PHY devicetree bindings
2014-12-12 17:13 [PATCH 0/5] Qualcomm PCIe and PCIe/PHY drivers Stanimir Varbanov
@ 2014-12-12 17:13 ` Stanimir Varbanov
2014-12-12 17:13 ` [PATCH 2/5] phy: qcom: Add Qualcomm PCIe PHY Stanimir Varbanov
` (3 subsequent siblings)
4 siblings, 0 replies; 14+ messages in thread
From: Stanimir Varbanov @ 2014-12-12 17:13 UTC (permalink / raw)
To: linux-arm-kernel
Document Qualcomm PCIe PHY devicetree bindings.
Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
---
.../devicetree/bindings/phy/qcom-pcie-phy.txt | 62 ++++++++++++++++++++
1 files changed, 62 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/qcom-pcie-phy.txt b/Documentation/devicetree/bindings/phy/qcom-pcie-phy.txt
new file mode 100644
index 0000000..f53eaf3
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-pcie-phy.txt
@@ -0,0 +1,62 @@
+* Qualcomm PCIe PHY controller
+
+PCIe PHY nodes are defined to describe on-chip SATA Physical layer controllers.
+Each SATA PHY controller should have its own node.
+
+- compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Value should contain "qcom,pcie-phy"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: Offset and length of the PCIe PHY registers
+
+- #phy-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: Must be zero
+
+- clocks:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: A list of phandles and clock specifier pair, one
+ for each entry in clock-names property
+
+- clock-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Must be "core" for PHY core clock
+
+- resets:
+ Usage: required
+ Value type: <phandle>
+ Definition: List of phandle and reset specifier pairs as listed
+ in reset-names property
+
+- reset-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Should contain "phy" for PHY reset
+
+- <name>-supply:
+ Usage: required
+ Value type: <phandle>
+ Definition: List of phandles to the supply regulators
+ - "vdda" analog Vdd supply
+ - "vdda_pll" analog Vdd PLL supply
+
+* Example
+
+ pciephy0: phy at fc526000 {
+ compatible = "qcom,pcie-phy";
+ reg = <0xfc526000 0x1000>;
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+ clock-names = "core";
+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+ reset-names = "phy";
+ vdda-supply = <&pma8084_l3>;
+ vdda_pll-supply = <&pma8084_l12>;
+ #phy-cells = <0>;
+ };
--
1.7.0.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/5] phy: qcom: Add Qualcomm PCIe PHY
2014-12-12 17:13 [PATCH 0/5] Qualcomm PCIe and PCIe/PHY drivers Stanimir Varbanov
2014-12-12 17:13 ` [PATCH 1/5] DT: phy: qcom: Add PCIe PHY devicetree bindings Stanimir Varbanov
@ 2014-12-12 17:13 ` Stanimir Varbanov
2015-01-21 9:11 ` Kishon Vijay Abraham I
2014-12-12 17:13 ` [PATCH 3/5] DT: PCI: qcom: Document PCIe devicetree bindings Stanimir Varbanov
` (2 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: Stanimir Varbanov @ 2014-12-12 17:13 UTC (permalink / raw)
To: linux-arm-kernel
Add a PCIe PHY driver used by PCIe host controller driver
on Qualcomm SoCs like Snapdragon 805.
Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
---
drivers/phy/Kconfig | 7 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-qcom-pcie.c | 311 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 319 insertions(+), 0 deletions(-)
create mode 100644 drivers/phy/phy-qcom-pcie.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 2a436e6..135bdcc 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -218,6 +218,13 @@ config PHY_QCOM_IPQ806X_SATA
depends on OF
select GENERIC_PHY
+config PHY_QCOM_PCIE
+ tristate "Qualcomm PCIe SerDes/PHY driver"
+ depends on ARCH_QCOM
+ depends on HAS_IOMEM
+ depends on OF
+ select GENERIC_PHY
+
config PHY_ST_SPEAR1310_MIPHY
tristate "ST SPEAR1310-MIPHY driver"
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index c4590fc..e7662fb 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -26,6 +26,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
+obj-$(CONFIG_PHY_QCOM_PCIE) += phy-qcom-pcie.o
obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
diff --git a/drivers/phy/phy-qcom-pcie.c b/drivers/phy/phy-qcom-pcie.c
new file mode 100644
index 0000000..3db348a
--- /dev/null
+++ b/drivers/phy/phy-qcom-pcie.c
@@ -0,0 +1,311 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+#define QSERDES_COM_PLL_CP_SETI 0x024
+#define QSERDES_COM_PLL_IP_SETP 0x028
+#define QSERDES_COM_PLL_CP_SETP 0x02c
+#define QSERDES_COM_SYSCLK_EN_SEL 0x038
+#define QSERDES_COM_RESETSM_CNTRL 0x040
+#define QSERDES_COM_PLLLOCK_CMP1 0x044
+#define QSERDES_COM_PLLLOCK_CMP2 0x048
+#define QSERDES_COM_PLLLOCK_CMP_EN 0x050
+#define QSERDES_COM_DEC_START1 0x064
+#define QSERDES_COM_DIV_FRAC_START1 0x098
+#define QSERDES_COM_DIV_FRAC_START2 0x09c
+#define QSERDES_COM_DIV_FRAC_START3 0x0a0
+#define QSERDES_COM_DEC_START2 0x0a4
+#define QSERDES_COM_PLL_RXTXEPCLK_EN 0x0a8
+#define QSERDES_COM_PLL_CRCTRL 0x0ac
+
+#define QSERDES_RX_CDR_CONTROL 0x400
+#define QSERDES_RX_CDR_CONTROL2 0x410
+#define QSERDES_RX_RX_TERM_HIGHZ_CM_AC_COUPLE 0x42c
+#define QSERDES_RX_RX_EQ_GAIN12 0x430
+
+#define PCIE_PHY_SW_RESET 0x600
+#define PCIE_PHY_POWER_DOWN_CONTROL 0x604
+#define PCIE_PHY_START 0x608
+#define PCIE_PHY_ENDPOINT_REFCLK_DRIVE 0x648
+#define PCIE_PHY_POWER_STATE_CONFIG1 0x650
+#define PCIE_PHY_POWER_STATE_CONFIG2 0x654
+#define PCIE_PHY_PWRUP_RESET_DLY_TIME_SYSCLK 0x678
+#define PCIE_PHY_PWRUP_RESET_DLY_TIME_AUXCLK 0x67c
+#define PCIE_PHY_PCS_STATUS 0x6c8
+
+#define PHY_DELAY_MIN_US 995
+#define PHY_DELAY_MAX_US 1005
+#define PHY_RETRIES_COUNT 10
+
+#define PIPE_CLK_DELAY_MIN_US 5000
+#define PIPE_CLK_DELAY_MAX_US 5100
+#define PIPE_CLK_RETRIES_COUNT 10
+
+struct qcom_pcie_phy {
+ void __iomem *base;
+ struct clk *clk;
+ struct reset_control *res_phy;
+ struct regulator *vdda_pll;
+ struct regulator *vdda;
+ struct device *dev;
+};
+
+struct phy_regs {
+ u32 reg_offset;
+ u32 val;
+};
+
+static const struct phy_regs pcie_phy_regs[] = {
+ { PCIE_PHY_POWER_DOWN_CONTROL, 0x03 },
+ { QSERDES_COM_SYSCLK_EN_SEL, 0x08 },
+ { QSERDES_COM_DEC_START1, 0x82 },
+ { QSERDES_COM_DEC_START2, 0x03 },
+ { QSERDES_COM_DIV_FRAC_START1, 0xd5 },
+ { QSERDES_COM_DIV_FRAC_START2, 0xaa },
+ { QSERDES_COM_DIV_FRAC_START3, 0x13 },
+ { QSERDES_COM_PLLLOCK_CMP_EN, 0x01 },
+ { QSERDES_COM_PLLLOCK_CMP1, 0x2b },
+ { QSERDES_COM_PLLLOCK_CMP2, 0x68 },
+ { QSERDES_COM_PLL_CRCTRL, 0xff },
+ { QSERDES_COM_PLL_CP_SETI, 0x3f },
+ { QSERDES_COM_PLL_IP_SETP, 0x07 },
+ { QSERDES_COM_PLL_CP_SETP, 0x03 },
+ { QSERDES_RX_CDR_CONTROL, 0xf3 },
+ { QSERDES_RX_CDR_CONTROL2, 0x6b },
+ { QSERDES_COM_RESETSM_CNTRL, 0x10 },
+ { QSERDES_RX_RX_TERM_HIGHZ_CM_AC_COUPLE, 0x87 },
+ { QSERDES_RX_RX_EQ_GAIN12, 0x54 },
+ { PCIE_PHY_POWER_STATE_CONFIG1, 0xa3 },
+ { PCIE_PHY_POWER_STATE_CONFIG2, 0xcb },
+ { QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10 },
+ { PCIE_PHY_ENDPOINT_REFCLK_DRIVE, 0x10 },
+ { PCIE_PHY_SW_RESET, 0x00 },
+ { PCIE_PHY_START, 0x03 },
+};
+
+static void qcom_pcie_phy_init(struct qcom_pcie_phy *pcie)
+{
+ const struct phy_regs *regs = pcie_phy_regs;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pcie_phy_regs); i++)
+ writel(regs[i].val, pcie->base + regs[i].reg_offset);
+}
+
+static bool qcom_pcie_phy_is_ready(struct qcom_pcie_phy *pcie)
+{
+ u32 val = readl(pcie->base + PCIE_PHY_PCS_STATUS);
+
+ return val & BIT(6) ? false : true;
+}
+
+static int qcom_pcie_phy_power_on(struct phy *phy)
+{
+ struct qcom_pcie_phy *pcie = phy_get_drvdata(phy);
+ struct device *dev = pcie->dev;
+ int ret, retries;
+
+ ret = regulator_enable(pcie->vdda_pll);
+ if (ret) {
+ dev_err(dev, "cannot enable vdda_pll regulator\n");
+ return ret;
+ }
+
+ ret = regulator_enable(pcie->vdda);
+ if (ret) {
+ dev_err(dev, "cannot enable vdda regulator\n");
+ goto fail_vdda_pll;
+ }
+
+ ret = reset_control_deassert(pcie->res_phy);
+ if (ret) {
+ dev_err(dev, "cannot deassert phy reset\n");
+ goto fail_vdda;
+ }
+
+ qcom_pcie_phy_init(pcie);
+
+ usleep_range(PHY_DELAY_MIN_US, PHY_DELAY_MAX_US);
+
+ ret = clk_set_rate(pcie->clk, ~0);
+ if (ret) {
+ dev_err(dev, "cannot set pipe clk rate\n");
+ goto fail_res;
+ }
+
+ /*
+ * setting pipe rate takes time, try arbitrary delay before enabling
+ * the clock
+ */
+ retries = PIPE_CLK_RETRIES_COUNT;
+ do {
+ usleep_range(PIPE_CLK_DELAY_MIN_US, PIPE_CLK_DELAY_MAX_US);
+
+ ret = clk_prepare_enable(pcie->clk);
+ if (!ret)
+ break;
+ } while (retries--);
+
+ if (retries < 0) {
+ dev_err(dev, "cannot enable phy clock\n");
+ goto fail_res;
+ }
+
+ retries = PHY_RETRIES_COUNT;
+ do {
+ ret = qcom_pcie_phy_is_ready(pcie);
+ if (ret)
+ break;
+ usleep_range(PHY_DELAY_MIN_US, PHY_DELAY_MAX_US);
+ } while (retries--);
+
+ if (retries < 0) {
+ dev_err(dev, "phy failed to come up\n");
+ ret = -ETIMEDOUT;
+ goto fail;
+ }
+
+ return 0;
+
+fail:
+ clk_disable_unprepare(pcie->clk);
+fail_res:
+ reset_control_assert(pcie->res_phy);
+fail_vdda:
+ regulator_disable(pcie->vdda);
+fail_vdda_pll:
+ regulator_disable(pcie->vdda_pll);
+
+ return ret;
+}
+
+static int qcom_pcie_phy_power_off(struct phy *phy)
+{
+ struct qcom_pcie_phy *pcie = phy_get_drvdata(phy);
+
+ writel(1, pcie->base + PCIE_PHY_SW_RESET);
+ writel(0, pcie->base + PCIE_PHY_POWER_DOWN_CONTROL);
+
+ reset_control_assert(pcie->res_phy);
+ clk_disable_unprepare(pcie->clk);
+ regulator_disable(pcie->vdda);
+ regulator_disable(pcie->vdda_pll);
+
+ return 0;
+}
+
+static struct phy_ops qcom_pcie_phy_ops = {
+ .power_on = qcom_pcie_phy_power_on,
+ .power_off = qcom_pcie_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int qcom_pcie_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct phy_provider *provider;
+ struct qcom_pcie_phy *pcie;
+ struct resource *res;
+ struct phy *phy;
+
+ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
+ if (!pcie)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ pcie->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(pcie->base))
+ return PTR_ERR(pcie->base);
+
+ pcie->clk = devm_clk_get(dev, "core");
+ if (IS_ERR(pcie->clk)) {
+ dev_err(dev, "failed to get pcie phy clock\n");
+ return PTR_ERR(pcie->clk);
+ }
+
+ pcie->vdda = devm_regulator_get(dev, "vdda");
+ if (IS_ERR(pcie->vdda)) {
+ dev_err(dev, "failed to get vdda regulator\n");
+ return PTR_ERR(pcie->vdda);
+ }
+
+ pcie->vdda_pll = devm_regulator_get(dev, "vdda_pll");
+ if (IS_ERR(pcie->vdda_pll)) {
+ dev_err(dev, "failed to get vdda_pll regulator\n");
+ return PTR_ERR(pcie->vdda_pll);
+ }
+
+ pcie->res_phy = devm_reset_control_get(dev, "phy");
+ if (IS_ERR(pcie->res_phy)) {
+ dev_err(dev, "cannot get phy reset controller");
+ return PTR_ERR(pcie->res_phy);
+ }
+
+ phy = devm_phy_create(dev, NULL, &qcom_pcie_phy_ops, NULL);
+ if (IS_ERR(phy)) {
+ dev_err(dev, "failed to create phy\n");
+ return PTR_ERR(phy);
+ }
+
+ provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(provider)) {
+ dev_err(dev, "failed to register phy provider\n");
+ return PTR_ERR(provider);
+ }
+
+ pcie->dev = dev;
+ phy_set_drvdata(phy, pcie);
+ platform_set_drvdata(pdev, pcie);
+
+ return 0;
+}
+
+static int qcom_pcie_phy_remove(struct platform_device *pdev)
+{
+ struct qcom_pcie_phy *pcie = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(pcie->clk);
+
+ return 0;
+}
+
+static const struct of_device_id qcom_pcie_phy_of_match[] = {
+ { .compatible = "qcom,pcie-phy" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, qcom_pcie_phy_of_match);
+
+static struct platform_driver qcom_pcie_phy_driver = {
+ .probe = qcom_pcie_phy_probe,
+ .remove = qcom_pcie_phy_remove,
+ .driver = {
+ .name = "pcie-phy",
+ .of_match_table = qcom_pcie_phy_of_match,
+ }
+};
+module_platform_driver(qcom_pcie_phy_driver);
+
+MODULE_AUTHOR("Stanimir Varbanov <svarbanov@mm-sol.com>");
+MODULE_DESCRIPTION("QCOM PCIe PHY driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:pcie-phy");
--
1.7.0.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/5] DT: PCI: qcom: Document PCIe devicetree bindings
2014-12-12 17:13 [PATCH 0/5] Qualcomm PCIe and PCIe/PHY drivers Stanimir Varbanov
2014-12-12 17:13 ` [PATCH 1/5] DT: phy: qcom: Add PCIe PHY devicetree bindings Stanimir Varbanov
2014-12-12 17:13 ` [PATCH 2/5] phy: qcom: Add Qualcomm PCIe PHY Stanimir Varbanov
@ 2014-12-12 17:13 ` Stanimir Varbanov
2014-12-12 17:14 ` [PATCH 4/5] PCI: qcom: Add Qualcomm PCIe controller driver Stanimir Varbanov
2014-12-12 17:14 ` [PATCH 5/5] ARM: qcom: Add Qualcomm APQ8084 SoC Stanimir Varbanov
4 siblings, 0 replies; 14+ messages in thread
From: Stanimir Varbanov @ 2014-12-12 17:13 UTC (permalink / raw)
To: linux-arm-kernel
Document Qualcomm PCIe driver devicetree bindings.
Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
---
.../devicetree/bindings/pci/qcom,pcie.txt | 159 ++++++++++++++++++++
1 files changed, 159 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
new file mode 100644
index 0000000..2331144
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -0,0 +1,159 @@
+* Qualcomm PCI express root complex
+
+- compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Value shall include "qcom,pcie"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: Four register ranges as listed in the reg-names property
+
+- reg-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Must include the following entries
+ - "parf" Qualcomm specific registers
+ - "dbi" Designware PCIe registers
+ - "elbi" External local bus interface registers
+ - "config" PCIe configuration space
+
+- device_type:
+ Usage: required
+ Value type: <string>
+ Definition: Should be "pci". As specified in designware-pcie.txt
+
+- #address-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: Should be set to 3. As specified in designware-pcie.txt
+
+- #size-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: Should be set 2. As specified in designware-pcie.txt
+
+- ranges:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: As specified in designware-pcie.txt
+
+- interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: MSI interrupt
+
+- interrupt-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Should contain "msi"
+
+- #interrupt-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: Should be 1. As specified in designware-pcie.txt
+
+- interrupt-map-mask:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: As specified in designware-pcie.txt
+
+- interrupt-map:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: As specified in designware-pcie.txt
+
+- clocks:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: Four clocks as listed in clock-names property
+
+- clock-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Must include the following entries
+ - "aux" auxiliary (AUX) clock
+ - "iface" configuration AHB clock
+ - "bus_master" master AXI clock
+ - "bus_slave" slave AXI clock
+
+- resets:
+ Usage: required
+ Value type: <phandle>
+ Definition: List of phandle and reset specifier pairs as listed
+ in reset-names property
+
+- reset-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Should contain the following entries
+ - "core" core reset
+
+- <name>-supply:
+ Usage: required
+ Value type: <phandle>
+ Definition: List of phandles to the supply regulators
+ - "vdd_pc" collapsing and restoring power to peripheral
+- gpios:
+ Usage: optional
+ Value type: <phandle>
+ Definition: List of phandle and gpio specifier. Should include
+ - "perst" PCIe endpoint reset signal line
+ - "pewake" PCIe endpoint wake signal line
+
+- pinctrl-0:
+ Usage: required
+ Value type: <phandle>
+ Definition: List of phandles pointing at a pin(s) configuration
+
+- pinctrl-names
+ Usage: required
+ Value type: <stringlist>
+ Definition: List of names of pinctrl-0 state
+
+* Example
+
+ pcie0 at fc520000 {
+ compatible = "qcom,pcie";
+ reg = <0xfc520000 0x2000>,
+ <0xff000000 0x1000>,
+ <0xff001000 0x1000>,
+ <0xff002000 0x2000>;
+ reg-names = "parf", "dbi", "elbi", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */
+ 0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* Memory */
+ interrupts = <0 243 0>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
+ clock-names = "aux", "iface", "master_bus", "slave_bus";
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "core";
+
+ vdd_pc-supply = <&gdsc_pcie0>;
+
+ phys = <&pciephy0>;
+ phy-names = "pciephy";
+
+ gpios = <&tlmm 70 0>; /* perst */
+
+ pinctrl-0 = <&pcie0_pins_default>;
+ pinctrl-names = "default";
+ };
--
1.7.0.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/5] PCI: qcom: Add Qualcomm PCIe controller driver
2014-12-12 17:13 [PATCH 0/5] Qualcomm PCIe and PCIe/PHY drivers Stanimir Varbanov
` (2 preceding siblings ...)
2014-12-12 17:13 ` [PATCH 3/5] DT: PCI: qcom: Document PCIe devicetree bindings Stanimir Varbanov
@ 2014-12-12 17:14 ` Stanimir Varbanov
2014-12-12 17:30 ` Arnd Bergmann
2015-01-12 18:20 ` Bjorn Helgaas
2014-12-12 17:14 ` [PATCH 5/5] ARM: qcom: Add Qualcomm APQ8084 SoC Stanimir Varbanov
4 siblings, 2 replies; 14+ messages in thread
From: Stanimir Varbanov @ 2014-12-12 17:14 UTC (permalink / raw)
To: linux-arm-kernel
The PCIe driver reuse the Designware common code for host
and MSI initialization, and also program the Qualcomm
application specific registers.
Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
---
drivers/pci/host/Kconfig | 9 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-qcom.c | 415 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 425 insertions(+), 0 deletions(-)
create mode 100644 drivers/pci/host/pcie-qcom.c
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index c4b6568..1b138c1 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -102,4 +102,13 @@ config PCI_LAYERSCAPE
help
Say Y here if you want PCIe controller support on Layerscape SoCs.
+config PCIE_QCOM
+ bool "Qualcomm PCIe controller"
+ depends on ARCH_QCOM && OF || (ARM && COMPILE_TEST)
+ select PCIE_DW
+ select PCIEPORTBUS
+ help
+ Say Y here to enable PCIe controller support on Qualcomm SoCs. The
+ PCIe controller use Designware core plus Qualcomm specific hardware
+ wrappers.
endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 44c2699..c45971a 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o
obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
+obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
diff --git a/drivers/pci/host/pcie-qcom.c b/drivers/pci/host/pcie-qcom.c
new file mode 100644
index 0000000..cc7df56
--- /dev/null
+++ b/drivers/pci/host/pcie-qcom.c
@@ -0,0 +1,415 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_gpio.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regulator/consumer.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#include "pcie-designware.h"
+
+#define PCIE20_PARF_DBI_BASE_ADDR 0x168
+#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16c
+#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
+
+#define PCIE20_ELBI_SYS_CTRL 0x04
+#define PCIE20_ELBI_SYS_STTS 0x08
+#define XMLH_LINK_UP BIT(10)
+
+#define PCIE20_CAP 0x70
+#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10)
+
+#define PERST_DELAY_MIN_US 1000
+#define PERST_DELAY_MAX_US 1005
+
+#define LINKUP_DELAY_MIN_US 5000
+#define LINKUP_DELAY_MAX_US 5100
+#define LINKUP_RETRIES_COUNT 20
+
+struct qcom_pcie {
+ struct pcie_port pp;
+ struct device *dev;
+ struct regulator *vdd_pc;
+ struct clk *aux;
+ struct clk *iface;
+ struct clk *master_bus;
+ struct clk *slave_bus;
+ struct clk *pipe;
+ struct reset_control *res_core;
+ void __iomem *parf;
+ void __iomem *dbi;
+ void __iomem *elbi;
+ struct phy *phy;
+ int reset_gpio;
+};
+
+#define to_qcom_pcie(x) container_of(x, struct qcom_pcie, pp)
+
+static inline void
+writel_masked(void __iomem *addr, u32 clear_mask, u32 set_mask)
+{
+ u32 val = readl(addr);
+
+ val &= ~clear_mask;
+ val |= set_mask;
+ writel(val, addr);
+}
+
+static void qcom_ep_reset_assert_deassert(struct qcom_pcie *pcie, int assert)
+{
+ if (pcie->reset_gpio < 0)
+ return;
+
+ if (assert)
+ gpio_set_value(pcie->reset_gpio, 0);
+ else
+ gpio_set_value(pcie->reset_gpio, 1);
+
+ usleep_range(PERST_DELAY_MIN_US, PERST_DELAY_MAX_US);
+}
+
+static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
+{
+ qcom_ep_reset_assert_deassert(pcie, 1);
+}
+
+static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
+{
+ qcom_ep_reset_assert_deassert(pcie, 0);
+}
+
+static irqreturn_t qcom_pcie_msi_irq_handler(int irq, void *arg)
+{
+ struct pcie_port *pp = arg;
+
+ return dw_handle_msi_irq(pp);
+}
+
+static int qcom_pcie_link_up(struct pcie_port *pp)
+{
+ struct qcom_pcie *pcie = to_qcom_pcie(pp);
+ u32 val = readl(pcie->dbi + PCIE20_CAP_LINKCTRLSTATUS);
+
+ return val & BIT(29) ? 1 : 0;
+}
+
+static void qcom_pcie_disable_resources(struct qcom_pcie *pcie)
+{
+ reset_control_assert(pcie->res_core);
+ clk_disable_unprepare(pcie->slave_bus);
+ clk_disable_unprepare(pcie->master_bus);
+ clk_disable_unprepare(pcie->iface);
+ clk_disable_unprepare(pcie->aux);
+ regulator_disable(pcie->vdd_pc);
+}
+
+static int qcom_pcie_enable_resources(struct qcom_pcie *pcie)
+{
+ struct device *dev = pcie->dev;
+ int ret;
+
+ ret = regulator_enable(pcie->vdd_pc);
+ if (ret) {
+ dev_err(dev, "cannot enable vdd_pc regulator\n");
+ return ret;
+ }
+
+ ret = regulator_set_mode(pcie->vdd_pc, REGULATOR_MODE_NORMAL);
+ if (ret) {
+ dev_err(dev, "cannot set vdd_pc regulator normal mode\n");
+ goto err_reg;
+ }
+
+ ret = reset_control_deassert(pcie->res_core);
+ if (ret) {
+ dev_err(dev, "cannot deassert core reset\n");
+ goto err_reg;
+ }
+
+ ret = clk_prepare_enable(pcie->aux);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable aux clock\n");
+ goto err_res;
+ }
+
+ ret = clk_prepare_enable(pcie->iface);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable iface clock\n");
+ goto err_aux;
+ }
+
+ ret = clk_prepare_enable(pcie->master_bus);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable master_bus clock\n");
+ goto err_iface;
+ }
+
+ ret = clk_prepare_enable(pcie->slave_bus);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable slave_bus clock\n");
+ goto err_master_bus;
+ }
+
+ return 0;
+
+err_master_bus:
+ clk_disable_unprepare(pcie->master_bus);
+err_iface:
+ clk_disable_unprepare(pcie->iface);
+err_aux:
+ clk_disable_unprepare(pcie->aux);
+err_res:
+ reset_control_assert(pcie->res_core);
+err_reg:
+ regulator_disable(pcie->vdd_pc);
+
+ return ret;
+}
+
+static void qcom_pcie_host_init(struct pcie_port *pp)
+{
+ struct qcom_pcie *pcie = to_qcom_pcie(pp);
+ struct device *dev = pp->dev;
+ int retries, ret;
+ u32 val;
+
+ qcom_ep_reset_assert(pcie);
+
+ ret = qcom_pcie_enable_resources(pcie);
+ if (ret)
+ goto err_assert;
+
+ /* change DBI base address */
+ writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
+
+ if (IS_ENABLED(CONFIG_PCI_MSI))
+ writel_masked(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT,
+ 0, BIT(31));
+
+ ret = phy_init(pcie->phy);
+ if (ret)
+ goto err_res;
+
+ ret = phy_power_on(pcie->phy);
+ if (ret)
+ goto err_phy;
+
+ dw_pcie_setup_rc(pp);
+
+ if (IS_ENABLED(CONFIG_PCI_MSI))
+ dw_pcie_msi_init(pp);
+
+ qcom_ep_reset_deassert(pcie);
+
+ /* enable link training */
+ writel_masked(pcie->elbi + PCIE20_ELBI_SYS_CTRL, 0, BIT(0));
+
+ /* wait for up to 100ms for the link to come up */
+ retries = LINKUP_RETRIES_COUNT;
+ do {
+ val = readl(pcie->elbi + PCIE20_ELBI_SYS_STTS);
+ if (val & XMLH_LINK_UP)
+ break;
+ usleep_range(LINKUP_DELAY_MIN_US, LINKUP_DELAY_MAX_US);
+ } while (retries--);
+
+ if (retries < 0 || !dw_pcie_link_up(pp)) {
+ dev_err(dev, "link initialization failed\n");
+ goto err;
+ }
+
+ return;
+
+err:
+ phy_power_off(pcie->phy);
+err_phy:
+ phy_exit(pcie->phy);
+err_res:
+ qcom_pcie_disable_resources(pcie);
+err_assert:
+ qcom_ep_reset_assert(pcie);
+}
+
+static int
+qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, u32 *val)
+{
+ if (where == PCI_CLASS_REVISION && size == 4) {
+ *val = readl(pp->dbi_base + PCI_CLASS_REVISION);
+ *val &= ~(0xffff << 16);
+ *val |= PCI_CLASS_BRIDGE_PCI << 16;
+ return PCIBIOS_SUCCESSFUL;
+ }
+
+ return dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
+ size, val);
+}
+
+static struct pcie_host_ops qcom_pcie_host_ops = {
+ .link_up = qcom_pcie_link_up,
+ .host_init = qcom_pcie_host_init,
+ .rd_own_conf = qcom_pcie_rd_own_conf,
+};
+
+static int __init qcom_pcie_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct resource *res;
+ struct qcom_pcie *pcie;
+ struct pcie_port *pp;
+ enum of_gpio_flags gp_flags;
+ int ret;
+
+ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
+ if (!pcie)
+ return -ENOMEM;
+
+ pcie->reset_gpio = of_get_gpio_flags(np, 0, &gp_flags);
+ if (pcie->reset_gpio > 0) {
+ ret = devm_gpio_request_one(dev, pcie->reset_gpio, gp_flags,
+ "perst");
+ if (ret < 0)
+ return ret;
+ }
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
+ pcie->parf = devm_ioremap_resource(dev, res);
+ if (IS_ERR(pcie->parf))
+ return PTR_ERR(pcie->parf);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
+ pcie->dbi = devm_ioremap_resource(dev, res);
+ if (IS_ERR(pcie->dbi))
+ return PTR_ERR(pcie->dbi);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
+ pcie->elbi = devm_ioremap_resource(dev, res);
+ if (IS_ERR(pcie->elbi))
+ return PTR_ERR(pcie->elbi);
+
+ pcie->phy = devm_phy_get(dev, "pciephy");
+ if (IS_ERR(pcie->phy))
+ return PTR_ERR(pcie->phy);
+
+ pcie->aux = devm_clk_get(dev, "aux");
+ if (IS_ERR(pcie->aux)) {
+ dev_err(dev, "failed to get aux clock\n");
+ return PTR_ERR(pcie->aux);
+ }
+
+ pcie->iface = devm_clk_get(dev, "iface");
+ if (IS_ERR(pcie->iface)) {
+ dev_err(dev, "failed to get iface clock\n");
+ return PTR_ERR(pcie->iface);
+ }
+
+ pcie->master_bus = devm_clk_get(dev, "master_bus");
+ if (IS_ERR(pcie->master_bus)) {
+ dev_err(dev, "failed to get master_bus clock\n");
+ return PTR_ERR(pcie->master_bus);
+ }
+
+ pcie->slave_bus = devm_clk_get(dev, "slave_bus");
+ if (IS_ERR(pcie->slave_bus)) {
+ dev_err(dev, "failed to get slave_bus clock\n");
+ return PTR_ERR(pcie->slave_bus);
+ }
+
+ pcie->vdd_pc = devm_regulator_get(dev, "vdd_pc");
+ if (IS_ERR(pcie->vdd_pc)) {
+ dev_err(dev, "failed to get vdd_pc regulator\n");
+ return PTR_ERR(pcie->vdd_pc);
+ }
+
+ pcie->res_core = devm_reset_control_get(dev, "core");
+ if (IS_ERR(pcie->res_core)) {
+ dev_err(dev, "cannot get core reset controller");
+ return PTR_ERR(pcie->res_core);
+ }
+
+ pcie->dev = dev;
+ pp = &pcie->pp;
+ pp->dev = dev;
+ pp->dbi_base = pcie->dbi;
+ pp->root_bus_nr = -1;
+ pp->ops = &qcom_pcie_host_ops;
+
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
+ pp->msi_irq = platform_get_irq_byname(pdev, "msi");
+ if (pp->msi_irq < 0) {
+ dev_err(dev, "failed to get msi irq\n");
+ return pp->msi_irq;
+ }
+
+ ret = devm_request_irq(dev, pp->msi_irq,
+ qcom_pcie_msi_irq_handler,
+ IRQF_SHARED, "qcom-pcie-msi", pp);
+ if (ret) {
+ dev_err(dev, "failed to request msi irq\n");
+ return ret;
+ }
+ }
+
+ ret = dw_pcie_host_init(pp);
+ if (ret) {
+ dev_err(dev, "failed to initialize host\n");
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, pcie);
+
+ return 0;
+}
+
+static int qcom_pcie_remove(struct platform_device *pdev)
+{
+ struct qcom_pcie *pcie = platform_get_drvdata(pdev);
+
+ qcom_ep_reset_assert(pcie);
+ phy_power_off(pcie->phy);
+ phy_exit(pcie->phy);
+ qcom_pcie_disable_resources(pcie);
+
+ return 0;
+}
+
+static struct of_device_id qcom_pcie_match[] = {
+ { .compatible = "qcom,pcie", },
+ { }
+};
+
+static struct platform_driver __refdata qcom_pcie_driver = {
+ .probe = qcom_pcie_probe,
+ .remove = qcom_pcie_remove,
+ .driver = {
+ .name = "qcom-pcie",
+ .of_match_table = qcom_pcie_match,
+ },
+};
+
+module_platform_driver(qcom_pcie_driver);
+
+MODULE_AUTHOR("Stanimir Varbanov <svarbanov@mm-sol.com>");
+MODULE_DESCRIPTION("Qualcomm PCIe root complex driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:qcom-pcie");
--
1.7.0.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 5/5] ARM: qcom: Add Qualcomm APQ8084 SoC
2014-12-12 17:13 [PATCH 0/5] Qualcomm PCIe and PCIe/PHY drivers Stanimir Varbanov
` (3 preceding siblings ...)
2014-12-12 17:14 ` [PATCH 4/5] PCI: qcom: Add Qualcomm PCIe controller driver Stanimir Varbanov
@ 2014-12-12 17:14 ` Stanimir Varbanov
2014-12-12 17:33 ` Arnd Bergmann
4 siblings, 1 reply; 14+ messages in thread
From: Stanimir Varbanov @ 2014-12-12 17:14 UTC (permalink / raw)
To: linux-arm-kernel
This adds Snapdragon 805 ARM-based SoC as multiplatform
compatible platform.
Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
---
arch/arm/mach-qcom/Kconfig | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig
index ee5697b..b8abe7d 100644
--- a/arch/arm/mach-qcom/Kconfig
+++ b/arch/arm/mach-qcom/Kconfig
@@ -23,6 +23,13 @@ config ARCH_MSM8974
bool "Enable support for MSM8974"
select HAVE_ARM_ARCH_TIMER
+config ARCH_APQ8084
+ bool "Enable support for APQ8084"
+ select HAVE_ARM_ARCH_TIMER
+ select PCI
+ select PCI_DOMAINS
+ select PCI_MSI
+
config QCOM_SCM
bool
--
1.7.0.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/5] PCI: qcom: Add Qualcomm PCIe controller driver
2014-12-12 17:14 ` [PATCH 4/5] PCI: qcom: Add Qualcomm PCIe controller driver Stanimir Varbanov
@ 2014-12-12 17:30 ` Arnd Bergmann
2014-12-16 9:43 ` Stanimir Varbanov
2015-01-12 18:20 ` Bjorn Helgaas
1 sibling, 1 reply; 14+ messages in thread
From: Arnd Bergmann @ 2014-12-12 17:30 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 12 December 2014 19:14:00 Stanimir Varbanov wrote:
> The PCIe driver reuse the Designware common code for host
> and MSI initialization, and also program the Qualcomm
> application specific registers.
>
> Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
Looks nice!
> +static int
> +qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, u32 *val)
> +{
> + if (where == PCI_CLASS_REVISION && size == 4) {
> + *val = readl(pp->dbi_base + PCI_CLASS_REVISION);
> + *val &= ~(0xffff << 16);
> + *val |= PCI_CLASS_BRIDGE_PCI << 16;
> + return PCIBIOS_SUCCESSFUL;
> + }
> +
> + return dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
> + size, val);
> +}
Could you add a comment here to explain what this is for?
> +static int __init qcom_pcie_probe(struct platform_device *pdev)
> +{
I think it's a bug to mark this function as __init. It breaks
deferred probing and detaching/reattaching the device trough sysfs.
After you fix that, you can remove the __refdata below.
> +static struct platform_driver __refdata qcom_pcie_driver = {
> + .probe = qcom_pcie_probe,
> + .remove = qcom_pcie_remove,
> + .driver = {
> + .name = "qcom-pcie",
> + .of_match_table = qcom_pcie_match,
> + },
> +};
Arnd
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 5/5] ARM: qcom: Add Qualcomm APQ8084 SoC
2014-12-12 17:14 ` [PATCH 5/5] ARM: qcom: Add Qualcomm APQ8084 SoC Stanimir Varbanov
@ 2014-12-12 17:33 ` Arnd Bergmann
2015-01-06 15:24 ` Stanimir Varbanov
0 siblings, 1 reply; 14+ messages in thread
From: Arnd Bergmann @ 2014-12-12 17:33 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 12 December 2014 19:14:01 Stanimir Varbanov wrote:
> +config ARCH_APQ8084
> + bool "Enable support for APQ8084"
> + select HAVE_ARM_ARCH_TIMER
> + select PCI
> + select PCI_DOMAINS
> + select PCI_MSI
> +
I would prefer not to see 'select PCI' here. Also the driver is written
to work without PCI_MSI, so I'd be much happier with just
config ARCH_APQ8084
bool "Enable support for APQ8084"
select HAVE_ARM_ARCH_TIMER
select PCI_DOMAINS if PCI
but you could even drop the last line if it's possible that some machines
enable only one host bridge.
Arnd
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 4/5] PCI: qcom: Add Qualcomm PCIe controller driver
2014-12-12 17:30 ` Arnd Bergmann
@ 2014-12-16 9:43 ` Stanimir Varbanov
2014-12-16 9:54 ` Arnd Bergmann
0 siblings, 1 reply; 14+ messages in thread
From: Stanimir Varbanov @ 2014-12-16 9:43 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd,
Thanks for the comments!
On 12/12/2014 07:30 PM, Arnd Bergmann wrote:
> On Friday 12 December 2014 19:14:00 Stanimir Varbanov wrote:
>> The PCIe driver reuse the Designware common code for host
>> and MSI initialization, and also program the Qualcomm
>> application specific registers.
>>
>> Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
>
> Looks nice!
>
>> +static int
>> +qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, u32 *val)
>> +{
>> + if (where == PCI_CLASS_REVISION && size == 4) {
>> + *val = readl(pp->dbi_base + PCI_CLASS_REVISION);
>> + *val &= ~(0xffff << 16);
>> + *val |= PCI_CLASS_BRIDGE_PCI << 16;
>> + return PCIBIOS_SUCCESSFUL;
>> + }
>> +
>> + return dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
>> + size, val);
>> +}
>
> Could you add a comment here to explain what this is for?
Sure I will add a comment. The issue is that the pci device class is not
reported correctly from the register.
>
>> +static int __init qcom_pcie_probe(struct platform_device *pdev)
>> +{
>
> I think it's a bug to mark this function as __init. It breaks
> deferred probing and detaching/reattaching the device trough sysfs.
>
My bad, I have tried to avoid mismatch section warnings came up from
dw_pcie_host_init() which is annotated as __init. Do you think we need
to remove __init from dw_pcie_host_init() declaration and fix the
drivers accordingly?
> After you fix that, you can remove the __refdata below.
>
>> +static struct platform_driver __refdata qcom_pcie_driver = {
>> + .probe = qcom_pcie_probe,
>> + .remove = qcom_pcie_remove,
>> + .driver = {
>> + .name = "qcom-pcie",
>> + .of_match_table = qcom_pcie_match,
>> + },
>> +};
>
> Arnd
>
regards,
Stan
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 4/5] PCI: qcom: Add Qualcomm PCIe controller driver
2014-12-16 9:43 ` Stanimir Varbanov
@ 2014-12-16 9:54 ` Arnd Bergmann
0 siblings, 0 replies; 14+ messages in thread
From: Arnd Bergmann @ 2014-12-16 9:54 UTC (permalink / raw)
To: linux-arm-kernel
On Tuesday 16 December 2014 11:43:12 Stanimir Varbanov wrote:
> >> +static int __init qcom_pcie_probe(struct platform_device *pdev)
> >> +{
> >
> > I think it's a bug to mark this function as __init. It breaks
> > deferred probing and detaching/reattaching the device trough sysfs.
> >
>
> My bad, I have tried to avoid mismatch section warnings came up from
> dw_pcie_host_init() which is annotated as __init. Do you think we need
> to remove __init from dw_pcie_host_init() declaration and fix the
> drivers accordingly?
Yes, that's probably best. Initially, it was ok because all front-ends
of the dw-pcie driver were using module_platform_probe(), but that
is not the case any more, so now at least keystone, layerscape and
spear13xx are broken, and I think it's safer to change dw_pcie_host_init
than to rely on everyone using module_platform_probe() correctly.
Arnd
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 5/5] ARM: qcom: Add Qualcomm APQ8084 SoC
2014-12-12 17:33 ` Arnd Bergmann
@ 2015-01-06 15:24 ` Stanimir Varbanov
0 siblings, 0 replies; 14+ messages in thread
From: Stanimir Varbanov @ 2015-01-06 15:24 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd,
Thanks for the comments!
On 12/12/2014 07:33 PM, Arnd Bergmann wrote:
> On Friday 12 December 2014 19:14:01 Stanimir Varbanov wrote:
>> +config ARCH_APQ8084
>> + bool "Enable support for APQ8084"
>> + select HAVE_ARM_ARCH_TIMER
>> + select PCI
>> + select PCI_DOMAINS
>> + select PCI_MSI
>> +
>
> I would prefer not to see 'select PCI' here. Also the driver is written
> to work without PCI_MSI, so I'd be much happier with just
>
> config ARCH_APQ8084
> bool "Enable support for APQ8084"
> select HAVE_ARM_ARCH_TIMER
> select PCI_DOMAINS if PCI
What about this
config ARCH_APQ8084
bool "Enable support for APQ8084"
select HAVE_ARM_ARCH_TIMER
select MIGHT_HAVE_PCI
select PCI_DOMAINS if PCI
--
regards,
Stan
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 4/5] PCI: qcom: Add Qualcomm PCIe controller driver
2014-12-12 17:14 ` [PATCH 4/5] PCI: qcom: Add Qualcomm PCIe controller driver Stanimir Varbanov
2014-12-12 17:30 ` Arnd Bergmann
@ 2015-01-12 18:20 ` Bjorn Helgaas
1 sibling, 0 replies; 14+ messages in thread
From: Bjorn Helgaas @ 2015-01-12 18:20 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Dec 12, 2014 at 07:14:00PM +0200, Stanimir Varbanov wrote:
> The PCIe driver reuse the Designware common code for host
> and MSI initialization, and also program the Qualcomm
> application specific registers.
>
> Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
> ---
> drivers/pci/host/Kconfig | 9 +
> drivers/pci/host/Makefile | 1 +
> drivers/pci/host/pcie-qcom.c | 415 ++++++++++++++++++++++++++++++++++++++++++
Hi Stanimir,
Can you also add a MAINTAINERS update so I'll know who should ack changes
to this driver?
Bjorn
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 2/5] phy: qcom: Add Qualcomm PCIe PHY
2014-12-12 17:13 ` [PATCH 2/5] phy: qcom: Add Qualcomm PCIe PHY Stanimir Varbanov
@ 2015-01-21 9:11 ` Kishon Vijay Abraham I
2015-01-21 9:52 ` Stanimir Varbanov
0 siblings, 1 reply; 14+ messages in thread
From: Kishon Vijay Abraham I @ 2015-01-21 9:11 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Friday 12 December 2014 10:43 PM, Stanimir Varbanov wrote:
> Add a PCIe PHY driver used by PCIe host controller driver
> on Qualcomm SoCs like Snapdragon 805.
>
> Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
> ---
> drivers/phy/Kconfig | 7 +
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-qcom-pcie.c | 311 +++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 319 insertions(+), 0 deletions(-)
> create mode 100644 drivers/phy/phy-qcom-pcie.c
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 2a436e6..135bdcc 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -218,6 +218,13 @@ config PHY_QCOM_IPQ806X_SATA
> depends on OF
> select GENERIC_PHY
>
> +config PHY_QCOM_PCIE
> + tristate "Qualcomm PCIe SerDes/PHY driver"
> + depends on ARCH_QCOM
> + depends on HAS_IOMEM
> + depends on OF
> + select GENERIC_PHY
Please add a small description about the driver here.
> +
> config PHY_ST_SPEAR1310_MIPHY
> tristate "ST SPEAR1310-MIPHY driver"
> select GENERIC_PHY
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index c4590fc..e7662fb 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -26,6 +26,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
> obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
> obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
> obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
> +obj-$(CONFIG_PHY_QCOM_PCIE) += phy-qcom-pcie.o
> obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
> obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
> obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
> diff --git a/drivers/phy/phy-qcom-pcie.c b/drivers/phy/phy-qcom-pcie.c
> new file mode 100644
> index 0000000..3db348a
> --- /dev/null
> +++ b/drivers/phy/phy-qcom-pcie.c
> @@ -0,0 +1,311 @@
> +/*
> + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +
> +#define QSERDES_COM_PLL_CP_SETI 0x024
> +#define QSERDES_COM_PLL_IP_SETP 0x028
> +#define QSERDES_COM_PLL_CP_SETP 0x02c
> +#define QSERDES_COM_SYSCLK_EN_SEL 0x038
> +#define QSERDES_COM_RESETSM_CNTRL 0x040
> +#define QSERDES_COM_PLLLOCK_CMP1 0x044
> +#define QSERDES_COM_PLLLOCK_CMP2 0x048
> +#define QSERDES_COM_PLLLOCK_CMP_EN 0x050
> +#define QSERDES_COM_DEC_START1 0x064
> +#define QSERDES_COM_DIV_FRAC_START1 0x098
> +#define QSERDES_COM_DIV_FRAC_START2 0x09c
> +#define QSERDES_COM_DIV_FRAC_START3 0x0a0
> +#define QSERDES_COM_DEC_START2 0x0a4
> +#define QSERDES_COM_PLL_RXTXEPCLK_EN 0x0a8
> +#define QSERDES_COM_PLL_CRCTRL 0x0ac
> +
> +#define QSERDES_RX_CDR_CONTROL 0x400
> +#define QSERDES_RX_CDR_CONTROL2 0x410
> +#define QSERDES_RX_RX_TERM_HIGHZ_CM_AC_COUPLE 0x42c
> +#define QSERDES_RX_RX_EQ_GAIN12 0x430
> +
> +#define PCIE_PHY_SW_RESET 0x600
> +#define PCIE_PHY_POWER_DOWN_CONTROL 0x604
> +#define PCIE_PHY_START 0x608
> +#define PCIE_PHY_ENDPOINT_REFCLK_DRIVE 0x648
> +#define PCIE_PHY_POWER_STATE_CONFIG1 0x650
> +#define PCIE_PHY_POWER_STATE_CONFIG2 0x654
> +#define PCIE_PHY_PWRUP_RESET_DLY_TIME_SYSCLK 0x678
> +#define PCIE_PHY_PWRUP_RESET_DLY_TIME_AUXCLK 0x67c
> +#define PCIE_PHY_PCS_STATUS 0x6c8
> +
> +#define PHY_DELAY_MIN_US 995
> +#define PHY_DELAY_MAX_US 1005
> +#define PHY_RETRIES_COUNT 10
> +
> +#define PIPE_CLK_DELAY_MIN_US 5000
> +#define PIPE_CLK_DELAY_MAX_US 5100
> +#define PIPE_CLK_RETRIES_COUNT 10
> +
> +struct qcom_pcie_phy {
> + void __iomem *base;
> + struct clk *clk;
> + struct reset_control *res_phy;
> + struct regulator *vdda_pll;
> + struct regulator *vdda;
> + struct device *dev;
> +};
> +
> +struct phy_regs {
> + u32 reg_offset;
> + u32 val;
> +};
> +
> +static const struct phy_regs pcie_phy_regs[] = {
> + { PCIE_PHY_POWER_DOWN_CONTROL, 0x03 },
> + { QSERDES_COM_SYSCLK_EN_SEL, 0x08 },
> + { QSERDES_COM_DEC_START1, 0x82 },
> + { QSERDES_COM_DEC_START2, 0x03 },
> + { QSERDES_COM_DIV_FRAC_START1, 0xd5 },
> + { QSERDES_COM_DIV_FRAC_START2, 0xaa },
> + { QSERDES_COM_DIV_FRAC_START3, 0x13 },
> + { QSERDES_COM_PLLLOCK_CMP_EN, 0x01 },
> + { QSERDES_COM_PLLLOCK_CMP1, 0x2b },
> + { QSERDES_COM_PLLLOCK_CMP2, 0x68 },
> + { QSERDES_COM_PLL_CRCTRL, 0xff },
> + { QSERDES_COM_PLL_CP_SETI, 0x3f },
> + { QSERDES_COM_PLL_IP_SETP, 0x07 },
> + { QSERDES_COM_PLL_CP_SETP, 0x03 },
> + { QSERDES_RX_CDR_CONTROL, 0xf3 },
> + { QSERDES_RX_CDR_CONTROL2, 0x6b },
> + { QSERDES_COM_RESETSM_CNTRL, 0x10 },
> + { QSERDES_RX_RX_TERM_HIGHZ_CM_AC_COUPLE, 0x87 },
> + { QSERDES_RX_RX_EQ_GAIN12, 0x54 },
> + { PCIE_PHY_POWER_STATE_CONFIG1, 0xa3 },
> + { PCIE_PHY_POWER_STATE_CONFIG2, 0xcb },
> + { QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10 },
> + { PCIE_PHY_ENDPOINT_REFCLK_DRIVE, 0x10 },
> + { PCIE_PHY_SW_RESET, 0x00 },
> + { PCIE_PHY_START, 0x03 },
No magic values for register writes.
> +};
> +
> +static void qcom_pcie_phy_init(struct qcom_pcie_phy *pcie)
> +{
> + const struct phy_regs *regs = pcie_phy_regs;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(pcie_phy_regs); i++)
> + writel(regs[i].val, pcie->base + regs[i].reg_offset);
> +}
> +
> +static bool qcom_pcie_phy_is_ready(struct qcom_pcie_phy *pcie)
> +{
> + u32 val = readl(pcie->base + PCIE_PHY_PCS_STATUS);
> +
> + return val & BIT(6) ? false : true;
> +}
> +
> +static int qcom_pcie_phy_power_on(struct phy *phy)
> +{
> + struct qcom_pcie_phy *pcie = phy_get_drvdata(phy);
> + struct device *dev = pcie->dev;
> + int ret, retries;
> +
> + ret = regulator_enable(pcie->vdda_pll);
> + if (ret) {
> + dev_err(dev, "cannot enable vdda_pll regulator\n");
> + return ret;
> + }
> +
> + ret = regulator_enable(pcie->vdda);
> + if (ret) {
> + dev_err(dev, "cannot enable vdda regulator\n");
> + goto fail_vdda_pll;
> + }
> +
> + ret = reset_control_deassert(pcie->res_phy);
> + if (ret) {
> + dev_err(dev, "cannot deassert phy reset\n");
> + goto fail_vdda;
> + }
> +
> + qcom_pcie_phy_init(pcie);
> +
> + usleep_range(PHY_DELAY_MIN_US, PHY_DELAY_MAX_US);
add a comment on why this delay is required.
> +
> + ret = clk_set_rate(pcie->clk, ~0);
What is the actual clock rate?
> + if (ret) {
> + dev_err(dev, "cannot set pipe clk rate\n");
> + goto fail_res;
> + }
> +
> + /*
> + * setting pipe rate takes time, try arbitrary delay before enabling
> + * the clock
> + */
> + retries = PIPE_CLK_RETRIES_COUNT;
> + do {
> + usleep_range(PIPE_CLK_DELAY_MIN_US, PIPE_CLK_DELAY_MAX_US);
> +
> + ret = clk_prepare_enable(pcie->clk);
> + if (!ret)
> + break;
> + } while (retries--);
> +
> + if (retries < 0) {
> + dev_err(dev, "cannot enable phy clock\n");
> + goto fail_res;
> + }
> +
> + retries = PHY_RETRIES_COUNT;
> + do {
> + ret = qcom_pcie_phy_is_ready(pcie);
> + if (ret)
> + break;
> + usleep_range(PHY_DELAY_MIN_US, PHY_DELAY_MAX_US);
> + } while (retries--);
> +
> + if (retries < 0) {
> + dev_err(dev, "phy failed to come up\n");
> + ret = -ETIMEDOUT;
> + goto fail;
> + }
> +
> + return 0;
> +
> +fail:
> + clk_disable_unprepare(pcie->clk);
> +fail_res:
> + reset_control_assert(pcie->res_phy);
> +fail_vdda:
> + regulator_disable(pcie->vdda);
> +fail_vdda_pll:
> + regulator_disable(pcie->vdda_pll);
> +
> + return ret;
> +}
> +
> +static int qcom_pcie_phy_power_off(struct phy *phy)
> +{
> + struct qcom_pcie_phy *pcie = phy_get_drvdata(phy);
> +
> + writel(1, pcie->base + PCIE_PHY_SW_RESET);
> + writel(0, pcie->base + PCIE_PHY_POWER_DOWN_CONTROL);
> +
> + reset_control_assert(pcie->res_phy);
> + clk_disable_unprepare(pcie->clk);
> + regulator_disable(pcie->vdda);
> + regulator_disable(pcie->vdda_pll);
> +
> + return 0;
> +}
> +
> +static struct phy_ops qcom_pcie_phy_ops = {
> + .power_on = qcom_pcie_phy_power_on,
> + .power_off = qcom_pcie_phy_power_off,
> + .owner = THIS_MODULE,
> +};
> +
> +static int qcom_pcie_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct phy_provider *provider;
> + struct qcom_pcie_phy *pcie;
> + struct resource *res;
> + struct phy *phy;
> +
> + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
> + if (!pcie)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + pcie->base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(pcie->base))
> + return PTR_ERR(pcie->base);
> +
> + pcie->clk = devm_clk_get(dev, "core");
> + if (IS_ERR(pcie->clk)) {
> + dev_err(dev, "failed to get pcie phy clock\n");
> + return PTR_ERR(pcie->clk);
> + }
> +
> + pcie->vdda = devm_regulator_get(dev, "vdda");
> + if (IS_ERR(pcie->vdda)) {
> + dev_err(dev, "failed to get vdda regulator\n");
> + return PTR_ERR(pcie->vdda);
> + }
> +
> + pcie->vdda_pll = devm_regulator_get(dev, "vdda_pll");
> + if (IS_ERR(pcie->vdda_pll)) {
> + dev_err(dev, "failed to get vdda_pll regulator\n");
> + return PTR_ERR(pcie->vdda_pll);
> + }
> +
> + pcie->res_phy = devm_reset_control_get(dev, "phy");
> + if (IS_ERR(pcie->res_phy)) {
> + dev_err(dev, "cannot get phy reset controller");
> + return PTR_ERR(pcie->res_phy);
> + }
> +
> + phy = devm_phy_create(dev, NULL, &qcom_pcie_phy_ops, NULL);
Please rebase it to the latest kernel.
Thanks
Kishon
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 2/5] phy: qcom: Add Qualcomm PCIe PHY
2015-01-21 9:11 ` Kishon Vijay Abraham I
@ 2015-01-21 9:52 ` Stanimir Varbanov
0 siblings, 0 replies; 14+ messages in thread
From: Stanimir Varbanov @ 2015-01-21 9:52 UTC (permalink / raw)
To: linux-arm-kernel
Hi Kishon,
Thanks for the comments!
On 01/21/2015 11:11 AM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Friday 12 December 2014 10:43 PM, Stanimir Varbanov wrote:
>> Add a PCIe PHY driver used by PCIe host controller driver
>> on Qualcomm SoCs like Snapdragon 805.
>>
>> Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
>> ---
>> drivers/phy/Kconfig | 7 +
>> drivers/phy/Makefile | 1 +
>> drivers/phy/phy-qcom-pcie.c | 311 +++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 319 insertions(+), 0 deletions(-)
>> create mode 100644 drivers/phy/phy-qcom-pcie.c
>>
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index 2a436e6..135bdcc 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -218,6 +218,13 @@ config PHY_QCOM_IPQ806X_SATA
>> depends on OF
>> select GENERIC_PHY
>>
>> +config PHY_QCOM_PCIE
>> + tristate "Qualcomm PCIe SerDes/PHY driver"
>> + depends on ARCH_QCOM
>> + depends on HAS_IOMEM
>> + depends on OF
>> + select GENERIC_PHY
>
> Please add a small description about the driver here.
Sure I will.
<snip>
>> +static const struct phy_regs pcie_phy_regs[] = {
>> + { PCIE_PHY_POWER_DOWN_CONTROL, 0x03 },
>> + { QSERDES_COM_SYSCLK_EN_SEL, 0x08 },
>> + { QSERDES_COM_DEC_START1, 0x82 },
>> + { QSERDES_COM_DEC_START2, 0x03 },
>> + { QSERDES_COM_DIV_FRAC_START1, 0xd5 },
>> + { QSERDES_COM_DIV_FRAC_START2, 0xaa },
>> + { QSERDES_COM_DIV_FRAC_START3, 0x13 },
>> + { QSERDES_COM_PLLLOCK_CMP_EN, 0x01 },
>> + { QSERDES_COM_PLLLOCK_CMP1, 0x2b },
>> + { QSERDES_COM_PLLLOCK_CMP2, 0x68 },
>> + { QSERDES_COM_PLL_CRCTRL, 0xff },
>> + { QSERDES_COM_PLL_CP_SETI, 0x3f },
>> + { QSERDES_COM_PLL_IP_SETP, 0x07 },
>> + { QSERDES_COM_PLL_CP_SETP, 0x03 },
>> + { QSERDES_RX_CDR_CONTROL, 0xf3 },
>> + { QSERDES_RX_CDR_CONTROL2, 0x6b },
>> + { QSERDES_COM_RESETSM_CNTRL, 0x10 },
>> + { QSERDES_RX_RX_TERM_HIGHZ_CM_AC_COUPLE, 0x87 },
>> + { QSERDES_RX_RX_EQ_GAIN12, 0x54 },
>> + { PCIE_PHY_POWER_STATE_CONFIG1, 0xa3 },
>> + { PCIE_PHY_POWER_STATE_CONFIG2, 0xcb },
>> + { QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10 },
>> + { PCIE_PHY_ENDPOINT_REFCLK_DRIVE, 0x10 },
>> + { PCIE_PHY_SW_RESET, 0x00 },
>> + { PCIE_PHY_START, 0x03 },
>
> No magic values for register writes.
Unfortunately these register values are taken as they are in CAF
downstream kernel and there are no bit/fields description for them.
>> +};
>> +
>> +static void qcom_pcie_phy_init(struct qcom_pcie_phy *pcie)
>> +{
>> + const struct phy_regs *regs = pcie_phy_regs;
>> + int i;
>> +
>> + for (i = 0; i < ARRAY_SIZE(pcie_phy_regs); i++)
>> + writel(regs[i].val, pcie->base + regs[i].reg_offset);
>> +}
>> +
>> +static bool qcom_pcie_phy_is_ready(struct qcom_pcie_phy *pcie)
>> +{
>> + u32 val = readl(pcie->base + PCIE_PHY_PCS_STATUS);
>> +
>> + return val & BIT(6) ? false : true;
>> +}
>> +
>> +static int qcom_pcie_phy_power_on(struct phy *phy)
>> +{
>> + struct qcom_pcie_phy *pcie = phy_get_drvdata(phy);
>> + struct device *dev = pcie->dev;
>> + int ret, retries;
>> +
>> + ret = regulator_enable(pcie->vdda_pll);
>> + if (ret) {
>> + dev_err(dev, "cannot enable vdda_pll regulator\n");
>> + return ret;
>> + }
>> +
>> + ret = regulator_enable(pcie->vdda);
>> + if (ret) {
>> + dev_err(dev, "cannot enable vdda regulator\n");
>> + goto fail_vdda_pll;
>> + }
>> +
>> + ret = reset_control_deassert(pcie->res_phy);
>> + if (ret) {
>> + dev_err(dev, "cannot deassert phy reset\n");
>> + goto fail_vdda;
>> + }
>> +
>> + qcom_pcie_phy_init(pcie);
>> +
>> + usleep_range(PHY_DELAY_MIN_US, PHY_DELAY_MAX_US);
>
> add a comment on why this delay is required.
Actually this delay is not required anymore and I will remove it in next
version. The delay which is important here is the delay between
clk_set_rate and clk_prepare_enable.
>> +
>> + ret = clk_set_rate(pcie->clk, ~0);
>
> What is the actual clock rate?
According to clk freq table in clock driver it could be 125Mhz or 250Mhz.
>> + if (ret) {
>> + dev_err(dev, "cannot set pipe clk rate\n");
>> + goto fail_res;
>> + }
>> +
>> + /*
>> + * setting pipe rate takes time, try arbitrary delay before enabling
>> + * the clock
>> + */
>> + retries = PIPE_CLK_RETRIES_COUNT;
>> + do {
>> + usleep_range(PIPE_CLK_DELAY_MIN_US, PIPE_CLK_DELAY_MAX_US);
>> +
>> + ret = clk_prepare_enable(pcie->clk);
>> + if (!ret)
>> + break;
>> + } while (retries--);
>> +
>> + if (retries < 0) {
>> + dev_err(dev, "cannot enable phy clock\n");
>> + goto fail_res;
>> + }
>> +
>> + retries = PHY_RETRIES_COUNT;
>> + do {
>> + ret = qcom_pcie_phy_is_ready(pcie);
>> + if (ret)
>> + break;
>> + usleep_range(PHY_DELAY_MIN_US, PHY_DELAY_MAX_US);
>> + } while (retries--);
>> +
>> + if (retries < 0) {
>> + dev_err(dev, "phy failed to come up\n");
>> + ret = -ETIMEDOUT;
>> + goto fail;
>> + }
>> +
>> + return 0;
>> +
>> +fail:
>> + clk_disable_unprepare(pcie->clk);
>> +fail_res:
>> + reset_control_assert(pcie->res_phy);
>> +fail_vdda:
>> + regulator_disable(pcie->vdda);
>> +fail_vdda_pll:
>> + regulator_disable(pcie->vdda_pll);
>> +
>> + return ret;
>> +}
>> +
<snip>
>> +
>> + phy = devm_phy_create(dev, NULL, &qcom_pcie_phy_ops, NULL);
>
> Please rebase it to the latest kernel.
Already done.
--
regards,
Stan
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2015-01-21 9:52 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-12-12 17:13 [PATCH 0/5] Qualcomm PCIe and PCIe/PHY drivers Stanimir Varbanov
2014-12-12 17:13 ` [PATCH 1/5] DT: phy: qcom: Add PCIe PHY devicetree bindings Stanimir Varbanov
2014-12-12 17:13 ` [PATCH 2/5] phy: qcom: Add Qualcomm PCIe PHY Stanimir Varbanov
2015-01-21 9:11 ` Kishon Vijay Abraham I
2015-01-21 9:52 ` Stanimir Varbanov
2014-12-12 17:13 ` [PATCH 3/5] DT: PCI: qcom: Document PCIe devicetree bindings Stanimir Varbanov
2014-12-12 17:14 ` [PATCH 4/5] PCI: qcom: Add Qualcomm PCIe controller driver Stanimir Varbanov
2014-12-12 17:30 ` Arnd Bergmann
2014-12-16 9:43 ` Stanimir Varbanov
2014-12-16 9:54 ` Arnd Bergmann
2015-01-12 18:20 ` Bjorn Helgaas
2014-12-12 17:14 ` [PATCH 5/5] ARM: qcom: Add Qualcomm APQ8084 SoC Stanimir Varbanov
2014-12-12 17:33 ` Arnd Bergmann
2015-01-06 15:24 ` Stanimir Varbanov
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