From: maxime.ripard@free-electrons.com (Maxime Ripard)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 0/7] ARM: mvebu: Enable perf support
Date: Tue, 3 Mar 2015 11:43:13 +0100 [thread overview]
Message-ID: <1425379400-4346-1-git-send-email-maxime.ripard@free-electrons.com> (raw)
Hi,
This patch enables the performance monitoring unit found on the Armada
370, 375, 38x and XP, in order to gain hardware-assisted tracing using
perf.
Due to the way the interrupts are implemented in these SoCs, it
required some additions to the interrupt controller in order to unmask
the PMU interrupts.
While doing so, we reworked the way the PPI are supported, in order to
make the driver both easier to read and to extend.
This has been tested on an Armada XP and an Armada 385, and this serie
depends on the patch "irqchip: armada: Fix chained per-cpu interrupts"
sent previously.
Thanks!
Maxime
Changes from v1:
- Dropped the mask/unmask refactoring
- Rebased on top of the v2 of the chained PPI fix
Ezequiel Garcia (5):
irqchip: armada-370-xp: Initialize per cpu registers when CONFIG_SMP=N
irqchip: armada-370-xp: Introduce a is_percpu_irq() helper for
readability
ARM: mvebu: Enable Performance Monitor Unit on Armada 375 SoC
ARM: mvebu: Enable Performance Monitor Unit on Armada 380/385 SoC
ARM: mvebu: Enable perf support in mvebu_v7_defconfig
Maxime Ripard (2):
irqchip: armada-370-xp: Enable the PMU interrupts
ARM: mvebu: Enable Performance Monitor Unit on Armada XP/370 SoCs
arch/arm/boot/dts/armada-370-xp.dtsi | 5 ++
arch/arm/boot/dts/armada-375.dtsi | 5 ++
arch/arm/boot/dts/armada-38x.dtsi | 5 ++
arch/arm/configs/mvebu_v7_defconfig | 1 +
drivers/irqchip/irq-armada-370-xp.c | 88 +++++++++++++++++++++++-------------
5 files changed, 73 insertions(+), 31 deletions(-)
--
2.3.0
next reply other threads:[~2015-03-03 10:43 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-03 10:43 Maxime Ripard [this message]
2015-03-03 10:43 ` [PATCH v2 1/7] irqchip: armada-370-xp: Initialize per cpu registers when CONFIG_SMP=N Maxime Ripard
2015-03-03 18:29 ` Gregory CLEMENT
2015-03-03 10:43 ` [PATCH v2 2/7] irqchip: armada-370-xp: Introduce a is_percpu_irq() helper for readability Maxime Ripard
2015-03-03 18:34 ` Gregory CLEMENT
2015-03-03 10:43 ` [PATCH v2 3/7] irqchip: armada-370-xp: Enable the PMU interrupts Maxime Ripard
2015-03-03 18:38 ` Gregory CLEMENT
2015-03-03 10:43 ` [PATCH v2 4/7] ARM: mvebu: Enable Performance Monitor Unit on Armada XP/370 SoCs Maxime Ripard
2015-03-03 18:56 ` Gregory CLEMENT
2015-03-03 10:43 ` [PATCH v2 5/7] ARM: mvebu: Enable Performance Monitor Unit on Armada 375 SoC Maxime Ripard
2015-03-03 18:54 ` Gregory CLEMENT
2015-03-03 10:43 ` [PATCH v2 6/7] ARM: mvebu: Enable Performance Monitor Unit on Armada 380/385 SoC Maxime Ripard
2015-03-03 18:54 ` Gregory CLEMENT
2015-03-03 10:43 ` [PATCH v2 7/7] ARM: mvebu: Enable perf support in mvebu_v7_defconfig Maxime Ripard
2015-03-03 18:57 ` Gregory CLEMENT
2015-03-08 5:38 ` [PATCH v2 0/7] ARM: mvebu: Enable perf support Jason Cooper
2015-03-17 9:10 ` Gregory CLEMENT
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1425379400-4346-1-git-send-email-maxime.ripard@free-electrons.com \
--to=maxime.ripard@free-electrons.com \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).