* [PATCH v17 0/4] ARM: rk3288: Add PM Domain support
@ 2015-09-02 8:59 Caesar Wang
2015-09-02 8:59 ` [PATCH v17 1/4] dt-bindings: add document of Rockchip power domains Caesar Wang
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Caesar Wang @ 2015-09-02 8:59 UTC (permalink / raw)
To: linux-arm-kernel
Thank you all for providing inputs and comments on previous versions of
this patchset.
Especially thanks to the (Kevin, Heiko, Dmitry, Doug, ULF, Michael....).
Add power domain drivers based on generic power domain for
Rockchip platform, and support RK3288 SoCs.
Verified on url =
https://chromium.googlesource.com/chromiumos/third_party/kernel/+/v3.14
localhost / # cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
domain status slaves
/device runtime status
----------------------------------------------------------------------
pd_video off
/devices/ff9a0800.iommu suspended
/devices/ff9a0000.video-codec suspended
pd_vio on
/devices/ff930300.iommu suspended
/devices/ff940300.iommu suspended
/devices/ff930000.vop suspended
/devices/ff940000.vop suspended
/devices/ff980000.hdmi unsupported
/devices/rockchip-edp unsupported
pd_hevc off
pd_gpu off
/devices/ffa30000.gpu suspended
The following is the easy example.
vopb: vop at ff930000 {
compatible = "rockchip,rk3288-vop";
...
iommus = <&vopb_mmu>;
power-domains = <&power RK3288_PD_VIO>;
status = "disabled";
...
};
vopb_mmu: iommu at ff930300 {
compatible = "rockchip,iommu";
...
interrupt-names = "vopb_mmu";
power-domains = <&power RK3288_PD_VIO>;
#iommu-cells = <0>;
status = "disabled";
...
};
vopl: vop at ff940000 {
compatible = "rockchip,rk3288-vop";
reg = <0xff940000 0x19c>;
...
iommus = <&vopl_mmu>;
power-domains = <&power RK3288_PD_VIO>;
status = "disabled";
...
};
vopl_mmu: iommu at ff940300 {
compatible = "rockchip,iommu";
...
interrupt-names = "vopl_mmu";
power-domains = <&power RK3288_PD_VIO>;
#iommu-cells = <0>;
status = "disabled";
};
Others, we can verify this driver for the EDP.
We can apply the following these patchs.
6967631 New [v2,1/8] drm: exynos/dp: fix code style
6967741 New [v2,2/8] drm: exynos/dp: convert to drm bridge mode
6967801 New [v2,3/8] drm: bridge: analogix_dp: split exynos dp driver to bridge dir
6967791 New [v2,4/8] drm: rockchip/dp: add rockchip platform dp driver
6968031 New [v2,5/8] drm: bridge/analogix_dp: add platform device type support
6968141 New [v2,6/8] drm: bridge: analogix_dp: add some rk3288 special registers setting
6967941 New [v2,7/8] drm: bridge: analogix_dp: try force hpd after plug in lookup failed
6967971 New [v2,8/8] drm: bridge/analogix_dp: expand the delay time for hpd detect
There is a recent addition from Linus Walleij,
called simple-mfd [a] that is supposed to get added real early for kernel 4.2
[a]:
https://git.kernel.org/cgit/linux/kernel/git/linusw/linux-integrator.git/commit/?id=fcf294c020ff7ee4e3b1e96159e4dc7a17ad5
Here is my branch, Tested by chromeos-3.14 and next-kernel.
f54144e ARM: dts: add the support power-domain node on RK3288 SoCs
acf07d3 soc: rockchip: power-domain: Add power domain driver
8cc2139 ARM: power-domain: rockchip: add all the domain type on RK3288 SoCs
7114c12 dt-bindings: add document of Rockchip power domains
ae98207 Merge tag 'pm+acpi-4.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
f1a3c0b Merge tag 'devicetree-for-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
089b669 Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial
45c680b Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/livepatching
851328f Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid
......
Changes in v17:
- add the decription in detail for RK3288 SoCs.
- delete the ugly chart in the commit.
- (re)defining config for ROCKCHIP.
- remove clocks of the HDMI ctrl.
- update the description.
- add Reviewed-by: Michale.
Changes in v16:
- remove the pmu node.
- Add more domain decription.
- the driver type from tristate to bool.
- Letter misspelled.
- As Ulf suggestion, remove #include <linux/clk-provider.h>,
use "%pC" as the formatting string for the dev_dbg().
- As the Ulf suggestion, set the genpd->flags to assign the
->stop|start() callbacks.
- Manually copy the problem in patch v15.
- rebase the description.
Changes in v15:
- change the comment.
- As the kevin suggestion, put the power-domain driver into driver/soc/vendor.
- As Heiko suggestion, Patch 1: binding doc, 2: binding-header, 3: driver,
4: dts-changes.
- return -ENXIO --> return -ENODEV.
- As Tomasz remarked previously the dts should represent the hardware
and the power-domains are part of the pmu.
Changes in v14:
- does not need to set an owner,remove the "THIS_MODULE".
- Remove essential clocks from rk3288 PD_VIO domain, Some clocks are
essential for the system health and should not be turned down.
However there is no owner for them so if they listed as belonging to power
domain we'll try toggling them up and down during power domain transition.
As a result we either fail to suspend or resume the system.
Changes in v13:
- Remove essential clocks from rk3288 PD_VIO domain Some clocks are essential
for the system health and should not be turned down. However there is no owner
for them so if they listed as belonging to power domain we'll try toggling them
up and down during power domain.
- Device drivers expect their devices to be powered on before their
probing code is invoked. To achieve that we should start with
power domains powered on (we may turn them off later once all devices enable
runtime powermanagment and go idle).
- This change switches Rockchip power domain driver to use updated
device_attach and device_detach API.
- set the gpu/core power domain power delay time.
- fix enumerating PM clocks for devices.
- fix use after free We can't use clk after we did clk_put(clk).
Changes in v12:
- fix the title doamin->domain.
- updated device_attach and device_detach API,otherwise it will
compile fail on next kernel.
Changes in v11:
- fix pm_genpd_init(&pd->genpd, NULL, false).
Changes in v10:
- this switches over domain infos to use masks instead of recomputing
them each time and also gets rid of custom domain translator and
uses standard onecell on.
- fix missing the #include <dt-bindings/power-domain/rk3288.h>.
- remove the notes.
Changes in v9:
- add document decription.
- fix v8 changes as follows:
- This reconciles the v2 and v7 code so that we power domain have lists of clocks
they trigger on and off during power transitions and independently from power
domains clocks. We attach clocks to devices comprising power domain and prepare
them so they are turn on and off by runtime PM.
- add rockchip_pm_add_one_domain() to control domains.
- add pd_start/pd_stop interface to control clocks.
- add decription for power-doamin node.
Changes in v8:
- document go back to v2.
- This reconciles the v2 and v7 code so that we power domain have
lists of clocks they toggle on and off during power transitions
and independently from power domains clocks we attach clocks to
devices comprising power domain and prepare them so they are
turn on and off by runtime PM.
- DTS go back to v2.
Changes in v7:
- Delete unused variables
Changes in v6:
- delete pmu_lock.
- modify dev_lock using mutex.
- pm_clk_resume(pd->dev) change to pm_clk_resume(ed->dev).
- pm_clk_suspend(pd->dev) change to pm_clk_suspend(ed->dev).
- add devm_kfree(pd->dev, de) in rockchip_pm_domain_detach_dev.
Changes in v5:
- delete idle_lock.
- add timeout in rockchip_pmu_set_idle_request().
Changes in v4:
- use list storage dev.
Changes in v3:
- DT structure has changed.
- change use pm_clk_resume() and pm_clk_suspend().
- Decomposition power-controller, changed to multiple controller
(gpu-power-controller, hevc-power-controller).
Changes in v2:
- move clocks to "optional".
- remove the "pd->pd.of_node = np".
- make pd_vio clocks all one entry per line and alphabetize.
- power: power-controller move back to pinctrl: pinctrl.
Caesar Wang (4):
dt-bindings: add document of Rockchip power domains
ARM: power-domain: rockchip: add all the domain type on RK3288 SoCs
soc: rockchip: power-domain: Add power domain driver
ARM: dts: add the support power-domain node on RK3288 SoCs
.../bindings/soc/rockchip/power_domain.txt | 114 +++++
arch/arm/boot/dts/rk3288.dtsi | 58 ++-
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/rockchip/Kconfig | 14 +
drivers/soc/rockchip/Makefile | 4 +
drivers/soc/rockchip/pm_domains.c | 485 +++++++++++++++++++++
include/dt-bindings/power-domain/rk3288.h | 31 ++
8 files changed, 707 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
create mode 100644 drivers/soc/rockchip/Kconfig
create mode 100644 drivers/soc/rockchip/Makefile
create mode 100644 drivers/soc/rockchip/pm_domains.c
create mode 100644 include/dt-bindings/power-domain/rk3288.h
--
1.9.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v17 1/4] dt-bindings: add document of Rockchip power domains
2015-09-02 8:59 [PATCH v17 0/4] ARM: rk3288: Add PM Domain support Caesar Wang
@ 2015-09-02 8:59 ` Caesar Wang
2015-09-02 18:12 ` Kevin Hilman
2015-09-02 8:59 ` [PATCH v17 2/4] ARM: power-domain: rockchip: add all the domain type on RK3288 SoCs Caesar Wang
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Caesar Wang @ 2015-09-02 8:59 UTC (permalink / raw)
To: linux-arm-kernel
This add the necessary binding documentation for the power domains
found on Rockchip SoCs.
Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---
Changes in v17:
- add the decription in detail for RK3288 SoCs.
Changes in v16:
- remove the pmu node.
Changes in v15: None
Changes in v14: None
Changes in v13: None
Changes in v12: None
Changes in v11: None
Changes in v10: None
Changes in v9:
- add document decription.
Changes in v8:
- document go back to v2.
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- DT structure has changed.
Changes in v2:
- move clocks to "optional".
.../bindings/soc/rockchip/power_domain.txt | 114 +++++++++++++++++++++
1 file changed, 114 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
diff --git a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
new file mode 100644
index 0000000..4cf6b27
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
@@ -0,0 +1,114 @@
+* Rockchip Power Domains
+
+Rockchip processors include support for multiple power domains which can be
+powered up/down by software based on different application scenes to save power.
+
+Required properties for power domain controller:
+- compatible: Should be one of the following.
+ "rockchip,rk3288-power-controller" - for RK3288 SoCs.
+- #power-domain-cells: Number of cells in a power-domain specifier.
+ Should be 1 for multiple PM domains.
+- #address-cells: Should be 1.
+- #size-cells: Should be 0.
+
+Required properties for power domain sub nodes:
+- reg: index of the power domain, should use macros in:
+ "include/dt-bindings/power-domain/rk3288.h" - for RK3288 type power domain.
+- clocks (optional): phandles to clocks which need to be enabled while power domain
+ switches state.
+
+Example:
+
+ power: power-controller {
+ compatible = "rockchip,rk3288-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_gpu {
+ reg = <RK3288_PD_GPU>;
+ clocks = <&cru ACLK_GPU>;
+ };
+ };
+
+Node of a device using power domains must have a power-domains property,
+containing a phandle to the power device node and an index specifying which
+power domain to use.
+The index should use macros in:
+ "include/dt-bindings/power-domain/rk3288.h" - for rk3288 type power domain.
+
+Example of the node using power domain:
+
+ node {
+ /* ... */
+ power-domains = <&power RK3288_PD_GPU>;
+ /* ... */
+ };
+
+Others, all the device clocks being listed in the power-domains itself.
+All the device clocks are included in someone domians that need to enable
+before you operate them.
+
+As the chip designs for PM hardware. We need turn on the noc clocks,
+if we are operating the "pd_vio" domain to enter the idle status.
+
+As the following described in detail for every device be included in domains
+on RK3288 SoCs.
+
+ /* GPU's ACLK_GPU on the ACLK_GPU_NIU */
+ pd_gpu {
+ reg = <RK3288_PD_GPU>;
+ clocks = <&cru ACLK_GPU>;
+ };
+
+ /* HEVC AXI clocks */
+ pd_hevc {
+ reg = <RK3288_PD_HEVC>;
+ clocks = <&cru ACLK_HEVC>,
+ <&cru SCLK_HEVC_CABAC>,
+ <&cru SCLK_HEVC_CORE>,
+ <&cru HCLK_HEVC>;
+ };
+
+ /*
+ * RGA, VOP, MIPI, LVDS, EDP..., says the ACLK* on the ACLK_VIO_NIU,
+ * others are on the HCLK_VIO_NIU.
+ */
+ pd_vio {
+ reg = <RK3288_PD_VIO>;
+ clocks = <&cru ACLK_IEP>,
+ <&cru ACLK_ISP>,
+ <&cru ACLK_RGA>,
+ <&cru ACLK_VIP>,
+ <&cru ACLK_VOP0>,
+ <&cru ACLK_VOP1>,
+ <&cru DCLK_VOP0>,
+ <&cru DCLK_VOP1>,
+ <&cru HCLK_IEP>,
+ <&cru HCLK_ISP>,
+ <&cru HCLK_RGA>,
+ <&cru HCLK_VIP>,
+ <&cru HCLK_VOP0>,
+ <&cru HCLK_VOP1>,
+ <&cru PCLK_EDP_CTRL>,
+ <&cru PCLK_HDMI_CTRL>,
+ <&cru PCLK_LVDS_PHY>,
+ <&cru PCLK_MIPI_CSI>,
+ <&cru PCLK_MIPI_DSI0>,
+ <&cru PCLK_MIPI_DSI1>,
+ <&cru SCLK_EDP_24M>,
+ <&cru SCLK_EDP>,
+ <&cru SCLK_ISP_JPE>,
+ <&cru SCLK_ISP>,
+ <&cru SCLK_RGA>;
+ };
+
+ /*
+ * Video's ACLK_VCODEC on the ACLK_VCODEC_NIU, Video's HCLK_VCODEC,
+ * on the HCLK_VCODEC_NIU.
+ */
+ pd_video {
+ reg = <RK3288_PD_VIDEO>;
+ clocks = <&cru ACLK_VCODEC>,
+ <&cru HCLK_VCODEC>;
+ };
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v17 2/4] ARM: power-domain: rockchip: add all the domain type on RK3288 SoCs
2015-09-02 8:59 [PATCH v17 0/4] ARM: rk3288: Add PM Domain support Caesar Wang
2015-09-02 8:59 ` [PATCH v17 1/4] dt-bindings: add document of Rockchip power domains Caesar Wang
@ 2015-09-02 8:59 ` Caesar Wang
2015-09-02 8:59 ` [PATCH v17 3/4] soc: rockchip: power-domain: Add power domain driver Caesar Wang
2015-09-02 8:59 ` [PATCH v17 4/4] ARM: dts: add the support power-domain node on RK3288 SoCs Caesar Wang
3 siblings, 0 replies; 9+ messages in thread
From: Caesar Wang @ 2015-09-02 8:59 UTC (permalink / raw)
To: linux-arm-kernel
According to a description from TRM, add all the power domains.
At the moment, we can support some domains on RK3288.
We can add more types on RK3288 in the future, that's need to do.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---
Changes in v17:
- delete the ugly chart in the commit.
Changes in v16:
- Add more domain decription.
Changes in v15:
- change the comment.
Changes in v14: None
Changes in v13: None
Changes in v12: None
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
include/dt-bindings/power-domain/rk3288.h | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 include/dt-bindings/power-domain/rk3288.h
diff --git a/include/dt-bindings/power-domain/rk3288.h b/include/dt-bindings/power-domain/rk3288.h
new file mode 100644
index 0000000..db5e810
--- /dev/null
+++ b/include/dt-bindings/power-domain/rk3288.h
@@ -0,0 +1,31 @@
+#ifndef __DT_BINDINGS_POWER_DOMAIN_RK3288_H__
+#define __DT_BINDINGS_POWER_DOMAIN_RK3288_H__
+
+/**
+ * RK3288 Power Domain and Voltage Domain Summary.
+ */
+
+/* VD_CORE */
+#define RK3288_PD_A17_0 0
+#define RK3288_PD_A17_1 1
+#define RK3288_PD_A17_2 2
+#define RK3288_PD_A17_3 3
+#define RK3288_PD_SCU 4
+#define RK3288_PD_DEBUG 5
+#define RK3288_PD_MEM 6
+
+/* VD_LOGIC */
+#define RK3288_PD_BUS 7
+#define RK3288_PD_PERI 8
+#define RK3288_PD_VIO 9
+#define RK3288_PD_ALIVE 10
+#define RK3288_PD_HEVC 11
+#define RK3288_PD_VIDEO 12
+
+/* VD_GPU */
+#define RK3288_PD_GPU 13
+
+/* VD_PMU */
+#define RK3288_PD_PMU 14
+
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v17 3/4] soc: rockchip: power-domain: Add power domain driver
2015-09-02 8:59 [PATCH v17 0/4] ARM: rk3288: Add PM Domain support Caesar Wang
2015-09-02 8:59 ` [PATCH v17 1/4] dt-bindings: add document of Rockchip power domains Caesar Wang
2015-09-02 8:59 ` [PATCH v17 2/4] ARM: power-domain: rockchip: add all the domain type on RK3288 SoCs Caesar Wang
@ 2015-09-02 8:59 ` Caesar Wang
2015-09-02 18:28 ` Kevin Hilman
2015-09-02 8:59 ` [PATCH v17 4/4] ARM: dts: add the support power-domain node on RK3288 SoCs Caesar Wang
3 siblings, 1 reply; 9+ messages in thread
From: Caesar Wang @ 2015-09-02 8:59 UTC (permalink / raw)
To: linux-arm-kernel
This driver is found on RK3288 SoCs.
In order to meet high performance and low power requirements, a power
management unit is designed or saving power when RK3288 in low power
mode.
The RK3288 PMU is dedicated for managing the power of the whole chip.
PMU can work in the Low Power Mode by setting bit[0] of PMU_PWRMODE_CON
register. After setting the register, PMU would enter the Low Power mode.
In the low power mode, pmu will auto power on/off the specified power
domain, send idle req to specified power domain, shut down/up pll and
so on. All of above are configurable by setting corresponding registers.
Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---
Changes in v17:
- (re)defining config for ROCKCHIP.
Changes in v16:
- the driver type from tristate to bool.
- Letter misspelled.
- As Ulf suggestion, remove #include <linux/clk-provider.h>,
use "%pC" as the formatting string for the dev_dbg().
- As the Ulf suggestion, set the genpd->flags to assign the
->stop|start() callbacks.
Changes in v15:
- As the kevin suggestion, put the power-domain driver into driver/soc/vendor.
- As Heiko suggestion, Patch 1: binding doc, 2: binding-header, 3: driver,
4: dts-changes.
- return -ENXIO --> return -ENODEV.
Changes in v14:
- does not need to set an owner,remove the "THIS_MODULE".
Changes in v13:
- Remove essential clocks from rk3288 PD_VIO domain Some clocks are essential
for the system health and should not be turned down. However there is no owner
for them so if they listed as belonging to power domain we'll try toggling them
up and down during power domain.
- Device drivers expect their devices to be powered on before their
probing code is invoked. To achieve that we should start with
power domains powered on (we may turn them off later once all devices enable
runtime powermanagment and go idle).
- This change switches Rockchip power domain driver to use updated
device_attach and device_detach API.
- set the gpu/core power domain power delay time.
- fix enumerating PM clocks for devices.
- fix use after free We can't use clk after we did clk_put(clk).
Changes in v12:
- fix the title doamin->domain.
- updated device_attach and device_detach API,otherwise it will
compile fail on next kernel.
Changes in v11:
- fix pm_genpd_init(&pd->genpd, NULL, false).
Changes in v10:
- this switches over domain infos to use masks instead of recomputing
them each time and also gets rid of custom domain translator and
uses standard onecell on.
Changes in v9:
- fix v8 changes as follows:
- This reconciles the v2 and v7 code so that we power domain have lists of clocks
they trigger on and off during power transitions and independently from power
domains clocks. We attach clocks to devices comprising power domain and prepare
them so they are turn on and off by runtime PM.
- add rockchip_pm_add_one_domain() to control domains.
- add pd_start/pd_stop interface to control clocks.
Changes in v8:
- This reconciles the v2 and v7 code so that we power domain have
lists of clocks they toggle on and off during power transitions
and independently from power domains clocks we attach clocks to
devices comprising power domain and prepare them so they are
turn on and off by runtime PM.
Changes in v7:
- Delete unused variables
Changes in v6:
- delete pmu_lock.
- modify dev_lock using mutex.
- pm_clk_resume(pd->dev) change to pm_clk_resume(ed->dev).
- pm_clk_suspend(pd->dev) change to pm_clk_suspend(ed->dev).
- add devm_kfree(pd->dev, de) in rockchip_pm_domain_detach_dev.
Changes in v5:
- delete idle_lock.
- add timeout in rockchip_pmu_set_idle_request().
Changes in v4:
- use list storage dev.
Changes in v3:
- change use pm_clk_resume() and pm_clk_suspend().
Changes in v2:
- remove the "pd->pd.of_node = np".
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/rockchip/Kconfig | 14 ++
drivers/soc/rockchip/Makefile | 4 +
drivers/soc/rockchip/pm_domains.c | 485 ++++++++++++++++++++++++++++++++++++++
5 files changed, 505 insertions(+)
create mode 100644 drivers/soc/rockchip/Kconfig
create mode 100644 drivers/soc/rockchip/Makefile
create mode 100644 drivers/soc/rockchip/pm_domains.c
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 96ddecb..ecb1a6c 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers"
source "drivers/soc/mediatek/Kconfig"
source "drivers/soc/qcom/Kconfig"
+source "drivers/soc/rockchip/Kconfig"
source "drivers/soc/sunxi/Kconfig"
source "drivers/soc/ti/Kconfig"
source "drivers/soc/versatile/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 0b12d77..c2b485f 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_MACH_DOVE) += dove/
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_QCOM) += qcom/
+obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_SOC_TI) += ti/
diff --git a/drivers/soc/rockchip/Kconfig b/drivers/soc/rockchip/Kconfig
new file mode 100644
index 0000000..6ee0399
--- /dev/null
+++ b/drivers/soc/rockchip/Kconfig
@@ -0,0 +1,14 @@
+#
+# Rockchip Soc drivers
+#
+config ROCKCHIP_PM_DOMAINS
+ bool "Rockchip generic power domain"
+ depends on PM
+ select PM_GENERIC_DOMAINS
+ help
+ Say y here to enable power domain support.
+ In order to meet high performance and low power requirements, a power
+ management unit is designed or saving power when RK3288 in low power
+ mode. The RK3288 PMU is dedicated for managing the power of the whole chip.
+
+ If unsure, say N.
diff --git a/drivers/soc/rockchip/Makefile b/drivers/soc/rockchip/Makefile
new file mode 100644
index 0000000..3d73d06
--- /dev/null
+++ b/drivers/soc/rockchip/Makefile
@@ -0,0 +1,4 @@
+#
+# Rockchip Soc drivers
+#
+obj-$(CONFIG_ROCKCHIP_PM_DOMAINS) += pm_domains.o
diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
new file mode 100644
index 0000000..fd772d2
--- /dev/null
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -0,0 +1,485 @@
+/*
+ * Rockchip Generic power domain support.
+ *
+ * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/pm_clock.h>
+#include <linux/pm_domain.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/clk.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <dt-bindings/power-domain/rk3288.h>
+
+struct rockchip_domain_info {
+ int pwr_mask;
+ int status_mask;
+ int req_mask;
+ int idle_mask;
+ int ack_mask;
+};
+
+struct rockchip_pmu_info {
+ u32 pwr_offset;
+ u32 status_offset;
+ u32 req_offset;
+ u32 idle_offset;
+ u32 ack_offset;
+
+ u32 core_pwrcnt_offset;
+ u32 gpu_pwrcnt_offset;
+
+ unsigned int core_power_transition_time;
+ unsigned int gpu_power_transition_time;
+
+ int num_domains;
+ const struct rockchip_domain_info *domain_info;
+};
+
+struct rockchip_pm_domain {
+ struct generic_pm_domain genpd;
+ const struct rockchip_domain_info *info;
+ struct rockchip_pmu *pmu;
+ int num_clks;
+ struct clk *clks[];
+};
+
+struct rockchip_pmu {
+ struct device *dev;
+ struct regmap *regmap;
+ const struct rockchip_pmu_info *info;
+ struct mutex mutex; /* mutex lock for pmu */
+ struct genpd_onecell_data genpd_data;
+ struct generic_pm_domain *domains[];
+};
+
+#define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
+
+#define DOMAIN(pwr, status, req, idle, ack) \
+{ \
+ .pwr_mask = BIT(pwr), \
+ .status_mask = BIT(status), \
+ .req_mask = BIT(req), \
+ .idle_mask = BIT(idle), \
+ .ack_mask = BIT(ack), \
+}
+
+#define DOMAIN_RK3288(pwr, status, req) \
+ DOMAIN(pwr, status, req, req, (req) + 16)
+
+static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
+{
+ struct rockchip_pmu *pmu = pd->pmu;
+ const struct rockchip_domain_info *pd_info = pd->info;
+ unsigned int val;
+
+ regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
+ return (val & pd_info->idle_mask) == pd_info->idle_mask;
+}
+
+static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
+ bool idle)
+{
+ const struct rockchip_domain_info *pd_info = pd->info;
+ struct rockchip_pmu *pmu = pd->pmu;
+ unsigned int val;
+
+ regmap_update_bits(pmu->regmap, pmu->info->req_offset,
+ pd_info->req_mask, idle ? -1U : 0);
+
+ dsb();
+
+ do {
+ regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
+ } while ((val & pd_info->ack_mask) != (idle ? pd_info->ack_mask : 0));
+
+ while (rockchip_pmu_domain_is_idle(pd) != idle)
+ cpu_relax();
+
+ return 0;
+}
+
+static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
+{
+ struct rockchip_pmu *pmu = pd->pmu;
+ unsigned int val;
+
+ regmap_read(pmu->regmap, pmu->info->status_offset, &val);
+
+ /* 1'b0: power on, 1'b1: power off */
+ return !(val & pd->info->status_mask);
+}
+
+static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
+ bool on)
+{
+ struct rockchip_pmu *pmu = pd->pmu;
+
+ regmap_update_bits(pmu->regmap, pmu->info->pwr_offset,
+ pd->info->pwr_mask, on ? 0 : -1U);
+
+ dsb();
+
+ while (rockchip_pmu_domain_is_on(pd) != on)
+ cpu_relax();
+}
+
+static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
+{
+ int i;
+
+ mutex_lock(&pd->pmu->mutex);
+
+ if (rockchip_pmu_domain_is_on(pd) != power_on) {
+ for (i = 0; i < pd->num_clks; i++)
+ clk_enable(pd->clks[i]);
+
+ if (!power_on) {
+ /* FIXME: add code to save AXI_QOS */
+
+ /* if powering down, idle request to NIU first */
+ rockchip_pmu_set_idle_request(pd, true);
+ }
+
+ rockchip_do_pmu_set_power_domain(pd, power_on);
+
+ if (power_on) {
+ /* if powering up, leave idle mode */
+ rockchip_pmu_set_idle_request(pd, false);
+
+ /* FIXME: add code to restore AXI_QOS */
+ }
+
+ for (i = pd->num_clks - 1; i >= 0; i--)
+ clk_disable(pd->clks[i]);
+ }
+
+ mutex_unlock(&pd->pmu->mutex);
+ return 0;
+}
+
+static int rockchip_pd_power_on(struct generic_pm_domain *domain)
+{
+ struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
+
+ return rockchip_pd_power(pd, true);
+}
+
+static int rockchip_pd_power_off(struct generic_pm_domain *domain)
+{
+ struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
+
+ return rockchip_pd_power(pd, false);
+}
+
+static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd,
+ struct device *dev)
+{
+ struct clk *clk;
+ int i;
+ int error;
+
+ dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);
+
+ error = pm_clk_create(dev);
+ if (error) {
+ dev_err(dev, "pm_clk_create failed %d\n", error);
+ return error;
+ }
+
+ i = 0;
+ while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) {
+ dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk);
+ error = pm_clk_add_clk(dev, clk);
+ clk_put(clk);
+ if (error) {
+ dev_err(dev, "pm_clk_add_clk failed %d\n", error);
+ pm_clk_destroy(dev);
+ return error;
+ }
+ }
+
+ return 0;
+}
+
+static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
+ struct device *dev)
+{
+ dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);
+
+ pm_clk_destroy(dev);
+}
+
+static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
+ struct device_node *node)
+{
+ const struct rockchip_domain_info *pd_info;
+ struct rockchip_pm_domain *pd;
+ struct clk *clk;
+ int clk_cnt;
+ int i;
+ u32 id;
+ int error;
+
+ error = of_property_read_u32(node, "reg", &id);
+ if (error) {
+ dev_err(pmu->dev,
+ "%s: failed to retrieve domain id (reg): %d\n",
+ node->name, error);
+ return -EINVAL;
+ }
+
+ if (id >= pmu->info->num_domains) {
+ dev_err(pmu->dev, "%s: invalid domain id %d\n",
+ node->name, id);
+ return -EINVAL;
+ }
+
+ pd_info = &pmu->info->domain_info[id];
+ if (!pd_info) {
+ dev_err(pmu->dev, "%s: undefined domain id %d\n",
+ node->name, id);
+ return -EINVAL;
+ }
+
+ clk_cnt = of_count_phandle_with_args(node, "clocks", "#clock-cells");
+ pd = devm_kzalloc(pmu->dev,
+ sizeof(*pd) + clk_cnt * sizeof(pd->clks[0]),
+ GFP_KERNEL);
+ if (!pd)
+ return -ENOMEM;
+
+ pd->info = pd_info;
+ pd->pmu = pmu;
+
+ for (i = 0; i < clk_cnt; i++) {
+ clk = of_clk_get(node, i);
+ if (IS_ERR(clk)) {
+ error = PTR_ERR(clk);
+ dev_err(pmu->dev,
+ "%s: failed to get clk %pC (index %d): %d\n",
+ node->name, clk, i, error);
+ goto err_out;
+ }
+
+ error = clk_prepare(clk);
+ if (error) {
+ dev_err(pmu->dev,
+ "%s: failed to prepare clk %pC (index %d): %d\n",
+ node->name, clk, i, error);
+ clk_put(clk);
+ goto err_out;
+ }
+
+ pd->clks[pd->num_clks++] = clk;
+
+ dev_dbg(pmu->dev, "added clock '%pC' to domain '%s'\n",
+ clk, node->name);
+ }
+
+ error = rockchip_pd_power(pd, true);
+ if (error) {
+ dev_err(pmu->dev,
+ "failed to power on domain '%s': %d\n",
+ node->name, error);
+ goto err_out;
+ }
+
+ pd->genpd.name = node->name;
+ pd->genpd.power_off = rockchip_pd_power_off;
+ pd->genpd.power_on = rockchip_pd_power_on;
+ pd->genpd.attach_dev = rockchip_pd_attach_dev;
+ pd->genpd.detach_dev = rockchip_pd_detach_dev;
+ pd->genpd.flags = GENPD_FLAG_PM_CLK;
+ pm_genpd_init(&pd->genpd, NULL, false);
+
+ pmu->genpd_data.domains[id] = &pd->genpd;
+ return 0;
+
+err_out:
+ while (--i >= 0) {
+ clk_unprepare(pd->clks[i]);
+ clk_put(pd->clks[i]);
+ }
+ return error;
+}
+
+static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
+{
+ int i;
+
+ for (i = 0; i < pd->num_clks; i++) {
+ clk_unprepare(pd->clks[i]);
+ clk_put(pd->clks[i]);
+ }
+
+ /* devm will free our memory */
+}
+
+static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu)
+{
+ struct generic_pm_domain *genpd;
+ struct rockchip_pm_domain *pd;
+ int i;
+
+ for (i = 0; i < pmu->genpd_data.num_domains; i++) {
+ genpd = pmu->genpd_data.domains[i];
+ if (genpd) {
+ pd = to_rockchip_pd(genpd);
+ rockchip_pm_remove_one_domain(pd);
+ }
+ }
+
+ /* devm will free our memory */
+}
+
+static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
+ u32 domain_reg_offset,
+ unsigned int count)
+{
+ /* First configure domain power down transition count ... */
+ regmap_write(pmu->regmap, domain_reg_offset, count);
+ /* ... and then power up count. */
+ regmap_write(pmu->regmap, domain_reg_offset + 4, count);
+}
+
+static int rockchip_pm_domain_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct device_node *node;
+ struct device *parent;
+ struct rockchip_pmu *pmu;
+ const struct of_device_id *match;
+ const struct rockchip_pmu_info *pmu_info;
+ int error;
+
+ if (!np) {
+ dev_err(dev, "device tree node not found\n");
+ return -ENODEV;
+ }
+
+ match = of_match_device(dev->driver->of_match_table, dev);
+ if (!match || !match->data) {
+ dev_err(dev, "missing pmu data\n");
+ return -EINVAL;
+ }
+
+ pmu_info = match->data;
+
+ pmu = devm_kzalloc(dev,
+ sizeof(*pmu) +
+ pmu_info->num_domains * sizeof(pmu->domains[0]),
+ GFP_KERNEL);
+ if (!pmu)
+ return -ENOMEM;
+
+ pmu->dev = &pdev->dev;
+ mutex_init(&pmu->mutex);
+
+ pmu->info = pmu_info;
+
+ pmu->genpd_data.domains = pmu->domains;
+ pmu->genpd_data.num_domains = pmu_info->num_domains;
+
+ parent = dev->parent;
+ if (!parent) {
+ dev_err(dev, "no parent for syscon devices\n");
+ return -ENODEV;
+ }
+
+ pmu->regmap = syscon_node_to_regmap(parent->of_node);
+
+ /*
+ * Configure power up and down transition delays for CORE
+ * and GPU domains.
+ */
+ rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
+ pmu_info->core_power_transition_time);
+ rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
+ pmu_info->gpu_power_transition_time);
+
+ error = -ENODEV;
+
+ for_each_available_child_of_node(np, node) {
+ error = rockchip_pm_add_one_domain(pmu, node);
+ if (error) {
+ dev_err(dev, "failed to handle node %s: %d\n",
+ node->name, error);
+ goto err_out;
+ }
+ }
+
+ if (error) {
+ dev_dbg(dev, "no power domains defined\n");
+ goto err_out;
+ }
+
+ of_genpd_add_provider_onecell(np, &pmu->genpd_data);
+
+ return 0;
+
+err_out:
+ rockchip_pm_domain_cleanup(pmu);
+ return error;
+}
+
+static const struct rockchip_domain_info rk3288_pm_domains[] = {
+ [RK3288_PD_GPU] = DOMAIN_RK3288(9, 9, 2),
+ [RK3288_PD_VIO] = DOMAIN_RK3288(7, 7, 4),
+ [RK3288_PD_VIDEO] = DOMAIN_RK3288(8, 8, 3),
+ [RK3288_PD_HEVC] = DOMAIN_RK3288(14, 10, 9),
+};
+
+static const struct rockchip_pmu_info rk3288_pmu = {
+ .pwr_offset = 0x08,
+ .status_offset = 0x0c,
+ .req_offset = 0x10,
+ .idle_offset = 0x14,
+ .ack_offset = 0x14,
+
+ .core_pwrcnt_offset = 0x34,
+ .gpu_pwrcnt_offset = 0x3c,
+
+ .core_power_transition_time = 24, /* 1us */
+ .gpu_power_transition_time = 24, /* 1us */
+
+ .num_domains = ARRAY_SIZE(rk3288_pm_domains),
+ .domain_info = rk3288_pm_domains,
+};
+
+static const struct of_device_id rockchip_pm_domain_dt_match[] = {
+ {
+ .compatible = "rockchip,rk3288-power-controller",
+ .data = (void *)&rk3288_pmu,
+ },
+ { /* sentinel */ },
+};
+
+static struct platform_driver rockchip_pm_domain_driver = {
+ .probe = rockchip_pm_domain_probe,
+ .driver = {
+ .name = "rockchip-pm-domain",
+ .of_match_table = rockchip_pm_domain_dt_match,
+ /*
+ * We can't forcibly eject devices form power domain,
+ * so we can't really remove power domains once they
+ * were added.
+ */
+ .suppress_bind_attrs = true,
+ },
+};
+
+static int __init rockchip_pm_domain_drv_register(void)
+{
+ return platform_driver_register(&rockchip_pm_domain_driver);
+}
+postcore_initcall(rockchip_pm_domain_drv_register);
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v17 4/4] ARM: dts: add the support power-domain node on RK3288 SoCs
2015-09-02 8:59 [PATCH v17 0/4] ARM: rk3288: Add PM Domain support Caesar Wang
` (2 preceding siblings ...)
2015-09-02 8:59 ` [PATCH v17 3/4] soc: rockchip: power-domain: Add power domain driver Caesar Wang
@ 2015-09-02 8:59 ` Caesar Wang
3 siblings, 0 replies; 9+ messages in thread
From: Caesar Wang @ 2015-09-02 8:59 UTC (permalink / raw)
To: linux-arm-kernel
We can add more domains node in the future.
This patch add the needed clocks into power-controller.
As the discuess about all the device clocks being listed in
the power-domains itself.
There are several reasons as follows:
Firstly, the clocks need be turned off to save power when
the system enter the suspend state. So we need to enumerate
the clocks in the dts. In order to power domain can turn on and off.
Secondly, the reset-circuit should reset be synchronous on RK3288,
then sync revoked. So we need to enable clocks of all devices.
In other words, we have to enable the clocks before you operate them
if all the device clocks are included in someone domians.
Thirdly, as the chip designs for PM hardhare. we need turn on the noc
clocks, if we are operating the "pd_vio" domain to enter the idle status.
The device's clock be included in domains that needed turn on if do that.
The clocks in the dts are needed to enable before you want to happy work.
At the moment, This patch is very good work for PM hardware.
Also, we can add it in the future if we have some hidden clocks.
Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Michael Turquette <mturquette@baylibre.com>
---
Changes in v17:
- remove clocks of the HDMI ctrl.
- update the description.
- add Reviewed-by: Michale.
Changes in v16:
- Manually copy the problem in patch v15.
- rebase the description.
Changes in v15:
- As Tomasz remarked previously the dts should represent the hardware
and the power-domains are part of the pmu.
Changes in v14:
- Remove essential clocks from rk3288 PD_VIO domain, Some clocks are
essential for the system health and should not be turned down.
However there is no owner for them so if they listed as belonging to power
domain we'll try toggling them up and down during power domain transition.
As a result we either fail to suspend or resume the system.
Changes in v13: None
Changes in v12: None
Changes in v11: None
Changes in v10:
- fix missing the #include <dt-bindings/power-domain/rk3288.h>.
- remove the notes.
Changes in v9:
- add decription for power-doamin node.
Changes in v8:
- DTS go back to v2.
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Decomposition power-controller, changed to multiple controller
(gpu-power-controller, hevc-power-controller).
Changes in v2:
- make pd_vio clocks all one entry per line and alphabetize.
- power: power-controller move back to pinctrl: pinctrl.
arch/arm/boot/dts/rk3288.dtsi | 58 ++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 57 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 906e938..4ce3099 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -44,6 +44,7 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3288-cru.h>
#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/power-domain/rk3288.h>
#include "skeleton.dtsi"
/ {
@@ -613,8 +614,63 @@
};
pmu: power-management at ff730000 {
- compatible = "rockchip,rk3288-pmu", "syscon";
+ compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
reg = <0xff730000 0x100>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3288-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_gpu {
+ reg = <RK3288_PD_GPU>;
+ clocks = <&cru ACLK_GPU>;
+ };
+
+ pd_hevc {
+ reg = <RK3288_PD_HEVC>;
+ clocks = <&cru ACLK_HEVC>,
+ <&cru SCLK_HEVC_CABAC>,
+ <&cru SCLK_HEVC_CORE>,
+ <&cru HCLK_HEVC>;
+ };
+
+ pd_vio {
+ reg = <RK3288_PD_VIO>;
+ clocks = <&cru ACLK_IEP>,
+ <&cru ACLK_ISP>,
+ <&cru ACLK_RGA>,
+ <&cru ACLK_VIP>,
+ <&cru ACLK_VOP0>,
+ <&cru ACLK_VOP1>,
+ <&cru DCLK_VOP0>,
+ <&cru DCLK_VOP1>,
+ <&cru HCLK_IEP>,
+ <&cru HCLK_ISP>,
+ <&cru HCLK_RGA>,
+ <&cru HCLK_VIP>,
+ <&cru HCLK_VOP0>,
+ <&cru HCLK_VOP1>,
+ <&cru PCLK_EDP_CTRL>,
+ <&cru PCLK_HDMI_CTRL>,
+ <&cru PCLK_LVDS_PHY>,
+ <&cru PCLK_MIPI_CSI>,
+ <&cru PCLK_MIPI_DSI0>,
+ <&cru PCLK_MIPI_DSI1>,
+ <&cru SCLK_EDP_24M>,
+ <&cru SCLK_EDP>,
+ <&cru SCLK_ISP_JPE>,
+ <&cru SCLK_ISP>,
+ <&cru SCLK_RGA>;
+ };
+
+ pd_video {
+ reg = <RK3288_PD_VIDEO>;
+ clocks = <&cru ACLK_VCODEC>,
+ <&cru HCLK_VCODEC>;
+ };
+ };
};
sgrf: syscon at ff740000 {
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v17 1/4] dt-bindings: add document of Rockchip power domains
2015-09-02 8:59 ` [PATCH v17 1/4] dt-bindings: add document of Rockchip power domains Caesar Wang
@ 2015-09-02 18:12 ` Kevin Hilman
2015-09-06 10:10 ` Caesar Wang
0 siblings, 1 reply; 9+ messages in thread
From: Kevin Hilman @ 2015-09-02 18:12 UTC (permalink / raw)
To: linux-arm-kernel
Caesar Wang <wxt@rock-chips.com> writes:
> This add the necessary binding documentation for the power domains
> found on Rockchip SoCs.
>
> Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>
> ---
>
> Changes in v17:
> - add the decription in detail for RK3288 SoCs.
>
> Changes in v16:
> - remove the pmu node.
>
> Changes in v15: None
> Changes in v14: None
> Changes in v13: None
> Changes in v12: None
> Changes in v11: None
> Changes in v10: None
> Changes in v9:
> - add document decription.
>
> Changes in v8:
> - document go back to v2.
>
> Changes in v7: None
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3:
> - DT structure has changed.
>
> Changes in v2:
> - move clocks to "optional".
>
> .../bindings/soc/rockchip/power_domain.txt | 114 +++++++++++++++++++++
> 1 file changed, 114 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
>
> diff --git
> a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
> b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
> new file mode 100644
> index 0000000..4cf6b27
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
> @@ -0,0 +1,114 @@
> +* Rockchip Power Domains
> +
> +Rockchip processors include support for multiple power domains which can be
> +powered up/down by software based on different application scenes to save power.
> +
> +Required properties for power domain controller:
> +- compatible: Should be one of the following.
> + "rockchip,rk3288-power-controller" - for RK3288 SoCs.
> +- #power-domain-cells: Number of cells in a power-domain specifier.
> + Should be 1 for multiple PM domains.
> +- #address-cells: Should be 1.
> +- #size-cells: Should be 0.
> +
> +Required properties for power domain sub nodes:
> +- reg: index of the power domain, should use macros in:
> + "include/dt-bindings/power-domain/rk3288.h" - for RK3288 type power domain.
> +- clocks (optional): phandles to clocks which need to be enabled while power domain
> + switches state.
> +
> +Example:
> +
> + power: power-controller {
> + compatible = "rockchip,rk3288-power-controller";
> + #power-domain-cells = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pd_gpu {
> + reg = <RK3288_PD_GPU>;
> + clocks = <&cru ACLK_GPU>;
> + };
> + };
> +
> +Node of a device using power domains must have a power-domains property,
> +containing a phandle to the power device node and an index specifying which
> +power domain to use.
> +The index should use macros in:
> + "include/dt-bindings/power-domain/rk3288.h" - for rk3288 type power domain.
> +
> +Example of the node using power domain:
> +
> + node {
> + /* ... */
> + power-domains = <&power RK3288_PD_GPU>;
> + /* ... */
> + };
> +
> +Others, all the device clocks being listed in the power-domains itself.
> +All the device clocks are included in someone domians that need to enable
> +before you operate them.
> +
> +As the chip designs for PM hardware. We need turn on the noc clocks,
> +if we are operating the "pd_vio" domain to enter the idle status.
> +
> +As the following described in detail for every device be included in domains
> +on RK3288 SoCs.
IMO, the below isn't really detailed enough, and also, the details
should be in the .dts file itself, not in the binding doc.
In particular, it's not obvious from the current series which of the
clocks are device clocks, and which are other/parent/infrastructure
clocks needed for the synchronous reset.
Kevin
> + /* GPU's ACLK_GPU on the ACLK_GPU_NIU */
> + pd_gpu {
> + reg = <RK3288_PD_GPU>;
> + clocks = <&cru ACLK_GPU>;
> + };
> +
> + /* HEVC AXI clocks */
> + pd_hevc {
> + reg = <RK3288_PD_HEVC>;
> + clocks = <&cru ACLK_HEVC>,
> + <&cru SCLK_HEVC_CABAC>,
> + <&cru SCLK_HEVC_CORE>,
> + <&cru HCLK_HEVC>;
> + };
> +
> + /*
> + * RGA, VOP, MIPI, LVDS, EDP..., says the ACLK* on the ACLK_VIO_NIU,
> + * others are on the HCLK_VIO_NIU.
> + */
> + pd_vio {
> + reg = <RK3288_PD_VIO>;
> + clocks = <&cru ACLK_IEP>,
> + <&cru ACLK_ISP>,
> + <&cru ACLK_RGA>,
> + <&cru ACLK_VIP>,
> + <&cru ACLK_VOP0>,
> + <&cru ACLK_VOP1>,
> + <&cru DCLK_VOP0>,
> + <&cru DCLK_VOP1>,
> + <&cru HCLK_IEP>,
> + <&cru HCLK_ISP>,
> + <&cru HCLK_RGA>,
> + <&cru HCLK_VIP>,
> + <&cru HCLK_VOP0>,
> + <&cru HCLK_VOP1>,
> + <&cru PCLK_EDP_CTRL>,
> + <&cru PCLK_HDMI_CTRL>,
> + <&cru PCLK_LVDS_PHY>,
> + <&cru PCLK_MIPI_CSI>,
> + <&cru PCLK_MIPI_DSI0>,
> + <&cru PCLK_MIPI_DSI1>,
> + <&cru SCLK_EDP_24M>,
> + <&cru SCLK_EDP>,
> + <&cru SCLK_ISP_JPE>,
> + <&cru SCLK_ISP>,
> + <&cru SCLK_RGA>;
> + };
> +
> + /*
> + * Video's ACLK_VCODEC on the ACLK_VCODEC_NIU, Video's HCLK_VCODEC,
> + * on the HCLK_VCODEC_NIU.
> + */
> + pd_video {
> + reg = <RK3288_PD_VIDEO>;
> + clocks = <&cru ACLK_VCODEC>,
> + <&cru HCLK_VCODEC>;
> + };
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v17 3/4] soc: rockchip: power-domain: Add power domain driver
2015-09-02 8:59 ` [PATCH v17 3/4] soc: rockchip: power-domain: Add power domain driver Caesar Wang
@ 2015-09-02 18:28 ` Kevin Hilman
2015-09-06 3:04 ` Caesar Wang
0 siblings, 1 reply; 9+ messages in thread
From: Kevin Hilman @ 2015-09-02 18:28 UTC (permalink / raw)
To: linux-arm-kernel
Caesar Wang <wxt@rock-chips.com> writes:
> This driver is found on RK3288 SoCs.
>
> In order to meet high performance and low power requirements, a power
> management unit is designed or saving power when RK3288 in low power
> mode.
> The RK3288 PMU is dedicated for managing the power of the whole chip.
>
> PMU can work in the Low Power Mode by setting bit[0] of PMU_PWRMODE_CON
> register. After setting the register, PMU would enter the Low Power mode.
> In the low power mode, pmu will auto power on/off the specified power
> domain, send idle req to specified power domain, shut down/up pll and
> so on. All of above are configurable by setting corresponding registers.
>
> Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
[...]
> +static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
> +{
> + int i;
> +
> + for (i = 0; i < pd->num_clks; i++) {
> + clk_unprepare(pd->clks[i]);
> + clk_put(pd->clks[i]);
> + }
You don't set pd->num_clks = 0 here, which means other places that
iterate over the clocks might race with this and try to use clocks that
have been unprepared/put.
This might be over-paranoid, but in particular, this could race with
rockchip_pd_power().
Also not setting the pd->num_clks to zero would be a problem for a
power-controller that is configured as a module which could be unloaded
and reloaded (I know that doesn't really work now, but it will
eventually, I hope.)
Maybe use the mutex here? It should at least protect the zeroing of
pm->num_clks.
Kevin
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v17 3/4] soc: rockchip: power-domain: Add power domain driver
2015-09-02 18:28 ` Kevin Hilman
@ 2015-09-06 3:04 ` Caesar Wang
0 siblings, 0 replies; 9+ messages in thread
From: Caesar Wang @ 2015-09-06 3:04 UTC (permalink / raw)
To: linux-arm-kernel
Kevin,
Thanks for having a look into it.
? 2015?09?03? 02:28, Kevin Hilman ??:
> Caesar Wang <wxt@rock-chips.com> writes:
>
>> This driver is found on RK3288 SoCs.
>>
>> In order to meet high performance and low power requirements, a power
>> management unit is designed or saving power when RK3288 in low power
>> mode.
>> The RK3288 PMU is dedicated for managing the power of the whole chip.
>>
>> PMU can work in the Low Power Mode by setting bit[0] of PMU_PWRMODE_CON
>> register. After setting the register, PMU would enter the Low Power mode.
>> In the low power mode, pmu will auto power on/off the specified power
>> domain, send idle req to specified power domain, shut down/up pll and
>> so on. All of above are configurable by setting corresponding registers.
>>
>> Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> [...]
>
>> +static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < pd->num_clks; i++) {
>> + clk_unprepare(pd->clks[i]);
>> + clk_put(pd->clks[i]);
>> + }
>
> You don't set pd->num_clks = 0 here, which means other places that
> iterate over the clocks might race with this and try to use clocks that
> have been unprepared/put.
Agree, we should set the "pd->num_cloks=0' in here.
> This might be over-paranoid, but in particular, this could race with
> rockchip_pd_power().
>
> Also not setting the pd->num_clks to zero would be a problem for a
> power-controller that is configured as a module which could be unloaded
> and reloaded (I know that doesn't really work now, but it will
> eventually, I hope.)
Yep.
>
> Maybe use the mutex here? It should at least protect the zeroing of
> pm->num_clks.
Sound resonable.
Done.
---
Thanks,
Caesar
>
> Kevin
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v17 1/4] dt-bindings: add document of Rockchip power domains
2015-09-02 18:12 ` Kevin Hilman
@ 2015-09-06 10:10 ` Caesar Wang
0 siblings, 0 replies; 9+ messages in thread
From: Caesar Wang @ 2015-09-06 10:10 UTC (permalink / raw)
To: linux-arm-kernel
Kevin,
? 2015?09?03? 02:12, Kevin Hilman ??:
> Caesar Wang <wxt@rock-chips.com> writes:
>
>> This add the necessary binding documentation for the power domains
>> found on Rockchip SoCs.
>>
>> Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>>
>> ---
>>
>> Changes in v17:
>> - add the decription in detail for RK3288 SoCs.
>>
>> Changes in v16:
>> - remove the pmu node.
>>
>> Changes in v15: None
>> Changes in v14: None
>> Changes in v13: None
>> Changes in v12: None
>> Changes in v11: None
>> Changes in v10: None
>> Changes in v9:
>> - add document decription.
>>
>> Changes in v8:
>> - document go back to v2.
>>
>> Changes in v7: None
>> Changes in v6: None
>> Changes in v5: None
>> Changes in v4: None
>> Changes in v3:
>> - DT structure has changed.
>>
>> Changes in v2:
>> - move clocks to "optional".
>>
>> .../bindings/soc/rockchip/power_domain.txt | 114 +++++++++++++++++++++
>> 1 file changed, 114 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
>>
>> diff --git
>> a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
>> b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
>> new file mode 100644
>> index 0000000..4cf6b27
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
>> @@ -0,0 +1,114 @@
>> +* Rockchip Power Domains
>> +
>> +Rockchip processors include support for multiple power domains which can be
>> +powered up/down by software based on different application scenes to save power.
>> +
>> +Required properties for power domain controller:
>> +- compatible: Should be one of the following.
>> + "rockchip,rk3288-power-controller" - for RK3288 SoCs.
>> +- #power-domain-cells: Number of cells in a power-domain specifier.
>> + Should be 1 for multiple PM domains.
>> +- #address-cells: Should be 1.
>> +- #size-cells: Should be 0.
>> +
>> +Required properties for power domain sub nodes:
>> +- reg: index of the power domain, should use macros in:
>> + "include/dt-bindings/power-domain/rk3288.h" - for RK3288 type power domain.
>> +- clocks (optional): phandles to clocks which need to be enabled while power domain
>> + switches state.
>> +
>> +Example:
>> +
>> + power: power-controller {
>> + compatible = "rockchip,rk3288-power-controller";
>> + #power-domain-cells = <1>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + pd_gpu {
>> + reg = <RK3288_PD_GPU>;
>> + clocks = <&cru ACLK_GPU>;
>> + };
>> + };
>> +
>> +Node of a device using power domains must have a power-domains property,
>> +containing a phandle to the power device node and an index specifying which
>> +power domain to use.
>> +The index should use macros in:
>> + "include/dt-bindings/power-domain/rk3288.h" - for rk3288 type power domain.
>> +
>> +Example of the node using power domain:
>> +
>> + node {
>> + /* ... */
>> + power-domains = <&power RK3288_PD_GPU>;
>> + /* ... */
>> + };
>> +
>> +Others, all the device clocks being listed in the power-domains itself.
>> +All the device clocks are included in someone domians that need to enable
>> +before you operate them.
>> +
>> +As the chip designs for PM hardware. We need turn on the noc clocks,
>> +if we are operating the "pd_vio" domain to enter the idle status.
>> +
>> +As the following described in detail for every device be included in domains
>> +on RK3288 SoCs.
> IMO, the below isn't really detailed enough, and also, the details
> should be in the .dts file itself, not in the binding doc.
> In particular, it's not obvious from the current series which of the
> clocks are device clocks, and which are other/parent/infrastructure
> clocks needed for the synchronous reset.
Okay, if we add some comments in dts. Says the following example.
What do you think of it?
I'm no sure if we should add these comments in dts.
It looks like it's always awkward. We can explain in the binding doc,
maybe for better reading.
/*
* Note: 'ACLK_GPU' is the GPU clock,
* and on the ACLK_GPU_NIU (NOC).
*/
pd_gpu {
reg = <RK3288_PD_GPU>;
clocks = <&cru ACLK_GPU>;
};
/*
* Note: The following 3 are HEVC(H.265) clocks,
* and on the ACLK_HEVC_NIU (NOC).
*/
pd_hevc {
reg = <RK3288_PD_HEVC>;
clocks = <&cru ACLK_HEVC>,
<&cru SCLK_HEVC_CABAC>,
<&cru SCLK_HEVC_CORE>;
};
/*
* Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
* (video endecoder & decoder) clocks that on the
* ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
*/
pd_video {
reg = <RK3288_PD_VIDEO>;
clocks = <&cru ACLK_VCODEC>,
<&cru HCLK_VCODEC>;
};
/*
* Note: Although SCLK_* are the working clocks
* of device without including on the NOC, needed for
* synchronous reset.
*
* ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU (NOC).
* ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU (NOC).
* ACLK_RGA is on ACLK_RGA_NIU (NOC).
* The others are on HCLK_VIO_NIU (NOC).
*
* *_IEP are the Image Enhancement Processos (IEP) clocks.
* *_ISP are the Image Signal Processing (ISP) clocks.
* *_RGA are the RGA clocks.
* *_VOP* are the Visual Output Processor(VOP) clocks.
* *_EDP* are the EDP clocks.
* *_LVDS_* are the LVDS clocks.
* *_HDMI are the HDMI clocks.
* *_MIPI_* are the MIPI clocks.
*/
pd_vio {
reg = <RK3288_PD_VIO>;
clocks = <&cru ACLK_IEP>,
<&cru ACLK_ISP>,
<&cru ACLK_RGA>,
<&cru ACLK_VIP>,
<&cru ACLK_VOP0>,
<&cru ACLK_VOP1>,
<&cru DCLK_VOP0>,
<&cru DCLK_VOP1>,
<&cru HCLK_IEP>,
<&cru HCLK_ISP>,
<&cru HCLK_RGA>,
<&cru HCLK_VIP>,
<&cru HCLK_VOP0>,
<&cru HCLK_VOP1>,
<&cru PCLK_EDP_CTRL>,
<&cru PCLK_HDMI_CTRL>,
<&cru PCLK_LVDS_PHY>,
<&cru PCLK_MIPI_CSI>,
<&cru PCLK_MIPI_DSI0>,
<&cru PCLK_MIPI_DSI1>,
<&cru SCLK_EDP_24M>,
<&cru SCLK_EDP>,
<&cru SCLK_ISP_JPE>,
<&cru SCLK_ISP>,
<&cru SCLK_RGA>;
};
---
Thanks,
Caesar
> Kevin
>
>> + /* GPU's ACLK_GPU on the ACLK_GPU_NIU */
>> + pd_gpu {
>> + reg = <RK3288_PD_GPU>;
>> + clocks = <&cru ACLK_GPU>;
>> + };
>> +
>> + /* HEVC AXI clocks */
>> + pd_hevc {
>> + reg = <RK3288_PD_HEVC>;
>> + clocks = <&cru ACLK_HEVC>,
>> + <&cru SCLK_HEVC_CABAC>,
>> + <&cru SCLK_HEVC_CORE>,
>> + <&cru HCLK_HEVC>;
>> + };
>> +
>> + /*
>> + * RGA, VOP, MIPI, LVDS, EDP..., says the ACLK* on the ACLK_VIO_NIU,
>> + * others are on the HCLK_VIO_NIU.
>> + */
>> + pd_vio {
>> + reg = <RK3288_PD_VIO>;
>> + clocks = <&cru ACLK_IEP>,
>> + <&cru ACLK_ISP>,
>> + <&cru ACLK_RGA>,
>> + <&cru ACLK_VIP>,
>> + <&cru ACLK_VOP0>,
>> + <&cru ACLK_VOP1>,
>> + <&cru DCLK_VOP0>,
>> + <&cru DCLK_VOP1>,
>> + <&cru HCLK_IEP>,
>> + <&cru HCLK_ISP>,
>> + <&cru HCLK_RGA>,
>> + <&cru HCLK_VIP>,
>> + <&cru HCLK_VOP0>,
>> + <&cru HCLK_VOP1>,
>> + <&cru PCLK_EDP_CTRL>,
>> + <&cru PCLK_HDMI_CTRL>,
>> + <&cru PCLK_LVDS_PHY>,
>> + <&cru PCLK_MIPI_CSI>,
>> + <&cru PCLK_MIPI_DSI0>,
>> + <&cru PCLK_MIPI_DSI1>,
>> + <&cru SCLK_EDP_24M>,
>> + <&cru SCLK_EDP>,
>> + <&cru SCLK_ISP_JPE>,
>> + <&cru SCLK_ISP>,
>> + <&cru SCLK_RGA>;
>> + };
>> +
>> + /*
>> + * Video's ACLK_VCODEC on the ACLK_VCODEC_NIU, Video's HCLK_VCODEC,
>> + * on the HCLK_VCODEC_NIU.
>> + */
>> + pd_video {
>> + reg = <RK3288_PD_VIDEO>;
>> + clocks = <&cru ACLK_VCODEC>,
>> + <&cru HCLK_VCODEC>;
>> + };
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2015-09-06 10:10 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-09-02 8:59 [PATCH v17 0/4] ARM: rk3288: Add PM Domain support Caesar Wang
2015-09-02 8:59 ` [PATCH v17 1/4] dt-bindings: add document of Rockchip power domains Caesar Wang
2015-09-02 18:12 ` Kevin Hilman
2015-09-06 10:10 ` Caesar Wang
2015-09-02 8:59 ` [PATCH v17 2/4] ARM: power-domain: rockchip: add all the domain type on RK3288 SoCs Caesar Wang
2015-09-02 8:59 ` [PATCH v17 3/4] soc: rockchip: power-domain: Add power domain driver Caesar Wang
2015-09-02 18:28 ` Kevin Hilman
2015-09-06 3:04 ` Caesar Wang
2015-09-02 8:59 ` [PATCH v17 4/4] ARM: dts: add the support power-domain node on RK3288 SoCs Caesar Wang
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