* [PATCH 1/5] clk: sunxi: Add support for the H3 usb phy clocks
@ 2015-11-15 19:46 Hans de Goede
2015-11-15 19:46 ` [PATCH 2/5] phy-sun4i-usb: Add support for the host usb-phys found on the H3 SoC Hans de Goede
` (5 more replies)
0 siblings, 6 replies; 18+ messages in thread
From: Hans de Goede @ 2015-11-15 19:46 UTC (permalink / raw)
To: linux-arm-kernel
From: Reinder de Haan <patchesrdh@mveas.com>
The H3 has a usb-phy clk register which is similar to that of earlier
SoCs, but with support for a larger number of phys. So we can simply add
a new set of clk-data and a new compatible and be done with it.
Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-usb.c | 12 ++++++++++++
2 files changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index d303dec..23e7bce 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -70,6 +70,7 @@ Required properties:
"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
"allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23
+ "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3
"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
diff --git a/drivers/clk/sunxi/clk-usb.c b/drivers/clk/sunxi/clk-usb.c
index 1a72cd6..67b8e38 100644
--- a/drivers/clk/sunxi/clk-usb.c
+++ b/drivers/clk/sunxi/clk-usb.c
@@ -243,3 +243,15 @@ static void __init sun9i_a80_usb_phy_setup(struct device_node *node)
sunxi_usb_clk_setup(node, &sun9i_a80_usb_phy_data, &a80_usb_phy_lock);
}
CLK_OF_DECLARE(sun9i_a80_usb_phy, "allwinner,sun9i-a80-usb-phy-clk", sun9i_a80_usb_phy_setup);
+
+static const struct usb_clk_data sun8i_h3_usb_clk_data __initconst = {
+ .clk_mask = BIT(19) | BIT(18) | BIT(17) | BIT(16) |
+ BIT(11) | BIT(10) | BIT(9) | BIT(8),
+ .reset_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
+};
+
+static void __init sun8i_h3_usb_setup(struct device_node *node)
+{
+ sunxi_usb_clk_setup(node, &sun8i_h3_usb_clk_data, &sun4i_a10_usb_lock);
+}
+CLK_OF_DECLARE(sun8i_h3_usb, "allwinner,sun8i-h3-usb-clk", sun8i_h3_usb_setup);
--
2.5.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/5] phy-sun4i-usb: Add support for the host usb-phys found on the H3 SoC
2015-11-15 19:46 [PATCH 1/5] clk: sunxi: Add support for the H3 usb phy clocks Hans de Goede
@ 2015-11-15 19:46 ` Hans de Goede
2015-11-16 15:29 ` Rob Herring
2015-11-20 19:49 ` [linux-sunxi] " Priit Laes
2015-11-15 19:46 ` [PATCH 3/5] ARM: dts: sun8i: Add support for H3 usb clocks Hans de Goede
` (4 subsequent siblings)
5 siblings, 2 replies; 18+ messages in thread
From: Hans de Goede @ 2015-11-15 19:46 UTC (permalink / raw)
To: linux-arm-kernel
From: Reinder de Haan <patchesrdh@mveas.com>
Note this commit only adds support for phys 1-3, phy 0, the otg phy, is
not yet (fully) supported after this commit.
Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
.../devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
drivers/phy/phy-sun4i-usb.c | 67 +++++++++++++++++-----
2 files changed, 53 insertions(+), 15 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index 0cebf74..95736d7 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -9,6 +9,7 @@ Required properties:
* allwinner,sun7i-a20-usb-phy
* allwinner,sun8i-a23-usb-phy
* allwinner,sun8i-a33-usb-phy
+ * allwinner,sun8i-h3-usb-phy
- reg : a list of offset + length pairs
- reg-names :
* "phy_ctrl"
diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index b12964b..17f97ab 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -46,6 +46,9 @@
#define REG_PHYBIST 0x08
#define REG_PHYTUNE 0x0c
#define REG_PHYCTL_A33 0x10
+#define REG_PHY_UNK_H3 0x20
+
+#define REG_PMU_UNK_H3 0x10
#define PHYCTL_DATA BIT(7)
@@ -79,7 +82,7 @@
#define PHY_DISCON_TH_SEL 0x2a
#define PHY_SQUELCH_DETECT 0x3c
-#define MAX_PHYS 3
+#define MAX_PHYS 4
/*
* Note do not raise the debounce time, we must report Vusb high within 100ms
@@ -88,12 +91,19 @@
#define DEBOUNCE_TIME msecs_to_jiffies(50)
#define POLL_TIME msecs_to_jiffies(250)
+enum sun4i_usb_phy_type {
+ sun4i_a10_phy,
+ sun8i_a33_phy,
+ sun8i_h3_phy
+};
+
struct sun4i_usb_phy_data {
+ struct device *dev;
void __iomem *base;
struct mutex mutex;
int num_phys;
u32 disc_thresh;
- bool has_a33_phyctl;
+ enum sun4i_usb_phy_type type;
struct sun4i_usb_phy {
struct phy *phy;
void __iomem *pmu;
@@ -164,12 +174,18 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
mutex_lock(&phy_data->mutex);
- if (phy_data->has_a33_phyctl) {
+ switch (phy_data->type) {
+ case sun4i_a10_phy:
+ phyctl = phy_data->base + REG_PHYCTL_A10;
+ break;
+ case sun8i_a33_phy:
phyctl = phy_data->base + REG_PHYCTL_A33;
/* A33 needs us to set phyctl to 0 explicitly */
writel(0, phyctl);
- } else {
- phyctl = phy_data->base + REG_PHYCTL_A10;
+ break;
+ case sun8i_h3_phy:
+ dev_err(phy_data->dev, "H3 usb_phy_write is not supported\n");
+ break;
}
for (i = 0; i < len; i++) {
@@ -230,6 +246,7 @@ static int sun4i_usb_phy_init(struct phy *_phy)
struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
int ret;
+ u32 val;
ret = clk_prepare_enable(phy->clk);
if (ret)
@@ -241,15 +258,26 @@ static int sun4i_usb_phy_init(struct phy *_phy)
return ret;
}
- /* Enable USB 45 Ohm resistor calibration */
- if (phy->index == 0)
- sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
+ if (data->type == sun8i_h3_phy) {
+ if (phy->index == 0) {
+ val = readl(data->base + REG_PHY_UNK_H3);
+ writel(val & ~1, data->base + REG_PHY_UNK_H3);
+ }
+
+ val = readl(phy->pmu + REG_PMU_UNK_H3);
+ writel(val & ~2, phy->pmu + REG_PMU_UNK_H3);
+ } else {
+ /* Enable USB 45 Ohm resistor calibration */
+ if (phy->index == 0)
+ sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
- /* Adjust PHY's magnitude and rate */
- sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
+ /* Adjust PHY's magnitude and rate */
+ sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
- /* Disconnect threshold adjustment */
- sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, data->disc_thresh, 2);
+ /* Disconnect threshold adjustment */
+ sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
+ data->disc_thresh, 2);
+ }
sun4i_usb_phy_passby(phy, 1);
@@ -522,11 +550,14 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
mutex_init(&data->mutex);
INIT_DELAYED_WORK(&data->detect, sun4i_usb_phy0_id_vbus_det_scan);
dev_set_drvdata(dev, data);
+ data->dev = dev;
if (of_device_is_compatible(np, "allwinner,sun5i-a13-usb-phy") ||
of_device_is_compatible(np, "allwinner,sun8i-a23-usb-phy") ||
of_device_is_compatible(np, "allwinner,sun8i-a33-usb-phy"))
data->num_phys = 2;
+ else if (of_device_is_compatible(np, "allwinner,sun8i-h3-usb-phy"))
+ data->num_phys = 4;
else
data->num_phys = 3;
@@ -538,13 +569,18 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
if (of_device_is_compatible(np, "allwinner,sun6i-a31-usb-phy") ||
of_device_is_compatible(np, "allwinner,sun8i-a23-usb-phy") ||
- of_device_is_compatible(np, "allwinner,sun8i-a33-usb-phy"))
+ of_device_is_compatible(np, "allwinner,sun8i-a33-usb-phy") ||
+ of_device_is_compatible(np, "allwinner,sun8i-h3-usb-phy"))
dedicated_clocks = true;
else
dedicated_clocks = false;
if (of_device_is_compatible(np, "allwinner,sun8i-a33-usb-phy"))
- data->has_a33_phyctl = true;
+ data->type = sun8i_a33_phy;
+ else if (of_device_is_compatible(np, "allwinner,sun8i-h3-usb-phy"))
+ data->type = sun8i_h3_phy;
+ else
+ data->type = sun4i_a10_phy;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_ctrl");
data->base = devm_ioremap_resource(dev, res);
@@ -620,7 +656,7 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
return PTR_ERR(phy->reset);
}
- if (i) { /* No pmu for usbc0 */
+ if (data->type == sun8i_h3_phy || i != 0) {
snprintf(name, sizeof(name), "pmu%d", i);
res = platform_get_resource_byname(pdev,
IORESOURCE_MEM, name);
@@ -696,6 +732,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
{ .compatible = "allwinner,sun7i-a20-usb-phy" },
{ .compatible = "allwinner,sun8i-a23-usb-phy" },
{ .compatible = "allwinner,sun8i-a33-usb-phy" },
+ { .compatible = "allwinner,sun8i-h3-usb-phy" },
{ },
};
MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
--
2.5.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 3/5] ARM: dts: sun8i: Add support for H3 usb clocks
2015-11-15 19:46 [PATCH 1/5] clk: sunxi: Add support for the H3 usb phy clocks Hans de Goede
2015-11-15 19:46 ` [PATCH 2/5] phy-sun4i-usb: Add support for the host usb-phys found on the H3 SoC Hans de Goede
@ 2015-11-15 19:46 ` Hans de Goede
2015-11-16 2:41 ` [linux-sunxi] " Chen-Yu Tsai
2015-11-15 19:46 ` [PATCH 4/5] ARM: dts: sun8i: Add usbphy and usb host controller nodes Hans de Goede
` (3 subsequent siblings)
5 siblings, 1 reply; 18+ messages in thread
From: Hans de Goede @ 2015-11-15 19:46 UTC (permalink / raw)
To: linux-arm-kernel
From: Reinder de Haan <patchesrdh@mveas.com>
Add a node describing the usb-clks found on the H3.
Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index c18b5f7..22ff593 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -266,6 +266,18 @@
"mmc2_sample";
};
+ usb_clk: clk at 01c200cc {
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ compatible = "allwinner,sun8i-h3-usb-clk";
+ reg = <0x01c200cc 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "usb_phy0", "usb_phy1",
+ "usb_phy2", "usb_phy3",
+ "usb_ohci0", "usb_ohci1",
+ "usb_ohci2", "usb_ohci3";
+ };
+
mbus_clk: clk at 01c2015c {
#clock-cells = <0>;
compatible = "allwinner,sun8i-a23-mbus-clk";
--
2.5.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 4/5] ARM: dts: sun8i: Add usbphy and usb host controller nodes
2015-11-15 19:46 [PATCH 1/5] clk: sunxi: Add support for the H3 usb phy clocks Hans de Goede
2015-11-15 19:46 ` [PATCH 2/5] phy-sun4i-usb: Add support for the host usb-phys found on the H3 SoC Hans de Goede
2015-11-15 19:46 ` [PATCH 3/5] ARM: dts: sun8i: Add support for H3 usb clocks Hans de Goede
@ 2015-11-15 19:46 ` Hans de Goede
2015-11-15 19:46 ` [PATCH 5/5] ARM: dts: sun8i-h3-orangepi-plus: Enable USB host controllers Hans de Goede
` (2 subsequent siblings)
5 siblings, 0 replies; 18+ messages in thread
From: Hans de Goede @ 2015-11-15 19:46 UTC (permalink / raw)
To: linux-arm-kernel
From: Reinder de Haan <patchesrdh@mveas.com>
Add nodes describing the H3's usbphy and usb host controller nodes.
Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 101 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 101 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 22ff593..0faa38a 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -359,6 +359,107 @@
#size-cells = <0>;
};
+ usbphy: phy at 01c19400 {
+ compatible = "allwinner,sun8i-h3-usb-phy";
+ reg = <0x01c19400 0x2c>,
+ <0x01c1a800 0x4>,
+ <0x01c1b800 0x4>,
+ <0x01c1c800 0x4>,
+ <0x01c1d800 0x4>;
+ reg-names = "phy_ctrl",
+ "pmu0",
+ "pmu1",
+ "pmu2",
+ "pmu3";
+ clocks = <&usb_clk 8>,
+ <&usb_clk 9>,
+ <&usb_clk 10>,
+ <&usb_clk 11>;
+ clock-names = "usb0_phy",
+ "usb1_phy",
+ "usb2_phy",
+ "usb3_phy";
+ resets = <&usb_clk 0>,
+ <&usb_clk 1>,
+ <&usb_clk 2>,
+ <&usb_clk 3>;
+ reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset",
+ "usb3_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci1: usb at 01c1b000 {
+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+ reg = <0x01c1b000 0x100>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 25>, <&bus_gates 29>;
+ resets = <&bus_rst 25>, <&bus_rst 29>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb at 01c1b400 {
+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+ reg = <0x01c1b400 0x100>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 29>, <&bus_gates 25>,
+ <&usb_clk 17>;
+ resets = <&bus_rst 29>, <&bus_rst 25>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci2: usb at 01c1c000 {
+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+ reg = <0x01c1c000 0x100>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 26>, <&bus_gates 30>;
+ resets = <&bus_rst 26>, <&bus_rst 30>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci2: usb at 01c1c400 {
+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+ reg = <0x01c1c400 0x100>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 30>, <&bus_gates 26>,
+ <&usb_clk 18>;
+ resets = <&bus_rst 30>, <&bus_rst 26>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci3: usb at 01c1d000 {
+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+ reg = <0x01c1d000 0x100>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 27>, <&bus_gates 31>;
+ resets = <&bus_rst 27>, <&bus_rst 31>;
+ phys = <&usbphy 3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci3: usb at 01c1d400 {
+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+ reg = <0x01c1d400 0x100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 31>, <&bus_gates 27>,
+ <&usb_clk 19>;
+ resets = <&bus_rst 31>, <&bus_rst 27>;
+ phys = <&usbphy 3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
pio: pinctrl at 01c20800 {
compatible = "allwinner,sun8i-h3-pinctrl";
reg = <0x01c20800 0x400>;
--
2.5.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 5/5] ARM: dts: sun8i-h3-orangepi-plus: Enable USB host controllers
2015-11-15 19:46 [PATCH 1/5] clk: sunxi: Add support for the H3 usb phy clocks Hans de Goede
` (2 preceding siblings ...)
2015-11-15 19:46 ` [PATCH 4/5] ARM: dts: sun8i: Add usbphy and usb host controller nodes Hans de Goede
@ 2015-11-15 19:46 ` Hans de Goede
2015-11-16 3:00 ` [linux-sunxi] " Chen-Yu Tsai
2015-11-16 2:36 ` [linux-sunxi] [PATCH 1/5] clk: sunxi: Add support for the H3 usb phy clocks Chen-Yu Tsai
2015-11-16 15:30 ` Rob Herring
5 siblings, 1 reply; 18+ messages in thread
From: Hans de Goede @ 2015-11-15 19:46 UTC (permalink / raw)
To: linux-arm-kernel
From: Reinder de Haan <patchesrdh@mveas.com>
Enable the 3 pairs of USB host controllers used on the Orange Pi Plus.
Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
index e67df59..e05a409 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
@@ -60,6 +60,18 @@
};
};
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
@@ -70,8 +82,24 @@
status = "okay";
};
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
+
+&usbphy {
+ status = "okay";
+};
--
2.5.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [linux-sunxi] [PATCH 1/5] clk: sunxi: Add support for the H3 usb phy clocks
2015-11-15 19:46 [PATCH 1/5] clk: sunxi: Add support for the H3 usb phy clocks Hans de Goede
` (3 preceding siblings ...)
2015-11-15 19:46 ` [PATCH 5/5] ARM: dts: sun8i-h3-orangepi-plus: Enable USB host controllers Hans de Goede
@ 2015-11-16 2:36 ` Chen-Yu Tsai
2015-11-20 12:49 ` Maxime Ripard
2015-11-16 15:30 ` Rob Herring
5 siblings, 1 reply; 18+ messages in thread
From: Chen-Yu Tsai @ 2015-11-16 2:36 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Nov 16, 2015 at 3:46 AM, Hans de Goede <hdegoede@redhat.com> wrote:
> From: Reinder de Haan <patchesrdh@mveas.com>
>
> The H3 has a usb-phy clk register which is similar to that of earlier
> SoCs, but with support for a larger number of phys. So we can simply add
> a new set of clk-data and a new compatible and be done with it.
>
> Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
> ---
> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
> drivers/clk/sunxi/clk-usb.c | 12 ++++++++++++
> 2 files changed, 13 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index d303dec..23e7bce 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -70,6 +70,7 @@ Required properties:
> "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
> "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
> "allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23
> + "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3
> "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
> "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
>
> diff --git a/drivers/clk/sunxi/clk-usb.c b/drivers/clk/sunxi/clk-usb.c
> index 1a72cd6..67b8e38 100644
> --- a/drivers/clk/sunxi/clk-usb.c
> +++ b/drivers/clk/sunxi/clk-usb.c
> @@ -243,3 +243,15 @@ static void __init sun9i_a80_usb_phy_setup(struct device_node *node)
> sunxi_usb_clk_setup(node, &sun9i_a80_usb_phy_data, &a80_usb_phy_lock);
> }
> CLK_OF_DECLARE(sun9i_a80_usb_phy, "allwinner,sun9i-a80-usb-phy-clk", sun9i_a80_usb_phy_setup);
> +
> +static const struct usb_clk_data sun8i_h3_usb_clk_data __initconst = {
> + .clk_mask = BIT(19) | BIT(18) | BIT(17) | BIT(16) |
> + BIT(11) | BIT(10) | BIT(9) | BIT(8),
> + .reset_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
> +};
> +
> +static void __init sun8i_h3_usb_setup(struct device_node *node)
> +{
> + sunxi_usb_clk_setup(node, &sun8i_h3_usb_clk_data, &sun4i_a10_usb_lock);
> +}
> +CLK_OF_DECLARE(sun8i_h3_usb, "allwinner,sun8i-h3-usb-clk", sun8i_h3_usb_setup);
> --
> 2.5.0
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe at googlegroups.com.
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [linux-sunxi] [PATCH 3/5] ARM: dts: sun8i: Add support for H3 usb clocks
2015-11-15 19:46 ` [PATCH 3/5] ARM: dts: sun8i: Add support for H3 usb clocks Hans de Goede
@ 2015-11-16 2:41 ` Chen-Yu Tsai
0 siblings, 0 replies; 18+ messages in thread
From: Chen-Yu Tsai @ 2015-11-16 2:41 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Nov 16, 2015 at 3:46 AM, Hans de Goede <hdegoede@redhat.com> wrote:
> From: Reinder de Haan <patchesrdh@mveas.com>
>
> Add a node describing the usb-clks found on the H3.
>
> Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
(Also updated Mike's email in my reply.)
> ---
> arch/arm/boot/dts/sun8i-h3.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> index c18b5f7..22ff593 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -266,6 +266,18 @@
> "mmc2_sample";
> };
>
> + usb_clk: clk at 01c200cc {
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + compatible = "allwinner,sun8i-h3-usb-clk";
> + reg = <0x01c200cc 0x4>;
> + clocks = <&osc24M>;
> + clock-output-names = "usb_phy0", "usb_phy1",
> + "usb_phy2", "usb_phy3",
> + "usb_ohci0", "usb_ohci1",
> + "usb_ohci2", "usb_ohci3";
> + };
> +
> mbus_clk: clk at 01c2015c {
> #clock-cells = <0>;
> compatible = "allwinner,sun8i-a23-mbus-clk";
> --
> 2.5.0
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe at googlegroups.com.
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [linux-sunxi] [PATCH 5/5] ARM: dts: sun8i-h3-orangepi-plus: Enable USB host controllers
2015-11-15 19:46 ` [PATCH 5/5] ARM: dts: sun8i-h3-orangepi-plus: Enable USB host controllers Hans de Goede
@ 2015-11-16 3:00 ` Chen-Yu Tsai
2015-11-16 8:11 ` Hans de Goede
0 siblings, 1 reply; 18+ messages in thread
From: Chen-Yu Tsai @ 2015-11-16 3:00 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Mon, Nov 16, 2015 at 3:46 AM, Hans de Goede <hdegoede@redhat.com> wrote:
> From: Reinder de Haan <patchesrdh@mveas.com>
>
> Enable the 3 pairs of USB host controllers used on the Orange Pi Plus.
>
> Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
> index e67df59..e05a409 100644
> --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
> @@ -60,6 +60,18 @@
> };
> };
>
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&ehci2 {
> + status = "okay";
> +};
> +
> +&ehci3 {
> + status = "okay";
> +};
> +
> &mmc0 {
> pinctrl-names = "default";
> pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
> @@ -70,8 +82,24 @@
> status = "okay";
> };
>
> +&ohci1 {
> + status = "okay";
> +};
This controller is connected to a FE1.1s USB 2.0 hub, giving us the
four usable external USB ports. We shouldn't need to enable OHCI.
> +
> +&ohci2 {
> + status = "okay";
> +};
According to the schematics, this port is never used. Please remove.
> +&ohci3 {
> + status = "okay";
> +};
This is connected to the GL830 USB-SATA bridge. Again, OHCI isn't
needed.
> +
> &uart0 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart0_pins_a>;
> status = "okay";
> };
> +
> +&usbphy {
> + status = "okay";
And what about power supplies / regulators?
Regards
ChenYu
> +};
> --
> 2.5.0
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe at googlegroups.com.
> For more options, visit https://groups.google.com/d/optout.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [linux-sunxi] [PATCH 5/5] ARM: dts: sun8i-h3-orangepi-plus: Enable USB host controllers
2015-11-16 3:00 ` [linux-sunxi] " Chen-Yu Tsai
@ 2015-11-16 8:11 ` Hans de Goede
2015-11-17 16:12 ` [PATCH] " Jens Kuske
0 siblings, 1 reply; 18+ messages in thread
From: Hans de Goede @ 2015-11-16 8:11 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On 16-11-15 04:00, Chen-Yu Tsai wrote:
> Hi,
>
> On Mon, Nov 16, 2015 at 3:46 AM, Hans de Goede <hdegoede@redhat.com> wrote:
>> From: Reinder de Haan <patchesrdh@mveas.com>
>>
>> Enable the 3 pairs of USB host controllers used on the Orange Pi Plus.
>>
>> Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>> ---
>> arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 28 ++++++++++++++++++++++++++++
>> 1 file changed, 28 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
>> index e67df59..e05a409 100644
>> --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
>> +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
>> @@ -60,6 +60,18 @@
>> };
>> };
>>
>> +&ehci1 {
>> + status = "okay";
>> +};
>> +
>> +&ehci2 {
>> + status = "okay";
>> +};
>> +
>> +&ehci3 {
>> + status = "okay";
>> +};
>> +
>> &mmc0 {
>> pinctrl-names = "default";
>> pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
>> @@ -70,8 +82,24 @@
>> status = "okay";
>> };
>>
>> +&ohci1 {
>> + status = "okay";
>> +};
>
> This controller is connected to a FE1.1s USB 2.0 hub, giving us the
> four usable external USB ports. We shouldn't need to enable OHCI.
Right, my bad, I actually tested this on an orangepi pc, for which
we need to create a new dts of course, the orangepi pc does have
all 3 controllers routed directly to the outside.
>> +
>> +&ohci2 {
>> + status = "okay";
>> +};
>
> According to the schematics, this port is never used. Please remove.
The same goes for ehci2 then, otherwise ack.
>
>> +&ohci3 {
>> + status = "okay";
>> +};
>
> This is connected to the GL830 USB-SATA bridge. Again, OHCI isn't
> needed.
My bad again.
>> +
>> &uart0 {
>> pinctrl-names = "default";
>> pinctrl-0 = <&uart0_pins_a>;
>> status = "okay";
>> };
>> +
>> +&usbphy {
>> + status = "okay";
>
> And what about power supplies / regulators?
On the orangepi pc none are needed. Jens can you test this
series (or my sunxi-wip kernel branch) on your orangepi plus ?
and send an updated version of this patch with the necessary changes?
I do not actually have an orangepi plus.
Regards,
Hans
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 2/5] phy-sun4i-usb: Add support for the host usb-phys found on the H3 SoC
2015-11-15 19:46 ` [PATCH 2/5] phy-sun4i-usb: Add support for the host usb-phys found on the H3 SoC Hans de Goede
@ 2015-11-16 15:29 ` Rob Herring
2015-11-20 19:49 ` [linux-sunxi] " Priit Laes
1 sibling, 0 replies; 18+ messages in thread
From: Rob Herring @ 2015-11-16 15:29 UTC (permalink / raw)
To: linux-arm-kernel
On Sun, Nov 15, 2015 at 08:46:14PM +0100, Hans de Goede wrote:
> From: Reinder de Haan <patchesrdh@mveas.com>
>
> Note this commit only adds support for phys 1-3, phy 0, the otg phy, is
> not yet (fully) supported after this commit.
>
> Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> .../devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
Acked-by: Rob Herring <robh@kernel.org>
> drivers/phy/phy-sun4i-usb.c | 67 +++++++++++++++++-----
> 2 files changed, 53 insertions(+), 15 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> index 0cebf74..95736d7 100644
> --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> @@ -9,6 +9,7 @@ Required properties:
> * allwinner,sun7i-a20-usb-phy
> * allwinner,sun8i-a23-usb-phy
> * allwinner,sun8i-a33-usb-phy
> + * allwinner,sun8i-h3-usb-phy
> - reg : a list of offset + length pairs
> - reg-names :
> * "phy_ctrl"
> diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
> index b12964b..17f97ab 100644
> --- a/drivers/phy/phy-sun4i-usb.c
> +++ b/drivers/phy/phy-sun4i-usb.c
> @@ -46,6 +46,9 @@
> #define REG_PHYBIST 0x08
> #define REG_PHYTUNE 0x0c
> #define REG_PHYCTL_A33 0x10
> +#define REG_PHY_UNK_H3 0x20
> +
> +#define REG_PMU_UNK_H3 0x10
>
> #define PHYCTL_DATA BIT(7)
>
> @@ -79,7 +82,7 @@
> #define PHY_DISCON_TH_SEL 0x2a
> #define PHY_SQUELCH_DETECT 0x3c
>
> -#define MAX_PHYS 3
> +#define MAX_PHYS 4
>
> /*
> * Note do not raise the debounce time, we must report Vusb high within 100ms
> @@ -88,12 +91,19 @@
> #define DEBOUNCE_TIME msecs_to_jiffies(50)
> #define POLL_TIME msecs_to_jiffies(250)
>
> +enum sun4i_usb_phy_type {
> + sun4i_a10_phy,
> + sun8i_a33_phy,
> + sun8i_h3_phy
> +};
> +
> struct sun4i_usb_phy_data {
> + struct device *dev;
> void __iomem *base;
> struct mutex mutex;
> int num_phys;
> u32 disc_thresh;
> - bool has_a33_phyctl;
> + enum sun4i_usb_phy_type type;
> struct sun4i_usb_phy {
> struct phy *phy;
> void __iomem *pmu;
> @@ -164,12 +174,18 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
>
> mutex_lock(&phy_data->mutex);
>
> - if (phy_data->has_a33_phyctl) {
> + switch (phy_data->type) {
> + case sun4i_a10_phy:
> + phyctl = phy_data->base + REG_PHYCTL_A10;
> + break;
> + case sun8i_a33_phy:
> phyctl = phy_data->base + REG_PHYCTL_A33;
> /* A33 needs us to set phyctl to 0 explicitly */
> writel(0, phyctl);
> - } else {
> - phyctl = phy_data->base + REG_PHYCTL_A10;
> + break;
> + case sun8i_h3_phy:
> + dev_err(phy_data->dev, "H3 usb_phy_write is not supported\n");
> + break;
> }
>
> for (i = 0; i < len; i++) {
> @@ -230,6 +246,7 @@ static int sun4i_usb_phy_init(struct phy *_phy)
> struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
> struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
> int ret;
> + u32 val;
>
> ret = clk_prepare_enable(phy->clk);
> if (ret)
> @@ -241,15 +258,26 @@ static int sun4i_usb_phy_init(struct phy *_phy)
> return ret;
> }
>
> - /* Enable USB 45 Ohm resistor calibration */
> - if (phy->index == 0)
> - sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
> + if (data->type == sun8i_h3_phy) {
> + if (phy->index == 0) {
> + val = readl(data->base + REG_PHY_UNK_H3);
> + writel(val & ~1, data->base + REG_PHY_UNK_H3);
> + }
> +
> + val = readl(phy->pmu + REG_PMU_UNK_H3);
> + writel(val & ~2, phy->pmu + REG_PMU_UNK_H3);
> + } else {
> + /* Enable USB 45 Ohm resistor calibration */
> + if (phy->index == 0)
> + sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
>
> - /* Adjust PHY's magnitude and rate */
> - sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
> + /* Adjust PHY's magnitude and rate */
> + sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
>
> - /* Disconnect threshold adjustment */
> - sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, data->disc_thresh, 2);
> + /* Disconnect threshold adjustment */
> + sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
> + data->disc_thresh, 2);
> + }
>
> sun4i_usb_phy_passby(phy, 1);
>
> @@ -522,11 +550,14 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
> mutex_init(&data->mutex);
> INIT_DELAYED_WORK(&data->detect, sun4i_usb_phy0_id_vbus_det_scan);
> dev_set_drvdata(dev, data);
> + data->dev = dev;
>
> if (of_device_is_compatible(np, "allwinner,sun5i-a13-usb-phy") ||
> of_device_is_compatible(np, "allwinner,sun8i-a23-usb-phy") ||
> of_device_is_compatible(np, "allwinner,sun8i-a33-usb-phy"))
> data->num_phys = 2;
> + else if (of_device_is_compatible(np, "allwinner,sun8i-h3-usb-phy"))
> + data->num_phys = 4;
> else
> data->num_phys = 3;
>
> @@ -538,13 +569,18 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
>
> if (of_device_is_compatible(np, "allwinner,sun6i-a31-usb-phy") ||
> of_device_is_compatible(np, "allwinner,sun8i-a23-usb-phy") ||
> - of_device_is_compatible(np, "allwinner,sun8i-a33-usb-phy"))
> + of_device_is_compatible(np, "allwinner,sun8i-a33-usb-phy") ||
> + of_device_is_compatible(np, "allwinner,sun8i-h3-usb-phy"))
> dedicated_clocks = true;
> else
> dedicated_clocks = false;
>
> if (of_device_is_compatible(np, "allwinner,sun8i-a33-usb-phy"))
> - data->has_a33_phyctl = true;
> + data->type = sun8i_a33_phy;
> + else if (of_device_is_compatible(np, "allwinner,sun8i-h3-usb-phy"))
> + data->type = sun8i_h3_phy;
> + else
> + data->type = sun4i_a10_phy;
>
> res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_ctrl");
> data->base = devm_ioremap_resource(dev, res);
> @@ -620,7 +656,7 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
> return PTR_ERR(phy->reset);
> }
>
> - if (i) { /* No pmu for usbc0 */
> + if (data->type == sun8i_h3_phy || i != 0) {
> snprintf(name, sizeof(name), "pmu%d", i);
> res = platform_get_resource_byname(pdev,
> IORESOURCE_MEM, name);
> @@ -696,6 +732,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
> { .compatible = "allwinner,sun7i-a20-usb-phy" },
> { .compatible = "allwinner,sun8i-a23-usb-phy" },
> { .compatible = "allwinner,sun8i-a33-usb-phy" },
> + { .compatible = "allwinner,sun8i-h3-usb-phy" },
> { },
> };
> MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
> --
> 2.5.0
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 1/5] clk: sunxi: Add support for the H3 usb phy clocks
2015-11-15 19:46 [PATCH 1/5] clk: sunxi: Add support for the H3 usb phy clocks Hans de Goede
` (4 preceding siblings ...)
2015-11-16 2:36 ` [linux-sunxi] [PATCH 1/5] clk: sunxi: Add support for the H3 usb phy clocks Chen-Yu Tsai
@ 2015-11-16 15:30 ` Rob Herring
5 siblings, 0 replies; 18+ messages in thread
From: Rob Herring @ 2015-11-16 15:30 UTC (permalink / raw)
To: linux-arm-kernel
On Sun, Nov 15, 2015 at 08:46:13PM +0100, Hans de Goede wrote:
> From: Reinder de Haan <patchesrdh@mveas.com>
>
> The H3 has a usb-phy clk register which is similar to that of earlier
> SoCs, but with support for a larger number of phys. So we can simply add
> a new set of clk-data and a new compatible and be done with it.
>
> Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Rob Herring <robh@kernel.org>
> ---
> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
> drivers/clk/sunxi/clk-usb.c | 12 ++++++++++++
> 2 files changed, 13 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index d303dec..23e7bce 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -70,6 +70,7 @@ Required properties:
> "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
> "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
> "allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23
> + "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3
> "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
> "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
>
> diff --git a/drivers/clk/sunxi/clk-usb.c b/drivers/clk/sunxi/clk-usb.c
> index 1a72cd6..67b8e38 100644
> --- a/drivers/clk/sunxi/clk-usb.c
> +++ b/drivers/clk/sunxi/clk-usb.c
> @@ -243,3 +243,15 @@ static void __init sun9i_a80_usb_phy_setup(struct device_node *node)
> sunxi_usb_clk_setup(node, &sun9i_a80_usb_phy_data, &a80_usb_phy_lock);
> }
> CLK_OF_DECLARE(sun9i_a80_usb_phy, "allwinner,sun9i-a80-usb-phy-clk", sun9i_a80_usb_phy_setup);
> +
> +static const struct usb_clk_data sun8i_h3_usb_clk_data __initconst = {
> + .clk_mask = BIT(19) | BIT(18) | BIT(17) | BIT(16) |
> + BIT(11) | BIT(10) | BIT(9) | BIT(8),
> + .reset_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
> +};
> +
> +static void __init sun8i_h3_usb_setup(struct device_node *node)
> +{
> + sunxi_usb_clk_setup(node, &sun8i_h3_usb_clk_data, &sun4i_a10_usb_lock);
> +}
> +CLK_OF_DECLARE(sun8i_h3_usb, "allwinner,sun8i-h3-usb-clk", sun8i_h3_usb_setup);
> --
> 2.5.0
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH] ARM: dts: sun8i-h3-orangepi-plus: Enable USB host controllers
2015-11-16 8:11 ` Hans de Goede
@ 2015-11-17 16:12 ` Jens Kuske
2015-11-20 14:38 ` Hans de Goede
[not found] ` <fff9e78a-e23e-4226-9cec-67550bf09efb@googlegroups.com>
0 siblings, 2 replies; 18+ messages in thread
From: Jens Kuske @ 2015-11-17 16:12 UTC (permalink / raw)
To: linux-arm-kernel
Enable the 2 USB host controllers used on the Orange Pi Plus
and add the necessary regulators.
Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
---
Hi Hans,
with these regulators USB works on the Orange Pi Plus too.
I don't know if adding the regulators in the dts is okay, since most
regulators are defined in the sunxi-common-regulators.dtsi, but
we use different pins.
Jens
arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 44 ++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
index e67df59..1cb6c66 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
@@ -58,6 +58,35 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ reg_usb3_vbus: usb3-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb3_vbus_pin_a>;
+ regulator-name = "usb3-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&pio {
+ usb3_vbus_pin_a: usb3_vbus_pin at 0 {
+ allwinner,pins = "PG11";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
};
&mmc0 {
@@ -70,8 +99,23 @@
status = "okay";
};
+®_usb1_vbus {
+ gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
+
+&usb1_vbus_pin_a {
+ allwinner,pins = "PG13";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb3_vbus-supply = <®_usb3_vbus>;
+ status = "okay";
+};
--
2.6.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [linux-sunxi] [PATCH 1/5] clk: sunxi: Add support for the H3 usb phy clocks
2015-11-16 2:36 ` [linux-sunxi] [PATCH 1/5] clk: sunxi: Add support for the H3 usb phy clocks Chen-Yu Tsai
@ 2015-11-20 12:49 ` Maxime Ripard
0 siblings, 0 replies; 18+ messages in thread
From: Maxime Ripard @ 2015-11-20 12:49 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Nov 16, 2015 at 10:36:02AM +0800, Chen-Yu Tsai wrote:
> On Mon, Nov 16, 2015 at 3:46 AM, Hans de Goede <hdegoede@redhat.com> wrote:
> > From: Reinder de Haan <patchesrdh@mveas.com>
> >
> > The H3 has a usb-phy clk register which is similar to that of earlier
> > SoCs, but with support for a larger number of phys. So we can simply add
> > a new set of clk-data and a new compatible and be done with it.
> >
> > Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
> > Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>
> Acked-by: Chen-Yu Tsai <wens@csie.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH] ARM: dts: sun8i-h3-orangepi-plus: Enable USB host controllers
2015-11-17 16:12 ` [PATCH] " Jens Kuske
@ 2015-11-20 14:38 ` Hans de Goede
2015-11-24 7:44 ` Maxime Ripard
[not found] ` <fff9e78a-e23e-4226-9cec-67550bf09efb@googlegroups.com>
1 sibling, 1 reply; 18+ messages in thread
From: Hans de Goede @ 2015-11-20 14:38 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On 17-11-15 17:12, Jens Kuske wrote:
> Enable the 2 USB host controllers used on the Orange Pi Plus
> and add the necessary regulators.
>
> Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> Signed-off-by: Jens Kuske <jenskuske@gmail.com>
> ---
>
> Hi Hans,
>
> with these regulators USB works on the Orange Pi Plus too.
> I don't know if adding the regulators in the dts is okay, since most
> regulators are defined in the sunxi-common-regulators.dtsi, but
> we use different pins.
Thanks, I've added this to my sunxi-wip branch for now.
Regards,
Hans
p.s.
Any progress on getting the "core" H3 kernel support upstream ?
Given Arnd's remarks about how we should not hard-code the
indices in the clk driver + the very KISS nature of the
change to 1 parent-clk per gate setup I still believe
that that one is best.
Maxime ? Chen-Yu ? It would be really good to be able to
move forward with this, how do you want to proceed ?
>
> Jens
>
>
> arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 44 ++++++++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
> index e67df59..1cb6c66 100644
> --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
> @@ -58,6 +58,35 @@
> chosen {
> stdout-path = "serial0:115200n8";
> };
> +
> + reg_usb3_vbus: usb3-vbus {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&usb3_vbus_pin_a>;
> + regulator-name = "usb3-vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-boot-on;
> + enable-active-high;
> + gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>;
> + };
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&ehci3 {
> + status = "okay";
> +};
> +
> +&pio {
> + usb3_vbus_pin_a: usb3_vbus_pin at 0 {
> + allwinner,pins = "PG11";
> + allwinner,function = "gpio_out";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> };
>
> &mmc0 {
> @@ -70,8 +99,23 @@
> status = "okay";
> };
>
> +®_usb1_vbus {
> + gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +};
> +
> &uart0 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart0_pins_a>;
> status = "okay";
> };
> +
> +&usb1_vbus_pin_a {
> + allwinner,pins = "PG13";
> +};
> +
> +&usbphy {
> + usb1_vbus-supply = <®_usb1_vbus>;
> + usb3_vbus-supply = <®_usb3_vbus>;
> + status = "okay";
> +};
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [linux-sunxi] [PATCH 2/5] phy-sun4i-usb: Add support for the host usb-phys found on the H3 SoC
2015-11-15 19:46 ` [PATCH 2/5] phy-sun4i-usb: Add support for the host usb-phys found on the H3 SoC Hans de Goede
2015-11-16 15:29 ` Rob Herring
@ 2015-11-20 19:49 ` Priit Laes
2015-11-22 11:29 ` Hans de Goede
1 sibling, 1 reply; 18+ messages in thread
From: Priit Laes @ 2015-11-20 19:49 UTC (permalink / raw)
To: linux-arm-kernel
On Sun, 2015-11-15 at 20:46 +0100, Hans de Goede wrote:
> From: Reinder de Haan <patchesrdh@mveas.com>
>
> Note this commit only adds support for phys 1-3, phy 0, the otg phy,
> is
> not yet (fully) supported after this commit.
This patch seems to be causing following compile warning:
In file included from include/linux/io.h:25:0,
?????????????????from drivers/phy/phy-sun4i-usb.c:28:
drivers/phy/phy-sun4i-usb.c: In function 'sun4i_usb_phy_write': ./arch/arm/include/asm/io.h:94:2: warning: 'phyctl' may be used uninitialized in this function [-Wmaybe-uni
nitialized]
? asm volatile("strb %1, %0"
? ^
drivers/phy/phy-sun4i-usb.c:172:8: note: 'phyctl' was declared here
? void *phyctl;
>
> Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> ?.../devicetree/bindings/phy/sun4i-usb-phy.txt??????|??1 +
> ?drivers/phy/phy-sun4i-usb.c????????????????????????| 67
> +++++++++++++++++-----
> ?2 files changed, 53 insertions(+), 15 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> index 0cebf74..95736d7 100644
> --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> @@ -9,6 +9,7 @@ Required properties:
> ???* allwinner,sun7i-a20-usb-phy
> ???* allwinner,sun8i-a23-usb-phy
> ???* allwinner,sun8i-a33-usb-phy
> +??* allwinner,sun8i-h3-usb-phy
> ?- reg : a list of offset + length pairs
> ?- reg-names :
> ???* "phy_ctrl"
> diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-
> usb.c
> index b12964b..17f97ab 100644
> --- a/drivers/phy/phy-sun4i-usb.c
> +++ b/drivers/phy/phy-sun4i-usb.c
> @@ -46,6 +46,9 @@
> ?#define REG_PHYBIST 0x08
> ?#define REG_PHYTUNE 0x0c
> ?#define REG_PHYCTL_A33 0x10
> +#define REG_PHY_UNK_H3 0x20
> +
> +#define REG_PMU_UNK_H3 0x10
> ?
> ?#define PHYCTL_DATA BIT(7)
> ?
> @@ -79,7 +82,7 @@
> ?#define PHY_DISCON_TH_SEL 0x2a
> ?#define PHY_SQUELCH_DETECT 0x3c
> ?
> -#define MAX_PHYS 3
> +#define MAX_PHYS 4
> ?
> ?/*
> ? * Note do not raise the debounce time, we must report Vusb high
> within 100ms
> @@ -88,12 +91,19 @@
> ?#define DEBOUNCE_TIME msecs_to_jiffies(50)
> ?#define POLL_TIME msecs_to_jiffies(250)
> ?
> +enum sun4i_usb_phy_type {
> + sun4i_a10_phy,
> + sun8i_a33_phy,
> + sun8i_h3_phy
> +};
> +
> ?struct sun4i_usb_phy_data {
> + struct device *dev;
> ? void __iomem *base;
> ? struct mutex mutex;
> ? int num_phys;
> ? u32 disc_thresh;
> - bool has_a33_phyctl;
> + enum sun4i_usb_phy_type type;
> ? struct sun4i_usb_phy {
> ? struct phy *phy;
> ? void __iomem *pmu;
> @@ -164,12 +174,18 @@ static void sun4i_usb_phy_write(struct
> sun4i_usb_phy *phy, u32 addr, u32 data,
> ?
> ? mutex_lock(&phy_data->mutex);
> ?
> - if (phy_data->has_a33_phyctl) {
> + switch (phy_data->type) {
> + case sun4i_a10_phy:
> + phyctl = phy_data->base + REG_PHYCTL_A10;
> + break;
> + case sun8i_a33_phy:
> ? phyctl = phy_data->base + REG_PHYCTL_A33;
> ? /* A33 needs us to set phyctl to 0 explicitly */
> ? writel(0, phyctl);
> - } else {
> - phyctl = phy_data->base + REG_PHYCTL_A10;
> + break;
> + case sun8i_h3_phy:
> + dev_err(phy_data->dev, "H3 usb_phy_write is not
> supported\n");
> + break;
> ? }
> ?
> ? for (i = 0; i < len; i++) {
> @@ -230,6 +246,7 @@ static int sun4i_usb_phy_init(struct phy *_phy)
> ? struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
> ? struct sun4i_usb_phy_data *data =
> to_sun4i_usb_phy_data(phy);
> ? int ret;
> + u32 val;
> ?
> ? ret = clk_prepare_enable(phy->clk);
> ? if (ret)
> @@ -241,15 +258,26 @@ static int sun4i_usb_phy_init(struct phy *_phy)
> ? return ret;
> ? }
> ?
> - /* Enable USB 45 Ohm resistor calibration */
> - if (phy->index == 0)
> - sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
> + if (data->type == sun8i_h3_phy) {
> + if (phy->index == 0) {
> + val = readl(data->base + REG_PHY_UNK_H3);
> + writel(val & ~1, data->base +
> REG_PHY_UNK_H3);
> + }
> +
> + val = readl(phy->pmu + REG_PMU_UNK_H3);
> + writel(val & ~2, phy->pmu + REG_PMU_UNK_H3);
> + } else {
> + /* Enable USB 45 Ohm resistor calibration */
> + if (phy->index == 0)
> + sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN,
> 0x01, 1);
> ?
> - /* Adjust PHY's magnitude and rate */
> - sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
> + /* Adjust PHY's magnitude and rate */
> + sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE,
> 0x14, 5);
> ?
> - /* Disconnect threshold adjustment */
> - sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, data-
> >disc_thresh, 2);
> + /* Disconnect threshold adjustment */
> + sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
> + ????data->disc_thresh, 2);
> + }
> ?
> ? sun4i_usb_phy_passby(phy, 1);
> ?
> @@ -522,11 +550,14 @@ static int sun4i_usb_phy_probe(struct
> platform_device *pdev)
> ? mutex_init(&data->mutex);
> ? INIT_DELAYED_WORK(&data->detect,
> sun4i_usb_phy0_id_vbus_det_scan);
> ? dev_set_drvdata(dev, data);
> + data->dev = dev;
> ?
> ? if (of_device_is_compatible(np, "allwinner,sun5i-a13-usb-
> phy") ||
> ? ????of_device_is_compatible(np, "allwinner,sun8i-a23-usb-
> phy") ||
> ? ????of_device_is_compatible(np, "allwinner,sun8i-a33-usb-
> phy"))
> ? data->num_phys = 2;
> + else if (of_device_is_compatible(np, "allwinner,sun8i-h3-
> usb-phy"))
> + data->num_phys = 4;
> ? else
> ? data->num_phys = 3;
> ?
> @@ -538,13 +569,18 @@ static int sun4i_usb_phy_probe(struct
> platform_device *pdev)
> ?
> ? if (of_device_is_compatible(np, "allwinner,sun6i-a31-usb-
> phy") ||
> ? ????of_device_is_compatible(np, "allwinner,sun8i-a23-usb-
> phy") ||
> - ????of_device_is_compatible(np, "allwinner,sun8i-a33-usb-
> phy"))
> + ????of_device_is_compatible(np, "allwinner,sun8i-a33-usb-
> phy") ||
> + ????of_device_is_compatible(np, "allwinner,sun8i-h3-usb-
> phy"))
> ? dedicated_clocks = true;
> ? else
> ? dedicated_clocks = false;
> ?
> ? if (of_device_is_compatible(np, "allwinner,sun8i-a33-usb-
> phy"))
> - data->has_a33_phyctl = true;
> + data->type = sun8i_a33_phy;
> + else if (of_device_is_compatible(np, "allwinner,sun8i-h3-
> usb-phy"))
> + data->type = sun8i_h3_phy;
> + else
> + data->type = sun4i_a10_phy;
> ?
> ? res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> "phy_ctrl");
> ? data->base = devm_ioremap_resource(dev, res);
> @@ -620,7 +656,7 @@ static int sun4i_usb_phy_probe(struct
> platform_device *pdev)
> ? return PTR_ERR(phy->reset);
> ? }
> ?
> - if (i) { /* No pmu for usbc0 */
> + if (data->type == sun8i_h3_phy || i != 0) {
> ? snprintf(name, sizeof(name), "pmu%d", i);
> ? res = platform_get_resource_byname(pdev,
> ? IORESOURCE_M
> EM, name);
> @@ -696,6 +732,7 @@ static const struct of_device_id
> sun4i_usb_phy_of_match[] = {
> ? { .compatible = "allwinner,sun7i-a20-usb-phy" },
> ? { .compatible = "allwinner,sun8i-a23-usb-phy" },
> ? { .compatible = "allwinner,sun8i-a33-usb-phy" },
> + { .compatible = "allwinner,sun8i-h3-usb-phy" },
> ? { },
> ?};
> ?MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
> --
> 2.5.0
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [linux-sunxi] [PATCH 2/5] phy-sun4i-usb: Add support for the host usb-phys found on the H3 SoC
2015-11-20 19:49 ` [linux-sunxi] " Priit Laes
@ 2015-11-22 11:29 ` Hans de Goede
0 siblings, 0 replies; 18+ messages in thread
From: Hans de Goede @ 2015-11-22 11:29 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On 11/20/2015 08:49 PM, Priit Laes wrote:
> On Sun, 2015-11-15 at 20:46 +0100, Hans de Goede wrote:
>> From: Reinder de Haan <patchesrdh@mveas.com>
>>
>> Note this commit only adds support for phys 1-3, phy 0, the otg phy,
>> is
>> not yet (fully) supported after this commit.
>
>
> This patch seems to be causing following compile warning:
>
> In file included from include/linux/io.h:25:0,
> from drivers/phy/phy-sun4i-usb.c:28:
> drivers/phy/phy-sun4i-usb.c: In function 'sun4i_usb_phy_write': ./arch/arm/include/asm/io.h:94:2: warning: 'phyctl' may be used uninitialized in this function [-Wmaybe-uni
> nitialized]
> asm volatile("strb %1, %0"
> ^
> drivers/phy/phy-sun4i-usb.c:172:8: note: 'phyctl' was declared here
> void *phyctl;
Good catch, thanks the "break;" after the dev_err for the h3 case should be a return (this is a dead code path,
the dev_err is there to avoid people trying to actually use sun4i_usb_phy_write() with the h3 in
the future).
v2 of this patch fixing this is on its way.
Regards,
Hans
>
>>
>> Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>> ---
>> .../devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
>> drivers/phy/phy-sun4i-usb.c | 67
>> +++++++++++++++++-----
>> 2 files changed, 53 insertions(+), 15 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
>> b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
>> index 0cebf74..95736d7 100644
>> --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
>> +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
>> @@ -9,6 +9,7 @@ Required properties:
>> * allwinner,sun7i-a20-usb-phy
>> * allwinner,sun8i-a23-usb-phy
>> * allwinner,sun8i-a33-usb-phy
>> + * allwinner,sun8i-h3-usb-phy
>> - reg : a list of offset + length pairs
>> - reg-names :
>> * "phy_ctrl"
>> diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-
>> usb.c
>> index b12964b..17f97ab 100644
>> --- a/drivers/phy/phy-sun4i-usb.c
>> +++ b/drivers/phy/phy-sun4i-usb.c
>> @@ -46,6 +46,9 @@
>> #define REG_PHYBIST 0x08
>> #define REG_PHYTUNE 0x0c
>> #define REG_PHYCTL_A33 0x10
>> +#define REG_PHY_UNK_H3 0x20
>> +
>> +#define REG_PMU_UNK_H3 0x10
>>
>> #define PHYCTL_DATA BIT(7)
>>
>> @@ -79,7 +82,7 @@
>> #define PHY_DISCON_TH_SEL 0x2a
>> #define PHY_SQUELCH_DETECT 0x3c
>>
>> -#define MAX_PHYS 3
>> +#define MAX_PHYS 4
>>
>> /*
>> * Note do not raise the debounce time, we must report Vusb high
>> within 100ms
>> @@ -88,12 +91,19 @@
>> #define DEBOUNCE_TIME msecs_to_jiffies(50)
>> #define POLL_TIME msecs_to_jiffies(250)
>>
>> +enum sun4i_usb_phy_type {
>> + sun4i_a10_phy,
>> + sun8i_a33_phy,
>> + sun8i_h3_phy
>> +};
>> +
>> struct sun4i_usb_phy_data {
>> + struct device *dev;
>> void __iomem *base;
>> struct mutex mutex;
>> int num_phys;
>> u32 disc_thresh;
>> - bool has_a33_phyctl;
>> + enum sun4i_usb_phy_type type;
>> struct sun4i_usb_phy {
>> struct phy *phy;
>> void __iomem *pmu;
>> @@ -164,12 +174,18 @@ static void sun4i_usb_phy_write(struct
>> sun4i_usb_phy *phy, u32 addr, u32 data,
>>
>> mutex_lock(&phy_data->mutex);
>>
>> - if (phy_data->has_a33_phyctl) {
>> + switch (phy_data->type) {
>> + case sun4i_a10_phy:
>> + phyctl = phy_data->base + REG_PHYCTL_A10;
>> + break;
>> + case sun8i_a33_phy:
>> phyctl = phy_data->base + REG_PHYCTL_A33;
>> /* A33 needs us to set phyctl to 0 explicitly */
>> writel(0, phyctl);
>> - } else {
>> - phyctl = phy_data->base + REG_PHYCTL_A10;
>> + break;
>> + case sun8i_h3_phy:
>> + dev_err(phy_data->dev, "H3 usb_phy_write is not
>> supported\n");
>> + break;
>> }
>>
>> for (i = 0; i < len; i++) {
>> @@ -230,6 +246,7 @@ static int sun4i_usb_phy_init(struct phy *_phy)
>> struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
>> struct sun4i_usb_phy_data *data =
>> to_sun4i_usb_phy_data(phy);
>> int ret;
>> + u32 val;
>>
>> ret = clk_prepare_enable(phy->clk);
>> if (ret)
>> @@ -241,15 +258,26 @@ static int sun4i_usb_phy_init(struct phy *_phy)
>> return ret;
>> }
>>
>> - /* Enable USB 45 Ohm resistor calibration */
>> - if (phy->index == 0)
>> - sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
>> + if (data->type == sun8i_h3_phy) {
>> + if (phy->index == 0) {
>> + val = readl(data->base + REG_PHY_UNK_H3);
>> + writel(val & ~1, data->base +
>> REG_PHY_UNK_H3);
>> + }
>> +
>> + val = readl(phy->pmu + REG_PMU_UNK_H3);
>> + writel(val & ~2, phy->pmu + REG_PMU_UNK_H3);
>> + } else {
>> + /* Enable USB 45 Ohm resistor calibration */
>> + if (phy->index == 0)
>> + sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN,
>> 0x01, 1);
>>
>> - /* Adjust PHY's magnitude and rate */
>> - sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
>> + /* Adjust PHY's magnitude and rate */
>> + sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE,
>> 0x14, 5);
>>
>> - /* Disconnect threshold adjustment */
>> - sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, data-
>>> disc_thresh, 2);
>> + /* Disconnect threshold adjustment */
>> + sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
>> + data->disc_thresh, 2);
>> + }
>>
>> sun4i_usb_phy_passby(phy, 1);
>>
>> @@ -522,11 +550,14 @@ static int sun4i_usb_phy_probe(struct
>> platform_device *pdev)
>> mutex_init(&data->mutex);
>> INIT_DELAYED_WORK(&data->detect,
>> sun4i_usb_phy0_id_vbus_det_scan);
>> dev_set_drvdata(dev, data);
>> + data->dev = dev;
>>
>> if (of_device_is_compatible(np, "allwinner,sun5i-a13-usb-
>> phy") ||
>> of_device_is_compatible(np, "allwinner,sun8i-a23-usb-
>> phy") ||
>> of_device_is_compatible(np, "allwinner,sun8i-a33-usb-
>> phy"))
>> data->num_phys = 2;
>> + else if (of_device_is_compatible(np, "allwinner,sun8i-h3-
>> usb-phy"))
>> + data->num_phys = 4;
>> else
>> data->num_phys = 3;
>>
>> @@ -538,13 +569,18 @@ static int sun4i_usb_phy_probe(struct
>> platform_device *pdev)
>>
>> if (of_device_is_compatible(np, "allwinner,sun6i-a31-usb-
>> phy") ||
>> of_device_is_compatible(np, "allwinner,sun8i-a23-usb-
>> phy") ||
>> - of_device_is_compatible(np, "allwinner,sun8i-a33-usb-
>> phy"))
>> + of_device_is_compatible(np, "allwinner,sun8i-a33-usb-
>> phy") ||
>> + of_device_is_compatible(np, "allwinner,sun8i-h3-usb-
>> phy"))
>> dedicated_clocks = true;
>> else
>> dedicated_clocks = false;
>>
>> if (of_device_is_compatible(np, "allwinner,sun8i-a33-usb-
>> phy"))
>> - data->has_a33_phyctl = true;
>> + data->type = sun8i_a33_phy;
>> + else if (of_device_is_compatible(np, "allwinner,sun8i-h3-
>> usb-phy"))
>> + data->type = sun8i_h3_phy;
>> + else
>> + data->type = sun4i_a10_phy;
>>
>> res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
>> "phy_ctrl");
>> data->base = devm_ioremap_resource(dev, res);
>> @@ -620,7 +656,7 @@ static int sun4i_usb_phy_probe(struct
>> platform_device *pdev)
>> return PTR_ERR(phy->reset);
>> }
>>
>> - if (i) { /* No pmu for usbc0 */
>> + if (data->type == sun8i_h3_phy || i != 0) {
>> snprintf(name, sizeof(name), "pmu%d", i);
>> res = platform_get_resource_byname(pdev,
>> IORESOURCE_M
>> EM, name);
>> @@ -696,6 +732,7 @@ static const struct of_device_id
>> sun4i_usb_phy_of_match[] = {
>> { .compatible = "allwinner,sun7i-a20-usb-phy" },
>> { .compatible = "allwinner,sun8i-a23-usb-phy" },
>> { .compatible = "allwinner,sun8i-a33-usb-phy" },
>> + { .compatible = "allwinner,sun8i-h3-usb-phy" },
>> { },
>> };
>> MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
>> --
>> 2.5.0
>>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH] ARM: dts: sun8i-h3-orangepi-plus: Enable USB host controllers
2015-11-20 14:38 ` Hans de Goede
@ 2015-11-24 7:44 ` Maxime Ripard
0 siblings, 0 replies; 18+ messages in thread
From: Maxime Ripard @ 2015-11-24 7:44 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Fri, Nov 20, 2015 at 03:38:47PM +0100, Hans de Goede wrote:
> Hi,
>
> On 17-11-15 17:12, Jens Kuske wrote:
> >Enable the 2 USB host controllers used on the Orange Pi Plus
> >and add the necessary regulators.
> >
> >Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
> >Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> >Signed-off-by: Jens Kuske <jenskuske@gmail.com>
> >---
> >
> >Hi Hans,
> >
> >with these regulators USB works on the Orange Pi Plus too.
> >I don't know if adding the regulators in the dts is okay, since most
> >regulators are defined in the sunxi-common-regulators.dtsi, but
> >we use different pins.
>
> Thanks, I've added this to my sunxi-wip branch for now.
>
> Regards,
>
> Hans
>
> p.s.
>
> Any progress on getting the "core" H3 kernel support upstream ?
>
> Given Arnd's remarks about how we should not hard-code the
> indices in the clk driver + the very KISS nature of the
> change to 1 parent-clk per gate setup I still believe
> that that one is best.
>
> Maxime ? Chen-Yu ? It would be really good to be able to
> move forward with this, how do you want to proceed ?
Yeah, sorry, Chen-Yu and I were busy because of $LIFE the past weeks,
we're getting back to speed.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [linux-sunxi] Re: [PATCH] ARM: dts: sun8i-h3-orangepi-plus: Enable USB host controllers
[not found] ` <fff9e78a-e23e-4226-9cec-67550bf09efb@googlegroups.com>
@ 2015-11-24 8:50 ` Hans de Goede
0 siblings, 0 replies; 18+ messages in thread
From: Hans de Goede @ 2015-11-24 8:50 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On 23-11-15 23:20, Troy Dack wrote:
>
>
> On Wednesday, 18 November 2015 03:12:11 UTC+11, Jens Kuske wrote:
>>
>> Enable the 2 USB host controllers used on the Orange Pi Plus
>> and add the necessary regulators.
>>
>> Signed-off-by: Reinder de Haan <patch...@mveas.com <javascript:>>
>> Signed-off-by: Hans de Goede <hdeg...@redhat.com <javascript:>>
>> Signed-off-by: Jens Kuske <jens...@gmail.com <javascript:>>
>> ---
>>
>> Hi Hans,
>>
>> with these regulators USB works on the Orange Pi Plus too.
>> I don't know if adding the regulators in the dts is okay, since most
>> regulators are defined in the sunxi-common-regulators.dtsi, but
>> we use different pins.
>>
>> Jens
>>
>>
>> arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 44
>> ++++++++++++++++++++++++++++
>> 1 file changed, 44 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
>> b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
>> index e67df59..1cb6c66 100644
>> --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
>> +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
>> @@ -58,6 +58,35 @@
>> chosen {
>> stdout-path = "serial0:115200n8";
>> };
>> +
>> + reg_usb3_vbus: usb3-vbus {
>> + compatible = "regulator-fixed";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&usb3_vbus_pin_a>;
>> + regulator-name = "usb3-vbus";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + regulator-boot-on;
>> + enable-active-high;
>> + gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>;
>> + };
>> +};
>> +
>> +&ehci1 {
>> + status = "okay";
>> +};
>> +
>> +&ehci3 {
>> + status = "okay";
>> +};
>> +
>> +&pio {
>> + usb3_vbus_pin_a: usb3_vbus_pin at 0 {
>> + allwinner,pins = "PG11";
>> + allwinner,function = "gpio_out";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> };
>>
>> &mmc0 {
>> @@ -70,8 +99,23 @@
>> status = "okay";
>> };
>>
>> +®_usb1_vbus {
>> + gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>;
>> + status = "okay";
>> +};
>> +
>> &uart0 {
>> pinctrl-names = "default";
>> pinctrl-0 = <&uart0_pins_a>;
>> status = "okay";
>> };
>> +
>> +&usb1_vbus_pin_a {
>> + allwinner,pins = "PG13";
>> +};
>> +
>> +&usbphy {
>> + usb1_vbus-supply = <®_usb1_vbus>;
>> + usb3_vbus-supply = <®_usb3_vbus>;
>> + status = "okay";
>> +};
>>
>
> I've been trying to test these patches by using Hans' github sunxi-wip
> branches of the kernel and U-Boot.
>
> U-Boot at commit 7e17fd2 "suxni: Add support for Orangepi Plus and Orangepi
> PC boards"
> Kernel at commit cb45b8 "ARM: dts: sun8i-h3-orangepi-plus: Enable USB host
> controllers"
>
> Both have been built using the default defconfig for an OrangePi Plus
>
> U-Boot starts and successfully boots the kernel, but the kernel does not
> appear to boot fully and hangs at:
>
> [ 0.861175] cpu cpu0: failed to get cpu0 clock: -2
> [ 0.865973] cpufreq-dt: probe of cpufreq-dt failed with error -2
> [ 0.872017] Registering SWP/SWPB emulation handler
>
> Full boot log: http://pastebin.com/VGkEix9p
>
> Building the kernel (or just using a dab) with the dts from commit 0a8c01
> "ARM: dts: sun8i: Add Orange Pi Plus support" results in the kernel booting
> fully to a login prompt. Of course without enabled/working USB.
>
> There is a fair chance I've done something wrong that is causing this. Any
> advice on how to get a bootable kernel?
Weird, are you sure you updated both the dtb and [u|z]image at the same time ?
I'm using this kernel config:
https://fedorapeople.org/~jwrdegoede/kernel-driver-programming/kernel-config
With that everything you need is builtin, no need to build modules.
Regards,
Hans
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2015-11-24 8:50 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-11-15 19:46 [PATCH 1/5] clk: sunxi: Add support for the H3 usb phy clocks Hans de Goede
2015-11-15 19:46 ` [PATCH 2/5] phy-sun4i-usb: Add support for the host usb-phys found on the H3 SoC Hans de Goede
2015-11-16 15:29 ` Rob Herring
2015-11-20 19:49 ` [linux-sunxi] " Priit Laes
2015-11-22 11:29 ` Hans de Goede
2015-11-15 19:46 ` [PATCH 3/5] ARM: dts: sun8i: Add support for H3 usb clocks Hans de Goede
2015-11-16 2:41 ` [linux-sunxi] " Chen-Yu Tsai
2015-11-15 19:46 ` [PATCH 4/5] ARM: dts: sun8i: Add usbphy and usb host controller nodes Hans de Goede
2015-11-15 19:46 ` [PATCH 5/5] ARM: dts: sun8i-h3-orangepi-plus: Enable USB host controllers Hans de Goede
2015-11-16 3:00 ` [linux-sunxi] " Chen-Yu Tsai
2015-11-16 8:11 ` Hans de Goede
2015-11-17 16:12 ` [PATCH] " Jens Kuske
2015-11-20 14:38 ` Hans de Goede
2015-11-24 7:44 ` Maxime Ripard
[not found] ` <fff9e78a-e23e-4226-9cec-67550bf09efb@googlegroups.com>
2015-11-24 8:50 ` [linux-sunxi] " Hans de Goede
2015-11-16 2:36 ` [linux-sunxi] [PATCH 1/5] clk: sunxi: Add support for the H3 usb phy clocks Chen-Yu Tsai
2015-11-20 12:49 ` Maxime Ripard
2015-11-16 15:30 ` Rob Herring
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