* [PATCH] clk: sunxi-ng: sun5i: Fix ahb_bist_clk definition
@ 2017-05-24 16:34 Boris Brezillon
2017-05-24 18:51 ` Angus Ainslie
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Boris Brezillon @ 2017-05-24 16:34 UTC (permalink / raw)
To: linux-arm-kernel
AHB BIST gate is actually controlled with bit 7.
This bug was detected while trying to use the NAND controller which is
using the DMA engine to transfer data to the NAND.
Since the ahb_bist_clk gate bit conflicts with the ahb_dma_clk gate bit,
the core was disabling the DMA engine clock as part of its 'disable
unused clks' procedure, which was causing all DMA transfers to fail after
this point.
Fixes: 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver")
Cc: stable at vger.kernel.org
Reported-by: Angus Ainslie <angus@akkea.ca>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
---
drivers/clk/sunxi-ng/ccu-sun5i.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.c b/drivers/clk/sunxi-ng/ccu-sun5i.c
index 5c476f966a72..5372bf8be5e6 100644
--- a/drivers/clk/sunxi-ng/ccu-sun5i.c
+++ b/drivers/clk/sunxi-ng/ccu-sun5i.c
@@ -243,7 +243,7 @@ static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
0x060, BIT(6), 0);
static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
- 0x060, BIT(6), 0);
+ 0x060, BIT(7), 0);
static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
0x060, BIT(8), 0);
static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] clk: sunxi-ng: sun5i: Fix ahb_bist_clk definition
2017-05-24 16:34 [PATCH] clk: sunxi-ng: sun5i: Fix ahb_bist_clk definition Boris Brezillon
@ 2017-05-24 18:51 ` Angus Ainslie
2017-05-25 7:47 ` Chen-Yu Tsai
2017-05-25 7:48 ` Chen-Yu Tsai
2017-05-25 18:50 ` Michael Turquette
2 siblings, 1 reply; 8+ messages in thread
From: Angus Ainslie @ 2017-05-24 18:51 UTC (permalink / raw)
To: linux-arm-kernel
On 2017-05-24 10:34, Boris Brezillon wrote:
> AHB BIST gate is actually controlled with bit 7.
>
> This bug was detected while trying to use the NAND controller which is
> using the DMA engine to transfer data to the NAND.
> Since the ahb_bist_clk gate bit conflicts with the ahb_dma_clk gate
> bit,
> the core was disabling the DMA engine clock as part of its 'disable
> unused clks' procedure, which was causing all DMA transfers to fail
> after
> this point.
>
> Fixes: 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver")
> Cc: stable at vger.kernel.org
> Reported-by: Angus Ainslie <angus@akkea.ca>compatible =
> "nextthing,chip-pro", "nextthing,gr8";
> Signed-off-by: Boris Brezillon <boris.brezillon@frecompatible =
> "nextthing,chip-pro", "nextthing,gr8";e-electrons.com>
> ---
> drivers/clk/sunxi-ng/ccu-sun5i.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.c
> b/drivers/clk/sunxi-ng/ccu-sun5i.c
> index 5c476f966a72..5372bf8be5e6 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun5i.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun5i.c
> @@ -243,7 +243,7 @@ static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
> static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
> 0x060, BIT(6), 0);
> static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
> - 0x060, BIT(6), 0);
> + 0x060, BIT(7), 0);
> static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
> 0x060, BIT(8), 0);
> static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
The patch works perfectly. Using that I was able to remove the
clk_ignore_unsed and CLK_IS_CRITICAL.
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] clk: sunxi-ng: sun5i: Fix ahb_bist_clk definition
2017-05-24 18:51 ` Angus Ainslie
@ 2017-05-25 7:47 ` Chen-Yu Tsai
2017-05-25 12:39 ` Angus Ainslie
0 siblings, 1 reply; 8+ messages in thread
From: Chen-Yu Tsai @ 2017-05-25 7:47 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, May 25, 2017 at 2:51 AM, Angus Ainslie <angus@akkea.ca> wrote:
> On 2017-05-24 10:34, Boris Brezillon wrote:
>>
>> AHB BIST gate is actually controlled with bit 7.
>>
>> This bug was detected while trying to use the NAND controller which is
>> using the DMA engine to transfer data to the NAND.
>> Since the ahb_bist_clk gate bit conflicts with the ahb_dma_clk gate bit,
>> the core was disabling the DMA engine clock as part of its 'disable
>> unused clks' procedure, which was causing all DMA transfers to fail after
>> this point.
>>
>> Fixes: 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver")
>> Cc: stable at vger.kernel.org
>> Reported-by: Angus Ainslie <angus@akkea.ca>compatible =
>> "nextthing,chip-pro", "nextthing,gr8";
>> Signed-off-by: Boris Brezillon <boris.brezillon@frecompatible =
>> "nextthing,chip-pro", "nextthing,gr8";e-electrons.com>
>> ---
>> drivers/clk/sunxi-ng/ccu-sun5i.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.c
>> b/drivers/clk/sunxi-ng/ccu-sun5i.c
>> index 5c476f966a72..5372bf8be5e6 100644
>> --- a/drivers/clk/sunxi-ng/ccu-sun5i.c
>> +++ b/drivers/clk/sunxi-ng/ccu-sun5i.c
>> @@ -243,7 +243,7 @@ static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss",
>> "ahb",
>> static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
>> 0x060, BIT(6), 0);
>> static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
>> - 0x060, BIT(6), 0);
>> + 0x060, BIT(7), 0);
>> static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
>> 0x060, BIT(8), 0);
>> static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
>
>
>
> The patch works perfectly. Using that I was able to remove the
> clk_ignore_unsed and CLK_IS_CRITICAL.
>
Is that a Tested-by? :)
ChenYu
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] clk: sunxi-ng: sun5i: Fix ahb_bist_clk definition
2017-05-24 16:34 [PATCH] clk: sunxi-ng: sun5i: Fix ahb_bist_clk definition Boris Brezillon
2017-05-24 18:51 ` Angus Ainslie
@ 2017-05-25 7:48 ` Chen-Yu Tsai
2017-05-25 18:50 ` Michael Turquette
2 siblings, 0 replies; 8+ messages in thread
From: Chen-Yu Tsai @ 2017-05-25 7:48 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, May 25, 2017 at 12:34 AM, Boris Brezillon
<boris.brezillon@free-electrons.com> wrote:
> AHB BIST gate is actually controlled with bit 7.
>
> This bug was detected while trying to use the NAND controller which is
> using the DMA engine to transfer data to the NAND.
> Since the ahb_bist_clk gate bit conflicts with the ahb_dma_clk gate bit,
> the core was disabling the DMA engine clock as part of its 'disable
> unused clks' procedure, which was causing all DMA transfers to fail after
> this point.
>
> Fixes: 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver")
> Cc: stable at vger.kernel.org
> Reported-by: Angus Ainslie <angus@akkea.ca>
> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] clk: sunxi-ng: sun5i: Fix ahb_bist_clk definition
2017-05-25 7:47 ` Chen-Yu Tsai
@ 2017-05-25 12:39 ` Angus Ainslie
0 siblings, 0 replies; 8+ messages in thread
From: Angus Ainslie @ 2017-05-25 12:39 UTC (permalink / raw)
To: linux-arm-kernel
On 2017-05-25 01:47, Chen-Yu Tsai wrote:
> On Thu, May 25, 2017 at 2:51 AM, Angus Ainslie <angus@akkea.ca> wrote:
>> On 2017-05-24 10:34, Boris Brezillon wrote:
>>>
>>> AHB BIST gate is actually controlled with bit 7.
>>>
>>> This bug was detected while trying to use the NAND controller which
>>> is
>>> using the DMA engine to transfer data to the NAND.
>>> Since the ahb_bist_clk gate bit conflicts with the ahb_dma_clk gate
>>> bit,
>>> the core was disabling the DMA engine clock as part of its 'disable
>>> unused clks' procedure, which was causing all DMA transfers to fail
>>> after
>>> this point.
>>>
>>> Fixes: 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver")
>>> Cc: stable at vger.kernel.org
>>> Reported-by: Angus Ainslie <angus@akkea.ca>compatible =
>>> "nextthing,chip-pro", "nextthing,gr8";
>>> Signed-off-by: Boris Brezillon <boris.brezillon@frecompatible =
>>> "nextthing,chip-pro", "nextthing,gr8";e-electrons.com>
>>> ---
>>> drivers/clk/sunxi-ng/ccu-sun5i.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.c
>>> b/drivers/clk/sunxi-ng/ccu-sun5i.c
>>> index 5c476f966a72..5372bf8be5e6 100644
>>> --- a/drivers/clk/sunxi-ng/ccu-sun5i.c
>>> +++ b/drivers/clk/sunxi-ng/ccu-sun5i.c
>>> @@ -243,7 +243,7 @@ static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss",
>>> "ahb",
>>> static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
>>> 0x060, BIT(6), 0);
>>> static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
>>> - 0x060, BIT(6), 0);
>>> + 0x060, BIT(7), 0);
>>> static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
>>> 0x060, BIT(8), 0);
>>> static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
>>
>>
>>
>> The patch works perfectly. Using that I was able to remove the
>> clk_ignore_unsed and CLK_IS_CRITICAL.
>>
>
> Is that a Tested-by? :)
>
> ChenYu
Yeah :)
Tested-by: Angus Ainslie <angus@akkea.ca>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] clk: sunxi-ng: sun5i: Fix ahb_bist_clk definition
2017-05-24 16:34 [PATCH] clk: sunxi-ng: sun5i: Fix ahb_bist_clk definition Boris Brezillon
2017-05-24 18:51 ` Angus Ainslie
2017-05-25 7:48 ` Chen-Yu Tsai
@ 2017-05-25 18:50 ` Michael Turquette
2017-05-25 19:23 ` Angus Ainslie
2 siblings, 1 reply; 8+ messages in thread
From: Michael Turquette @ 2017-05-25 18:50 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Boris Brezillon (2017-05-24 09:34:29)
> AHB BIST gate is actually controlled with bit 7.
>
> This bug was detected while trying to use the NAND controller which is
> using the DMA engine to transfer data to the NAND.
> Since the ahb_bist_clk gate bit conflicts with the ahb_dma_clk gate bit,
> the core was disabling the DMA engine clock as part of its 'disable
> unused clks' procedure, which was causing all DMA transfers to fail after
> this point.
>
> Fixes: 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver")
> Cc: stable at vger.kernel.org
> Reported-by: Angus Ainslie <angus@akkea.ca>
> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Patch looks good to me. Did this ever work? I'm trying to figure out if
it should go into -fixes or -next.
Thanks,
Mike
> ---
> drivers/clk/sunxi-ng/ccu-sun5i.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.c b/drivers/clk/sunxi-ng/ccu-sun5i.c
> index 5c476f966a72..5372bf8be5e6 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun5i.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun5i.c
> @@ -243,7 +243,7 @@ static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
> static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
> 0x060, BIT(6), 0);
> static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
> - 0x060, BIT(6), 0);
> + 0x060, BIT(7), 0);
> static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
> 0x060, BIT(8), 0);
> static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] clk: sunxi-ng: sun5i: Fix ahb_bist_clk definition
2017-05-25 18:50 ` Michael Turquette
@ 2017-05-25 19:23 ` Angus Ainslie
2017-05-25 21:05 ` Michael Turquette
0 siblings, 1 reply; 8+ messages in thread
From: Angus Ainslie @ 2017-05-25 19:23 UTC (permalink / raw)
To: linux-arm-kernel
On 2017-05-25 12:50, Michael Turquette wrote:
> Quoting Boris Brezillon (2017-05-24 09:34:29)
>> AHB BIST gate is actually controlled with bit 7.
>>
>> This bug was detected while trying to use the NAND controller which is
>> using the DMA engine to transfer data to the NAND.
>> Since the ahb_bist_clk gate bit conflicts with the ahb_dma_clk gate
>> bit,
>> the core was disabling the DMA engine clock as part of its 'disable
>> unused clks' procedure, which was causing all DMA transfers to fail
>> after
>> this point.
>>
>> Fixes: 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver")
>> Cc: stable at vger.kernel.org
>> Reported-by: Angus Ainslie <angus@akkea.ca>
>> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
>
> Patch looks good to me. Did this ever work? I'm trying to figure out if
> it should go into -fixes or -next.
>
> Thanks,
> Mike
>
It fixed the problem for me so I think fixes is the right place.
Angus
>> ---
>> drivers/clk/sunxi-ng/ccu-sun5i.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.c
>> b/drivers/clk/sunxi-ng/ccu-sun5i.c
>> index 5c476f966a72..5372bf8be5e6 100644
>> --- a/drivers/clk/sunxi-ng/ccu-sun5i.c
>> +++ b/drivers/clk/sunxi-ng/ccu-sun5i.c
>> @@ -243,7 +243,7 @@ static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss",
>> "ahb",
>> static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
>> 0x060, BIT(6), 0);
>> static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
>> - 0x060, BIT(6), 0);
>> + 0x060, BIT(7), 0);
>> static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
>> 0x060, BIT(8), 0);
>> static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
>> --
>> 2.7.4
>>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] clk: sunxi-ng: sun5i: Fix ahb_bist_clk definition
2017-05-25 19:23 ` Angus Ainslie
@ 2017-05-25 21:05 ` Michael Turquette
0 siblings, 0 replies; 8+ messages in thread
From: Michael Turquette @ 2017-05-25 21:05 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Angus Ainslie (2017-05-25 12:23:54)
> On 2017-05-25 12:50, Michael Turquette wrote:
> > Quoting Boris Brezillon (2017-05-24 09:34:29)
> >> AHB BIST gate is actually controlled with bit 7.
> >>
> >> This bug was detected while trying to use the NAND controller which is
> >> using the DMA engine to transfer data to the NAND.
> >> Since the ahb_bist_clk gate bit conflicts with the ahb_dma_clk gate
> >> bit,
> >> the core was disabling the DMA engine clock as part of its 'disable
> >> unused clks' procedure, which was causing all DMA transfers to fail
> >> after
> >> this point.
> >>
> >> Fixes: 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver")
> >> Cc: stable at vger.kernel.org
> >> Reported-by: Angus Ainslie <angus@akkea.ca>
> >> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
> >
> > Patch looks good to me. Did this ever work? I'm trying to figure out if
> > it should go into -fixes or -next.
> >
> > Thanks,
> > Mike
> >
>
> It fixed the problem for me so I think fixes is the right place.
Applied to clk-fixes towards -rc3 or -rc4.
Regards,
Mike
>
> Angus
>
> >> ---
> >> drivers/clk/sunxi-ng/ccu-sun5i.c | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.c
> >> b/drivers/clk/sunxi-ng/ccu-sun5i.c
> >> index 5c476f966a72..5372bf8be5e6 100644
> >> --- a/drivers/clk/sunxi-ng/ccu-sun5i.c
> >> +++ b/drivers/clk/sunxi-ng/ccu-sun5i.c
> >> @@ -243,7 +243,7 @@ static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss",
> >> "ahb",
> >> static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
> >> 0x060, BIT(6), 0);
> >> static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
> >> - 0x060, BIT(6), 0);
> >> + 0x060, BIT(7), 0);
> >> static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
> >> 0x060, BIT(8), 0);
> >> static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
> >> --
> >> 2.7.4
> >>
>
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2017-05-25 21:05 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
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2017-05-24 16:34 [PATCH] clk: sunxi-ng: sun5i: Fix ahb_bist_clk definition Boris Brezillon
2017-05-24 18:51 ` Angus Ainslie
2017-05-25 7:47 ` Chen-Yu Tsai
2017-05-25 12:39 ` Angus Ainslie
2017-05-25 7:48 ` Chen-Yu Tsai
2017-05-25 18:50 ` Michael Turquette
2017-05-25 19:23 ` Angus Ainslie
2017-05-25 21:05 ` Michael Turquette
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